16 MBit Synchronous DRAM (second generation) HYB 39S16400/800/160AT-8/-10 Advanced Information • High Performance: CAS latency = 3 • Multiple Burst Read with Single Write Operation -8 -10 Units fCK 125 100 MHz • Automatic and Controlled Precharge Command tCK3 8 10 ns • Data Mask for Read/Write control (× 4, × 8) tAC3 7 8 ns • Dual Data Mask for byte control (× 16) • Auto Refresh (CBR) and Self Refresh • Single Pulsed RAS Interface • Suspend Mode and Power Down Mode • Fully Synchronous to Positive Clock Edge • 4096 refresh cycles/64 ms • 0 to 70 °C operating temperature • Random Column Address every CLK (1-N Rule) • Dual Banks controlled by A11 (Bank Select) • Single 3.3 V ± 0.3 V Power Supply • Programmable CAS Latency: 1, 2, 3 • LVTTL Interface versions • Programmable Wrap Sequence: Sequential or Interleave • Plastic Packages: P-TSOPII-44-1 400 mil width (× 4, × 8) P-TSOPII-50-1 400 mil width (× 16) • Programmable Burst Length: 1, 2, 4, 8 and full page for Sequential type 1, 2, 4, 8 for Interleave type The HYB 39S1640x/80x/16xAT are dual bank Synchronous DRAM’s based on the die revisions “B” and “C” and organized as 2 banks × 2 MBit × 4, 2 banks × 1 MBit × 8 and 2 banks × 512 kBit × 16 respectively. These synchronous devices achieve high speed data transfer rates up to 125 MHz by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is fabricated with SIEMENS advanced 16 MBit DRAM process technology. The device is designed to comply with all JEDEC standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. Operating the two memory banks in an interleaved fashion allows random access operation to occur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 125 MHz is possible depending on burst length, CAS latency and speed grade of the device. Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single 3.3 V ± 0.3 V power supply and are available in TSOPII packages. Semiconductor Group 1 1998-10-01 HYB 39S16400/800/160AT-8/-10 16 MBit Synchronous DRAM Ordering Information Type Ordering Code Package Description LVTTL-Version HYB 39S16400AT-8 Q67100-Q1333 P-TSOPII-44-1 (400 mil) 125 MHz 2B × 2 M × 4 SDRAM PC66 2-2-2 HYB 39S16400AT-10 Q67100-Q1323 P-TSOPII-44-1 (400 mil) 100 MHz 2B × 2 M × 4 SDRAM PC66 2-2-2 HYB 39S16800AT-8 Q67100-Q1335 P-TSOPII-44-1 (400 mil) 125 MHz 2B × 1 M × 8 SDRAM PC66 2-2-2 HYB 39S16800AT-10 Q67100-Q1327 P-TSOPII-44-1 (400 mil) 100 MHz 2B × 1 M × 8 SDRAM PC66 2-2-2 HYB 39S16160AT-8 Q67100-Q1337 P-TSOPII-50-1 (400 mil) 125 MHz 2B × 512 k × 16 SDRAM HYB 39S16160AT-10 Q67100-Q1331 P-TSOPII-50-1 (400 mil) 100 MHz 2B × 512 k × 16 SDRAM Pin Names CLK Clock Input DQ Data Input/Output CKE Clock Enable DQM, LDQM, UDQM Data Mask CS Chip Select VDD Power (+ 3.3 V) RAS Row Address Strobe VSS Ground CAS Column Address Strobe VDDQ Power for DQ’s (+ 3.3 V) WE Write Enable VSSQ Ground for DQ’s A0 - A10 Address Inputs NC Not connected A11 (BS) Bank Select Semiconductor Group 2 1998-10-01 HYB 39S16400/800/160AT-8/-10 16 MBit Synchronous DRAM VDD DQ0 VSSQ DQ1 VDDQ DQ2 VSSQ DQ3 VDDQ N.C. N.C. WE CAS RAS CS A11 A10 A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 VSS DQ7 VSSQ DQ6 VDDQ DQ5 VSSQ DQ4 VDDQ N.C. N.C. DQM CLK CKE N.C. A9 A8 A7 A6 A5 A4 VSS SPP03402 Pin Configuration Semiconductor Group 3 1998-10-01 HYB 39S16400/800/160AT-8/-10 16 MBit Synchronous DRAM Signal Pin Description Pin Type Signal Polarity Function CLK Input Pulse Positive Edge The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock. CKE Input Level Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby initiates either the Power Down mode, Suspend mode or the Self Refresh mode. CS Input Pulse Active Low CS enables the command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS CAS WE Input Pulse Active Low When sampled at the positive rising edge of the clock, CAS, RAS and WE define the command to be executed by the SDRAM. A0 - A10 Input Level – During a Bank Activate command cycle, A0 - A10 defines the row address (RA0 - RA10) when sampled at the rising clock edge. During a Read or Write command cycle, A0 - A9 defines the column address (CA0 - CAn) when sampled at the rising clock edge. CAn depends from the SDRAM organisation. 4M × 4 SDRAM CAn = CA9 2M × 8 SDRAM CAn = CA8 1M × 16 SDRAM CAn = CA7 In addition to the column address, A10 is used to invoke autoprecharge operation at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and A11 defines the bank to be precharged (low = bank A, high = bank B). If A10 is low, autoprecharge is disabled. During a Precharge command cycle, A10 is used in conjunction with A11 to control which bank(s) to precharge. If A10 is high, both bank A and bank B will be precharged regardless of the state of A11. If A10 is low, then A11 is used to define which bank to precharge. A11 (BS) Input Level – Selects which bank is to be active. A11 low selects bank A and A11 high selects bank B. DQx Input Level Output – Data Input/Output pins operate in the same manner as on conventional DRAMs. Semiconductor Group 4 1998-10-01 HYB 39S16400/800/160AT-8/-10 16 MBit Synchronous DRAM Signal Pin Description (cont’d) Pin Type Signal Polarity Function DQM LDQM UDQM Input Pulse VDD VSS VDDQ VSSQ Active High The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable. In Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if DQM is high. Supply – – Power and ground for the input buffers and the core logic. Supply – – Isolated power supply and ground for the output buffers to provide improved noise immunity. Semiconductor Group 5 1998-10-01 HYB 39S16400/800/160AT-8/-10 16 MBit Synchronous DRAM CKE CKE Buffer Self Refresh Clock 2048 x 1024 Memory Bank A Row Decoder 2048 11 Sense Amplifiers Column Decoder and DQ Gate Predecode A 8 12 3 Sequential Control Bank A Data Latches 8 12 11 Mode Register 8 CS CS Buffer RAS RAS Buffer CAS Buffer Command Decoder 3 CAS 4 11 Sequential Control Bank B Data Input/Output Buffers A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 (BS) CLK Buffer Address Buffers (12) CLK 1024 Bank A Row/Column Select Row Address Counter DQ0 DQ1 DQ2 DQ3 Data Latches 8 Predecode B Column Decoder and DQ Gate Bank B Row/Column Sense Amplifiers Select WE WE Buffer DQM DQM Buffer 1024 Memory Bank B 2048 x 1024 Row Decoder 2048 SPB02835 Block Diagram for HYB 39S16400T (2 banks × 4 M × 4 SDRAM) Semiconductor Group 6 1998-10-01 HYB 39S16400/800/160AT-8/-10 16 MBit Synchronous DRAM CKE CKE Buffer Self Refresh Clock 2048 x 512 Memory Bank A Row Decoder 2048 Bank A Row/Column Select Row Address Counter 11 8 Sense Amplifiers 8 Predecode A Column Decoder and DQ Gate 8 12 3 Sequential Control Bank A 8 Data Latches 8 12 11 Mode Register 8 CS CS Buffer RAS RAS Buffer CAS Buffer WE WE Buffer DQM DQM Buffer Command Decoder 3 CAS 512 11 Sequential Control Bank B 8 Data Input/Output Buffers A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 (BS) CLK Buffer Address Buffers (12) CLK 8 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 Data Latches 8 Predecode B 8 Bank B Row/Column Select Column Decoder and DQ Gate Sense Amplifiers 8 512 Memory Bank B 2048 x 512 Row Decoder 2048 SPB02836 Block Diagram for HYB 39S16800T (2 banks × 1 M × 8 SDRAM) Semiconductor Group 7 1998-10-01 HYB 39S16400/800/160AT-8/-10 16 MBit Synchronous DRAM CKE Buffer Self Refresh Clock Bank A Row/Column Select Row Address Counter A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 (BS) CLK Buffer 11 12 3 11 RAS RAS Buffer CAS Buffer Command Decoder CS Buffer UDQM Sense Amplifiers 16 Predecode A Column Decoder and DQ Gate Sequential Control Bank A 16 Data Latches Mode Register 8 CS WE 16 256 8 12 3 CAS 2048 16 8 Address Buffers (12) CLK 2048 x 256 Memory Bank A Row Decoder 11 Sequential Control Bank B Data Latches DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 8 Predecode B 16 Bank B Row/Column Select WE Buffer DQM Buffer 16 Data Input/Output Buffers CKE Column Decoder and DQ Gate Sense Amplifiers 16 256 Memory Bank B 2048 x 256 Row Decoder 2048 LDQM DQM Buffer SPB02837 Block Diagram for HYB 39S16160T (2 banks × 512 k × 16 SDRAM) Semiconductor Group 8 1998-10-01 HYB 39S16400/800/160AT-8/-10 16 MBit Synchronous DRAM Operation Definition All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the positive edge of the clock. The following list shows the most important operation commands. Operation CS RAS CAS WE (L/U)DQM Standby, Ignore RAS, CAS, WE and Address H X X X X Row Address Strobe and Activating a Bank L L H H X Column Address Strobe and Read Command L H L H X Column Address Strobe and Write Command L H L L X Precharge Command L L H L X Burst Stop Command L H H L X Self Refresh Entry L L L H X Mode Register Set Command L L L L X Write Enable/Output Enable X X X X L Write Inhibit/Output Disable X X X X H No Operation (NOP) L H H H X Mode Register For application flexibility, a CAS latency, a burst length, and a burst sequence can be programmed in the SDRAM mode register. The mode set operation must be done before any activate command after the initial power up. Any content of the mode register can be altered by reexecuting the mode set command. Both banks must be in precharged state and CKE must be high at least one clock before the mode set operation. After the mode register is set, a Standby or NOP command is required. Low signals of RAS, CAS, and WE at the positive edge of the clock activate the mode set operation. Address input data at this timing defines parameters to be set as shown in the following table. Semiconductor Group 9 1998-10-01 HYB 39S16400/800/160AT-8/-10 16 MBit Synchronous DRAM BS A10 A9 A8 A7 A6 Operation Mode A5 A4 CAS Latency A2 BT Operation Mode M11 M10 M9 A3 A1 A0 Address Bus (Ax) Burst Length Mode Register (Mx) Burst Type M8 M7 Mode M3 Type 0 0 0 0 0 Normal 0 Sequential Interleave X 1 0 0 Multiple Burst with Single Write 1 X Burst Length Length CAS Latency M2 M1 M6 M5 M4 Latency 0 0 0 Reserve 0 0 0 0 1 1 0 0 1 0 2 0 1 1 1 0 1 M0 Sequential Interleave 0 1 1 0 1 2 2 0 1 0 4 4 3 0 1 1 8 8 0 Reserve 1 0 0 Reserve Reserve 0 1 Reserve 1 0 1 Reserve Reserve 1 1 0 Reserve 1 1 0 Reserve Reserve 1 1 1 Reserve 1 1 1 Full Page *) Reserve *) Sequential Burst Addressing 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 optional Interleave Burst Addressing 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0 SPD03138 Address Input for Mode Set (Mode Register Operation) Semiconductor Group 10 1998-10-01 HYB 39S16400/800/160AT-8/-10 16 MBit Synchronous DRAM Read and Write Access Mode When RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle starts. According to address data, a word line of the selected bank is activated and all of sense amplifiers associated to the word line are fired. A CAS cycle is triggered by setting RAS high and CAS low at a clock timing after a necessary delay, tRCD, from the RAS timing. WE is used to define either a read (WE = H) or a write (WE = L) at this stage. SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read or write operations are allowed at up to a 125 MHz data rate. The numbers of serial data bits are the burst length programmed at the mode set operation, i.e., one of 1, 2, 4, 8 and full page. Column addresses are segmented by the burst length and serial data accesses are done within this boundary. The first column address to be accessed is supplied at the CAS timing and the subsequent addresses are generated automatically by the programmed burst length and its sequence. For example, in a burst length of 8 with interleave sequence, if the first address is ‘2’, then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5. Full page burst operation is only possible using the sequential burst type and page length is a function of the I/O organisation and column addressing. Full page burst operation do not self terminate once the burst length has been reached. In other words, unlike burst length of 2, 3 or 8, full page burst continues until it is terminated using another command. Similar to the page mode of conventional DRAM’s, burst read or write accesses on any column address are possible once the RAS cycle latches sense amplifiers. The maximum tRAS or the refresh interval time limits the number of random column accesses. A new burst access can be done even before the previous burst ends. The interrupt operation at every clock cycles is supported. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. An interrupt which accompanies with an operation change from a read to a write is possible by exploiting DQM to avoid bus contention. When two banks are activated sequentially, interleaved bank read or write operations are possible. With the programmed burst length, alternate access and precharge operations on two banks can realize fast serial data access modes among many different pages. Once two banks are activated, column to column interleave operation can be done between two different pages. Refresh Mode SDRAM has two refresh modes, a CAS-before-RAS (CBR) automatic refresh and a self refresh. All of banks must be precharged before applying any refresh mode. An on-chip address counter increments the word and the bank addresses and no bank information is required for both refresh modes. The chip enters the automatic refresh mode, when RAS and CAS are held low and CKE and WE are held high at a clock timing. The mode restores word line after the refresh and no external precharge command is necessary. A minimum tRC time is required between two automatic refreshes in a burst refresh mode. The same rule applies to any access command after the automatic refresh operation. The chip has an on-chip timer and the self refresh mode is available. It enters the mode when RAS, CAS, and CKE are low and WE is high at a clock timing. All of external control signals including the clock are disabled. Returning CKE to high enables the clock and initiates the refresh exit operation. After the exit command, at least one tRC delay is required prior to any access command. Semiconductor Group 11 1998-10-01 HYB 39S16400/800/160AT-8/-10 16 MBit Synchronous DRAM DQM Function DQM has two functions for data I/O read write operations. During reads, when it turns to high at a clock timing, data outputs are disabled and become high impedance after two clock delay (DQM Data Disable Latency tDQZ). It also provides a data mask function for writes. When DQM is activated, the write operation at the next clock is prohibited (DQM Write Mask Latency tDQW = zero clocks). Suspend Mode During normal access mode, CKE is held high and CLK is enabled. When CKE is low, it freezes the internal clock and extends data read and write operations. One clock delay is required for mode entry and exit (Clock Suspend Latency tCSL). Power Down In order to reduce standby power consumption, a power down mode is available. Bringing CKE low enters the power down mode and all of receiver circuits are gated. All banks must be precharged before entering this mode. One clock delay is required for mode entry and exit. The Power Down mode does not perform any refresh operation. Auto Precharge Two methods are available to precharge SDRAMs. In an automatic precharge mode, the CAS timing accepts one extra address, CA10, to determine whether the chip restores or not after the operation. If CA10 is high when a Read Command is issued, the Read with Auto-Precharge function is initiated. The SDRAM automatically enters the precharge operation one clock after the Read Command is registered for CAS latencies of 1 and 2, and two clocks for CAS latencies of 3. If CAS10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The SDRAM automatically enters the precharge operation one clock delay form the last data-in for CAS latencies of 1 and 2 and two clocks for CAS latencies of 3. This delay is referenced as tDPL. Precharge Command If CA10 is low, the chip needs another way to precharge. In this mode, a separate precharge command is necessary. When RAS and WE are low and CAS is high at a clock timing, it triggers the precharge operation. Two address bits, A10 and A11, are used to define banks as shown in the following list. The precharge command may be applied coincident with the last of burst reads for CAS Latency = 1 and with the second to the last read data for CAS Latencies = 2 & 3. Writes require a time tDPL from the last burst data to apply the precharge command. Semiconductor Group 12 1998-10-01 HYB 39S16400/800/160AT-8/-10 16 MBit Synchronous DRAM Bank Selection by Address Bits A10 A11 Bank A only Low Low Bank B only Low High Both A and B High Don’t Care Burst Termination Once a burst read or write operation has been initiated, there are several methods in which to terminate the burst operation prematurely. These methods include using another Read or Write Command to interrupt an existing burst operation, use a Precharge Command to interrupt a burst cycle and close the active bank, or using the Burst Stop Command to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank. When interrupting a burst with another Read or Write Command care must be taken to avoid DQ contention. The Burst Stop Command, however, has the fewest restrictions making it the easiest method to use when terminating a burst operation before it has been completed. If a Burst Stop command is issued during a burst write operation, then any residual data from the burst write cycle will be ignored. Data that is presented on the DQ pins before the Burst Stop Command is registered will be written to the memory. Power Up Procedure All VDD and VDDQ must reach the specified voltage no later than any of input signal voltages. An initial pause of 200 µs is required after power on. All banks have to be precharged and a minimum of 2 auto-refresh cycles are required prior to the mode register set operation. Semiconductor Group 13 1998-10-01 HYB 39S16400/800/160AT-8/-10 16 MBit Synchronous DRAM Absolute Maximum Ratings Operating temperature range ........................................................................................ 0 to + 70 °C Storage temperature range..................................................................................... – 55 to + 150 °C Input/output voltage .......................................................................... – 0.5 to min (VCC + 0.5, 4.6) V Power supply voltage VDD / VDDQ ............................................................................. – 1.0 to + 4.6 V Power Dissipation ....................................................................................................................... 1 W Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operation and Characteristics for LV-TTL Versions TA = 0 to 70 °C; VSS = 0 V; VDD, VDDQ = 3.3 V ± 0.3 V Parameter Symbol Limit Values min. max. Unit Notes Input high voltage VIH 2.0 VCC + 0.3 V 1, 2 Input low voltage VIL – 0.3 0.8 V 1, 2 Output high voltage (IOUT = – 2.0 mA) VOH 2.4 – V Output low voltage (IOUT = 2.0 mA) VOL – 0.4 V Input leakage current, any input (0 V < VIN < VDDQ, all other inputs = 0 V) II(L) – 10 10 µA Output leakage current (DQ is disabled, 0 V < VOUT < VCC) IO(L) – 10 10 µA Capacitance TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz Parameter Symbol max. Values Unit Input capacitance (A0 to A11) CI1 4 pF Input capacitance (RAS, CAS, WE, CS, CLK, CKE, DQM) CI2 4 pF Output capacitance (DQ) CIO 5 pF VREF CREF 8 pF Semiconductor Group 14 1998-10-01 HYB 39S16400/800/160AT-8/-10 16 MBit Synchronous DRAM Operating Currents TA = 0 to 70 oC, VCC = 3.3 V ± 0.3 V (Recommended Operating Conditions unless otherwise noted) Parameter -8 -10 Unit Note CAS Latency max. max. Symbol Test Condition Operating current ICC1 Burst Length = 4 1 tRC ≥ tRC(MIN.) 2 tCK ≥ tCK(MIN.), IO = 0 mA 3 2 bank interleave operation 80 115 125 65 90 100 mA mA mA Precharge ICC2P Standby current in Power Down ICC2PS Mode CKE ≤ VIL(MAX.), tCK ≥ tCK(MIN.) – 3 3 mA CKE ≤ VIL(MAX.), tCK = infinite – 2 2 mA Precharge ICC2N Standby current in Non-power down Mode I CKE ≥ VIH(MIN.), tCK ≥ tCK(MIN.) input signals changed once in 3 cycles – 20 20 mA CKE ≥ VIH(MIN.), tCK = infinite, – input signals are stable 10 10 mA CC2NS 6, 7 CS = High Active Standby current in Power Down Mode ICC3P CKE ≤ VIL(MAX)., tCK ≥ tCK(MIN.) – 3 3 mA ICC3PS CKE ≤ VIL(MAX.), tCK = infinite, input signals are stable 2 2 mA Active Standby current in Nonpower Down Mode ICC3N – CKE ≥ VIH(MIN.), tCK ≥ tCK(MIN.), changed once in 3 cycles 25 25 mA ICC3NS CKE ≥ VIH(MIN.), tCK = infinite, input signals are stable – 15 15 mA Burst Operating current ICC4 Burst Length = full page tRC = infinite tCK ≥ tCK(MIN.), IO = 0 mA 2 banks activated 1 2 3 50 80 120 40 65 95 mA 6, 7 Auto (CBR) Refresh current ICC5 tRC ≥ tRC(MIN.) 1 2 3 75 95 115 60 75 90 mA mA mA 6, 7 Self Refresh ICC6 CKE ≤ 0.2 V – 2 2 mA 6, 7 Semiconductor Group 15 – CS = High 6 1998-10-01 HYB 39S16400/800/160AT-8/-10 16 MBit Synchronous DRAM AC Characteristics 8, 9 TA = 0 to 70 °C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 1 ns Parameter Symbol Limit Values -8 Unit Note -10 min. max. min. max. 8 12 24 – – – 10 15 30 – – – ns ns ns – – – 125 83 41 – – – 100 66 33 MHz MHz MHz – – – 7 8 21 – – – 8 9 27 ns ns ns Clock and Clock Enable tCK Clock Cycle time CAS Latency = 3 CAS Latency = 2 CAS Latency = 1 tCK System frequency CAS Latency = 3 CAS Latency = 2 CAS Latency = 1 tAC Clock Access time CAS Latency = 3 CAS Latency = 2 CAS Latency = 1 10 Clock High Pulse width tCH 3 – 3.5 – ns Clock Low Pulse width tCL 3 – 3.5 – ns Transition time (rise and fall) tT 1 30 1 30 ns Command Setup time tCS 2.5 – 3 – ns 11 Address Setup time tAS 2.5 – 3 – ns 11 Data In Setup time tDS 2.5 – 3 – ns 11 CKE Setup time tCKS 2.5 – 3 – ns 11 CKE Set-up time (Power down mode) tCKSP 2.5 – 3 – ns 11 CKE Set-up time (Self Refresh Exit) tCKSR 8 – 8 – ns Command Hold time tCH 1 – 1 – ns 11 Address Hold time tAH 1 – 1 – ns 11 Data In Hold time tDH 1 – 1 – ns 11 CKE Hold time tCKH 1 – 1 – ns 11 Setup and Hold Times Semiconductor Group 16 1998-10-01 HYB 39S16400/800/160AT-8/-10 16 MBit Synchronous DRAM AC Characteristics (cont’d) 8, 9 TA = 0 to 70 °C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 1 ns Parameter Symbol Limit Values -8 Unit Note -10 min. max. min. max. Common Parameters Row to Column Delay time tRCD 24 – 30 – ns Row Active time tRAS 36 120k 45 120k ns Precharge time tRP 24 – 30 – ns Row Cycle time tRC 60 120k 75 120k ns Bank to Bank delay time tRRD 16 – 20 – ns CAS to CAS delay time (same bank) tCCD 1 – 1 – CLK Refresh Cycle ns 13 64 ms 12 3 – ns 0 – ns Self Refresh Exit time tSREX 2 CLK + tRC Refresh period (4096 cycles) tREF – 64 – Data Out Hold time tOH 3 – Data Out to Low Impedance time tLZ 0 – Read Cycle 14 Data Out to High Impedance time tHZ CAS Latency = 3 CAS Latency = 2 CAS Latency = 1 DQM Data Out Disable Latency – – – 5 7 19 – – – 6 8 25 ns ns ns tDQZ 2 – 2 – CLK tDPL 1 2 – – 1 2 – – CLK CLK tDQW 0 – 0 – CLK Write Cycle Last Data-Input to Precharge (Write Recovery Latency) CL = 1, 2 CL = 3 DQM Write Mask Latency Semiconductor Group 17 1998-10-01 HYB 39S16400/800/160AT-8/-10 16 MBit Synchronous DRAM Notes 1. All voltages are referenced to VSS. 2. VIH may overshoot to VCC + 2.0 V for pulse width of < 4 ns with 3.3 V. VIL may undershoot to – 2.0 V for pulse width < 4.0 ns with 3.3 V. Pulse width measured at 50 % points with amplitude measured peak to DC reference. 3. Under all conditions VDDQ must be less than or equal to VDD. 4. The value of VREF may be selected by the user to provide optimum noise margin in the system. VREF has to be in the range between 0.43 × VDDQ and 0.47 × VDDQ and is expected to track variations in VDDQ. 5. VIH may overshoot to VDD, VDDQ + 1.2 V for pulse width < 5 ns and VIL may undershoot to VSS, VSSQ – 1.2 V for pulse width < 5 ns. 6. The specified values are valid when addresses are changed no more than three times during tRC(MIN.) and when No Operation commands are registered on every rising clock edge during tRC(MIN.). 7. The specified values are valid when data inputs (DQ’s) are stable during tRC(MIN.). 8. An initial pause of 200 µs is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. 9. AC timing tests for LV-TTL versions have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit shown in figure below. 10. If clock rising time is longer than 1 ns, (tT/2 – 0.5) ns has to be added to this parameter. 11. If tT is longer than 1 ns, a time (tT – 1) ns has to be added to this parameter. 12. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to “wake-up” the device. 13. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. 14. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels. Semiconductor Group 18 1998-10-01 HYB 39S16400/800/160AT-8/-10 16 MBit Synchronous DRAM t CH 2.4 V 0.4 V CLOCK t CL t SETUP tT t HOLD INPUT 1.4 V t AC t LZ t AC t OH OUTPUT 1.4 V t HZ SPT03404 Semiconductor Group 19 1998-10-01 HYB 39S16400/800/160AT-8/-10 16 MBit Synchronous DRAM Clock Frequency and Latency Parameter Symbol Speed Sort -8 Clock frequency max. tCK Clock Cycle time min. CAS latency Unit -10 125 83 100 66 MHz tCK 8 12 10 15 ns min. tAA 3 2 3 2 CLK Row to Column delay min. tRCD 3 2 3 2 CLK RAS latency min. tRL 6 4 6 4 CLK Row Active time min. tRAS 5 3 5 3 CLK 120 120 120 120 µs max. tRAS Row Precharge time min. tRP 3 2 3 2 CLK Row Cycle time min. tRC 8 5 8 5 CLK Last Data-In to Precharge (Write Recovery) min. tDPL 2 1 2 1 CLK Last Data-In to Active/Refresh min. tDPL + tRP 5 3 5 3 CLK Bank to Bank delay time min. tRRD 2 2 2 2 CLK CAS to CAS delay time min. tCCD 1 1 1 1 CLK Write latency fixed tWL 0 0 0 0 CLK DQM Write Mask latency fixed tDQW 0 0 0 0 CLK DQM Data Disable latency fixed tDQZ 2 2 2 2 CLK Clock Suspend latency fixed tCSL 1 1 1 1 CLK Semiconductor Group 20 1998-10-01 HYB 39S16400/800/160AT-8/-10 16 MBit Synchronous DRAM Package Outlines 0.8 15˚±5˚ 21x 0.8 = 16.8 3) 0.1 44x 0.5 ±0.1 11.76 ±0.2 0.2 M 44x 44 23 1 2.5 max 22 6 max 0.35 +0.1 -0.05 10.16 ±0.13 2) 0.15 +0.06 -0.03 1±0.05 15˚±5˚ 0.1 ±0.05 Plastic Package P-TSOPII-44 (400 mil, 0.8 mm lead pitch) Thin Small Outline Package, SMD 18.41 ±0.13 1) GPX05941 Index Marking 1) Does not include plastic or metal protrusion of 0.15 max per side Does not include plastic protrusion of 0.25 max per side 3) Does not include dambar protrusion of 0.13 max per side 2) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 21 Dimensions in mm 1998-10-01 HYB 39S16400/800/160AT-8/-10 16 MBit Synchronous DRAM 0.8 0.4 +- 0.05 0.1 0.5 ± 0.1 11.76 ± 0.2 0.2 M 50 1 10.16 ± 0.13 0.06 0.15 +- 0.0 3 0.1± 0.05 1± 0.05 1.2 max. Plastic Package P-TSOPII-50 (400 mil, 0.8 mm lead pitch) Thin Small Outline Package, SMD 50x 0.1 26 20.95 ± 0.131) 25 GPX05956 Index Marking 1) Does not include plastic or metal protrusion of 0.25 max. per side Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 22 Dimensions in mm 1998-10-01