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ESDALC6-4N4
ESD array with low capacitance
Datasheet  production data
Features
■
Stand-off voltage 7 V
■
Very low capacitance: 9.5 pF
■
Small package: 1.0 x 0.8 mm
■
Very thin package: 0.40 mm max
■
Low leakage current: 70 nA at 25 °C
µQFN-4L
Benefits
■
High ESD protection level
■
High integration
■
suitable for high speed interface
Figure 1.
Complies with the following standards
■
■
Functional diagram (top view)
I/O4
I/O1
IEC 61000-4-2:
– 15 kV (air discharge)
– 8 kV (contact discharge)
GND
MIL STD 883G- Method 3015-7: class3B:
– >25 kV (human body model)
I/O2
I/O3
Applications
Where transient overvoltage protection and
electrical overstress protection in sensitive
equipment is required, such as:
■
Communication systems
■
Cellular phone handsets and accessories
■
Video equipment
■
Portable equipment
Description
The ESDALC6-4N4 is monolithic array designed
to protect up to 4 lines against ESD transients. It
has been designed specifically for the protection
of the high speed interface of integrated circuits in
portable equipment and miniaturized electronics
devices. The µQFN-4L package minimizes PCB
space.
September 2012
This is information on a product in full production.
Doc ID 022191 Rev 2
1/11
www.st.com
11
Characteristics
1
ESDALC6-4N4
Characteristics
Table 1.
Absolute maximum ratings (Tamb = 25 °C)
Symbol
Parameter
Value
Unit
11
kV
27
W
VPP
ESD IEC 61000-4-2, level 4 (contact discharge)
PPP
Peak pulse power dissipation (8/20 µs)(1)
Ipp
Repetitive peak pulse current typical value (8/20 µs)
2.3
A
Tj
Maximum junction temperature
125
°C
-55 + 150
°C
Tstg
Tj initial = Tamb
Storage temperature range
1. For a surge greater than the maximum values, the diode will fail in short-circuit.
Figure 2.
Electrical characteristics (definitions)
I
IF
Symbol
VBR =
IRM =
VRM =
VCL =
IPP =
Parameter
Breakdown voltage
Leakage current @ VRM
Stand-off voltage
Clamping voltage
Peak pulse current
VF
VCL VBR
VRM
Slope: 1/Rd
Table 2.
V
IRM
IPP
Electrical characteristics (values, Tamb = 25 °C)
Symbol
Test conditions
Min.
Typ.
Max.
Unit
VBR
IR = 1 mA
IRM
VRM = 3 V
70
nA
VCL
Ipp = 1 A, 8/20 µs
10
V
11
pF
C
2/11
6
VR = 0 V, F = 1 MHz, Vosc = 30 mV
Doc ID 022191 Rev 2
V
9.5
ESDALC6-4N4
Figure 3.
Characteristics
Peak pulse power versus initial
junction temperature (typical
values, 8/20 µs waveform)
Figure 4.
Ppp (W)
100
60
Peak pulse power versus
exponential pulse duration (typical
values)
PPP(W)
50
40
30
10
20
10
tp (µs)
Tj (°C)
0
1
25
35
Figure 5.
45
55
65
75
85
95 105 115 125 135 145 155 165 175
Clamping voltage versus peak
pulse current (typical values,
8/20 µs waveform)
10
Figure 6.
1000
Forward voltage drop versus peak
forward current (typical values)
IFM(A)
IPP(A)
10.0
100
2.0
1.0
1.0
VCL (V)
VFM(V)
0.1
7
8
Figure 7.
10.0
9
10
11
12
Junction capacitance versus
reverse voltage applied
(typical values)
0.0
0.8
1.3
Figure 8.
1.8
2.3
Leakage current versus junction
temperature (typical values)
IR (nA)
C(pF)
10.00
F=1 MHz
Vosc =30mVRMS
Vr=0V
Tj=25 °C
9.0
8.0
VR=VRM=3V
7.0
6.0
5.0
1.00
4.0
3.0
2.0
1.0
T j (°C)
VR(V)
0.0
0
1
2
3
4
5
6
0.10
25
Doc ID 022191 Rev 2
35
45
55
65
75
85
3/11
Characteristics
Figure 9.
ESDALC6-4N4
ESD response to IEC 6100-4-2
(+8 kV contact discharge) on each
channel
Figure 10. ESD response to IEC 6100-4-2
(-8 kV contact discharge) on each
channel
5 V/div
5 V/div
20 ns/div
Figure 11. S21 attenuation measurement
0.00
20 ns/div
Figure 12. Analog crosstalk measurement
dB
0.00
dB
-10.00
-5.00
-20.00
-30.00
-10.00
-40.00
-15.00
-50.00
-60.00
-20.00
-70.00
-80.00
-25.00
-90.00
F/Hz
-30.00
100.0 k
4/11
F/Hz
-100.00
1.0 M
10.0 M
100.0 M
1.0 G
Doc ID 022191 Rev 2
100.0k
1.0M
10.0M
100.0M
1.0G
ESDALC6-4N4
2
Ordering information scheme
Ordering information scheme
Figure 13. Ordering information scheme
ESDA LC
6
4N4
ESD array
Low capacitance
Breakdown voltage
6 = 6 Volts min
Package
4 = 4 lines
N4 = µQFN-4L
Doc ID 022191 Rev 2
5/11
Package information
3
ESDALC6-4N4
Package information
●
Epoxy meets UL94, V0
●
Lead-free package
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
µQFN-4L dimensions
Table 3.
Dimensions
Ref.
D
D2
e
2
Index
area
1
E2
E
L
3
4
L1
b
Millimeters
Inches
Min.
Typ.
Max.
Min.
Typ.
Max.
A
0.31
0.38
0.40
0.012 0.015 0.016
A1
0.00
0.02
0.05
0.00
b
0.10
0.15
0.20
0.004 0.006 0.008
D
0.70
0.80
0.90
0.028 0.031 0.035
D2
0.50
0.58
0.65
0.020 0.023 0.026
e
0.35
0.40
0.45
0.014 0.016 0.018
E
0.90
1.00
1.10
0.035 0.039 0.043
E2
0.15
0.20
0.25
0.006 0.008 0.010
L
0.18
0.23
0.28
0.007 0.009 0.011
L1
0.00
--
0.05
0.00
0.0008 0.002
A
A1
--
0.002
Figure 14. Footprint dimensions (in mm) Figure 15. Marking
0.4
0.43
0.2
0.58
N
0.17
1.4
0.18
0.58
Note:
6/11
Product marking may be rotated by multiples of 90° for assembly plant differentiation. In no
case should this product marking be used to orient the component for its placement on a
PCB. Only pin 1 mark is to be used for this purpose.
Doc ID 022191 Rev 2
ESDALC6-4N4
Package information
Figure 16. Tape and reel specifications
Dot identifying Pin A1 location
2.0
Ø 1.55
4.0
3.5
N
N
N
0.89
N
N
N
N
8.0
1.07
1.75
0.22
2.0
0.63
All dimensions are typical values in mm
User direction of unreeling
Doc ID 022191 Rev 2
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Recommendation on PCB assembly
ESDALC6-4N4
4
Recommendation on PCB assembly
4.1
Stencil opening design
Reference design
●
Stencil opening thickness: 100 µm
●
Stencil opening for leads: Opening to footprint ratio is 100%.
Figure 17. Recommended stencil window position
430 µm
T=100 µm and opening
ratio is 100%
180 µm
580 µm
200 µm
Footprint
Stencil window
Footprint
4.2
4.3
8/11
Solder paste
1.
Halide-free flux qualification ROL0 according to ANSI/J-STD-004.
2.
“No clean” solder paste is recommended.
3.
Offers a high tack force to resist component movement during high speed.
4.
Solder paste with fine particles: powder particle size is 20-45 µm.
Placement
1.
Manual positioning is not recommended.
2.
It is recommended to use the lead recognition capabilities of the placement system, not
the outline centering.
3.
Standard tolerance of ± 0.05 mm is recommended.
Doc ID 022191 Rev 2
ESDALC6-4N4
4.4
4.5
Recommendation on PCB assembly
4.
3.5 N placement force is recommended. Too much placement force can lead to
squeezed out solder paste and cause solder joints to short. Too low placement force
can lead to insufficient contact between package and solder paste that could cause
open solder joints or badly centered packages.
5.
To improve the package placement accuracy, a bottom side optical control should be
performed with a high resolution tool.
6.
For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is
recommended during solder paste printing, pick and place and reflow soldering by
using optimized tools.
PCB design preference
1.
To control the solder paste amount, the closed via is recommended instead of open
vias.
2.
The position of tracks and open vias in the solder area should be well balanced. The
symmetrical layout is recommended, in case any tilt phenomena caused by
asymmetrical solder paste amount due to the solder flow away.
Reflow profile
Figure 18. ST ECOPACK® recommended soldering reflow profile for PCB mounting
240-245 °C
Temperature (°C)
250
-2 °C/s
2 - 3 °C/s
60 sec
(90 max)
200
-3 °C/s
150
-6 °C/s
100
0.9 °C/s
50
Time (s)
0
Note:
30
60
90
120
150
180
210
240
270
300
Minimize air convection currents in the reflow oven to avoid component movement.
Doc ID 022191 Rev 2
9/11
Ordering information
5
ESDALC6-4N4
Ordering information
Table 4.
Ordering information
Order code
Marking
Package
Weight
Base qty
Delivery mode
ESDALC6-4N4
N(1)
µQFN-4L
1.17 mg
10000
Tape and reel
1. The marking can be rotated by multiples of 90° to differentiate assembly location
6
Revision history
Table 5.
10/11
Document revision history
Date
Revision
Changes
06-Sep-2011
1
Initial release.
25-Sep-2012
2
Updated ECOPACK statement.
Doc ID 022191 Rev 2
ESDALC6-4N4
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Doc ID 022191 Rev 2
11/11
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