SmartFusion2 and IGLOO2 CoreJESD204BRX and CoreJESD204BTX Interoperability TR0022 Test Report June 2016 Table of Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Hardware Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 AD9250 Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ISLA224S Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DAC1658 Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ADC34J44 Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Deterministic Latency Test Setup for ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Deterministic Latency Test Setup for DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Interoperability Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 AD9250 Interoperability Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Test1: Data Link Layer - Code Group Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Test2: Data Link Layer - Initial Lane Alignment Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Test3: Receiver Transport Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Test4: Descrambling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Test5: Deterministic Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 ISLA224S Interoperability Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Test1: Data Link Layer - Code Group Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Test2: Data Link Layer -Initial Lane Alignment Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Test3: Receiver Transport Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Test4: Descrambling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Test5: Deterministic Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DAC1658 Interoperability Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Test1: Data Link Layer - Code Group Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Test2: Data Link Layer -Initial Lane Alignment Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Test3: Receiver Transport Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Test4: Descrambling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Test5: Deterministic latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ADC34J44 Interoperability Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Test1: Data Link Layer - Code Group Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Test2: Data Link Layer - Initial Lane Alignment Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Test3: Receiver Transport Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Test4: Descrambling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Test5.1: Deterministic Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Test5.2: Deterministic Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Revision 2 2 SmartFusion2 and IGLOO2 CoreJESD204BRX and CoreJESD204BTX Interoperability Introduction Microsemi provides solutions for interfacing to analog-to-digital converter (ADC) and digital -to-analog converter (DAC) devices using the JESD204B JEDEC standard. These solutions are provided as DirectCore IPs - CoreJESD204BRX and CoreJESD204BTX. Both of these are soft IPs interfacing to the high-speed serial interfaces (SERDESIF) of the SmartFusion®2 system-on-chip (SoC) field programmable gate array (FPGA) and IGLOO®2 FPGA devices. This interoperability report gives the information that was obtained while working with third party ADC and DAC devices. The interoperability test results describe the JESD204B link parameters, hardware test setup, equipment used, and final test report of Microsemi DirectCores - CoreJESD204BRX and CoreJESD204BTX. References • CoreJESD204BRX v2.5 Handbook • CoreJESD204BTX v2.0 Handbook • UG0447: SmartFusion2 and IGLOO2 FPGA High Speed Serial Interfaces User Guide • JESD204B - Serial Interface for Data Converters (Revision of JESD204B, July 2011). Date: January 2012 (www.jedec.org) • AD9250 Datasheet from Analog Devices (www.analog.com) • ISLA224S Datasheet from Intersil (www.intersil.com) • DAC1658 Datasheet from IDT (www.idt.com) • ADC34J44 Datasheet from Texas Instruments (www.ti.com) Scope The interoperability test results described in this report are limited to the JESD204B link. To develop a reference platform to work with JESD204B and third party ADC and DAC devices, other IP was used in the SmartFusion2 based design. This report describes the hardware setup used for interoperability testing and reporting the test results of the JESD204B link. The SmartFusion2 and IGLOO2 JESD204B solution supports link widths of x1, x2, and x4 up to 3.2 Gbps per lane using subclass 0, 1, and 2. Table 1 shows the configuration for the devices tested. Table 1 • Configuration for the Devices Tested Device Link Rate Link Width Subclass Analog Devices - AD9250 2.45 Gbps x2 0, 1 Intersil - ISLA224S25 2.5 Gbps x2 0, 2 IDT - DAC1658D1G5NLGA 2.5 Gbps x2 0, 1 Texas Instruments - ADC34J44 2.5 Gbps x4 0, 1, 2 Revision 2 3 SmartFusion2 and IGLOO2 CoreJESD204BRX and CoreJESD204BTX Hardware Setup The interoperability testing is carried out on the SmartFusion2 Advanced Development Kit (MS2150ADV-KIT) and the FMC cards from the ADC and DAC vendors. The design for interoperability is developed using the Libero® SoC tool by instantiating the CoreJESD204BRX IP and CoreJESD204BTX IP cores in SmartDesign. Identify Debugger, JESD204B Demo GUI and serial terminal programs (for example, RealTerm) are used for the interoperability testing and for the ADC register configuration. CoreJESD204BRX IP is configured in JESD204B Subclass 0, Subclass 1 and Subclass 2 modes. CoreJESD204BTX IP is configured in JESD204B Subclass 0, Subclass 1 modes. AD9250 Setup AD9250 ADC is operated in two converters and two-lane mode. Each lane is operated in 2.45 Gbps mode. The fabric logic and SERDES blocks are operated with 122.8 MHz frequency. Figure 1 shows the hardware setup for the interoperability testing with AD9250 Figure 1 • Hardware Setup for Interoperability Testing with AD9250 4 R e vi s i o n 2 SmartFusion2 and IGLOO2 CoreJESD204BRX and CoreJESD204BTX ISLA224S Setup ISLA224S ADC is operated in two converters and two-lane mode. Each lane is operated in 2.5 Gbps mode. The fabric logic and SERDES blocks are operated with 125 MHz frequency. Figure 2 shows the hardware setup for the interoperability testing with ISLA224S. Figure 2 • Hardware Setup for Interoperability Testing with ISLA224S Revision 2 5 SmartFusion2 and IGLOO2 CoreJESD204BRX and CoreJESD204BTX DAC1658 Setup DAC1658 DAC is operated in two converters, two-lane mode and the interpolation factor is two. Each lane is operated in 2.5 Gbps mode. The fabric logic and SERDES blocks are operated with 125 MHz frequency. Figure 3 shows the hardware setup for the interoperability testing with DAC1658. Figure 3 • Hardware Setup for Interoperability Testing with DAC1658 6 R e vi s i o n 2 SmartFusion2 and IGLOO2 CoreJESD204BRX and CoreJESD204BTX ADC34J44 Setup ADC34J44 ADC is operated in four converters and four-lane mode. Each lane is operated at 2.5 Gbps mode. The fabric logic and SerDes blocks are operated at 125 MHz frequency. Figure 4 hardware setup for interoperability testing with ADC34J44. Figure 4 • Hardware Setup for Interoperability Testing with ADC34J44 Revision 2 7 SmartFusion2 and IGLOO2 CoreJESD204BRX and CoreJESD204BTX Deterministic Latency Test Setup for ADC A pulse signal was fed into the analog input of the ADC and channel A of an oscilloscope using a pulse generator. The most significant bit (MSB) of COREJESD204BRX DATA_OUT was routed to the BB_GPIO11 (FPGA pin number: P8) on the SmartFusion2 Advanced Development Kit. This was connected to the channel B on the oscilloscope. With this setup the latency between the pulse entering the ADC and the MSB toggled at the output of the COREJESD204BRX IP can be measured. Figure 5 shows the setup used to measure the deterministic latency. 3XOVH*HQHUDWRU $QDORJ,QSXWWR$'& 2VFLOORVFRSH $'& &KDQQHO$ )0&&RQQHFWRU &KDQQHO% 6)$GYDQFHG 'HYHORSPHQW.LW /DWHQF\ 06%RI6DPSOH'DWD Figure 5 • Deterministic Latency Setup - ADC Deterministic Latency Test Setup for DAC A pulse signal was generated from the FPGA fabric and was fed to the DAC converter. The MSB of the generated pulse is routed to the BB_GPIO6 (FPGA pin number: P7) on the SmartFusion2 Advanced Development Kit. This was connected to the channel A on the oscilloscope. The analog output from DAC is connected to channel B on the oscilloscope. With this setup the latency between the pulse sent from CoreJESD204BTX and the pulse observed at the DAC output can be measured. Figure 6 shows the test setup used to measure the deterministic latency. $QDORJ2XWSXWIURP '$& 2VFLOORVFRSH '$& &KDQQHO% )0&&RQQHFWRU &KDQQHO$ 6)$GYDQFHG 'HYHORSPHQW.LW 06%RI7UDQVPLWWHG'DWD Figure 6 • Deterministic Latency Setup - DAC 8 R e vi s i o n 2 /DWHQF\ SmartFusion2 and IGLOO2 CoreJESD204BRX and CoreJESD204BTX Interoperability Tests CoreJESD204BRX, AD9250, ISLA224S, and ADC34J44 are configured for interoperability testing, as shown in Table 2. Table 2 • JESD204B Parameter Settings Parameter CoreJESD204 Analog Devices Intersil BRX Value AD9250 ISLA224S Texas Instruments ADC34J44 Description SCR 0/1 0x1/0x0 0x1/0x0 0x1/0x0 Both scramble enable/disable L 2 0x1 0x1 0x03 Number of lanes F 2 0x1 0x1 0x1 Number of octets per frame K 32 0x1F 0x1F 0x08 Number of frames per multi-frame M 2 0x1 0x1 0x03 Number of converters CS 0 0x0 0x0 0x0 Control bits per sample N 14 0xD 0xD 0xD Sample resolution N' 16 0xF 0xF 0xF Sample envelope S 1 0x0 0x0 0x0 No of samples per converter per frame HD 0 0x0 0x0 0x0 High density mode CF 0 0x0 0x0 0x0 Control bits per frame 0x0/0x1 0x0/0x2 0x0/0x1/0x2 Subclass0/Subclass1/Subclass2 SUBCLASSV 0/1/2 CoreJESD204BTX and DAC1658 are configured for interoperability testing, as shown in Table 3. Table 3 • JESD204B Parameter Settings Parameter CoreJESD204BTX Value IDT DAC1658 Description SCR 0/1 0x1 / 0x0 Scramble enable or disable L 2 0x1 Number of lanes F 2 0x1 Number of octets per frame K 32 0x1F Number of frames per multi-frame M 2 0x1 Number of converters CS 0 0x0 Control bits per sample N 16 0xF Sample resolution N' 16 0xF Sample envelope S 1 0x0 No of samples per converter per frame HD 0 0x0 High density mode CF 0 0x0 Control bits per frame SUBCLASSV 0/1 0x0/0x1 Subclass0/Subclass1/Subclass2 The following tests are performed for the interoperability report: • Test1: Data Link Layer - Code Group Synchronization • Test2: Data Link Layer - Initial Lane alignment sequence • Test3: Receiver Transport Layer • Test4: Descrambling • Test5: Deterministic latency Revision 2 9 SmartFusion2 and IGLOO2 CoreJESD204BRX and CoreJESD204BTX AD9250 Interoperability Tests Test1: Data Link Layer - Code Group Synchronization On link startup, the receiver issues a synchronization request and the transmitter emits comma characters /K/=/K28.5/. Identify debugger is used to monitor the operation of the receiver data link layer. Table 4 shows the data link layer - code group synchronization test results. Table 4 • Data Link Layer - Code Group Synchronization Test Results Test Case Objective Passing Criteria Result AD1.1 Check if the receiver CoreJESD204BRX _0 asserts SYNC_N signal SYNC_N signal is observed in when the link is down Identify Debugger SYNC_N goes low Passed AD1.2 Check if SYNC_N request is deasserted after the correct reception of at least four successive /K/ characters CoreJESD204BRX _0 DATA_OUT[31:16], DATA_OUT[15:0],SYNC_N signals are observed in Identify Debugger K28.5 or /K/ character (0xBC) is observed on DATA_OUT and SYNC_N Passed Check the full code group synchronization at receiver after the correct reception of another four 8B/10B characters CoreJESD204BRX _0 CGS error not asserted DATA_OUT[31:16], DATA_OUT[15:0], SYNC_N,CGS_ERR[1:0] signals are observed in Identify Debugger AD1.3 Description is deasserted after the correct reception of at least four successive /K/ characters. Passed Test2: Data Link Layer - Initial Lane Alignment Sequence Table 5 shows the data link layer - initial lane alignment sequence test results. Table 5 • Data Link Layer-Initial Lane Alignment Sequence Test Results Test Case Objective Description Passing Criteria AD2.1 Check if the ILAS phase CoreJESD204BRX _0 Multi-frame starts with 0x1C Passed starts after the CGS DATA_OUT[31:16], and is aligned with phase DATA_OUT[15:0] SOMF_U[1:0] SOMF_U[1:0],SOMF_L[1:0], SOF_U[1:0],SOF_L[1:0] signals are observed in Identify Debugger AD2.2 Check the JESD CoreJESD204BRX _0 configuration data in the DATA_OUT[31:16], second multi-frame DATA_OUT[15:0] SOMF_U[1:0],SOMF_L[1:0], SOF_U[1:0],SOF_L[1:0], LINK_CD_ERROR[1:0] signals are observed in Identify Debugger Revision 2 Result Observe the second multi- Passed frame that starts with 0x1C followed by 0x9C and JESD204B configuration data 10 SmartFusion2 and IGLOO2 CoreJESD204BRX and CoreJESD204BTX Test3: Receiver Transport Layer Table 6 shows the receiver transport layer test results. Table 6 • Receiver Transport Layer Test Results Test Case Objective Description Passing Criteria Result AD3.1 Check data integrity in test mode ADC is configured in PRBS test mode. RX_PRBS_16 O_bad signal not Passed asserted PRBS checker in the FPGA fabric checks for data reliability. CoreJESD204BRX _0 DATA_OUT[31:16], DATA_OUT[15:0] RX_PRBS_16 O_error[3:0],O_bad signals are observed in Identify Debugger AD3.2 Check data integrity in normal mode ADC is configured in normal Received signal correlates with the Passed mode. input signal given for ADC CoreJESD204BRX _0 sampling. DATA_OUT[31:16], DATA_OUT[15:0] signals are observed in Identify Debugger Test4: Descrambling Scrambler is enabled in ADC and descrambler is enabled in CoreJESD204BRX IP. Table 7 shows the descrambling test results. Table 7 • Descrambling Test Results Test Case Objective Description Passing Criteria Result AD4.1 Check descrambler functionality ADC is configured in PRBS test mode. RX_PRBS_16 O_bad signal should not be asserted Passed PRBS checker in the FPGA fabric checks for data reliability. CoreJESD204BRX _0 DATA_OUT[31:16], DATA_OUT[15:0] RX_PRBS_16 O_error[3:0], O_bad signals are observed in Identify Debugger 11 R e visio n 2 SmartFusion2 and IGLOO2 CoreJESD204BRX and CoreJESD204BTX Test5: Deterministic Latency CoreJESD204BRX IP is configured in Subclass 1 mode and AD9250 is configured in different LMF modes. Table 8 shows the CoreJESD204BRX IP parameter settings for different ADC modes. Table 8 • CoreJESD204BRX IP Parameter Settings for different ADC Modes ADC Mode M L F K 11 1 1 2 32 21 2 1 4 32 22 2 2 2 32 Table 9 shows the JESD204B deterministic latency measurement test results. Table 9 • JESD204B Deterministic Latency Measurement Test Results Test Case Objective Description Passing Criteria Result AD5.1 Check LMFC alignment CoreJESD204BRX _0 clkgen_lmfc and SYSREF_IN signals are observed in Identify Debugger SYSREF_IN aligned with clkgen_lmfc Passed AD5.2 SYSREF CoreJESD204BRX _0 c2l_mf_phase and SYSREF_IN signals are observed in Identify Debugger LMFC counter restarts after the SYSREF_IN capture Passed Latency fixed for multiple runs (between the FPGA resets/link resets) Passed capture AD5.3 Check the latency A single pulse input is applied to the ADC and the oscilloscope channel A using 2-port splitter. Core output MSB is connected to the oscilloscope channel B. The delay between captured pulses on channel A and Channel B is measured. AD5.4 Check the data latency during user data phase Check if the data latency is fixed during the user data phase. CoreJESD204BRX _0 The ramp pattern is seen without Passed distortion DATA_OUT[31:16], DATA_OUT[15:0] signals are observed in Identify Debugger Revision 2 12 SmartFusion2 and IGLOO2 CoreJESD204BRX and CoreJESD204BTX ISLA224S Interoperability Tests Test1: Data Link Layer - Code Group Synchronization When the link starts, the receiver issues a synchronization request and the transmitter emits comma characters /K/=/K28.5/. The receiver data link layer operation is monitored by Identify Debugger. Table 10 shows the data link layer - code group synchronization test results. Table 10 • Data Link Layer - Code Group Synchronization Test Results Test Case Objective ISL1.1 Description Passing Criteria Result Check if the receiver CoreJESD204BRX _0 asserts SYNC_N SYNC_N signal is observed in signal when the link is Identify Debugger down SYNC_N goes low Passed ISL1.2 Check if SYNC_N request is deasserted after the correct reception of at least four successive /K/ characters CoreJESD204BRX _0 DATA_OUT[31:16], DATA_OUT[15:0],SYNC_N signals are observed in Identify Debugger K28.5 or /K/ character (0xBC) Passed is observed on DATA_OUT and SYNC_N is deasserted after the correct reception of at least four successive /K/ characters. ISL1.3 Check full code group synchronization at the receiver after the correct reception of another four 8B/10B characters CoreJESD204BRX _0 CGS error not asserted DATA_OUT[31:16], DATA_OUT[15:0], SYNC_N,CGS_ERR[1:0] signals are observed in Identify Debugger Passed Test2: Data Link Layer -Initial Lane Alignment Sequence Table 11 shows the data link layer - initial lane alignment sequence test results. Table 11 • Data Link Layer - Initial Lane Alignment Sequence Test Results Test Case Objective Description ISL2.1 Check if the ILAS phase starts after the CGS phase CoreJESD204BRX _0 Multi-frame starts with 0x1C DATA_OUT[31:16], and is aligned with DATA_OUT[15:0] SOMF_U[1:0] SOMF_U[1:0],SOMF_L[1:0], SOF_U[1:0],SOF_L[1:0] signals are observed in Identify Debugger Passed ISL2.2 Check the JESD configuration data in the second multiframe CoreJESD204BRX _0 DATA_OUT[31:16], DATA_OUT[15:0] SOMF_U[1:0],SOMF_L[1:0], SOF_U[1:0],SOF_L[1:0], LINK_CD_ERROR[1:0] signals are observed in Identify Debugger Passed 13 Passing Criteria R e visio n 2 Observe the second multiframe that starts with 0x1C followed by 0x9C and JESD204B configuration data Result SmartFusion2 and IGLOO2 CoreJESD204BRX and CoreJESD204BTX Test3: Receiver Transport Layer Table 12 shows the receiver transport layer test results. Table 12 • Receiver Transport Layer Test Results Test Case Objective Description Passing Criteria Result ISL3.1 Check data integrity ADC is configured in PRBS RX_PRBS_16 O_bad signal not Passed in test mode test mode. PRBS checker in asserted. the FPGA fabric checks for data reliability. CoreJESD204BRX _0 DATA_OUT[31:16], DATA_OUT[15:0] RX_PRBS_16 O_error[3:0], O_bad signals are observed in Identify Debugger ISL3.2 Check data integrity ADC is configured in normal Received signal correlates with the Passed in normal mode mode. input signal given for ADC CoreJESD204BRX _0 sampling. DATA_OUT[31:16], DATA_OUT[15:0] signals are observed in Identify Debugger Test4: Descrambling Scrambler is enabled in ADC and descrambler is enabled in CoreJESD204BRX IP. Table 13 shows the descrambling test results. Table 13 • Descrambling Test Results Test Case Objective Description Passing Criteria ISL4.1 Check descrambler ADC is configured in PRBS RX_PRBS_16 O_bad signal not functionality test mode. asserted Result Passed PRBS checker in the FPGA fabric checks for data reliability. CoreJESD204BRX _0 DATA_OUT[31:16], DATA_OUT[15:0] RX_PRBS_16 O_error[3:0], O_bad signals are observed in Identify Debugger Revision 2 14 SmartFusion2 and IGLOO2 CoreJESD204BRX and CoreJESD204BTX Test5: Deterministic Latency CoreJESD204BRX IP is configured in Subclass 2 mode and ISLAS224S is configured in L=2 and M=2 modes. Table 14 shows the deterministic latency test results. Table 14 • Deterministic Latency Test Results Test Case Objective Description Passing Criteria Result ISL5.1 SYNC_N capture CoreJESD204BRX _0 c2l_mf_phase and SYNC_N signals are observed in Identify Debugger LMFC counter restarts after the Passed SYNC_N capture ISL5.2 Check the latency A single pulse input is applied to the ADC and the oscilloscope channel A using 2-port splitter. Latency fixed for multiple runs Passed (between the FPGA resets/link resets) Core output MSB is connected to the oscilloscope channel B. The delay between captured pulses on channel A and Channel B is measured. ISL5.3 Check the data Check if the data latency is fixed latency during during the user data phase. user data phase CoreJESD204BRX _0 DATA_OUT[31:16], DATA_OUT[15:0] signals are observed in Identify Debugger The ramp pattern is seen without distortion Passed DAC1658 Interoperability Tests Test1: Data Link Layer - Code Group Synchronization When the link starts, the receiver issues a synchronization request and the transmitter emits comma characters /K/=/K28.5/. The transmitter data link layer operation is monitored by Identify Debugger. Table 15 shows the data link layer - code group synchronization test results. Table 15 • Data Link Layer - Code Group Synchronization Test Results Test Case Objective Description IDT1.1 Check if SYNC_Request is deasserted on SYNC_N assertion. CoreJESD204BTX _0 SYNC_request goes low SYNC_request signal is observed in Identify Debugger Passed IDT1.2 Check if at least four successive /K/ characters are transmitted on SYNC_N assertion CoreJESD204BTX _0 EPCS_0_TX_DATA[19:0], EPCS_1_TX_DATA[19:0], SYNC_N signals are observed in Identify Debugger At least four K28.5 or /K/ characters are observed on EPCS_0_TX_DATA, EPCS_1_TX_DATA, on assertion of SYNC_N Passed IDT1.3 Check full code group synchronization at the transmitter after the correct transmission of another four 8B/10B characters CoreJESD204BTX _0 TX_STATE[1:0] signal is observed in Identify Debugger Check the DAC register CS_STATE_LNX (address 00EDh). CoreJESD204BTX TX_STATE Passed changes from SYNC_ST(0x00) to INIT_LANE_ST (0x01). DAC register CS_STATE_LNX is in CS_DATA (0x02) state. 15 Passing Criteria R e visio n 2 Result SmartFusion2 and IGLOO2 CoreJESD204BRX and CoreJESD204BTX Test2: Data Link Layer -Initial Lane Alignment Sequence Table 16 shows the data link layer - initial lane alignment sequence test results. Table 16 • Data Link Layer - Initial Lane Alignment Sequence Test Results Test Case Objective Description Passing Criteria IDT2.1 Check the ILAS phase 1. CoreJESD204BTX _0 1. Observe the /R/, /A/, /Q/ in Passed EPCS_0_TX_DATA[19:0], the correct order as per EPCS_1_TX_DATA[19:0], ILAS. Signals are observed in 2. The flags /R/, /A/, /Q/ and Identify Debugger. /K/ set in DAC K28 2. Check DAC K28 registers. registers IDT2.2 Check the JESD configuration data IDT2.3 Check if ILA phase is 1. CoreJESD204BTX _0 TX_STATE[1:0] Signal is completed successfully observed in Identify Debugger. Check if the DAC has received DAC link configuration data the expected configuration matches with data. CoreJESD204BTX link configuration data 2. Check if the DAC has achieved ILA. 1. CoreJESD204BTX TX_STATE changes from INIT_LANE_ST (0x01) to DATA_ENC_ST (0x02). Result Passed Passed 2. In DAC ila_rcv_flag goes high. Test3: Receiver Transport Layer Table 17 shows the receiver transport layer test results. Table 17 • Receiver Transport Layer Test Results Test Case Objective Description Passing Criteria Result IDT3.1 Check the data phase Check if the expected waveform Observe the expected waveform is obtained at the DAC outputs. on the scope. Passed IDT3.2 Check the data rate CoreJESD204BTX transfer data Observe the expected waveform at 2.5 Gbps per lane for on the scope. LMF=222. Passed Test4: Descrambling Scrambler is enabled in ADC and descrambler is enabled in CoreJESD204BTX IP. Table 18 shows the descrambling test results. Table 18 • Descrambling Test Results Test Case IDT4.1 Objective Description Passing Criteria Check the scrambler functionality Enable scrambler and check data Observe the expected waveform at the output. on the scope. Revision 2 Result Passed 16 SmartFusion2 and IGLOO2 CoreJESD204BRX and CoreJESD204BTX Test5: Deterministic latency CoreJESD204BTX IP is configured in Subclass 1 mode and DAC1658 is configured in LMF = 222 mode and interpolation factor = 2. Table 19 shows the deterministic latency test results. Table 19 • Deterministic Latency Test Results Test Case Objective Description Passing Criteria IDT5.1 Check the LMFC alignment CoreJESD204BTX _0 SYSREF_IN aligned with clkgen_lmfc and SYSREF_IN signals clkgen_lmfc are observed in Identify Debugger IDT5.2 SYSREF capture CoreJESD204BTX _0 c2l_mf_phase and SYSREF_IN signals are observed in Identify Debugger IDT5.3 Check the latency A single pulse input generated in FPGA is sent to the DAC and the oscilloscope channel A. Result Passed LMFC counter restarts after the Passed SYSREF_IN capture Latency fixed for every link reset. (SYNC_N ON/OFF). Passed The DAC output is connected to oscilloscope channel B. The delay between captured pulses on channel A and Channel B is measured. ADC34J44 Interoperability Tests Test1: Data Link Layer - Code Group Synchronization On link startup, the receiver issues a synchronization request and the transmitter emits comma characters /K/=/K28.5/. Identify the debugger that is used to monitor the operation of the receiver data link layer. Table 20 shows the data link layer - code group synchronization test results. Table 20 • Data Link Layer - Code Group Synchronization Test Results Test Case Objective TI_ADC1.1 Passing Criteria Result Check if the receiver CoreJESD204BRX _0 asserts SYNC_N signal SYNC_N signal is observed in when the link is down Identify Debugger SYNC_N goes low Passed TI_ADC1.2 Check if SYNC_N request is deasserted after the correct reception of at least four successive /K/ characters CoreJESD204BRX _0 DATA_OUT[63:48], DATA_OUT[47:32], DATA_OUT[31:16], DATA_OUT[15:0],SYNC_N signals are observed in Identify Debugger K28.5 or /K/ character Passed (0xBC) is observed on DATA_OUT and SYNC_N is deasserted after the correct reception of at least four successive /K/ characters. TI_ADC1.3 Check the full code group synchronization at receiver after the correct reception of another four 8B/10B characters CoreJESD204BRX _0 CGS error not asserted DATA_OUT[63:48], DATA_OUT[47:32], DATA_OUT[31:16], DATA_OUT[15:0], SYNC_N,CGS_ERR[1:0] signals are observed in Identify Debugger 17 Description R e visio n 2 Passed SmartFusion2 and IGLOO2 CoreJESD204BRX and CoreJESD204BTX Test2: Data Link Layer - Initial Lane Alignment Sequence Table 21 shows the data link layer - initial lane alignment sequence test results. Table 21 • Data Link Layer-Initial Lane Alignment Sequence Test Results Test Case Objective Description Passing Criteria Result TI_ADC2.1 Check if the ILAS phase CoreJESD204BRX _0 Multi-frame starts with 0x1C Passed starts after the CGS DATA_OUT[63:48], and is aligned with phase DATA_OUT[47:32], SOMF_U[3:0] DATA_OUT[31:16], DATA_OUT[15:0] SOMF_U[3:0],SOMF_L[3:0], SOF_U[1:0],SOF_L[1:0] signals are observed in Identify Debugger TI_ADC2.2 Check the JESD CoreJESD204BRX _0 configuration data in the DATA_OUT[63:48], second multi-frame DATA_OUT[47:32], DATA_OUT[31:16], DATA_OUT[15:0] SOMF_U[3:0],SOMF_L[3:0], SOF_U[3:0],SOF_L[3:0], LINK_CD_ERROR[3:0] signals are observed in Identify Debugger Observe the second Passed multi-frame that starts with 0x1C followed by 0x9C and JESD204B configuration data Test3: Receiver Transport Layer Table 22 shows the receiver transport layer test results. Table 22 • Receiver Transport Layer Test Results Test Case Objective Description Passing Criteria TI_ADC3.1 Check data integrity in ADC is configured in PRBS test mode transport layer test mode Result Observe the DATA_OUT for PRBS Passed pattern CoreJESD204BRX _0 DATA_OUT[63:48], DATA_OUT[47:32], DATA_OUT[31:16], DATA_OUT[15:0] signals are observed in Identify Debugger TI_ADC3.2 Check data integrity in ADC is configured in normal Received signal correlates with the Passed normal mode mode input signal given for ADC CoreJESD204BRX _0 sampling. DATA_OUT[63:48], DATA_OUT[47:32], DATA_OUT[31:16], DATA_OUT[15:0] signals are observed in Identify Debugger Revision 2 18 SmartFusion2 and IGLOO2 CoreJESD204BRX and CoreJESD204BTX Test4: Descrambling Scrambler is enabled in ADC and descrambler is enabled in the CoreJESD204BRX IP. Table 23 shows the descrambling test results. Table 23 • Descrambling Test Results Test Case Objective Description Passing Criteria Result TI_ADC4.1 Check descrambler functionality ADC is configured in PRBS Transport layer test mode Observe the DATA_OUT for PRBS pattern Passed CoreJESD204BRX _0 DATA_OUT[63:48], DATA_OUT[47:32], DATA_OUT[31:16], DATA_OUT[15:0] signals are observed in Identify Debugger Test5.1: Deterministic Latency The CoreJESD204BRX IP is configured in subclass 1 mode and ADC34J44 is configured in subclass 1 mode with parameters LMFK = 4429. Table 24 shows the JESD204B deterministic latency measurement test results. Table 24 • JESD204B Deterministic Latency Measurement Test Results Test Case Objective Description Passing Criteria Result TI_ADC5.1.1 Check LMFC alignment CoreJESD204BRX _0 clkgen_lmfc and SYSREF_IN signals are observed in Identify Debugger SYSREF_IN is aligned with clkgen_lmfc Passed TI_ADC5.1.2 SYSREF CoreJESD204BRX _0 LMFC counter restarts after the c2l_mf_phase and SYSREF_IN SYSREF_IN capture signals are observed in Identify Debugger capture TI_ADC5.1.3 Check latency Passed A single pulse input is applied to Latency is fixed for multiple runs Passed (between the FPGA resets/link ADC and the oscilloscope channel A using 2-port splitter. resets) Core output MSB is connected to the oscilloscope channel B. The delay between captured pulses on channel A and Channel B is measured TI_ADC5.1.4 19 Check the data latency during user data phase Check if the data latency is fixed The ramp pattern is seen without Passed during the user data phase. distortion CoreJESD204BRX _0 CoreJESD204BRX _0 DATA_OUT[63:48], DATA_OUT[47:32], DATA_OUT[31:16], DATA_OUT[15:0] signals are observed in Identify Debugger R e visio n 2 SmartFusion2 and IGLOO2 CoreJESD204BRX and CoreJESD204BTX Test5.2: Deterministic Latency The CoreJESD204BRX IP is configured in subclass 2 mode and ADC34J44 is configured in subclass 2 mode with parameters LMFK = 4429. Table 25 shows the JESD204B deterministic latency measurement test results. Table 25 • JESD204B Deterministic Latency Measurement Test Results Test Case Objective Description Passing Criteria TI_ADC5.2.1 SYNC_N capture CoreJESD204BRX _0 c2l_mf_phase and SYNC_N signals are observed in Identify Debugger TI_ADC5.2.2 Check latency Result LMFC counter and the SYNC_N Passed signals should be aligned A single pulse input is applied to Latency is fixed for multiple runs Passed ADC and the oscilloscope (between the FPGA resets/core channel A using 2-port splitter. resets) Core output MSB is connected to the oscilloscope channel B The delay between captured pulses on channel A and Channel B is measured TI_ADC5.2.3 Check the data latency during user data phase Check if the data latency is fixed The ramp pattern is seen without Passed during the user data phase. distortion CoreJESD204BRX _0 DATA_OUT[63:48], DATA_OUT[47:32], DATA_OUT[31:16], DATA_OUT[15:0] signals are observed in Identify Debugger Revision 2 20 SmartFusion2 and IGLOO2 CoreJESD204BRX and CoreJESD204BTX List of Changes The following table shows important changes made in this document for each revision. Revision Revision 2 (June 2016) Changes Updated Table 1 for ADC34J44 device entry (SAR 80233). 3 Added a third-part reference in the "References" section (SAR 80233). 3 Added the "ADC34J44 Setup" section in this document (SAR 80233). 7 Added the ADC34J44 entry in the "Interoperability Tests" section and added the ADC34J44 related details in Table 2 (SAR 80233). Revision 1 (August 2015) 21 Page 9 and 9 Added "ADC34J44 Interoperability Tests" section in the document (SAR 80233). 17 Initial release N/A R e visio n 2 Microsemi Corporate Headquarters One Enterprise, Aliso Viejo, CA 92656 USA Within the USA: +1 (800) 713-4113 Outside the USA: +1 (949) 380-6100 Sales: +1 (949) 380-6136 Fax: +1 (949) 215-4996 E-mail: [email protected] www.microsemi.com © 2016 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners. 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