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ESDAVLC6-1BV2
Single line low capacitance Transil™ for ESD protection
Datasheet − production data
Features
• PCB area: 0.09 mm²
• Bidirectional device
• Low capacitance: 8 pF max.
• Minimum breakdown voltage VBR = 6 V
• Low leakage current: lower than 50 nA at 3 V
• RoHS compliant
ST01005
ESDAVLC6-1BV2
Figure 1. Functional diagram
Applications
Where transient over voltage protection in ESD
sensitive equipment is required, such as:
• Portable multimedia devices and accessories
Pin1
• MID, netbooks and notebooks
• Digital cameras and camcorders
• Communication systems
• Smart phones and accessories
Description
The ESDAVLC6-1BV2 is a single line bidirectional
Transil diode designed specially for the protection
of integrated circuits in portable equipment and
miniaturized electronic devices subject to ESD
transient overvoltage.
The device is ideal for applications where both
reduced printed circuit board space and high ESD
protection levels are required.
TM: Transil is a trademark of STMicroelectronics
March 2014
This is information on a product in full production.
DocID023822 Rev 2
1/9
www.st.com
Characteristics
1
ESDAVLC6-1BV2
Characteristics
Table 1. Absolute maximum ratings (Tamb = 25 °C)
Symbol
Parameter
IEC 61000-4-2 contact discharge
IEC 61000-4-2 air discharge
Value
Unit
12
15
kV
VPP
Peak pulse voltage
IPP
Peak pulse current (8/20 µs)(1)
2.5
A
PPP
Peak pulse power (8/20 µs)(1)
45
W
Tj
Operating temperature range
-55 to +150
°C
Tstg
Storage temperature range
- 65 to +150
°C
TL
Maximum lead temperature for soldering during 10 s
260
°C
1. For a surge greater than the maximum values, the diode will fail in short-circuit.
Figure 2. Electrical characteristics (definitions)
I
Symbol
VBR
VRM
VCL
IRM
IPP
=
=
=
=
=
RD
=
CLINE
=
Parameter
Breakdown voltage
Stand-off voltage
Clamping voltage
Leakage current @ VRM
Peak pulse current
VCL VBR
VRM
IRM
Dynamic resistance
Line capacitance
Slope: 1/Rd
V
VRM VBR VCL
IPP
Table 2. Electrical characteristics (values, Tamb = 25 °C)
Value
Symbol
Parameter
Min.
Typ.
Max.
VBR
Breakdown voltage
IR = 1 mA
IRM
Leakage current
VRM = 3 V
50
Clamping voltage
IPP = 1 A, 8/20 µs
12
VCL
IPP = 2.5 A maximum, 8/20 µs
18
Cline
Line capacitance, I/O to GND VR = 0 V, F = 1 MHz, Vosc = 30 mV
Rd
2/9
Unit
Test conditions
Dynamic resistance, pulse
width 100 ns
6
V
V
7.5
I/O to GND
1.43
GND to I/O
1.38
DocID023822 Rev 2
nA
8
pF
Ω
ESDAVLC6-1BV2
Characteristics
Figure 3. ESD response to IEC 61000-4-2
(typical values, +8 kV contact discharge)
Figure 4. ESD response to IEC 61000-4-2
(typical values, -8 kV contact discharge)
10 V/div
10 V/div
1 49.7 V
1
2
3
4
22 29.3 V
VPP: ESD peak voltage
VCL :clamping voltage at 30 ns
VCL :clamping voltage at 60 ns
VCL :clamping voltage at 100 ns
3 20.3 V
4 13.8 V
4 -13.1 V
3 -19.4 V
1
2
3
4
2 -29.7 V
VPP: ESD peak voltage
VCL :clamping voltage at 30 ns
VCL :clamping voltage at 60 ns
VCL :clamping voltage at 100 ns
1 -50.8 V
20 ns/div
20 ns/div
Figure 5. S21 attenuation measurement
Figure 6. Junction capacitance versus reverse
applied voltage (typical values)
S21 (dB)
C (pF)
0
10
-2
F=1 MHz
Vosc = 30 mVRMS
Tj = 25 °C
IO/GND
9
-4
8
-6
7
-8
6
-10
5
-12
4
-14
3
-16
2
-18
F (Hz)
-20
100k
1M
S21
10M
100M
1
1G
VR(V)
0
10G
0
1
2
3
4
5
6
Figure 7. TLP measurement
26
24
22
20
18
16
14
12
10
8
6
4
2
0
IPP (A)
GND to I/O
I/O to GND
VCL (V)
0
5
10
15
20
25
30
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40
45
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9
Package information
2
ESDAVLC6-1BV2
Package information
•
Epoxy meets UL94, V0
•
Lead-free package
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 8. Package dimensions
205 µm ± 20
25 µm ± 10
50 µm
75 µm
75 µm
50 µm
200 µm
200 µm ± 20
50 µm
50 µm
450 µm ± 20
Figure 9. Footprint recommendation
A
B
H
I
F
J
E
D
C
G
A = 225 µm
B = 225 µm
C = 50 µm E = 180 µm G = 530 µm I = 112.5 µm
D = 180 µm F = 100 µm H = 40 µm
J = 270 µm
Solder pad
PCB opening
4/9
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ESDAVLC6-1BV2
Package information
Figure 10. Tape and reel specification
Ø 1.5
4.0
2.0
1.75
Bar identifying Pin A1 location
0.20
8.0
3.5
0.51
0.35
0.03
0.23
0.20
4.0
0.03 Raised cross-bar
All dimensions are typical values in mm
User direction of unreeling
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Recommendation on PCB assembly
ESDAVLC6-1BV2
3
Recommendation on PCB assembly
3.1
Stencil opening design
Stencil opening thickness: 80 µm
Figure 11. Recommended stencil window position
K
M
N
L
K = 180 µm
L = 180 µm
M = 150 µm N = 30 µm
Solder pad
PCBopening
Stencil aperture (thickness stencil: 80 µm)
3.2
6/9
Solder paste
1.
Use halide-free flux, qualification ROL0 according to ANSI/J-STD-004.
2.
“No clean” solder paste recommended.
3.
Offers a high tack force to resist component displacement during PCB movement.
4.
Solder paste with fine particles: type 4 (powder particle size 20-38 µm per
IPC J STD 005).
DocID023822 Rev 2
ESDAVLC6-1BV2
3.3
3.4
3.5
Recommendation on PCB assembly
Placement
1.
Manual positioning is not recommended.
2.
It is recommended to use the lead recognition capabilities of the placement system, not
the outline centering.
3.
Tolerance of ± 0.02 mm is recommended.
4.
1.0 N placement force is recommended. Too much placement force can lead to
squeezed out solder paste and cause solder joints to short. Too low placement force
can lead to insufficient contact between package and solder paste that could cause
open solder joints or badly centered packages.
5.
To improve the package placement accuracy, a bottom side optical control should be
performed with a high resolution tool.
6.
For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is
recommended during solder paste printing, pick and place and reflow soldering by
using optimized tools.
PCB design preference
1.
To control the solder paste amount, the closed via is recommended instead of open
vias.
2.
The position of tracks and open vias in the solder area should be well balanced. The
symmetrical layout is recommended, in case any tilt phenomena caused by
asymmetrical solder paste amount due to the solder flow away.
Reflow profile
Figure 12. ST ECOPACK® recommended soldering reflow profile for PCB mounting
240-245 °C
Temperature (°C)
250
-2 °C/s
2 - 3 °C/s
60 sec
(90 max)
200
-3 °C/s
150
-6 °C/s
100
0.9 °C/s
50
Time (s)
0
Note:
30
60
90
120
150
180
210
240
270
300
Minimize air convection currents in the reflow oven to avoid component movement.
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Ordering information
4
ESDAVLC6-1BV2
Ordering information
Figure 13. Ordering information scheme
ESDA VLC 6 - 1 B V 2
ESD array
Very low capacitance
Breakdown voltage
6 = 6 V min.
Number of lines
Directional
B = bidirectional
Package
V = ST01005 package
2 = 2 pads
Table 3. Ordering information
5
Order code
Marking
Weight
Base qty
Delivery mode
ESDAVLC6-1BV2
No marking
0.041 mg
20 000
Tape and reel
Revision history
Table 4. Document revision history
8/9
Date
Revision
Changes
06-Nov-2012
1
First issue
20-Mar-2014
2
Updated Figure 9, and Figure 11. Updated values for dynamic
resistance in Table 2 and added Figure 7 and Figure 10.
DocID023822 Rev 2
ESDAVLC6-1BV2
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