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ESDAVLC8-4BN4
4-line very low capacitance Transil™ array for ESD protection
Datasheet − production data
Features
• Stand-off voltage: 3 V
• Very low capacitance: 4.5 pF
• Small package: 1.0 x 0.8 mm
• Very thin package: 0.40 mm max
• Low leakage current: 50 nA at 25 °C
µQFN-4L
Benefits
Figure 1. Functional diagram (top view)
• High ESD robustness of the equipment
• Suitable for high speed interface
Complies with the following standards:
I/O4
I/O1
GND
I/O2
I/O3
• IEC 61000-4-2:
– ±15 kV (air discharge)
– ±8 kV (contact discharge)
• MIL STD 883G- Method 3015-7: class3B:
– >25 kV (human body model)
Applications
Where transient overvoltage protection and
electrical overstress protection in sensitive
equipment is required, such as:
• Communication systems
• Cellular phone handsets and accessories
• Video equipment
Description
The ESDAVLC8-4BN4 is monolithic array
designed to protect up to 4 lines against ESD
transients. It has been designed specifically for
the protection of the high speed interface of
integrated circuits in portable equipment and
miniaturized electronics devices. The µQFN-4L
package minimizes PCB space.
TM: Transil is a trademark of STMicroelectronics.
March 2014
This is information on a product in full production.
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10
Characteristics
1
ESDAVLC8-4BN4
Characteristics
Table 1. Absolute maximum ratings (Tamb = 25 °C)
Symbol
VPP
Parameter
Value
Unit
16
kV
45
32
W
1.6
A
Peak pulse voltage, IEC 61000-4-2, level 4 (contact discharge)
(1)
GND to I/O
I/O to GND
PPP
Peak pulse power dissipation (8/20 µs)
Tj initial = Tamb
Ipp
Peak pulse current (8/20 µs)
Tj
Maximum junction temperature range
-40 to 125
°C
Storage temperature range
-55 + 150
°C
Tstg
1. For a surge greater than the maximum values, the diode will fail in short-circuit.
Figure 2. Electrical characteristics (definitions)
Symbol
VBR
VCL
IRM
VRM
IPP
Parameter
Breakdown voltage
Clamping voltage
Leakage current @ VRM
Stand-off voltage
Peak pulse current
=
=
=
=
=
Table 2. Electrical characteristics (values, Tamb = 25 °C)
Symbol
Typ.
Max.
Unit
IR = 1 mA, GND to I/O
8.5
11
14
V
VBR2
IR = 1 mA, I/O to GND
14.5
17
20
V
VRM = 3 V
50
nA
Ipp = 1 A, 8/20 µs, GND to I/O
20
Ipp = 1 A, 8/20 µs, I/O to GND
28
VCL
2/10
Min.
VBR1
IRM
Note:
Test conditions
C
VI/O = 0 V, F = 1 MHz, Vosc = 30 mV
Rd
Dynamic resistance,
pulse width 100 ns
V
4.5
I/O to GND
0.36
GND to I/O
0.28
5.5
pF
Ω
For component test in its final application, the minimum clamping voltage has to be 20 V on
VBR1 (GND to I/O) and 25 V on VBR2 (I/O to GND).
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ESDAVLC8-4BN4
Characteristics
Figure 3. Peak pulse power versus initial
junction temperature (8/20 µs waveform)
Figure 4. Peak pulse power versus exponential
pulse duration
Ppp (W)
100
100
8/20 µs
PPP(W)
Tj=25 °C
Direct
Reverse
80
Direct
Reverse
60
10
40
20
tp (µs)
Tj (°C)
1
0
25
35
45
55
65
75
85
95
105
115
125
135
Figure 5. Clamping voltage versus peak pulse
current (typical values, 8/20 µs waveform)
10.0
10
145
IPP(A)
100
1000
Figure 6. Junction capacitance versus reverse
voltage applied (typical values)
C(pF)
5.0
8/20µs
Tj initial = 25 °C
Direct
Reverse
F=1 MHz
Vosc =30mVRMS
Vr=0V
Tj=25 °C
4.0
Direct
Reverse
3.0
1.0
2.0
1.0
VR(V)
VCL (V)
0.0
0.1
10
20
30
Figure 7. ESD response to IEC 61000-4-2
(+8 kV contact discharge) on each channel
0
1
2
3
4
5
6
Figure 8. ESD response to IEC 61000-4-2
(-8 kV contact discharge) on each channel
10 V/div
10 V/div
20 ns/div
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20 ns/div
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Characteristics
ESDAVLC8-4BN4
Figure 9. S21 attenuation measurement
Figure 10. Analog crosstalk measurement
dB
0.00
0.00
dB
-10.00
-5.00
-20.00
-30.00
-10.00
-40.00
-15.00
-50.00
-60.00
-20.00
-70.00
-80.00
-25.00
F/Hz
-90.00
F/Hz
-100.00
-30.00
100.0 k
100.0 M
10.0 M
1.0 M
1.0 G
100.0k
Figure 11. Leakage current versus junction
temperature (typical values)
IR (nA)
1.0M
10.0M
100.0M
1.0G
Figure 12. TLP measurement
25
IPP (A)
VR=VRM=3V
10.00
Direct
Reverse
20
GND to I/O
I/O to GND
15
1.00
10
0.10
5
T j (°C)
0.01
25
4/10
35
45
55
65
75
85
95
105
115
125
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0
VCL (V)
0
5
10
15
20
25
ESDAVLC8-4BN4
2
Package information
Package information
•
Epoxy meets UL94, V0
•
Lead-free package
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 13. µQFN-4L dimension definitions
D
D2
e
2
Index
area
1
E2
E
L
3
4
L1
b
A
A1
Table 3. µQFN-4L dimension values
Dimensions
Ref.
Millimeters
Inches
Min.
Typ.
Max.
Min.
Typ.
Max.
A
0.31
0.38
0.40
0.012
0.015
0.016
A1
0.00
0.02
0.05
0.00
0.0008
0.002
b
0.10
0.15
0.20
0.004
0.006
0.008
D
0.70
0.80
0.90
0.028
0.031
0.035
D2
0.50
0.58
0.65
0.020
0.023
0.026
e
0.35
0.40
0.45
0.014
0.016
0.018
E
0.90
1.00
1.10
0.035
0.039
0.043
E2
0.15
0.20
0.25
0.006
0.008
0.010
L
0.18
0.23
0.28
0.007
0.009
0.011
L1
0.00
--
0.05
0.00
--
0.002
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Package information
ESDAVLC8-4BN4
Figure 14. Footprint dimensions (in mm)
Figure 15. Marking
0.4
0.43
B
0.17
0.2
1.4
0.58
0.18
0.58
Note:
Product marking may be rotated by multiples of 90° for assembly plant differentiation. In no
case should this product marking be used to orient the component for its placement on a
PCB. Only pin 1 mark is to be used for this purpose.
Figure 16. Tape and reel specifications
Dot identifying Pin A1 location
2.0
Ø 1.55
4.0
3.5
2.0
0.63
All dimensions are typical values in mm
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User direction of unreeling
DocID022192 Rev 3
B
B
B
0.89
B
B
B
B
8.0
1.07
1.75
0.22
ESDAVLC8-4BN4
Recommendation on PCB assembly
3
Recommendation on PCB assembly
3.1
Stencil opening design
Reference design
•
Stencil opening thickness: 100 µm
•
Stencil opening for leads: Opening to footprint ratio is 100%.
Figure 17. Recommended stencil window position
430 µm
T=100 µm and opening
ratio is 100%
180 µm
580 µm
200 µm
Footprint
Stencil window
Footprint
3.2
Solder paste
1.
Halide-free flux qualification ROL0 according to ANSI/J-STD-004.
2.
“No clean” solder paste is recommended.
3.
Offers a high tack force to resist component movement during high speed.
4.
Solder paste with fine particles: powder particle size is 20-45 µm.
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Recommendation on PCB assembly
3.3
3.4
3.5
ESDAVLC8-4BN4
Placement
1.
Manual positioning is not recommended.
2.
It is recommended to use the lead recognition capabilities of the placement system, not
the outline centering.
3.
Standard tolerance of ± 0.05 mm is recommended.
4.
3.5 N placement force is recommended. Too much placement force can lead to
squeezed out solder paste and cause solder joints to short. Too low placement force
can lead to insufficient contact between package and solder paste that could cause
open solder joints or badly centered packages.
5.
To improve the package placement accuracy, a bottom side optical control should be
performed with a high resolution tool.
6.
For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is
recommended during solder paste printing, pick and place and reflow soldering by
using optimized tools.
PCB design preference
1.
To control the solder paste amount, the closed via is recommended instead of open
vias.
2.
The position of tracks and open vias in the solder area should be well balanced. The
symmetrical layout is recommended, in case any tilt phenomena caused by
asymmetrical solder paste amount due to the solder flow away.
Reflow profile
Figure 18. ST ECOPACK® recommended soldering reflow profile for PCB mounting
240-245 °C
Temperature (°C)
250
-2 °C/s
2 - 3 °C/s
60 sec
(90 max)
200
-3 °C/s
150
-6 °C/s
100
0.9 °C/s
50
Time (s)
0
Note:
8/10
30
60
90
120
150
180
210
240
270
300
Minimize air convection currents in the reflow oven to avoid component movement.
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ESDAVLC8-4BN4
4
Ordering information
Ordering information
Figure 19. Ordering information scheme
ESDA VLC 8 4 B N4
ESD array
Very low capacitance
Breakdown voltage
8 = 8.5 Volts min
Number of lines
4 = 4 lines
Direction
B = Bidirectional
Package
N4 = µQFN-4L
Table 4. Ordering information
Order code
Marking
Package
Weight
Base qty
Delivery mode
ESDAVLC8-4BN4
B(1)
µQFN-4L
1.17 mg
10000
Tape and reel
1. The marking can be rotated by multiples of 90° to differentiate assembly location
5
Revision history
Table 5. Document revision history
Date
Revision
Changes
06-Sep-2011
1
Initial release.
25-Sep-2012
2
Updated ECOPACK statement.
25-Mar-2014
3
For Table 2 added maximum values for VBR1 and VBR2, and the
note following the table.Updated values for dynamic resistance in
Table 2 and added Figure 12.
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