INFINEON HYB314400BJ-60

1M × 4-Bit Dynamic RAM
HYB 314400BJ-50/-60
Advanced Information
• 1 048 576 words by 4-bit organization
• 0 to 70 °C operating temperature
• Fast Page Mode Operation
• Performance:
-50
-60
tRAC
RAS access time
50
60
ns
tCAC
CAS access time
13
15
ns
tAA
Access time from address
25
30
ns
tRC
Read/Write cycle time
95
110
ns
tPC
Fast page mode cycle time
35
40
ns
• Fast access and cycle time
Single + 3.3 V (± 0.3 V) supply with a built-in VBB generator
• Low power dissipation
max. 252 mW active (-50 version)
max. 216 mW active (-60 version)
• Standby power dissipation:
7.2 mW max. standby (LVTTL)
3.6 mW max. standby (LVCMOS)
• Output unlatched at cycle end allows two-dimensional chip selection
• Read, write, read-modify write, CAS-before-RAS refresh, RAS-only refresh,
hidden refresh and test mode capability
• All inputs and outputs LVTTL-compatible
• 1024 refresh cycles / 16 ms
• Plastic Packages: P-SOJ-26/20-2 with 300 mil width
Semiconductor Group
1
1998-10-01
HYB 314400BJ-50/-60
3.3 V 1M × 4 DRAM
The HYB 314400BJ is the new generation dynamic RAM organized as 1 048 576 words by 4-bit.
The HYB 314400BJ utilizes CMOS silicon gate process as well as advances circuit techniques to
provide wide operation margins, both internally and for the system user. Multiplexed address inputs
permit the HYB 314400BJ to be packed in a standard plastic P-SOJ-26/20 package. This package
size provides high system bit densities and is compatible with commonly used automatic testing and
insertion equipment. System oriented features include single + 3.3 V (± 0.3 V ) power supply, direct
interfacing with high performance logic device families.
Ordering Information
Type
Ordering Code Package
Descriptions
HYB 314400BJ-50 on request
P-SOJ-26/20-2 300 mil 3.3 V DRAM (access time 50 ns)
HYB 314400BJ-60 on request
P-SOJ-26/20-2 300 mil 3.3 V DRAM (access time 60 ns)
Semiconductor Group
2
1998-10-01
HYB 314400BJ-50/-60
3.3 V 1M × 4 DRAM
P-SOJ-26/20-2
I/O1
I/O2
WE
RAS
A9
1
2
3
4
5
26
25
24
23
22
V SS
I/O4
I/O3
CAS
OE
A0
A1
A2
A3
V CC
9
10
11
12
13
18
17
16
15
14
A8
A7
A6
A5
A4
SPP02807
Pin Configuration
Pin Names
A0 - A9
Address Input
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Read/Write Input
OE
Output Enable
I/O1 - I/O4
Data Input/Output
VCC
Power Supply (+ 3.3 V)
VSS
Ground (0 V)
N.C.
No Connection
Semiconductor Group
3
1998-10-01
HYB 314400BJ-50/-60
3.3 V 1M × 4 DRAM
I/O1 I/O2 I/O3 I/O4
Data In
Buffer
OE
4
&
WE
Data Out
Buffer
4
CAS
No.2 Clock
Generator
10
Column
Address
Buffers (10)
10
A0
Column
Decoder
A1
Refresh
Controller
A2
A3
Sense Amplifier
I/O Gating
A4
4
A5
.
..
1024
x4
A7
.
..
Refresh
Counter (10)
A6
A8
A9
10
RAS
Row
Address
Buffers (10)
10
Row
Decoder
..
.
1024
..
.
Memory Array
1024 x 1024 x 4
No.1 Clock
Generator
SPB02831
Block Diagram
Semiconductor Group
4
1998-10-01
HYB 314400BJ-50/-60
3.3 V 1M × 4 DRAM
Absolute Maximum Ratings
Operating temperature range ........................................................................................... 0 to 70 °C
Storage temperature range.................................................................................... – 55 to + 150 °C
Input/output voltage ............................................................................ – 1 to min (VCC + 0.5, 4.6) V
Power Supply voltage ................................................................................................. – 1 to + 4.6 V
Data out current (short circuit) ............................................................................................... 50 mA
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
DC Characteristics
TA = 0 to 70 °C, VSS = 0 V, VCC = 3.3 V ± 0.3 V, tT = 5 ns
Parameter
Symbol
Limit Values
min.
max.
Unit Test
Condition
Input high voltage
VIH
2.0
VCC + 0.5 V
1
Input low voltage
VIL
– 1.0
0.8
V
1
TTL Output high voltage (IOUT = – 2 mA)
VOH
2.4
–
V
1
TTL Output low voltage (IOUT = 2 mA)
VOL
–
0.4
V
1
CMOS Output high voltage (IOUT = – 100 µA)
VOH
VCC – 0.2 –
V
CMOS Output low voltage (IOUT = 100 µA)
VOL
–
0.2
V
– 10
10
µA
1
– 10
10
µA
1
mA
2, 3, 4
Input leakage current, any input
II(L)
(0 V < VIN < VCC + 0.3 V, all other input = 0 V)
Output leakage current
(DO is disabled, 0 < VOUT < VCC)
IO(L)
Average VCC supply current
ICC1
-50 version
-60 version
Standby VCC supply current
(RAS = CAS = WE = VIH)
ICC2
Average VCC supply current during RAS-only
ICC3
refresh cycles
-50 version
-60 version
Average VCC supply current during fast page
ICC4
mode operation
-50 version
-60 version
Semiconductor Group
5
–
–
70
60
–
2
–
–
–
–
mA
mA
2, 4
mA
2, 3, 4
70
60
50
45
1998-10-01
HYB 314400BJ-50/-60
3.3 V 1M × 4 DRAM
DC Characteristics (cont’d)
TA = 0 to 70 °C, VSS = 0 V, VCC = 3.3 V ± 0.3 V, tT = 5 ns
Parameter
Symbol
Standby VCC supply current
(RAS = CAS = WE = VCC – 0.2 V)
ICC5
Average VCC supply current during
CAS-before-RAS refresh mode
ICC6
-50 version
-60 version
Limit Values
min.
max.
Unit Test
Condition
–
1
µA
1
mA
2, 4
–
–
70
60
Capacitance
TA = 0 to 70 °C; VCC = 3.3 V ± 0.3 V; f = 1 MHz
Parameter
Symbol
Limit Values
min.
max.
Unit
Input capacitance (A0 to A9)
CI1
–
5
pF
Input capacitance (RAS, CAS, WE, OE)
CI2
–
7
pF
Output capacitance (IO1 to IO4)
CIO
–
7
pF
Semiconductor Group
6
1998-10-01
HYB 314400BJ-50/-60
3.3 V 1M × 4 DRAM
AC Characteristics 5, 6
TA = 0 to 70 °C, VCC = 3.3 V ± 0.3 V, tT = 5 ns
Parameter
Symbol
Limit Values
-50
Unit Note
-60
min.
max. min.
max.
Common Parameters
Random read or write cycle time
tRC
95
–
110
–
ns
RAS precharge time
tRP
35
–
40
–
ns
RAS pulse width
tRAS
50
10k
60
10k
ns
CAS pulse width
tCAS
13
10k
15
10k
ns
Row address setup time
tASR
0
–
0
–
ns
Row address hold time
tRAH
8
–
10
–
ns
Column address setup time
tASC
0
–
0
–
ns
Column address hold time
tCAH
10
–
15
–
ns
RAS to CAS delay time
tRCD
18
37
20
45
RAS to column address delay time
tRAD
13
25
15
30
ns
RAS hold time
tRSH
13
15
–
ns
CAS hold time
tCSH
50
60
–
ns
CAS to RAS precharge time
tCRP
5
–
5
–
ns
Transition time (rise and fall)
tT
3
50
3
50
ns
Refresh period
tREF
–
16
–
16
ms
Access time from RAS
tRAC
–
50
–
60
ns
8, 9
Access time from CAS
tCAC
–
13
–
15
ns
8, 9
Access time from column address
tAA
–
25
–
30
ns
8, 10
OE access time
tOEA
–
13
–
15
ns
Column address to RAS lead time
tRAL
25
–
30
–
ns
Read command setup time
tRCS
0
–
0
–
ns
Read command hold time
tRCH
0
–
0
–
ns
11
Read command hold time referenced to RAS
tRRH
0
–
0
–
ns
11
CAS to output in low-Z
tCLZ
0
–
0
–
ns
8
Output buffer turn-off delay
tOFF
0
13
0
15
ns
12
Output buffer turn-off delay from OE
tOEZ
0
13
0
15
ns
12
7
Read Cycle
Semiconductor Group
7
1998-10-01
HYB 314400BJ-50/-60
3.3 V 1M × 4 DRAM
AC Characteristics (cont’d) 5, 6
TA = 0 to 70 °C, VCC = 3.3 V ± 0.3 V, tT = 5 ns
Parameter
Symbol
Limit Values
-50
Unit Note
-60
min.
max. min.
max.
Data to OE low delay
tDZO
0
–
0
–
ns
13
CAS high to data delay
tCDD
13
–
15
–
ns
14
OE high to data delay
tODD
13
–
15
–
ns
14
Write command hold time
tWCH
8
–
10
–
ns
Write command pulse width
tWP
8
–
10
–
ns
Write command setup time
tWCS
0
–
0
–
ns
Write command to RAS lead time
tRWL
13
–
15
–
ns
Write command to CAS lead time
tCWL
13
–
15
–
ns
Data setup time
tDS
0
–
0
–
ns
16
Data hold time
tDH
10
–
10
–
ns
16
Data to CAS low delay
tDZC
0
–
0
–
ns
13
Read-write cycle time
tRWC
131
–
150
–
ns
RAS to WE delay time
tRWD
68
–
80
–
ns
15
CAS to WE delay time
tCWD
31
–
35
–
ns
15
Column address to WE delay time
tAWD
43
–
50
–
ns
15
OE command hold time
tOEH
13
–
15
–
ns
Fast page mode cycle time
tPC
35
–
40
–
ns
CAS precharge time
tCP
10
–
10
–
ns
Access time from CAS precharge
tCPA
–
30
–
35
ns
RAS pulse width
tRAS
50
200k 60
200k ns
CAS precharge to RAS delay
tRHCP
30
–
35
–
ns
Fast page mode read-write cycle time
tPRWC
71
–
80
–
ns
CAS precharge to WE
tCPWD
48
–
55
–
ns
Write Cycle
15
Read-Modify-Write Cycle
Fast Page Mode Cycle
7
Fast Page Mode Read-Modify-Write Cycle
Semiconductor Group
8
1998-10-01
HYB 314400BJ-50/-60
3.3 V 1M × 4 DRAM
AC Characteristics (cont’d) 5, 6
TA = 0 to 70 °C, VCC = 3.3 V ± 0.3 V, tT = 5 ns
Parameter
Symbol
Limit Values
-50
Unit Note
-60
min.
max. min.
max.
CAS-before-RAS Refresh Cycle
CAS setup time
tCSR
10
–
10
–
ns
CAS hold time
tCHR
10
–
10
–
ns
RAS to CAS precharge time
tRPC
5
–
5
–
ns
Write to RAS precharge time
tWRP
10
–
10
–
ns
Write hold time referenced to RAS
tWRH
10
–
10
–
ns
tCPT
35
–
40
–
ns
Write command setup time
tWTS
10
–
10
–
ns
Write command hold time
tWTH
10
–
10
–
ns
CAS-before-RAS Counter Test Cycle
CAS precharge time
Test Mode
Semiconductor Group
9
1998-10-01
HYB 314400BJ-50/-60
3.3 V 1M × 4 DRAM
Notes
All voltages are referenced to VSS.
ICC1, ICC3, ICC4 and ICC6 depend on cycle rate.
ICC1 and ICC4 depend on output loading. Specified values are measured with the output open.
Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once
or less during a fast page mode cycle (tPC).
5. An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least
one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using
internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS
cycles are required.
6. AC measurements assume tT = 5 ns.
7. VIH (MIN.) and VIL (MAX.) are reference levels for measuring timing of input signals. Transition times
are also measured between VIH and VIL.
8. Measured with a load equivalent to 100 pF and at VOH = 2.0 V (IOH = – 2 mA), VOL = 0.8 V
(IOL = 2 mA).
9. Operation within the tRCD (MAX.) limit ensures that tRAC (MAX.) can be met. tRCD (MAX.) is specified as
a reference point only: If tRCD is greater than the specified tRCD (MAX.) limit, then access time is
controlled by tCAC.
10.Operation within the tRAD (MAX.) limit ensures that tRAC (MAX.) can be met. tRAD (MAX.) is specified as
a reference point only: If tRAD is greater than the specified tRAD (MAX.) limit, then access time is
controlled by tAA.
11.Either tRCH or tRRH must be satisfied for a read cycle.
12.tOFF (MAX.) and tOEZ (MAX.) define the time at which the outputs achieve the open-circuit condition
and are not referenced to output voltage levels.
13.Either tDZC or tDZO must be satisfied.
14.Either tCDD or tODD must be satisfied.
15.tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only. If tWCS > tWCS (MIN.), the cycle is an early write cycle
and the I/O pin will remain open-circuit (high impedance) through the entire cycle; if
tRWD > tRWD (MIN.), tCWD > tCWD (MIN.), tAWD > tAWD (MIN.) and tCPWD > tCPWD (MIN.), the cycle is a readwrite cycle and I/O pins will contain data read from the selected cells. If neither of the above sets
of conditions is satisfied, the condition of the I/O pins (at access time) is indeterminate.
16.These parameters are referenced to the CAS leading edge in early write cycles and to the WE
leading edge in read-write cycles.
1.
2.
3.
4.
Semiconductor Group
10
1998-10-01
HYB 314400BJ-50/-60
3.3 V 1M × 4 DRAM
t RC
t RAS
t RP
VIH
RAS
VIL
t CSH
t RCD
t RSH
t CRP
t CAS
VIH
CAS
VIL
t RAD
t ASR
t RAL
t CAH
t ASC
t ASR
VIH
Address
Row
VIL
Column
Row
t RAH
t RCH
t RRH
t RCS
VIH
WE
VIL
t AA
t OEA
VIH
OE
VIL
t DZC
t CDD
t DZO
I/O
(Inputs)
t ODD
VIH
VIL
t OFF
t CAC
t CLZ
VOH
I/O
(Outputs) V
OL
Hi Z
t OEZ
Valid Data OUT
Hi Z
t RAC
"H" or "L"
SPT03025
Read Cycle
Semiconductor Group
11
1998-10-01
HYB 314400BJ-50/-60
3.3 V 1M × 4 DRAM
t RC
t RAS
t RP
VIH
RAS
VIL
t CSH
t RCD
t RSH
t CRP
t CAS
VIH
CAS
VIL
t RAL
t RAD
t ASR
t ASC
t CAH
t ASR
VIH
Address
Row
VIL
Column
t RAH
t CWL
t WCS
VIH
Row
t WP
WE
VIL
t WCH
t RWL
VIH
OE
VIL
t DS
I/O
(Inputs)
t DH
VIH
Valid Data IN
VIL
VOH
I/O
(Outputs) V
OL
Hi Z
"H" or "L"
SPT03026
Write Cycle (Early Write)
Semiconductor Group
12
1998-10-01
HYB 314400BJ-50/-60
3.3 V 1M × 4 DRAM
t RC
t RAS
t RP
VIH
RAS
VIL
t CSH
t RCD
t RSH
t CAS
VIH
t CRP
CAS
VIL
t RAD
t RAL
t CAH
t ASC
t ASR
t ASR
VIH
Address
Row
VIL
Column
Row
t RAH
t CWL
t RWL
t WP
VIH
WE
VIL
t OEH
VIH
OE
VIL
t ODD
t DZO
t DZC
I/O
(Inputs)
t DH
t DS
VIH
Valid Data
VIL
t CLZ
t OEZ
t OEA
VOH
I/O
(Outputs) V
OL
Hi Z
Hi Z
"H" or "L"
SPT03027
Write Cycle (OE Controlled Write)
Semiconductor Group
13
1998-10-01
HYB 314400BJ-50/-60
3.3 V 1M × 4 DRAM
t RWC
t RAS
VIH
RAS
VIL
t CSH
t RP
t RSH
t RCD
t CAS
t CRP
VIH
CAS
VIL
t RAH
t ASR
t CAH
t ASC
t ASR
VIH
Address
Row
Column
Row
VIL
t RAD
t CWL
t AWD
t CWD
t RWL
t RWD
t WP
VIH
WE
VIL
t AA
t RCS
t OEA
t OEH
VIH
OE
VIL
t DZC
t DS
t DZO
I/O
(Inputs)
t DH
VIH
Valid
Data IN
VIL
t ODD
t CAC
t OEZ
t CLZ
VOH
I/O
(Outputs) V
OL
Data
OUT
t RAC
"H" or "L"
SPT03028
Read-Write (Read-Modify-Write) Cycle
Semiconductor Group
14
1998-10-01
HYB 314400BJ-50/-60
3.3 V 1M × 4 DRAM
t RASP
VIH
RAS
VIL
t PC
t CAS
t RCD
t RP
t CRP
t RHCP
t RSH
t CAS
t CAS
t CP
VIH
CAS
VIL
t RAH
t ASR
t ASC
t CSH
t CAH
t ASC
t CAH
t CAH
t ASR
t ASC
VIH
Address
Row
Column
Column
VIL
Column
Row
t RCH
t RCH
t RAD
t RCS
t RCS
t RCS
t RRH
VIH
WE
VIL
t CPA
t AA
t AA
t OEA
t CPA
t AA
t OEA
t OEA
VIH
OE
VIL
t DZC
t DZC
t DZC
t DZO
t DZO
t ODD
I/O
(Inputs)
t CDD
t DZO
t ODD
t ODD
VIH
VIL
t OFF
t OEZ
t OFF
t OEZ
t OFF
t OEZ
t RAC
t CAC
t CLZ
VOH
I/O
(Outputs) V
OL
t CAC
t CLZ
Valid
Data OUT
t CAC
t CLZ
Valid
Data OUT
Valid
Data OUT
"H" or "L"
SPT03029
Fast Page Mode Read Cycle
Semiconductor Group
15
1998-10-01
HYB 314400BJ-50/-60
3.3 V 1M × 4 DRAM
t RASP
VIH
RAS
VIL
t PC
t CAS
t RCD
t RP
t RSH
t CAS
t CAS
t CP
t CRP
VIH
CAS
VIL
t RAH
t ASR
t ASC
t RAL
t CAH
t ASC
t CAH
t CAH
t ASC
t ASR
VIH
Address
Row
Column
Column
Column
Row
VIL
t RAD
t WCS
t CWL
t CWL
t WCS
t WCH
t WCS
t WCH
t WP
t RWL
t CWL
t WCH
t WP
t WP
VIH
WE
VIL
VIH
OE
VIL
t DS
I/O
(Inputs)
VIH
t DH
Valid
Data IN
VIL
t DH
t DS
Valid
Data IN
VOH
I/O
(Outputs) V
OL
t DS
t DH
Valid
Data IN
Hi Z
"H" or "L"
SPT03030
Fast Page Mode Early Write Cycle
Semiconductor Group
16
1998-10-01
HYB 314400BJ-50/-60
3.3 V 1M × 4 DRAM
t RAS
VIH
RAS
VIL
t CSH
t RP
t CP
t RCD
t PRWC
t CAS
t RSH
t CAS
t CAS
t CRP
VIH
CAS
VIL
t ASR
t RAD
t RAH
t ASC
t RAL
t CAH
t CAH
t CAH
t ASC
t ASC
t ASR
VIH
Address
Row
Column
Column
Column
Row
VIL
t RWD
t CWD
t RCS
t CPWD
t CWD
t CWL
t CPWD
t CWD
t CWL
t RWL
t CWL
VIH
WE
VIL
t AWD
t AA
t AWD
t WP
t OEA
t AWD
t WP
t OEA
t WP
t OEA
t OEH
t OEH
t OEH
VIH
OE
VIL
t CLZ
t DZC
t CLZ
t ODD
t CLZ
t CPA
t ODD
t DZC
t DZO
VIH
I/O
(Inputs) V
IL
Data IN
t CAC
t RAC
VOH
I/O
(Outputs) V
t DZC
t CPA
t ODD
Data IN
t DH
t DS
t OEZ
Data IN
t DH
t AA
t DS
t OEZ
Data
OUT
Data
OUT
t DH
t CAC
t DS
t AA
t OEZ
Data
OUT
OL
"H" or "L"
SPT03031
Fast Page Mode Read-Modify-Write Cycle
Semiconductor Group
17
1998-10-01
HYB 314400BJ-50/-60
3.3 V 1M × 4 DRAM
t RC
t RAS
t RP
VIH
RAS
VIL
t CRP
t RPC
VIH
CAS
VIL
t RAH
t ASR
t ASR
VIH
Row
Address
Row
VIL
VOH
I/O
(Outputs) V
OL
Hi Z
"H" or "L"
SPT03032
RAS-Only Refresh Cycle
Semiconductor Group
18
1998-10-01
HYB 314400BJ-50/-60
3.3 V 1M × 4 DRAM
t RC
t RP
t RAS
t RP
VIH
RAS
VIL
t RPC
t CP
t CHR
t RPC
t CSR
t CRP
VIH
CAS
VIL
t WRH
t WRP
VIH
WE
VIL
VIH
OE
VIL
t ODD
I/O
(Inputs)
VIH
VIL
t CDD
t OEZ
VOH
Hi Z
I/O
(Outputs) V
OL
t OFF
"H" or "L"
SPT03033
CAS-Before-RAS Refresh Cycle
Semiconductor Group
19
1998-10-01
HYB 314400BJ-50/-60
3.3 V 1M × 4 DRAM
t RC
t RC
t RP
t RP
t RAS
t RAS
VIH
RAS
VIL
t RCD
t RSH
t CHR
t CRP
VIH
CAS
VIL
t RAD
t ASC
t WRP
t RAH
t ASR
t WRH
t CAH
t ASR
VIH
Address
Row
VIL
Column
Row
t RCS
t RRH
VIH
WE
VIL
t AA
t OEA
VIH
OE
VIL
t DZC
t CDD
t DZO
I/O
(Inputs)
t ODD
VIH
VIL
t CLZ
t CAC
t OFF
t RAC
t OEZ
VOH
I/O
(Outputs) V
OL
Valid Data OUT
"H" or "L"
Hi Z
SPT03034
Hidden Refresh Cycle (Read)
Semiconductor Group
20
1998-10-01
HYB 314400BJ-50/-60
3.3 V 1M × 4 DRAM
t RC
t RC
t RAS
t RP
t RAS
t RP
VIH
RAS
VIL
t RCD
t RSH
t CHR
t CRP
VIH
CAS
VIL
t RAD
t ASC
t RAH
t ASR
t ASR
t CAH
VIH
Address
Row
VIL
Column
Row
t WCS
t WCH
t WP
t WRH
t WRP
VIH
WE
VIL
t DS
t DH
I/O
(Input)
VIN
Valid Data
VIL
VOH
I/O
(Output) V
OL
Hi Z
"H" or "L"
SPT03035
Hidden Refresh Cycle (Early Write)
Semiconductor Group
21
1998-10-01
HYB 314400BJ-50/-60
3.3 V 1M × 4 DRAM
Read Cycle
t RAS
t RP
VIH
RAS
VIL
t CHR
t CSR
t RSH
t CP
VIH
t CAS
CAS
VIL
t RAL
t CAH
t ASR
t ASC
VIH
Address
Column
VIL
t WRP
Row
t AA
t RRH
VIH
WE
VIL
t WRH
t CAC
t RCS
t RCH
t OEA
VIH
OE
VIL
t CDD
t DZC
VIH
I/O
(Inputs) V
IL
t ODD
t OFF
t DZO
t CLZ
t OEZ
VOH
I/O
(Outputs) V
Write Cycle
Data OUT
t WCS
OL
t RWL
t CWL
t WRP
t WCH
VIH
WE
VIL
t WRH
t DH
VIH
OE
VIL
t DS
VIH
I/O
(Inputs) V
IL
Data IN
VOH
I/O
(Outputs) V
Hi Z
OL
"H" or "L"
SPT03036
CAS-Before-RAS Refresh Counter Test Cycle
Semiconductor Group
22
1998-10-01
HYB 314400BJ-50/-60
3.3 V 1M × 4 DRAM
t RC
t RP
t RAS
t RP
VIH
RAS
VIL
t RPC
t CP
t RPC
t CHR
t CRP
t CSR
VIH
CAS
VIL
t RAH
t ASR
VIH
Row
Address
VIL
t WTH
t WTS
VIH
WE
VIL
VIH
OE
VIL
t ODD
I/O
(Inputs)
VIH
Hi Z
VIL
t CDD
t OEZ
VOH
I/O
(Outputs) V
OL
Hi Z
t OFF
"H" or "L"
SPT03042
Test Mode Entry
Semiconductor Group
23
1998-10-01
HYB 314400BJ-50/-60
3.3 V 1M × 4 DRAM
Test Mode
As the HYB 314400BJ is organized internally as 512k × 8-bits, a test mode cycle using 8:1
compression can be used to improve test time. Note that in the 1M × 4 version the test time is
reduced by 1/2 for a linear test pattern.
In a test mode “write” the data from each I/O1 pin is written into eight bits simultaneously (all “1” or
all “0”).The I/O2 - I/O4 inputs are not used for writing in test mode. In test mode “read” each I/O
output is used for indicating the test mode result. If the internal eight bits are equal, the I/O would
indicate a “1”. If they were not equal, the I/O would indicate a “0”. Note that in test mode "read"
I/O1-I/O3 are always driven to “ones”, i.e. all outputs will be “1” for a test mode “pass”. The WCBR
cycle (WE, CAS-before-RAS) puts the device into test mode. To exit from test mode, a
“CAS-before-RAS refresh”, “RAS-only refresh” or “Hidden refresh” can be used.
Addresses A10R, A10C and A0C are don‘t care during test mode.
Semiconductor Group
24
1998-10-01
HYB 314400BJ-50/-60
3.3 V 1M × 4 DRAM
Package Outlines
1.27
0.51-0.1
0.85 max
0.1
0.2 20x
15.24
26
6.8 ±0.3
8.63 -0.25
0.25 B
0.18 B
0.25 A
22
18
14
5
9
13
1.4
ø1
7.75 -0.25
0.3
30˚
B
0.2 +0.1
3.75 -0.5
0.8 min
2.75
0.6
Plastic Package, P-SOJ-26/20-2 (SMD)
(Plastic small outline J-leaded)
1
1
17.27 -0.25
A
Index Marking
GPJ09100
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
Semiconductor Group
25
Dimensions in mm
1998-10-01