INFINEON HYB18T256324F-20

Data Sheet, Rev. 1.11, April 2005
HYB18T256324F–16
HYB18T256324F–20
HYB18T256324F–22
256-Mbit GDDR3 DRAM [600MHz]
RoHS compliant
Memory Products
N e v e r
s t o p
t h i n k i n g .
Edition 04-2005
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2005.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Under no circumstances may the Infineon Technologies product as referred to in this data sheet be used in
1. Any applications that are intended for military usage (including but not limited to weaponry), or
2. Any applications, devices or systems which are safety critical or serve the purpose of supporting, maintaining,
sustaining or protecting human life (such applications, devices and systems collectively referred to as "Critical
Systems"), if
a) A failure of the Infineon Technologies product can reasonable be expected to - directly or indirectly (i) Have a detrimental effect on such Critical Systems in terms of reliability, effectiveness or safety; or
(ii) Cause the failure of such Critical Systems; or
b) A failure or malfunction of such Critical Systems can reasonably be expected to - directly or indirectly (i) Endanger the health or the life of the user of such Critical Systems or any other person; or
(ii) Otherwise cause material damages (including but not limited to death, bodily injury or significant
damages to property, whether tangible or intangible).
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
HYB18T256324F–16 HYB18T256324F–20 HYB18T256324F–22
Revision History:
Rev. 1.11
Previous Revision:
Rev. 1.0
04-2005
Page
Subjects (major changes since last revision)
2
added disclaimer
30
figure 11: note 1 changed
75
table 41: added currents for -16
79
table 42-44: new values
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
[email protected]
Data Sheet
3
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2
2.1
2.2
2.3
2.3.1
2.3.2
2.4
2.4.1
2.4.2
2.4.3
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ball Definition and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description of Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
State Diagram and Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
State Diagram for One Activated Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Function Truth Table for more than one Activated Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Function Truth Table for CKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
12
14
15
15
16
19
19
20
21
3
3.1
3.2
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
3.5
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.5.6
3.6
3.7
3.7.1
3.7.2
3.7.3
3.7.3.1
3.7.3.2
3.7.4
3.7.5
3.7.6
3.7.7
3.7.8
3.8
3.8.1
3.8.2
3.8.3
3.8.3.1
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clocks, CKE, Commands and Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programmable impedance output drivers and active terminations . . . . . . . . . . . . . . . . . . . . . . . . . . .
GDDR3 IO Driver and Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Self Calibration for Driver and Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dynamic Switching of DQ terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output impedance and Termination DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Mode Register Set Command (EMRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DLL enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Termination Rtt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Driver Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Vendor Code and Revision Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode Register Set Command (MRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DLL Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bank / Row Activation (ACT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Writes (WR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Basic Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write - Basic Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write - Consecutive Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gapless Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bursts with Gaps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write with Autoprecharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write followed by Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write followed by DTERDIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write with Autoprecharge followed by Read / Read with Autoprecharge . . . . . . . . . . . . . . . . . . . .
Write followed by Precharge on same Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reads (RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read - Basic Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read - Basic Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Consecutive Read Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gapless Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
22
23
24
24
25
26
27
28
29
29
29
29
30
30
31
32
32
33
33
33
33
34
35
35
38
39
39
40
41
42
43
44
45
46
46
48
49
49
Data Sheet
4
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
3.8.3.2
3.8.3.3
3.8.4
3.8.5
3.8.6
3.9
3.9.1
3.9.2
3.10
3.11
3.12
3.12.1
3.12.2
3.13
Bursts with Gaps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read followed by DTERDIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read with Autoprecharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read followed by Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read followed by Precharge on the same Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Termination Disable (DTERDIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DTERDIS followed by READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DTERDIS followed by Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Precharge (PRE/PREALL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Auto Refresh Command (AREF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Self-Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Self-Refresh Entry (SREFEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Self-Refresh Exit (SREFEX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
51
52
53
54
55
57
58
59
61
62
62
63
64
4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.7.1
4.8
4.9
4.10
4.11
4.11.1
4.12
4.13
4.14
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Power & DC Operation Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC & AC Logic Input Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential Clock DC and AC Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Driver current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Driver IV characteristics at 40 Ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Termination IV Characteristic at 60 Ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Termination IV Characteristic at 120 Ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Termination IV Characteristic at 240 Ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Current Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Current Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Summary of timing parameters for –1.6, –2.0 and –2.2 ns speed sorts in DLL on mode . . . . . . . . .
AC Characteristics and Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
65
65
66
67
67
68
68
69
69
70
71
72
73
73
73
75
77
5
5.1
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Data Sheet
5
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
Table 29
Table 30
Table 31
Table 32
Table 33
Table 34
Table 35
Table 36
Table 37
Table 38
Table 39
Table 40
Table 41
Table 42
Table 43
Table 44
Table 45
Table 46
Table 47
Data Sheet
Key Timing and Power Supply Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Ball description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Command Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Description of Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Minimum delay from RD/A and WR/A to any other command (to another bank) with concurrent
Autoprecharge 18
Function Truth Table I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Function Truth Table II (CKE Table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
General Timing Parameters for –1.6, –2.0 and –2.2 speed sorts. . . . . . . . . . . . . . . . . . . . . . . . . 22
Reset Timing Parameters for –1.6, –2.0 and –2.2 speed sorts . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Range of external resistance ZQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Termination types and activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Termination update Keep Out time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Number of Legs used for Terminator and Driver Self Calibration . . . . . . . . . . . . . . . . . . . . . . . . . 25
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
EMRS Timing Parameters for –1.6, –2.0 and –2.2 speed sorts . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Revision ID and Vendor Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Vendor Code and Revision ID Timing Parameters for –1.6, –2.0 and –2.2 speed sorts . . . . . . . 30
MRS Timing Parameters for –1.6, –2.0 and –2.2 speed sorts . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
ACT Timing Parameters for –1.6, –2.0 and –2.2 speed sorts . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Mapping of WDQS and DM signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
WR Timing Parameters for –1.6, –2.0 and –2.2 speed sorts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
WL / CL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
READ Timing Parameters for –1.6, –2.0 and –2.2 speed sorts . . . . . . . . . . . . . . . . . . . . . . . . . . 47
BA1, BA0 precharge bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Precharge Timing Parameters for –1.6, –2.0 and –2.2 speed sorts . . . . . . . . . . . . . . . . . . . . . . . 60
Autorefresh Timing Parameters for –1.6, –2.0 and –2.2 speed sorts . . . . . . . . . . . . . . . . . . . . . . 61
Self Refresh Exit Timing Parameter for –1.6, –2.0 and –2.2 speed sorts. . . . . . . . . . . . . . . . . . . 63
Power Down Exit Timing Parameter for –1.6, –2.0 and –2.2 speed sorts . . . . . . . . . . . . . . . . . . 64
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Power & DC Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
DC & AC Logic Input Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Differential Clock DC and AC Input conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Programmed Driver IV Characteristics at 40 Ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Programmed Terminator Characterisitc at 60 Ohm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Programmed Terminator Characterisitics at 120 Ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Programmed Terminator Characterisitc at 240 Ohm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Operating Current Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Operating Current Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Timing Parameters for –1.6, –2.0 and –2.2 speed sorts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
HYB18T256324F–16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
HYB18T256324F–20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
HYB18T256324F–22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
P-FBGA 144 Package Thermal Resitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
Figure 36
Figure 37
Figure 38
Figure 39
Figure 40
Figure 41
Figure 42
Figure 43
Figure 44
Figure 45
Figure 46
Figure 47
Figure 48
Figure 49
Figure 50
Figure 51
Figure 52
Figure 53
Figure 54
Figure 55
Data Sheet
Standard Ballout 256-Mbit GDDR3 DRAM [600MHz]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
State diagram for one bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock, CKE and Command/Address Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Driver simplified schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Termination update keep out time after Autorefresh command . . . . . . . . . . . . . . . . . . . . . . . . . . .
Self Calibration of PMOS and NMOS Legs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ODT Disable Timing during a READ command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Mode Register Bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Mode Register Bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Mode Register Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing of Vendor Code and Revision ID generation on DQ[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode Register Set Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode Register Bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode Register Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Activating a specific row . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bank Activation timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Basic Write Burst / DM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Burst Basic Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gapless Write Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Consecutive Write Bursts with Gaps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write with Autoprecharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write followed by Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Command followed by DTERDIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write with Autoprecharge followed by Read or Read with Autoprecharge on another bank . . . . .
Write followed by Precharge on same Bank. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Basic Read Burst Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gapless Consecutive Read Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Consecutive Read Bursts with Gaps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Command followed by DTERDIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read with Autoprecharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read followed by Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read followed by Precharge on the same Bank. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Termination Disable Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DTERDIS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DTERDIS followed by DTERDIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DTERDIS Command followed by READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DTERDIS Command followed by Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Precharge Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Precharge Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Auto Refresh Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Auto Refresh Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Self Refresh Entry Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Self Refresh Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Self Refresh Exit Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Self Refresh Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Down Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40 Ohm Driver Pull-Down and Pull-Up characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
60 Ohm Active Termination Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
11
14
19
22
23
24
25
26
27
28
28
29
30
31
31
32
34
34
35
36
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
55
56
57
58
59
60
61
61
62
62
63
63
64
64
68
69
70
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Figure 56
Figure 57
Figure 58
Data Sheet
120 Ohm Active Termination Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
240 Ohm Active Termination Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Package Outline FBGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
8
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
256-Mbit GDDR3 DRAM [600MHz]
1
Overview
1.1
Features
•
•
•
•
•
•
•
•
•
•
•
•
HYB18T256324F–16
HYB18T256324F–20
HYB18T256324F–22
Maximum clock frequency of 600 MHz
Organization: 2048K x 32 x 4 banks
4096 rows and 512 columns (128 burst start
locations) per bank
Differential clock inputs (CLK and CLK)
CAS latencies of 5, 6 and 7
Write latencies of 2, 3, 4
Fixed burst sequence with length of 4.
4n prefetch
Short RAS to CAS timing for Writes
tRAS Lockout support
tWR programmable for Writes with Auto-Precharge
Data mask for write commands
Table 1
•
•
•
•
•
•
•
•
•
Single ended READ strobe (RDQS) per byte.
RDQS edge-aligned with READ data
Single ended WRITE strobe (WDQS) per byte.
WDQS center-aligned with WRITE data
DLL aligns RDQS and DQ transitions with Clock
Programmable IO interface including on chip
termination (ODT)
Autoprecharge option with concurrent
autoprecharge support
4K Refresh (32ms)
Autorefresh and Self Refresh
P-TBGA 144 package (11mm × 11mm)
VDD / VDDQ Voltage (according to Table 1)
Calibrated output drive. Active termination support.
Key Timing and Power Supply Parameters
Speed Sort
Power Supply
CAS latency = 7
CAS latency = 6
CAS latency = 5
Access Time
RDQS-DQ Skew
Data Sheet
•
VDD / VDDQ
tCK7 min
fCK7 max
tCK6 min
fCK6 max
tCK5 min
fCK5 max
tACmin
tACmax
tDQSQ
–1.6
- 2.0
- 2.2
Units
2.0 ± 100 mV
2.0 ± 100 mV
2.0 ± 100 mV
V
1.6
2.0
2.2
ns
600
500
455
MHz
2.0
2.0
2.2
ns
500
500
455
MHz
—
—
2.7
ns
—
—
370
MHz
–0.4
–0.4
–0.45
ns
0.4
0.4
0.45
ns
0.225
0.225
0.25
ns
9
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Overview
Table 2
Ordering Information
Part Number1)
Organisation
VDD / VDDQ (V)
Clock (MHz) Package
HYB18T256324F–16
×32
2.0
600
HYB18T256324F–20
2.0
500
HYB18T256324F–22
2.0
455
P-TBGA 144
1) HYB: designator for memory components
256: 256-Mbit density
32: 32 bit interface
4: Die Revision
F: Green Product
1.2
General Description
Read and write accesses to the HYB18T256324F–
[16/20/22] are burst oriented. The burst length is fixed
to 4 and the two least significant bits of the burst
address are ’Don’t Care’ and internally set to LOW.
Accesses begin with the registration of an ACTIVATE
command, which is then followed by a READ or WRITE
command. The address bits registered coincident with
the ACTIVATE command are used to select the bank
and the row to be accessed. The address bits
registered coincident with the READ or WRITE
command are used to select the bank and the column
location for the burst access. Each of the 4 banks
consists of 4096 row locations and 512 column
locations. An AUTO PRECHARGE function can be
combined with READ and WRITE to provide a selftimed row precharge that is initiated at the end of the
burst access. The pipelined, multibank architecture of
the HYB18T256324F–[16/20/22] allows for concurrent
operation, thereby providing high effective bandwidth
by hiding row precharge and activation time.
The Infineon 256-Mbit GDDR3 DRAM [600MHz]is a
high speed memory device, designed for high
bandwidth intensive applications like PC graphics
systems. The chip’s quad bank architecture is
optimized for high speed and achieves a peak
bandwidth of 8 Gbyte/s using a 32 bit interface and a
maximum system clock of 600 MHz.
HYB18T256324F–[16/20/22] uses a double data rate
interface and a 4n-prefetch architecture. The GDDR3
interface transfers two 32 bit wide data words per clock
cycle to/from the I/O pins. Corresponding to the 4nprefetch a single write or read access consists of a 128
bit wide, one-clock-cycle data transfer at the internal
memory core and four corresponding 32 bit wide, onehalf-clock-cycle data transfers at the I/O pins.
Single-ended unidirectional Read and Write Data
strobes are transmitted simultaneously with Read and
Write data respectively in order to capture data properly
at the receivers of both the Graphics SDRAM and the
controller. Data strobes are organized per byte of the
32 bit wide interface. For read commands the RDQS
are edge-aligned with data, and the WDQS are centeraligned with data for write commands.
The device is supplied with 2.0 V for output drivers and
core. (VDD / VDDQ voltages see Table 1)
The “On Die Termination” interface (ODT) is optimized
for high frequency digital data transfers and is internally
controlled. The termination resistor value can be set
using an external ZQ resistor or disabled through the
Extended Mode Register.
The HYB18T256324F–[16/20/22] operates from a
differential clock (CLK and CLK). Commands
(addresses and control signals) are registered at every
positive edge of CLK. Input data is registered on both
edges of WDQS, and output data is referenced to both
edges of RDQS.
The output driver impedance can be set using the
Extended Mode Register. It can either be set to ZQ / 6
(autocalibration) or to 35, 40 or 45 Ohms.
In this document references to ’the positive edge of
CLK’ imply the crossing of the positive edge of CLK and
the negative edge of CLK. Similarly, the ’negative edge
of CLK’ refers to the crossing of the negative edge of
CLK and the positive edge of CLK. References to
RDQS are to be interpreted as any or all RDQS<3:0>.
WDQS, DM and DQ should be interpreted in a similar
fashion.
Data Sheet
Auto Refresh and Power Down with Self Refresh
operations are supported.
A standard P-TBGA 144 package is used which
enables ultra high speed data transfer rates and a
simple upgrade path from former DDR Graphics
SDRAM products.
10
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Pin Configuration
2
Pin Configuration
!
7$1
3
2$1
3
6331
$1
$1
$1
$1
$1
$1
6331 2$1
3
7$1
3
"
$1
$-
6$$1
6$$1
$1
6$$1
6$$1
$1
6$$1
6$$1
$-
$1
#
$1
$1
6331
6331 6331 6$$
6$$
6331
6331 6331
$1
$1
$
$1
2&5
6$$
633
6331 633
633
6331
633
6$$
2&5
$1
%
$1
$1
6$$1
6331 THERM
THER M
633
6331 6$$1
$1
$1
&
$1
$1
6$$1
6331 THERM
THER M
633
6331 6$$1
$1
$1
'
7$1
3
2$1
3
6$$1
6331
THERM
THER M
633
6331 6$$1
2$1
3
7$1
3
(
$1
$-
6$$1
6331
THERM
THER M
THE
RM
THER M
633
6331 6$$1
$-
$1
*
$1
$1
6$$1
6331 633
633
633
633
6331 6$$1
$1
$1
+
$1
!
6$$
633
2&5
6$$
6$$
2&5
633
6$$
!
$1
,
62%& !
!
2!3
2%3%
4
#+%
2&5
:1
#3
!
!
62%&
-
!
!
!
"!
"!
!!0
!
!
633
633
633
633
633
THER M
633
THER M
633
THER M
633
#!3
#,+
633
THE
RM
633
THE
RM
633
THE
RM
633
#,+
7%
"
!,,0
4
&"'! 4/
0
6
)%7
Figure 1
Standard Ballout 256-Mbit GDDR3 DRAM [600MHz]
Note: Figure shows top view
Data Sheet
11
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Pin Configuration
2.1
Ball Definition and Description
Table 3
Ball description
Ball
Type
Detailed Function
CLK, CLK
Input
Clock: CLK and CLK are differential clock inputs. Address and command inputs are
latched on the positive edge of CLK. Graphics SDRAM outputs (RDQS, DQs) are
referenced to CLK. CLK and CLK are not internally terminated.
CKE
Input
Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal clock and
input buffers. Taking CKE LOW provides Power Down. If all banks are precharged, this
mode is called Precharge Power Down and Self Refresh mode is entered if a Autorefresh
command is issued. If at least one bank is open, Active Power Down mode is entered and
no Self Refresh allowed. All input receivers except CLK, CLK and CKE are disabled
during Power Down. In Self Refresh mode the clock receivers are disabled too. Self
Refresh Exit is performed by setting CKE asynchronously HIGH. Exit of Power Down
without Self Refresh is accomplished by setting CKE HIGH with a positive edge of CLK.
The value of CKE is latched asynchronously by Reset during Power On to determine the
value of the termination resistor of the address and command inputs.
CKE is not allowed to go LOW during a RD, a RW or a snoop BURST.
CS
Input
Chip Select: CS enables the command decoder when low and disables it when high.
When the command decoder is disabled, new commands with the exeption of DETERNIS
are ignored, but internal operations continue. CS is one of the four command balls.
RAS, CAS,
WE
Input
Command Inputs: Sampled at the positive edge of CLK, CAS, RAS, and WE define
(together with CS) the command to be executed.
DQ<0:31>
I/O
Data Input/Output: The DQ signals form the 32 bit data bus. During READs the balls are
outputs and during WRITEs they are inputs. Data is transferred at both edges of RDQS.
DM<0:3>
Input
Input Data Mask: The DM signals are input mask signals for WRITE data. Data is
masked when DM is sampled HIGH with the WRITE data. DM is sampled on both edges
of WDQS. DM0 is for DQ<0:7>, DM1 is for DQ<8:15>, DM2 is for DQ<16:23> and DM3
is for DQ<24:31>. Although DM balls are input-only, their loading is designed to match
the DQ and WDQS balls.
RDQS<0:3>
Output Read Data Strobes: RDQSx are unidirectional strobe signals. During READs the RDQSx
are transmitted by the Graphics SDRAM and edge-aligned with data. RDQS have
preamble and postamble requirements. RDQS0 is for DQ<0:7>, RDQS1 for DQ<8:15>,
RDQS2 for DQ<16:23> and RDQS3 for DQ<24:31>.
WDQS<0:3> Input
Write Data Strobes: WDQS are unidirectional strobe signals. During WRITEs the WDQS
are generated by the controller and center aligned with data. WDQS have preamble and
postamble requirements. WDQS0 is for DQ<0:7>, WDQS1 for DQ<8:15>, WDQS2 for
DQ<16:23> and WDQS3 for DQ<24:31>.
BA<0:1>
Input
Bank Address Inputs: BA select to which internal bank an ACTIVATE, READ, WRITE
or PRECHARGE command is being applied. BA are also used to distinguish between the
MODE REGISTER SET and EXTENDED MODE REGISTER SET commands.
A<0:11>
Input
Address Inputs: During ACTIVATE, A0-A11 defines the row address. For
READ/WRITE, A2-A7 and A9 defines the column address, and A8 defines the auto
precharge bit. If A8 is HIGH, the accessed bank is precharged after execution of the
column access. If A8 is LOW, AUTO PRECHARGE is disabled and the bank remains
active. Sampled with PRECHARGE, A8 determines whether one bank is precharged
(selected by BA<0:1>, A8 LOW) or all 4 banks are precharged (A8 HIGH). During
(EXTENDED) MODE REGISTER SET the address inputs define the register settings.
A<0:11> are sampled with the positive edge of CLK.
ZQ
-
ODT Impedance Reference: The ZQ ball is used to control the ODT impedance.
Data Sheet
12
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Pin Configuration
Table 3
Ball description
Ball
Type
RES
Input
Vref
VDD, VSS
VDDQ, VSSQ
Supply Voltage Reference: Vref is the reference voltage input.
NC, RFU
-
Data Sheet
Detailed Function
Reset pin: The RES pin is a VDDQ CMOS input. RES is not internally terminated. The
LOW to HIGH transition of the Reset signal is used to latch the CKE value during Power
On in order to set the value of the termination resistors of the address and command
inputs. When RES is LOW, all terminations are switched off. The LOW to HIGH transition
of the RES signal must occur at the beginning of the power up sequence in order to insure
functionnality.
Supply Power Supply: Power and Ground for the internal logic.
Supply I/O Power Supply: Isolated Power and Ground for the output buffers to provide improved
noise immunity.
Please do not connect No Connect and Reserved for Future Use balls.
13
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Pin Configuration
2.2
Functional Block Diagram
A0-A7,A9, A8/AP, A10-A11
BA0, BA1
Address buffer
A8/AP
Row Addresses A0-A11, BA0-BA1
Mode Register
Refresh
Counter
Column Addresses A2-A7,A9
Row Address Buffer
Column Address Buffer
4096 x 512
x 32 bit
Memory
Array
Bank 2
4096 x 512
x 32 bit
Column Decoder
Bank 1
Row Decoder
Sense Amplifiers and Data Bus Buffer
4096 x 512
x 32 bit
Memory
Array
Column Decoder
Bank 0
Row Decoder
Sense Amplifiers and Data Bus Buffer
Memory
Array
Column Decoder
RES
Row Decoder
Sense Amplifiers and Data Bus Buffer
WE#
Column Decoder
CAS#
Sense Amplifiers and Data Bus Buffer
RAS#
Control Logic & Timing Generator
CS#
Row Decoder
Memory
Array
Bank 3
4096 x 512
x 32 bit
ZQ
CKE
Figure 2
Data Sheet
Input Buffers
DQ0-DQ7
DQ8-DQ15
DQ16-DQ23
DQ24-DQ31
Data
RDQS3
WDQS3
DM3
Output Buffers
Data
RDQS2
WDQS2
DM2
DLL
Data
RDQS1
WDQS1
DM1
CLK#
Data
RDQS0
WDQS0
DM0
CLK
Functional Block Diagram
14
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Pin Configuration
2.3
Commands
2.3.1
Command Table
In the following table CKEn refers to the positive edge of CLK corresponding to the clock cycle when the command
is given to the Graphics SDRAM. CKEn-1 refers to the previous positive edge of CLK. For all command and
address inputs CKEn is implied.
All input states or sequences not shown are illegal or reserved.
Table 4
Command Overview
Operation
Code
CKE CKE CS
n-1 n
RAS CAS WE
BA0 BA1 A8
A2-7 Note
A9-11
Device Deselect
DESEL
H
H
H
L
X
H
X
X
H
X
L
H
X
X
X
X
1
Data Terminator Disable
DTERDIS H
H
H
H
L
H
X
X
X
X
1,9
No Operation
NOP
H
H
L
H
H
H
X
X
X
X
Mode Register Set
MRS
H
H
L
L
L
L
0
0
OPCODE
Extended Mode Register
Set
EMRS
H
H
L
L
L
L
1
0
OPCODE
Bank Activate
ACT
H
H
L
L
H
H
BA
BA
Row
Address
1,2
Read
RD
H
H
L
H
L
H
BA
BA
L
Col.
1,3
Read w/ Autoprecharge
RD/A
H
H
L
H
L
H
BA
BA
H
Col.
1,3
Write
WR
H
H
L
H
L
L
BA
BA
L
Col.
1,3
Write w/ Autoprecharge
WR/A
H
H
L
H
L
L
BA
BA
H
Col.
1,3
Precharge
PRE
H
H
L
L
H
L
BA
BA
L
X
1
Precharge All
PREALL
H
H
L
L
H
L
X
X
H
X
1
Auto Refresh
AREF
H
H
L
L
L
H
X
X
X
X
1,4
Power Down Mode Entry
PWDNEN H
L
H
L
X
H
X
H
X
H
X
X
X
X
1,5
Power Down Mode Exit
PWDNEX L
H
X
X
X
X
X
X
X
X
1,6
Self Refresh Entry
SREFEN
H
L
L
L
L
H
X
X
X
X
1,7
Self Refresh Exit
SREFEX
L
H
X
X
X
X
X
X
X
X
1,8
1. X represents “Don’t Care”.
2. BA0 and BA1 provide bank address, A0 - A11
provide the row address.
3. BA0 and BA1 provide bank address, A2- A7, A9
provide the column address, A8/AP controls Auto
Precharge.
4. Auto Refresh and Self Refresh Entry differ only by
the state of CKE
5. PWDNEN is selected by issuing a DESEL or NOP
at the first positive CLK edge following the HIGH to
LOW transition of CKE.
6. First possible valid command after tXPN. During tXPN
only NOP or DESEL commands are allowed.
Data Sheet
7. Self Refresh is selected by issuing AREF at the first
positive CLK edge following the HIGH to LOW
transition of CKE.
8. First possible valid command after tXSC. During tXSC
only NOP or DESEL commands are allowed.
9. This command is invoked when a Read is issued on
another DRAM rank placed on the same command
bus. Cannot be in power-down or self-refresh state.
The Read command will cause the data termination
to be disabled. Refer to for timing.
Abbreviations:
BA:Bank Address
Col.:Column Address
15
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Pin Configuration
2.3.2
Description of Commands
Table 5
Description of Commands
Command
Description
DESEL
The DESEL function prevents new commands from being executed by the Graphics SDRAM. The
Graphics SDRAM is effectively deselected. Operations in progress are not affected.
NOP
The NOP command is used to perform a no operation to the Graphics SDRAM, which is selected
(CS is LOW). This prevents unwanted commands from being registered during idle or wait states.
Operations already in progress are not affected.
MRS
The Mode Register is loaded via address inputs A0 - A11. For more details see sections
Chapter 3.5. The MRS command can only be issued when all banks are idle and no bursts are in
progress. A subsequent executable command cannot be issued until tMRD is met.
EMRS
The Extended Mode Register is loaded via address inputs A0 - A11. For more details see section
Chapter 3.4. The EMRS command can only be issued when all banks are idle and no bursts are in
progress. A subsequent executable command cannot be issued until tMRD is met.
ACT
The ACT command is used to open (or activate) a row in a particular bank for a subsequent access.
The value on the BA0 and BA1 inputs selects the bank, and the address provided in inputs A0 - A11
selects the row. This row remains active (or open) for accesses until a precharge (PRE, RD/A, or
WR/A command) is issued to that bank. A precharge must be issued before opening a different row
in the same bank.
RD
The RD command is used to initiate a burst read access to an active row. The value on the BA0 and
BA1 inputs selects the bank, and the address provided on inputs A2-A7, A9 selects the column
location. The row will remain open for subsequent accesses. For RD commands the value on A8 is
set LOW.
RD/A
The RD/A command is used to initiate a burst read access to an active row. The value on the BA0
and BA1 inputs selects the bank, and the address provided on inputs A2-A7, A9 selects the column
location. The value on input A8 is set HIGH. The row being accessed will be precharged at the end
of the read burst. The same individual-bank precharge function is performed like it is described for
the PRE command. Auto precharge ensures that the precharge is initiated at the earliest valid stage
within the burst. The user must not issue a new ACT command to the same bank until the precharge
time (tRP) is completed. This time is determined as if an explicit PRE command was issued at the
earliest possible time as described in section Chapter 3.10.
WR
The WR command is used to initiate a burst write access to an active row. The value on the BA0
and BA1 inputs selects the bank, and the address provided on inputs A2-A7, A9 selects the column
location. The row will remain open for subsequent accesses. For WR commands the value on A8 is
set LOW.
Input data appearing on the DQs is written to the memory array depending on the value on the DM
input appearing coincident with the data. If a given DM signal is registered LOW, the corresponding
data will be written to the memory; if the DM signal is registered HIGH, the corresponding data inputs
will be ignored, and a write will not be executed for that byte / column location.
WR/A
The WR/A command is used to initiate a burst write access to an active row. The value on the BA0
and BA1 inputs selects the bank, and the address provided on inputs A2-A7, A9 selects the column
location. The value on input A8 is set HIGH. The row being accessed will be precharged at the end
of the write burst. The same individual-bank precharge function is performed which is described for
the PRE command. Auto precharge ensures that the precharge is initiated at the earliest valid stage
within the burst. The user is not allowed to issue a new ACT to the same bank until the precharge
time (tRP) is completed. This time is determined as if an explicit PRE command was issued at the
earliest possible time as described in section Chapter 3.7.
Input data appearing on the DQs is written to the memory array depending on the DM input logic
level appearing coincident with the data. If a given DM signal is registered LOW, the corresponding
data will be written to the memory; if the DM signal is registered HIGH, the corresponding data inputs
will be ignored, and a write will not be executed to that byte / column location.
Data Sheet
16
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Pin Configuration
Table 5
Description of Commands
Command
Description
PRE
The PRE command is used to deactivate the open row in a particular bank. The bank will be
available for a subsequent row access a specified time (tRP) after the PRE command is issued.
Inputs BA0 and BA1 select the bank to be precharged. A8/AP is set to LOW. Once a bank has been
precharged, it is in the idle state and must be activated again prior to any RD or WR commands
being issued to that bank. A PRE command will be treated as a NOP if there is no open row in that
bank, or if the previously open row is already in the process of precharging.
PREALL
The PREALL command is used to deactivate all open rows in the memory device. The banks will
be available for a subsequent row access a specified time (tRP) after the PREALL command is
issued. Once the banks have been precharged, they are in the idle state and must be activated prior
to any read or write commands being issued. The PREALL command will be treated as a NOP for
those banks where there is no open row, or if a previously open row is already in the process of
precharging. PREALL is issued by a PRE command with A8/AP set to HIGH.
AREF
The AREF is used during normal operation of the GDDR3 Graphics RAM to refresh the memory
content. The refresh addressing is generated by the internal refresh controller. This makes the
address bits “Don’t Care” during an AREF command. The HYB18T256324F–[16/20/22] requires
AREF cycles at an average periodic interval of tREFI(max)=7.8µs. To improve efficiency a maximum
number of eight AREF commands can be posted to one memory device (with tRFC from AREF to
AREF) as described in section Chapter 3.11. This means that the maximum absolute interval
between any AREF command is 8 x 7.8µs (62.4µs). This maximum absolute interval is to allow the
GDDR3 Graphics RAM output drivers and internal terminators to recalibrate, compensating for
voltage and temperature changes. All banks must be in the idle state before issuing the AREF
command. They will be simultaneously refreshed and return to the idle state after AREF is
completed. tRFC is the minimum required time between an AREF command and a following
ACT/AREF command.
SREFEN
The Self Refresh function can be used to retain data in the GDDR3 Graphics RAM even if the rest
of the system is powered down. When entering the self refresh mode by issuing the SREFEN
command, the GDDR3 Graphics RAM retains data without external clocking. The SREFEN
command is initiated like an AREF command except CKE is disabled (LOW). The DLL is
automatically disabled upon entering Self Refresh mode and automatically enabled and reset upon
exiting Self Refresh. (200 cycles must then occur before a RD command can be issued) The adress,
command and data terminators remain on input signals except CKE are “Don’t Care”. If two GDDR3
Graphics RAMs share the same cimmand and address bus, Self Refresh max be entered only for
the two devices at the sme time.
SREFEX
The SREFEX command is used to exit the self refresh mode. The DLL is automatically enabled and
resetted upon exiting. The procedure for exiting self refresh requires a sequence of commands. First
CLK and CLK must be stable prior to CKE going from LOW to HIGH. Once CKE is HIGH, the
GDDR3 Graphics RAM must receive only NOP/DESEL commands until tXSNR is satisfied. This time
is required for the completion of any internal refresh in progress. A simple algorithm for meeting both
refresh, DLL requirements and output calibration is to apply NOPs for 200 cycles before applying
any other command to allow the DLL to lock and the output drivers to recalibrate.
PWDNEN
The PWDNEN command enables the power down mode. It is entered when CKE is set low together
with a NOP/DESEL. The CKE signal is sampled at the rising edge of the clock. Once the power
down mode is initiated, all of the receiver circuits except CLK and CKE are gated off to reduce power
consumption. The DLL remains active (unless disabled before with EMRS). All banks can be set to
idle state or stay active. During Power Down Mode, refresh operations cannot be performed;
therefore the refresh conditions of the chip have to be considered and if necessary Power Down
state has to be left to perform an Autorefresh cycle.
Data Sheet
17
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Pin Configuration
Table 5
Description of Commands
Command
Description
PWDNEX
A CKE HIGH value sampled at a low to high transition of CLK is required to exit power down mode.
Once CKE is HIGH, the GDDR3 Graphics RAM must receive only NOP/DESEL commands until tXPN
is satisfied. After tXPN any command can be issued, but it has to comply with the state in which the
power down mode was entered.
DTERDIS
Data Termination Disable (Bus snooping for RD commands) : The Data Termination Disable
Command is detected by the device by snooping the bus for RD commands excluding CS. The
GDDR3 Graphics RAM will disable its Data terminators when a RD command is detected. The
terminators are disabled starting at CL - 1 clocks after the RD command is detected and the duration
is 4 clocks. In a two rank system, both DRAM devices will snoop the bus for RD commands to either
device and both will disable their terminators if a RD command is detected. The command and
address terminators are always enabled. See Figure 9 for an example of when the data terminators
are disabled during a RD command.
Table 6
Minimum delay from RD/A and WR/A to any other command (to another bank) with concurrent
Autoprecharge
From Command
To Command
Minimum delay to another bank
(with concurrent autoprecharge)
WR/A
RD or RD/A
(WL + 2) . tCK + tWTR
WR or WR/A
2 . tCK
PRE
tCK
ACT
tCK
RD or RD/A
2 . tCK
WR or WR/A
(CL + 4 - WL) . tCK
PRE
tCK
ACT
tCK
RD/A
Data Sheet
18
Note
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Pin Configuration
2.4
State Diagram and Truth Tables
2.4.1
State Diagram for One Activated Bank
The following diagram shows all possible states and transitions for one activated bank. The other three banks of
the Graphics SDRAM are assumed to be in idle state.
single bank
WR
ACT
RD
ACTIVE
PRE
WR/A
RD/A
PDEN
PDEX
MRS
EMRS
IDLE
PDEN
AUTO
REFRESH
PDEX
active
POWER DOWN
precharge
SREX
SREN
SELF
REFRESH
all banks
Figure 3
State diagram for one bank
Note: MRS, EMRS, AUTO REFRESH, SELF REFRESH and precharge POWER DOWN are only allowed if all four
banks are idle.
Data Sheet
19
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Pin Configuration
2.4.2
Function Truth Table for more than one Activated Bank
submitted command. This table is based on the
assumption that there are no other actions ongoing on
bank n or bank m. If there are any actions ongoing on a
third bank tRRD, tRTW and tWTR have to be taken always
into account.
If there is more than one bank activated in the Graphics
SDRAM, some commands can be performed in parallel
due to the chip’s multibank architecture. The following
table defines for which commands such a scheme is
possible. All other transitions are illegal. Notes 1-11
define the start and end of the actions belonging to a
Table 7
Function Truth Table I
Current
State
ongoing action on bank n
possible action in parallel on bank m
ACTIVE
ACTIVATE 1
ACT, PRE, WRITE, WRITE/A, READ, READ/A 12
WRITE 2
ACT, PRE, WRITE, WRITE/A, READ, READ/A13
WRITE/A 3
ACT, PRE, WRITE, WRITE/A, READ 14
READ 4
ACT, PRE, WRITE, WRITE/A, READ, READ/A15
READ/A 5
ACT, PRE, WRITE, WRITE/A, READ, READ/A 15
PRECHARGE 6
ACT, PRE, WRITE, WRITE/A, READ, READ/A 12
PRECHARGE ALL 6
-
POWER DOWN ENTRY 7
-
IDLE
ACTIVATE
1
ACT
POWER DOWN ENTRY
AUTO REFRESH
7
-
8
-
SELF REFRESH ENTRY
7
-
MODE REGISTER SET (MRS)
EXTENDED MRS
9
9
10
POWER DOWN
POWER DOWN EXIT
SELF REFRESH
SELF REFRESH EXIT 11
-
1. Action ACTIVATE starts with issuing the command
and ends after tRCD
2. Action WRITE starts with issuing the command and
ends tWR after the first pos. edge of CLK following
the last falling WDQS edge; exept for READ,
READ/A. WRITE, WRITE/A ends tWTR after the first
pos. edge of CLK following the last falling WDQS
edge.
3. Action WRITE/A starts with issuing the command
and ends tWR after the first positive edge of CLK
following the last falling WDQS edge; exept for
READ, READ/A. WRITE, WRITE/A ends tWTR after
the first pos. edge of CLK following the last falling
WDQS edge.
4. Action READ starts with issuing the command and
ends with the first positive edge of CLK following the
last falling edge of RDQS
5. Action READ/A starts with issuing the command
and ends with the first positive edge of CLK
following the last falling edge of RDQS
6. Action PRECHARGE and PRECHARGE ALL start
with issuing the command and ends after tRP
Data Sheet
-
7. During POWER DOWN and SELF REFRESH only
the EXIT commands are allowed
8. Action AUTO REFRESH starts with issuing the
command and ends after tRFC
9. Actions MODE REGISTER SET and EXTENDED
MODE REGISTER SET start with issuing the
command and ends after tMRD
10. Action POWER DOWN EXIT starts with issuing the
command and ends after tXPN
11. Action SELF REFRESH EXIT starts with issuing the
command and ends after tXSC
12. During action ACTIVATE an ACT command on
another bank is allowed considering tRRD, a PRE
command on another bank is allowed any time.
WR, WR/A, RD and RD/A are always allowed.
13. During action WRITE an ACT or a PRE command
on another bank is allowed any time. A new WR or
WR/A command on another bank must be
separated by at least one NOP from the ongoing
WRITE. RD or RD/A are not allowed before tWTR is
met.
20
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Pin Configuration
14. During action WRITE/A an ACT or a PRE command
on another bank is allowed any time. A new WR or
WR/A command on another bank has to be
separated by at least one NOP from the ongoing
command. RD is not allowed before tWTR is met.
RD/A is not allowed during an ongoing WRITE/A
action.
2.4.3
Function Truth Table for CKE
Table 8
Function Truth Table II (CKE Table)
15. During action READ and READ/A an ACT or a PRE
command on another bank is allowed any time. A
new RD or RD/A command on another bank has to
be separated by at least one NOP from the ongoing
command. A WR or WR/A command on another
bank has to meet tRTW.
CKE
n-1
CKE
n
CURRENT STATE
COMMAND
ACTION
L
L
Power Down
X
stay in Power Down
Self Refresh
X
stay in Self Refresh
Power Down
DESEL or NOP
Exit Power Down
Self Refresh
DESEL or NOP
Exit Self Refresh 5
L
H
H
L
All Banks Idle
DESEL or NOP
Entry Precharge Power Down
Bank(s) Active
DESEL or NOP
Entry Active Power Down
All Banks Idle
Auto Refresh
Entry Self Refresh
4. All states and sequences not shown are illegal or
reserved.
5. DESEL or NOP commands should be issued on
any clock edges occuring during the tXSR period. A
minimum of 200 clock cycles is required before
applying any other valid command.
1. CKEn is the logic step at clock edge n; CKEn-1 was
the state of CKE at the previous clock edge.
2. Current state is the state of the GDDR3 Graphics
RAM immediatly prior to clock edge n.
3. COMMAND is the command registered at clock
edge n, and ACTION is a result of COMMAND.
Data Sheet
21
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
3
Functional Description
3.1
Clocks, CKE, Commands and Addresses
T#+
T#,
T#(
#,+
#,+
T)07
#-$
!$$
2
#+%
6ALID
6ALID
6ALID
$ON
gT#A
R E
T)3
Figure 4
T)(
Clock, CKE and Command/Address Timings
Setup and Hold Timing for CKE is equal to CMD and ADDR Setup and Hold Timing. The DLL ensures the
alignment of DQs and CLK. Therefore the preferred operation mode for high frequencies is DLL on. The DLL
frequency range is from 600 MHz down to 250 MHz.
Table 9
General Timing Parameters for –1.6, –2.0 and –2.2 speed sorts
Parameter
CAS
Symbol
latency
Limit Values
–1.6
Unit
–2.0
–2.2
min
max
min
max
min
max
1.6
3.3
2.0
4.0
2.2
4.0
ns
2.0
3.3
2.0
4.0
2.2
4.0
ns
—
—
—
—
2.7
4.0
ns
300
600
250
500
250
455
MHz
300
500
250
500
250
455
MHz
—
—
—
—
250
370
MHz
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
tCK
Clock
Clock Cycle Time
7
6
5
System frequency
7
6
5
Clock high level width
Clock low-level width
tCK7
tCK6
tCK5
fCK7
fCK6
fCK5
tCH
tCL
Command, CKE and Address Setup and Hold Times
tIS
0.6
—
0.75
—
0.75
—
ns
Address/Command/CKE input hold time tIH
0.6
—
0.75
—
0.75
—
ns
0.85
—
0.85
—
0.85
—
tCK
Address/Command/CKE input setup
time
Address/Command/CKE input pulse
width
Data Sheet
tIPW
22
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
3.2
Initialization
The HYB18T256324F–[16/20/22] must be powered up and initialized in a predefined manner. Operational
procedures other than those specified may result in undefined operation or permanent damage to the device.
The following sequence is highly recommended for Power-Up:
1. Apply power (VDD, VDDQ, VREF). Apply VDD before or at the same time as VDDQ, apply VDDQ before or at the same
time as VREF. Maintain RES=L and CS=H to ensure that all the DQ ouputs will be in HiZ state, all active
terminations off and the DLL off. All other pins may be undefined.
2. Maintain stable conditions for 200 µs minimum for the GDDR3 Graphics RAM to power up.
3. After clock is stable, set CKE to L. After tATS minimum set RES to high. On the rising edge of RES, the CKE
value is latched to determine the address and command bus termination value. If CKE is sampled LOW the
address termination value is set to ZQ / 2. If CKE is sampled HIGH, the address and command bus termination
is set to ZQ.
4. After tATH minimum, set CKE to high.
5. Wait a minimum of 350 cycles to calibrate and update the address and command termination impedances.
Issue DESELECT on the command bus during these 350 cycles.
6. Apply a PRECHARGE ALL command, followed by an Extended Mode Register command after tRP is met and
activate the DLL.
7. Issue an Mode Register Set command after tMRD is met to reset the DLL and define the operating parameters.
8. Wait 200 cycles of clock input to lock the DLL. No Read command can be applied during this time. Since the
impedance calibration is already completed, the DLL mimic circuitry can use the actual programmed driver
impedance value.
9. Issue a PRECHARGE ALL command or issue 4 single bank PRECHARGE commands, one to each of the 4
banks to place the chip in an idle state.
10. Issue two or more AUTO REFRESH commands to update the driver impedance.
6$$
6$$1
62%
&
T!43 T!4(
2%3
#+%
#,+
#,+
$%3
$%3
#OM
MIN —
S
%-
2
0!
T20
MIN CYCLES
-23
T-2$ T-2$
T 20
-23
-23
C OM
M
AND
W
ITH
$,
,
2E
SE
T
%-2 %
-2
3
C O
MMA
ND
$%3
$
ES E
LE
CT
Figure 5
Power Up Sequence
Table 10
Reset Timing Parameters for –1.6, –2.0 and –2.2 speed sorts
Symbol
RES to CKE hold time
Data Sheet
T2&# tATS
tATH
0! 0
2
%
!
,,
C OM
MAN
D
!2&
!5
4
/
2
%
&2
%
3
(
CO
MM
AND
!# !
N
YC OMM
AN
D
$ONgT#
A
RE
Limit Values
–1.6
RES to CKE setup time
T2&#
!#
MIN CYCLES
6$$
AND
#,+STA
BLE
Parameter
!2&
!2&
0!
Unit
–2.0
–2.2
min
max
min
max
min
max
10
—
10
—
10
—
ns
10
—
10
—
10
—
ns
23
Notes
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
3.3
Programmable impedance output drivers and active terminations
3.3.1
GDDR3 IO Driver and Termination
DM<0:3>. The two termination values that are
selectable using EMRS[3:2] are ZQ / 4 and ZQ / 2.
The GDDR3 SGRAM is equipped with programmable
impedance output buffers and active terminations. This
allows the user to match the driver impedance to the
system impedance.
The value of ZQ is also used to calibrate the internal
address command termination resistors. The inputs
terminated in this manner are A<0:11>, CKE, CS, RAS,
CAS, WE. The two termination values that are
selectable upon power up (CKE latched a the LOW to
HIGH transition of RES) are ZQ/2 and ZQ.
To adjust the impedance of DQ<0:31> and
RDQS<0:3> , an external precision resistor (ZQ) is
connected between the ZQ pin and VSS. The value of
the resitor must be six times the value of the desired
impedance. For example, a 240Ω resistor is required
for an output impedance of 40Ω. The range of ZQ is
210Ω to 270Ω, giving an output impedance range of
35Ω to 45Ω (one sixth the value of ZQ within 10%).
RES, CLK and CLK are not internally terminated.
The signals RES and CLK/CLK are not internally
terminated.
If no resistance is connected to ZQ, an internal default
value of 240Ω will be used. In this case, no calibration
will be performed.
The value of ZQ is used to calibrate the internal DQ
termination resistors of DQ<0:31>, WDQS<0:3> and
VDDQ
ZQ/4 or ZQ/2
Terminator when
receiving
Read to
other Rank
Output Data
Read Data
Enable
DQ
ZQ/6 Driver
when transmitting
VSSQ
Figure 6
Output Driver simplified schematic
Table 11
Range of external resistance ZQ
Parameter
Symbol
min
nom
max
Unit
External resistance value
ZQ
210
240
270
Ω
Table 12
Notes
Termination types and activation
Ball
Termination type
Termination activation
CLK, CLK, RDQS<0:3>, ZQ, RES
No termination
CKE, CS, RAS, CAS, WE, BA<0:1>, A<0:11>
Add / CMDs
Always ON
DM<0:3>, WDQS<0:3>,
DQ
Always ON
DQ<0:31>
DQ
CMD bus snooping
Data Sheet
24
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
3.3.2
Self Calibration for Driver and Termination
#,+
#,+
#OM
!2&
./0
!DD
$1
!2&!UTOREFRESH
T
+/
$ONgT#ARE
+EEP/UTTIME
Figure 7
Termination update keep out time after Autorefresh command
Table 13
Termination update Keep Out time
Symbol
Limit Values
Parameter
–1.6
Termination update Keep Out time
tKO
Unit
–2.0
Notes
–2.2
min
max
min
max
min
max
10
—
10
—
10
—
ns
To guarantee optimum driver impedance after power-up, the GDDR3 SGRAM needs 350 cycles after the clock is
applied and stable to calibrate the impedance upon power-up. The user can operate the part with fewer than 350
cycles, but optimal output impedance will not be guaranteed.
The GDDR3 Graphics RAM proceeds in the following manner for Self Calibration :
The PMOS device is calibrated against the external ZQ resistor value (Figure 8). First one PMOS leg is calibrated
against ZQ. The number of legs used for the terminators ( DQ and ADD/CMD) and the PMOS driver is represented
in Table 14. Next, one NMOS leg is calibrated against the already calibrated PMOS leg. The NMOS driver uses
6 NMOS legs.
Table 14
Number of Legs used for Terminator and Driver Self Calibration
Termination
Number of Legs Notes
0
ZQ/2
2
1
ZQ
1
00
Disabled
0
10
ZQ/4
4
CKE (at RES)
Terminator
ADD / CMD
EMRS[3:2]
DQ
11
Driver
ZQ/2
2
PMOS
ZQ/6
6
NMOS
ZQ/6
6
1
Note: EMRS[3:2] = 00 disables the ADD and CMD terminations as well.
Data Sheet
25
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
Figure 8 represents a simplified schematic of the calibration circuits. First, the strength control bits are adjusted
in such a way that the VDDQ voltage is divided equaly between the PMOS device and the ZQ resistor. The best bit
pattern will cause the comparator to switch the PMOS Match signal output value. In a second step, the NFET is
calibrated against the already calibrated PFET. In the same manner, the best control bit combination will cause
the comparator to switch the NMOS Match signal output value.
VDDQ
VDDQ
Strength
Control [2:0]
NMOS
Calibration
VSSQ
PMOS
Calibration
Match
VDDQ / 2
Strength
Control [2:0]
ZQ
Match
VDDQ / 2
VSSQ
VSSQ
Figure 8
Self Calibration of PMOS and NMOS Legs
3.3.3
Dynamic Switching of DQ terminations
The GDDR3 Graphics RAM will disable its data terminators when a READ or DTERDIS command is detected. The
terminators are disabled starting at CL - 1 Clocks after the READ / DTERDIS command is detected and the
duration is 4 clocks. In a two rank system, both devices will snoop the bus for a READ / DTERDIS command to
either device and both will disable their terminators if a READ / DTERDIS command is detected. The address and
command terminators are always enabled.
Data Sheet
26
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
#OM
2$
.$
.$
.$
.$
.$
.$
.$
.$
.$
!DDR "#
#,+
#,+
#!3
LATE
NCY 2$1
3
$1
$
$1
4ERM
INATION
$
$
$
$ATA
4E
RMINATIO
NS A
RE
D
ISA
BLED
"#
"
A
N
K#
OLU
MNA
D
D
RE
SS
2$ 2%
!
$
.$
.
/
0OR $
ES ELECT
$X $A
TAFR O
M
"
#
#OM
#
O
MMA
ND
!DD
R !
D
DR E
SS"
#
$ONgT#
A
RE
Figure 9
ODT Disable Timing during a READ command
3.3.4
Output impedance and Termination DC Electrical Characteristics
The Driver and Termination impedances are determined by applying VDDQ/2 nominal (1.0 V) at the corresponding
input / output and by measuring the current flowing into or out of the device. VDDQ is set to the nominal value of
2.0 V. (see Table 1)
IOH is the current flowing out of DQ when the Pull-Up transistor is activated and the DQ termination disabled.
IOLis the current flowing into DQ when the Pull-Down transistor is activated and the DQ termination disabled.
ITCAH(ZQ) is the current flowing out of the Termination of Commands and Addresses for a ZQ termination value.
Table 15
DC Electrical Characteristics
Parameter
IOH
IOL
ITCAH(ZQ)
Nom.
Unit
Notes
ZQ Value
240
Ω
min
max
ZQ/6
20.5
25.0
mA
1
ZQ/6
20.5
25.0
mA
1
ZQ
3.4
4.2
mA
1
Note: 1: Measurement performed with VDDQ =2.0 V (nominal see Table 1) and by applying VDDQ/2 (1.0 V) at the
corresponding Input / Output.
0°C ≤ TC ≤ 85°C.
Data Sheet
27
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
3.4
Extended Mode Register Set Command (EMRS)
The Extended Mode Register is used to set the output
driver impedance value, the termination impedance
value, the Write Recovery time value for Write with
Autoprecharge. It is used as well to enable/disable the
DLL, to issue the Vendor ID and to enable/disable the
Low Power mode. There is no default value for the
Extended Mode Register. Therefore it must be written
after power up to operate the GDDR3 Graphics RAM.
The Extended Mode Register can be programmed by
performing a normal Mode Register Set operation and
setting the BA0 bit to HIGH. All other bits of the EMR
register are reserved and should be set to LOW.
#,+
#,+
#+%
#3
2!3
The Extended Mode Register must be loaded when all
banks are idle and no burst are in progress. The
controller must wait the specified time tMRD before
initiating any subsequent operation).
#!3
7%
!!
The timing of the EMRS command operation is
equivalent to the timing of the MRS command
operation.
#/$
"!
"!
#/$#ODETOBELOADEDINTO
THEREGISTER
$ONgT#ARE
Figure 10
Extended Mode Register Bitmap
"!
"!
!
!
,0
6
!
!
!
2&5
!
$,,
!
!
%NAB
LE
$ISA
BLE
,OW
0
OWE
R !
$ISAB
LE
%NA
BLE
! 6EN
DO
R)$
Figure 11
/FF
/N
!
!
T72!
$,,
%NA
BLE
!
!
!
!
2TT
!
$ATA
:
!
!UTOC AL
/HM
/HM
/HM
!
!
4ERM
INA
TION
/$4
D
IS ABLED
2&5
:1
:1
$E
FAU
LT !
/UTP
U
T$
R IV ER )MPE
DA
NCE
T72!
Extended Mode Register Bitmap
1. Autocalibration is not supported for these settings.
2. Default termination values at Power Up.
Data Sheet
28
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
3. The ODT disable function disables all terminators on th device.
4. If the user activates bits in an extended mode register in an optional field, either the optional field is activated
(if option implemented on the device) or no action is taken by the device (if ioption not implemented).
5. WR (write recovery time for write with autoprecharge) in clock cycles is calculated by dividing tWR (in ns) and
rounding up to the next integer (WR[cycles]=tWR[ns]/tCK[ns]). The mode register must be programmed to this
value.
#,+
#,+
#OMMAND
0!
./0
%-23
./0
./0
T
-2$
T
20
!#!NYCOMMAND
%-23%XTENDED-23COMMAND
$ONgT#ARE
0!02%!,,COMMAND
Figure 12
Extended Mode Register Set Timing
Table 16
EMRS Timing Parameters for –1.6, –2.0 and –2.2 speed sorts
Parameter
Symbol
Limit Values
–1.6
Mode Register Set cycle time
3.4.1
!#
tMRD
Unit
–2.0
Notes
–2.2
min
max
min
max
min
max
5
—
4
—
4
—
tCK
DLL enable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon
returning to normal operation after having disabled the DLL. (When the device exits self-refresh mode, the DLL is
enabled automatically). Anytime the DLL is enabled, 200 cycles must occur before a READ command can be
issued.
3.4.2
WR
The WR parameter is programmed using the register bits A4 and A5. This integer parameter defines as a number
of clock cycles the Write Recovery time in a Write with Autoprecharge operation.
The following inequality has to be complied with : WR * tCK ≥ tWR, where tCK is the clock cycle time as defined in
Table 8 and tWR the Write Recovery time as defined in Table 23.
Note: Refer to Figure 3.7.4 for more details.
3.4.3
Termination Rtt
The data termination, Rtt , is used to set the value of the internal terminaton resistors. The GDDR III DRAM
supports ZQ / 4 and ZQ / 2 termination values. The termination may also be disabled for testing and other
purposes.
3.4.4
Output Driver Impedance
The Output Driver Impedance extended mode register is used to set the value of the data output driver impedance.
When the autocalibration is used, the output driver impedance is set nominally to ZQ / 6.
Data Sheet
29
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
3.4.5
Low Power
When the Low Power extended mode register is set, the device enters a low power mode of operation. This mode
is not enabled for the HYB18T256324F–[16/20/22]. Setting this bit to HIGH will have no effect on the behavior of
the GDDR3 DRAM.
3.4.6
Vendor Code and Revision Identification
The Manufacturer Vendor Code is selected by issuing an Extended Mode Register Set command with bit A10 set
to 1 and bits A0-A9 and A11 set to the desired value. When the Vendor Code function is enabled the GDDR3
DRAM will provide the Infineon vendor code on DQ[3:0] and the revision identification on DQ[7:4]. The code will
be driven onto the DQ bus after tRIDon following the EMRS command that sets A10 to 1. The Vendor Code and
Revision ID will be driven on DQ[7:0] until a new EMRS command is issued with A10 set back to 0. After tRDoff
following the second EMRS command, the data bus is driven back to HIGH. This second EMRS command must
be issued before initiating any subsequent operation. Violating this requirement will result in unspecified operation.
Table 17
Revision ID and Vendor Code
Revision Identification
Infineon Vendor Code
DQ[7:4]
DQ[3:0]
0001
0010
Note: Please refer to Revision Release Note for Revision ID value
#OM
%-2
3
.$
.$
.$
.$
.$
%-23
.$
.$
.$
.$
!;=
!
!DD
#,+
#,+
!DD
!
T
2)$O
N
T
2)$
O
FF
2$1
3
$1;
=
6ENDOR #
OD
EA
N
D2
E
VIS ION
)$
%-23
%
X TE
NDE
D
OD
E2
E
GIS TER 3
E
T#O
M
MAN
D
!DD !D
D
RE
S S
.$
./
0OR $
E
SELEC T
$ON
gT#A
R E
Figure 13
Timing of Vendor Code and Revision ID generation on DQ[7:0]
Table 18
Vendor Code and Revision ID Timing Parameters for –1.6, –2.0 and –2.2 speed sorts
Parameter
Symbol
Limit Values
–1.6
EMRS to DQ on time
EMRS to DQ off time
Data Sheet
tRIDon
tRIDoff
Unit
–2.0
–2.2
min
max
min
max
min
max
—
20
—
20
—
20
ns
—
20
—
20
—
20
ns
30
Notes
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
3.5
Mode Register Set Command (MRS)
The mode register stores the data for controlling the
operating modes of the memory. It programs read
latency, test mode, DLL Reset and the value of the
write latency. There is no default value for the mode
register; therefore it must be written after power up to
operate the GDDR3 Graphics RAM. During a Mode
Register Set command the address inputs are sampled
and stored in the mode register.
#,+
#,+
#+%
#3
tMRD must be met before any command can be issued
to the Graphics SDRAM. The Mode Register contents
can only be set or changed when the Graphics SDRAM
is in idle state.
2!3
#!3
7%
!!
#/$
"!
"!
#/$ #
O
DETO
B
ELOA
DED
INTO
THER E
GIS TE
R $ONgT#
A
RE
Figure 14
Mode Register Set Command
"! "! ! ! !
!
7,
!
$,, 4-
7RITE,ATENCY
!! !
!
!
!
!
2EAD,ATENCY
"4
!
MODE
.ORMAL
4ESTMODE
ALLOTHERS
! ! ! ,ATENCY
$,,2ESET
!
.O
9ES
2&5
ALLOTHERS
Figure 15
ALLOTHERS
2EAD,ATENCY
2&5
!
",
!
"URST,ENGTH
!
! ! ! ",
4ESTMODE
7,
!
2&5
"URST4YPE
!
"4
SEQUENTIAL
2&5
2&5
Mode Register Bitmap
Note: The DLL Reset command is self-clearing
Data Sheet
31
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
#,+
#,+
#OM
0!
./0
-23
./0
./0
!#
./0
2$
T
-2$
T
20
T
-2$2
-23-23COMMAND
0!02%!,,COMMAND
!#!NYOTHERCOMMANDAS2%!$
2$2%!$COMMAND
$ONgT#ARE
Figure 16
Mode Register Set Timing
Table 19
MRS Timing Parameters for –1.6, –2.0 and –2.2 speed sorts
Parameter
Symbol
Limit Values
–1.6
Mode Register Set cycle time
Mode Register Set to READ timing
tMRD
tMRDR
–2.0
Unit
Notes
–2.2
min
max
min
max
min
max
5
—
4
—
4
—
tCK
1, 2
15
—
12
—
12
—
tCK
1
1. This value of tMRD applies only to the case where the
“DLL reset” bit is not activated.
2. tMRD is defined from MRS to any other command as READ.
3.5.1
Burst length
Read and Write accesses to the GDDR3 Graphics RAM are burst oriented with burst length 4. This value must be
programmed using the Mode Register Set command (A0 .. A2). The burst length determines the number of column
locations that can be accessed for a given READ or WRITE command.
When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected.
All accesses for that burst take place within this block if a boundary is reached. The block is uniquely selected by
A2-Ai where Ai is the most significant bit for a given configuration. The starting location within this block is
determined by the two least significant bits A0 and A1 which are set internally to the fixed value of zero each.
Reserved states should not be used, as unknow operation or incompatibility with future versions may result.
3.5.2
Burst type
Accesses within a given bank must be programmed to be sequential. This is done using the Mode Register Set
command (A3) . This device does not support the burst interleave mode.
Table 20
Burst Type
Burst Length
Starting Column address
Order of accesses within the burst
Type = Sequential
4
A1 A0
xx
0-1-2-3
The value applied at the balls A0 and A1 for the column address is “Don’t care”.
Data Sheet
32
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
3.5.3
CAS Latency
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability
of the first bit of output data as shown on Figure 31. The latency can be set to 5 to 7 clocks as shown in Figure 15.
If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally
concident with clock edge n+m. Refer to Appendix, Figure 42, for values of operating frequencies at which each
CAS latency setting can be used.
Reserved states should not be used as unknown operation or incompatibility with future versions may result.
3.5.4
Write Latency
The WRITE latency, WL, is the delay, in clock cycles, between the registration of a WRITE command and the
availability of the first bit of input data as shown in Figure 21. WL can be set from 2 to 4 clocks depending on the
operating frequency. Setting the WRITE latency to 2 or 3 clocks will cause the device to enable the data input
receivers on all ACT commands.
3.5.5
Test mode
The normal operating mode is selected by issuing a Mode Register Set command with bit A7 set to zero and bits
A0-A6 and A8-A11 set to the desired value.
3.5.6
DLL Reset
The normal operating mode is selected by issuing a Mode Register Set command with bit A8 set to zero and bits
A0-A7 and A9-A11 set to the desired values. A DLL Reset is initiated by issuing a Mode Register Set command
with bit A8 set to one and bits A0-A7 and A9-A11 set to the desired values. The GDDR3 SGRAM returns
automatically in the normal mode of operations once the DLL reset is completed.
Data Sheet
33
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
3.6
Bank / Row Activation (ACT)
Before a READ or WRITE command can be issued to
a bank, a row in that bank must be opened. This is
accomplished via the ACT command, which selects
both the bank and the row to be activated.
#,+
#,+
#+%
After opening a row by issuing an ACT command, a
READ or WRITE command may be issued after tRCD to
that row.
#3
A subsequent ACT command to a different row in the
same bank can only be issued after the previous active
row has been closed (precharged). The minimum time
interval between successive ACT commands to the
same bank is defined by tRC.
2!3
#!3
A subsequent ACT command to another bank can be
issued while the first bank is being accessed, which
results in a reduction of total row-access overhead. The
minimum time interval between successive ACT
commands to different banks is defined by tRRD.
7%
!!
2!
"! "!
"!
There is a minimum time tRAS between opening and
closing a row.
2! 2
O
W!
D
DRE
SS
"! "
A
NK!D
D
RE
S S
$ONgT#
A
RE
Figure 17
Activating a specific row
#,+
#,+
#OM
!#4
27
02%
!#4
!#4
!!
2OW
#OL
!
2OW
2OW
"!
"
!
"9
"9
"9
"9
"8
T2#$
T2!3 T2#
Figure 18
Data Sheet
T22$
2OW 2
O
W!
D
DRE
SS
#OL #
O
LU
MN
!
D
DRE
S S
"8 "
A
NK 8
"9 "
A
NK 9
27
2
%
!$
OR 7
2)4%
C OM
MAN
D
02%
0
2%
#
(
!
2
'
%C OM
MAN
D
!#4
!
#
4)6
!
4%
CO
MMA
ND
$ON
gT#
A
R E
Bank Activation timing
34
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
Table 21
ACT Timing Parameters for –1.6, –2.0 and –2.2 speed sorts
Parameter
Symbol
Limit Values
–1.6
Unit Notes
–2.0
–2.2
min
max
min
max
min
max
tRC
tRAS
tRRD
37.2
—
37.2
—
39.6
—
ns
24.0
8 x tREFI
24.0
8 x tREFI
26.2
8 x tREFI
ns
8.0
—
8.0
—
8.8
—
ns
Row to Column Delay Time for
Reads
tRCDRD
16.0
—
16.0
—
17.5
—
ns
Row to Column Delay Time for
Writes
tRCDWR
Row Cycle Time
Row Active Time
ACT(a) to ACT(b) Command
period
3.7
Writes (WR)
3.7.1
Write Basic Information
tRCDWR(min) = tRCDRD(min) - (WL + 1) x tCK(min)
Write bursts are initiated with a WR command, as
shown in Figure 19. The column and bank addresses
are provided with the WR command, and Auto
Precharge is either enabled or disabled for that access.
The length of the burst initiated with a WR command is
always four. There is no interruption of WR bursts. The
two least significant address bits A0 and A1 are ’Don’t
Care’.
#,+
#,+
#+%
#3
For WR commands with Autoprecharge the row being
accessed is precharged tWR/A after the completion of
the burst. If tRAS(min) is violated the begin of the internal
Autoprecharge will be performed one cycle after
tRAS(min) is met. tWR/A can be programmed in the Mode
Register. Choosing high values for tWR/A will prevent the
chip to delay the internal Autoprecharge in order to
meet tRAS(min).
2!3
#!3
7%
!!!
During WR bursts data will be registered with the edges
of WDQS. The write latency can be programmed during
Extended Mode Register Set. The first valid data is
registered with the first valid rising edge of WDQS
following the WR command. The externally provided
WDQS must switch from HIGH to LOW at the beginning
of the preamble. There is also a postamble requirement
before the WDQS returns to HIGH. The WDQS signal
can only transition when data is applied at the chip input
and during pre- and postambles.
#!
!!
!!
!
!0
"! "!
"!
tDQSS is the time between WR command and first valid
rising edge of WDQS. Nominal case is when WDQS
edges are aligned with edges of external CLK.
Minimum and maximum values of tDQSS define early
and late WDQS operation. Any input data will be
ignored before the first valid rising WDQS transition.
tDQSL and tDQSH define the width of low and high phase
of WDQS. The sum of tDQSL and tDQSH has to be tCK.
!0 !
UTO
0R E
CHA
RG
E
#! #
O
LU
MN!
DD
RE
SS "! "
AN
K!D
D
RE
SS
$ONgT#
A
RE
Figure 19
Data Sheet
ns
Write Command
35
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
Back to back WR commands are possible and produce
a continuous flow of input data. There must be one
NOP cycle between two back to back WR commands.
Setup and hold time for incoming DQs and DMs relative
to the WDQS edges are specified as tDS and tDH. DQ
and DM input pulse width for each input is defined as
tDIPW. The input data is masked if the corresponding DM
signal is high.
Any WR burst may be followed by a subsequent RD
command. Figure 3.7.5 shows the timing requirements
for a WR followed by a RD. A WR may also be followed
by a PRE command to the same bank. tWR has to be
met as shown in Figure 3.7.8.
Table 22
All timing parameters are defined with graphics DRAM
terminations on.
Mapping of WDQS and DM signals
WDQS
Data mask signal
Controlled DQs
WDQS0
DM0
DQ0 - DQ7
WDQS1
DM1
DQ8 - DQ15
WDQS2
DM2
DQ16 - DQ23
WDQS3
DM3
DQ24 - DQ31
#,+
#,+
NOM
IN
AL7$
1
3
T$133
T$13 T702%
0REAM
BLE
T$13
T$13 ,
(
T703 4
(
T$3 T$(
T$3 T$(
0OS TA
MB
LE
7$1
3
T$)0 7
$1
$
T$3
$-X EAR LY
7
$
1
3
$
$
$
T$(
T$)0 7
$ATA
MA
S KE
D
MINT$
133
$ATA
M
A
SK E
D
7$1
3
LATE
7$
1
3
MAX T$
13 3
7$1
3
$ONgT#
A
RE
Figure 20
$-X 2
E
PRE
S EN
TS O
NE
$
LIN
E
Basic Write Burst / DM Timing
Note: : WDQS can only transition when data is applied at the chip input and during pre- and postambles
Data Sheet
36
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
Table 23
WR Timing Parameters for –1.6, –2.0 and –2.2 speed sorts
Parameter
Symbol
Limit Values
–1.6
CAS(a) to CAS(b) Command period
tCCD
–2.0
Unit
Notes
tCK
1)
–2.2
min
max
min
max
min
max
2
—
2
—
2
—
Write Cycle Timing Parameters for Data and Data Strobe
Write command to first WDQS latching
transition
tDQSS
WL
WL +0.25 0.25
Data-in and Data Mask to WDQS Setup tDS
Time
0.35
—
0.375 —
0.375 —
ns
2)
tDH
0.35
—
0.375 —
0.375 —
ns
2)
Data-in and DM input pulse width (each tDIPW
input)
0.45
—
0.45
—
0.45
—
tCK
tDQSL
tDQSH
tWPRE
tWPST
tWTR
tWR
0.45
—
0.45
—
0.45
—
3)
0.45
—
0.45
—
0.45
—
0.75
1.25
0.75
1.25
0.75
1.25
0.75
1.25
0.75
1.25
0.75
1.25
tCK
tCK
tCK
tCK
6.0
—
6.0
—
6.6
—
ns
2)4)
Data-in and Data Mask to WDQS Hold
Time
WDQS input low pulse width
WDQS input high pulse width
WDQS Write Preamble Time
WDQS Write Postamble Time
Write to Read Command Delay
WL
WL +0.25 0.25
WL
tCK
+0.25
WL 0.25
3)
2)4)
Write Recovery Time
11.0 —
11.0 —
11.0 —
ns
1) tCCD is either for gapless consecutive writes or gapless consecutive reads
2) Timing parameters defined with Graphics DRAM terminations on.
3) tDQSL. and tDQSH apply for the Write preamble and postamble as well.
4) tWTR and tWR start at the first rising edge of CLK after the last valid (falling) WDQS edge of the slowest WDQSx
signal
Data Sheet
37
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
3.7.2
Write - Basic Sequence
#OM
72
.$
$%3
$%3
$%3
$%3
$%3
$%3
$%3
!DDR "#
./0
./0
./0
#,+
#,+
7,
7$1
3
$1
$
$
$
$
7,
7$1
3
$1
$
#OM
72
!DDR "#
.$
./0
./0
$
./0
$
$
./0
7,
$1
$
$
$
$
7,
7$1
3
$1
$
$
$
$
"# "
A
NK #
OLUM
NA
D
DR E
SS
72 7
2)4
%
./0 .
O/PE
R A
TION
$%3
$
ES ELEC T
.0
.
/
0OR $
%3
Figure 21
1.
2.
3.
4.
#OM
#
OM
MAN
D
!DDR !D
D
RE
SS"
#
$ $A
TA
TO
"
#
7, 7
R ITE,
A
TE
NC Y
$ON
gT#A
R E
Write Burst Basic Sequence
Shown with nominal value of tDQSS.
WDQS can only transition when data is applied at the chip input and during pre- and postambles.
When NOPs are applied on the command bus, the WDQS and the DQ busses remain stable High.
When DESs are applied on the command bus, the status of the WDQS and DQ busses is unknown.
Data Sheet
38
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
3.7.3
Write - Consecutive Bursts
3.7.3.1
Gapless Bursts
#OM
72
.$
72
.$
$%3
$%3
$%3
$%3
$%3
$%3
!DDR "#X #,+
#,+
"#Y 7,
7$1
3
$1
$X
$X
$X
$X
$Y
$Y
$Y
$Y
7,
7$1
3
$1
$X
$X
$X
$X
$Y
$Y
$Y
$Y
7,
7$1
3
$1
$X
$X
$X
$X
$Y
$Y
$Y
$Y
72 7
2)4
%
$%3
$
ES ELEC T
.$ .
/
0$
E
SELECT
"#X "
AN
K #
O
LU
MNA
DD
RE
SSX "#Y "
AN
K #
O
LU
MNA
DD
RE
SSY 7, 7R ITE
,
ATE
NC Y
$ONgT#
A
RE
Figure 22
$X $
ATA
TO
"
#
X $Y $
ATA
TO
"
#
Y #OM #O
M
MAN
D
!DDR !D
D
RE
S S"
#
Gapless Write Bursts
1. Shown with nominal value of tDQSS
2. The second WR command may be either for the same bank or another bank
3. WDQS can only transition when data is applied at the chip input and during pre- and postambles
Data Sheet
39
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
3.7.3.2
Bursts with Gaps
#OM
72
.$
.$
72
.$
$%3
$%3
$%3
$%3
$%3
$%3
!DDR "#X #,+
#,+
"#Y 7,
7$1
3
$1
$X
$X
$X
$X
$Y
$Y
$Y
$Y
7,
7$1
3
$1
$X
$X
$X
$X
$Y
$Y
$Y
$Y
7,
7$1
3
$1
$X
$X
$X
$X
$Y
$Y
$Y
$Y
#OM #O
M
MAN
D
!DD
R !
D
DR E
SS"#
7, 7
RITE,
ATE
N
CY $%3 $E
S ELE
CT
.$
.
/
0$
E
SELEC T
"#
X "A
N
K#O
LUM
NAD
DRE
SSX
"#
Y "A
N
K#O
LUM
NAD
DRE
SSY
72 7
2)4
%
$X$A
TA
TO
"
#
X $Y$A
TA
TO
"
#
Y $ON
gT#
A
R E
Figure 23
Consecutive Write Bursts with Gaps
1. Shown with nominal value of tDQSS.
2. The second WR command may be either for the same bank or another bank.
3. WDQS can only transition when data is applied at the chip input and during pre- and postambles.
Data Sheet
40
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
3.7.4
Write with Autoprecharge
#OM
72!
.$
$%3
$%3
$%3
$%3
$%3
$%3
$%3
$%3
!
! !
"#
#,+
#,+
$%3
!
T72! 7,
7$1
3
T20
$1
$
$
$
$
"EGIN
O
F
T2!3-
).
PRE
CH
ARGE
SATISFIED
!UTO
7,
T72!
7$1
3
T20
$1
$
$
$
$
"EGINOF
T2!3-
).
P
RECH
AR GE
SATISFIED
!UTO
7,
T72! 7$13
T20
$
$1
$
$
$
"EGINOF
T2!3-
).
P
RECH
AR GE
SATISFIED
!UTO
#OM
#O
M
MAN
D
!DDR !D
D
RE
SS"
#
7, 7
R ITE,
A
TE
NC Y
$ON
gT#A
R E
Figure 24
"# "
A
NK #
O
LU
MN
A
DD
R E
SS
72!
7
2
)4%
WITHA
UTO P
RE
C HA
RG
E
$ $
ATA
TO"
#
$%3
$
E
SE
LEC T
.$
.
/
0O
R$
ES E
LEC T
Write with Autoprecharge
Shown with nominal value of tDQSS
tWR/A starts at the first rising edge of CLK after the last valid edge of WDQS.
tRP starts after tWR/A has been expired.
when issuing a WR/A command please consider that the tRAS requirement also must be met at the beginning
of tRP
5. tWR/A * tCYC ≥ tWR
6. WDQS can only transition when data is applied at the chip input and during pre- and postambles
1.
2.
3.
4.
Data Sheet
41
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
3.7.5
Write followed by Read
#OM
72
.$
$%3
$%3
$%3
$%3
$%3
2$
$%3
$%3
!DDR "#
2$
.$
#,+
#,+
"#
T742
7,
7$1
3
$1
$
72
.$
$
$%3
$
$
$%3
$%3
$%3
$%3
$%3
"#
"#
7,
T742
7$13
$1
$
72
.$
$%3
$%3
$
$
$
$%3
$%3
$%3
$%3
$%3
"#
2$
"#
7,
T742
7$1
3
$1
$
$
$
$
$ $
A
TATO
"
#
X #OM #
O
M
MAN
D
!DD
R !
D
DR E
SS"#
7, 7R ITE,
ATE
N
CY $ON
gT#
A
R E
Figure 25
"#
"
AN
K#
OLUM
NAD
DR E
SS 72 72
)4
%
2$ 2
%
!
$
$%3
$
E
SELEC T
.$
.
/
0$
ES ELEC T
Write followed by Read
1. Shown with nominal value of tDQSS.
2. The RD command may be either for the same bank or another bank.
3. WDQS can only transition when data is applied at the chip input and during pre- and postambles.
Data Sheet
42
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
3.7.6
Write followed by DTERDIS
#OM
72
$4$
$%3
$%3
$%3
$%3
$%3
$%3
$%3
$%3
!DDR "#
$%3
$%3
$%3
$%3
$%3
$%3
$%3
$%3
$%3
$%3
#,+
#,+
#,
7,
7$1
3
$1
$
72
$4$
$%3
$
$
$
$%3
$%3
"#
#,
7,
7$13
$1
$
72
.$
$4$
$%3
$
$
$
$%3
"#
#,
7,
7$1
3
$1
$
$
$
$
"# "
ANK #
O
LU
MNA
DDR E
S S
72 72
)4
%
$4$
$
4
%2
$
)3
$ $
A
TA
TO
"
#
X #OM
#
OM
M
AND
!DD
R !
D
DR E
SS"#
Figure 26
7, 7
RITE
,
ATEN
C Y
#, #!
3
,A
TE
N
CY
$%3
$
ES E
LE
CT
.$
./
0O
R$E
S ELE
CT
$ONgT#
A
RE
$ATA
4
ERM
INA
TION
/FF
Write Command followed by DTERDIS
1. Write shown with nominal value of tDQSS.
2. WDQS can only transition when data is applied at the chip input and during pre- and postambles
3. A margin of one clock has been introduced in order to make sure that the data termination are still on when
the last Write data reaches the memory.
4. The minimum distance between Write and DTERDIS is (WL -CL + 4) clocks and always bigger than or equal
to 1. For (CL=6 / WL=2) and (CL=7 / WL=3) as well as for (CL=7 / WL=2) the minimum distance between Write
and DTERDIS is set to 1 clock. Please refer to table below:
Table 24
WL / CL
WL \ CL
5
6
7
2
1
1
1
3
2
1
1
4
3
2
1
Data Sheet
43
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
3.7.7
Write with Autoprecharge followed by Read / Read with Autoprecharge
#OM
72!
.$
$%3
$%3
$%3
$%3
$%3
2$
2$!
$%3
$%3
!
! !
"#
#,+
#,+
"#
!
T742
T72! 7,
T20
7$13
$1
#OM
!
! !
$
72!
.$
$%3
$
$
$
$%3
"EG
INOF!
UTOP
REC HAR GE
$%3
$%3
$%3
2$
2$!
$%3
"#
$%3
"#
!
T72! 7,
T742
T20
7$1
3
$1
#OM
!
! !
$
72!
.$
$%3
$%3
$
$
$
$%3
"EGINO
F!UTOPR ECH
AR GE
$%3
$%3
$%3
"#
$%3
2$
2$!
"#
!
T72! 7,
T742
T20
7$1
3
$1
$
$
$
$
"EGIN
OF!UTO
PREC HAR GE
#OM #O
M
MAN
D
!DDR !D
D
RE
SS"
#
7, 7
R ITE,
A
TE
NC Y
$ON
gT#A
R E
2
$
2
$
!
Figure 27
1.
2.
3.
4.
"#
"A
N
K#O
LUM
NA
D
D
RE
SS
72!
7
2)4
%
W
ITH!
UTO
PR EC H
ARG
E
2$2$
!
2
%
!
$O
R
2
%!
$
W
ITH
!
U
TO
PRE
CHA
RG
E
$ $
A
TA
TO
"#X $%3 $
ES E
LE
CT
.$ ./
0O
R$E
S ELE
CT
Write with Autoprecharge followed by Read or Read with Autoprecharge on another bank
Shown with nominal value of tDQSS.
The RD command is only allowed for another activated bank
tWR/A is set to 3 in this example
WDQS can only transition when data is applied at the chip input and during pre- and postambles
Data Sheet
44
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
3.7.8
Write followed by Precharge on same Bank
#OM
72
.$
$%3
$%3
$%3
$%3
$%3
$%3
02%
$%3
$%3
!DDR "#
#,+
#,+
"
7,
T20
T72
7$13
$
$1
72
.$
$%3
$
$
$
$%3
$%3
$%3
$%3
$%3
$%3
02%
"#
$%3
"
7,
T20
T72
7$13
$1
$
72
.$
$%3
$%3
$
$
$
$%3
$%3
$%3
$%3
$%3
$%3
"#
02%
"
7,
T72
T20
7$1
3
$1
$
$
$
$
.$ .
/
0O
R $E
S ELE
CT
$%3 $
E
SELEC T
#OM #
O
MM
AND
!DDR !
D
DR E
S S"
#
7, 7
RITE,
ATEN
CY
"#
"
A
NK#O
LUM
NAD
DRE
SS
72 7
2)4
%
02%
0
2
%
#(
!
2
'
%
$X $
ATA
TO
"
#
X $Y $
ATA
TO
"
#
Y $ONgT#
A
RE
Figure 28
1.
2.
3.
4.
Write followed by Precharge on same Bank
Shown with nominal value of tDQSS.
WR and PRE commands are to same bank
tRAS requirement must also be met before issuing PRE command
WDQS can only transition when data is applied at the chip input and during pre- and postambles
Data Sheet
45
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
3.8
Reads (RD)
3.8.1
Read - Basic Information
During RD bursts the memory device drives the read
data edge aligned with the RDQS signal which is also
driven by the memory. After a programmable CAS
latency of 5, 6 or 7 the data is driven to the controller.
RDQS leaves HIGH state one cycle before its first rising
edge (RD preamble tRPRE). After the last falling edge of
RDQS a postamble of tRPST is performed.
#,+
#,+
#+%
#3
tAC is the time between the positive edge of CLK and the
appearance of the corresponding driven read data. The
skew between RDQS and the crossing point of
CLK/CLK is specified as tDQSCK. tAC and tDQSCK are
defined relatively to the positive edge of CLK. tDQSQ is
the skew between a RDQS edge and the last valid data
edge belonging to the RDQS edge. tDQSQ is derived at
each RDQS edge and begins with RDQS transition and
ends with the last valid transition of DQs. tQHS is the
data hold skew factor and tQH is the time from the first
valid rising edge of RDQS to the first conforming DQ
going non-valid and it depends on tHP and tQHS. tHP is
the minimum of tCL and tCH. tQHS is effectively the time
from the first data transition (before RDQS) to the
RDQS transition. The data valid window is derived for
each RDQS transition and is defined as tQH minus
tDQSQ.
2!3
#!3
7%
!!!
#!
!!
!!
!
!0
"! "!
"!
After completion of a burst, assuming no other
commands have been initiated, data will go High-Z and
RDQS will go HIGH. Back to back RD commands are
possible producing a continuous flow of output data.
There has to be one NOP cycle between back to back
RD commands.
!0 !
UTO
0R E
CHA
RG
E
#! #
O
LU
MN!
DD
RE
SS "! "
AN
K!D
D
RE
SS
Any RD burst may be followed by a subsequent WR
command. The minimum required number of NOP
commands between the RD command and the WR
command (tRTW) depends on the programmed Read
latency and the programmed Write latency
$ONgT#
A
RE
Figure 29
Read Command
Read bursts are initiated with a RD command, as
shown in Figure 29. The column and bank addresses
are provided with the RD command and Autoprecharge
is either enabled or disabled for that access. The length
of the burst initiated with a RD command is always four.
There is no interruption of RD bursts. The two least
significant start address bits are ’Don’t Care’.
tRTW(min)= (CL+4-WL)
Chapter 3.8.5 shows the timing requirements for RD
followed by a WR with some combinations of CL and
WL.
A RD may also be followed by a PRE command. Since
no interruption of bursts is allowed the minimum time
between a RD command and a PRE is two clock cycles
as shown in Chapter 3.8.6.
If Autoprecharge is enabled, the row being accessed
will start precharge at the completion of the burst. The
begin of the internal Autoprecharge will always be one
cycle after tRAS(min) is met.
Data Sheet
All timing parameters are defined with controller
terminations on.
46
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
T#(
T#,
T#+
T(0
#,+
#,+
T$13#+
2$1
3
0REAMB
LE
T202% 0OSTA
MB
LE
T2034
$1 FIR STD
ATAV A
LID
$
$1LASTD
A
TAV ALID $
$
$
$
$
$
$
T!#
!LL$1
S C OLLE
CTIVE
LY $
$
T$13 1
T1(
Figure 30
DATA
VALID
WINDOW
T1(3 T,:
$
$
T$13 1
$ONgT#
A
RE
(I : .O
TD
RIVEN
BY$$
2
)))3
'
2!
T(:
Basic Read Burst Timing
1. The GDDR3 SGRAM switches off the DQ terminations one cycle before data appears on the busand drives
the data bus HIGH.
2. The GDDR3 SGRAM drives the data bus HIGH one cycle after the last data driven on the bus before switching
the termination on again.
Table 25
READ Timing Parameters for –1.6, –2.0 and –2.2 speed sorts
Parameter
Symbol
Limit Values
–1.6
CAS (a) to CAS (b) Command period
tCCD
Read to Write command delay
tRTW
–2.0
Unit
Note
tCK
1
tCK
2
4
–2.2
min
max
min
max
min
max
2
—
2
—
2
—
tRTW(min)= (CL+4-WL)
Read Cycle Timing Parameters for Data and Data Strobe
–0.4
0.4
–0.4
0.4
–0.45
0.45
ns
Read Preamble
tAC
tRPRE
0.75
1.25
0.75
1.25
0.75
1.25
tCK
Read Postamble
tRPST
0.75
1.25
0.75
1.25
0.75
1.25
tCK
tACmin
tACmin
tACmax tACmin
tACmax tACmin
Data Access Time from Clock
Data-out high impedance time from CLK tHZ
Data-out low impedance time from CLK tLZ
RDQS edge to Clock edge skew
RDQS edge to output data edge skew
Data hold skew factor
Data output hold time from RDQS
Minimum clock half period
1.
2.
3.
4.
tDQSCK
tDQSQ
tQHS
tQH
tHP
4
0.4
0.45
ns
4
0.225 —
0.225 —
0.25
ns
4
0
0.225 0
0.225 0
0.25
ns
4
ns
4
tCK
3
tHP–tQHS
—
0.45
–0.45
4
—
0.45
0.4
tACmax ns
tACmax ns
–0.4
tHP–tQHS
–0.4
tACmax tACmin
tACmax tACmin
tHP–tQHS
—
0.45
—
tCCD is either for gapless consecutive reads or gapless consecutive writes.
Please round up tRTW to the next integer of tCK.
tHP is the minimum of tCL and tCH
Timing parameters defined with controller terminations on.
Data Sheet
47
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
3.8.2
Read - Basic Sequence
#OM
2$
.$
.$
.$
.$
.$
.$
.$
.$
.$
!DDR
"#
#,+
#,+
#!3LATENCY
2$13
$1
$ $ $
$
#!3LATENCY
2$13
$1
$
$ $
$
"#"ANK#OLUMNADDRESS 2$2%!$
.$.OPOR$ESELECT
$X$ATAFROM"#
#OM#OMMAND
!DDR!DDRESS"#
Figure 31
$ONgT#ARE
$1S4ERMINATIONSOFF
2$13.OTDRIVEN
Read Burst
1. Shown with nominal tAC and tDQSQ
2. RDQS will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge
of RDQS
3. The DQ terminations are switched off 1 cycle before the first Read Data and on again 1 cycle after the last
Read data
Data Sheet
48
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
3.8.3
Consecutive Read Bursts
3.8.3.1
Gapless Bursts
#OM
2$
.$
2$
.$
.$
.$
.$
.$
.$
.$
.$
.$
!DD
R "#X
#,+
#,+
"#Y
#!3LATE
NCY 2$13
$X $X $X
$X $Y
$Y
$Y $Y
$1
#!3LA
TE
NCY 2$13
$1
$X
$X $X
$X
$Y $Y $Y
$Y
"#X "
ANK#OLU
MNADD
RESS X
"#Y "AN
K#OLU
MN
AD
DRESS Y
$X
$ATAFROM"
#
X
$Y
$ATAFROM"
#
Y
#OM #OMMA
ND
!DDR !DDR ES S "#
Figure 32
2$ 2%
!$
.$ ./0O
R$ES ELEC T
$ONgT#AR E
$1S 4E
RMIN
ATION
SO
FF
2$13
.OTD
RIVE
N
Gapless Consecutive Read Bursts
1.
2.
3.
4.
The second RD command may be either for the same bank or another bank
Shown with nominal tAC and tDQSQ
Example applies only when READ commands are issued to same device
RDQS will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge
of RDQS
5. The DQ terminations are switched off 1 cycle before the first Read Data and on again 1 cycle after the last
Read data
Data Sheet
49
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
3.8.3.2
Bursts with Gaps
#OM
2$
.$
.$
2$
.$
.$
.$
.$
.$
.$
.$
!DDR "#X #,+
#,+
"#Y #!3
LATE
NCY 2$1
3
$X
$X
$X
$X
$1
$Y
$Y
$Y
$Y
#!3
LATEN
CY 2$1
3
$X
$X
$X
$X
$1
$Y
$Y
$Y
"#
X "
A
NK #
OLUM
NA
D
DR ES SX "#
Y "
A
NK #
OLUM
NA
D
DR ES SY 2$ 2
%!
$
$X $
ATA
FRO
M"
#
X $Y $
ATA
FRO
M"
#
Y #OM #O
M
MAN
D
!DDR !D
D
RE
SS "
#
Figure 33
$ONgT#
A
RE
$1S 4
E
RM
INA
TION
SO
FF
2$1
3 .
O
TDR IV EN
Consecutive Read Bursts with Gaps
1. The second RD command may be either for the same bank or another bank
2. RDQS will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge
of RDQS.
3. The DQ terminations are switched off 1 cycle before the first Read Data and on again 1 cycle after the last
Read data
Data Sheet
50
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
3.8.3.3
Read followed by DTERDIS
#O M
2$
.$
.$
.$
$4
$
.$
.$
.$
.$
.$
.$
.$
.$
.$
!D
D R "#
X .$
.$
.$
.$
.$
.$
#,
+
#, +
#!
3
LA
TE
N C
Y
2$
1
3
$X
$X $X $X $1
#O M
2$
!D
D R "#
X .$
.$
.$
.$
$4
$
.$
.$
#!
3
LA
TE
N C
Y
2$
1
3
$1
Figure 34
$X
$X $X $X "#
X "
A
N K #
O
LU
M
NA
D D RE
S S X
2$
2
%
!
$
$X
$
ATA
FRO
M
"
#
X $4$
$
4%
2
$)3
#OM
#
O M
MA
N D $%3
$
E S E
LE
C T
!D
D R
!
D
D RE
S S
"
#
.$
.
/0
O
R$
E
S E
LE
C T
$O
N gT
#
A
RE
$1
S 4
E
RM
IN
A TIO
N S O
FF
2$
13
.
OTD RIV
E
N Read Command followed by DTERDIS
1. At least 3 NOPs are required between a READ command and a DTERDIS command in order to avoid
contention on the RDQS bus in a 2 rank system.
2. CAS Latency 5 is used as an example.
3. The DQ terminations are switched off (CL-1) clock periods after the DTERDIS command for a duration of
(BL/2 + 2 ) clocks.
4. The dashed lines (RDQS bus) describe the RDQS behavior in the case where the DTERDIS command
corresponds to a Read command applied to the second Graphics DRAM in a 2 rank system. In this case,
RDQS would be driven by the second Graphics DRAM.
Data Sheet
51
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
3.8.4
Read with Autoprecharge
#OM
2$!
.$
.$
.$
.$
.$
.$
.$
.$
!
!!
"#
#,+
#,+
!
#!3LATE
NCY 2$1
3
$1
$
$
$
$
$
$
#!3LA
TE
NCY 2$1
3
$1
$
$
",
T20
"#
"
A
N
K#
OLU
MNA
D
D
RE
SS
2$!
2
%
!$
W
ITH
A
UTO
P
RE
CHA
RG
E
$X $
A
TA
FRO
M"
#
#OM #
O
MMA
ND
!DDR !
DD
RE
SS"
#
"EG
INO
F
!UTOPR ECH
A
RGE
Figure 35
.$ .
/0
O
R$
E
SE
LE
CT
$ONgT#
A
RE
$1S 4E
R MINA
TIO
NSOFF
2$1
3 .
O
TD
RIV EN
Read with Autoprecharge
1. When issuing a RD/A command , the tRAS requirement must be met at the beginning of Autoprecharge
2. Shown with nominal tAC and tDQSQ
3. RDQS will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge
of RDQS
4. The DQ terminations are switched off 1 cycle before the first Read Data and on again 1 cycle after the last
Read data
5. tRAS Lockout support
Data Sheet
52
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
3.8.5
Read followed by Write
#OM
2$
$%3
$%3
$%3
$%3
$%3
72
$%3
$%3
$%3
$%3
$%3
!DDR "#R #,+
#,+
"#W
#!3LATE
N
CY
7RITELATENC Y T247
2$13
7$1
3
$R
$1
2$
$%3
$%3
$%3
$%3
$%3
"#R $R $R
$R
72
$W
$W $W $W
$%3
$%3
$%3
$%3
$%3
"#W
#!3
LATEN
CY 7RITE
LATE
NC Y T247
2$13
7$1
3
$R
$1
$R $R
"#
R "
A
NK#
OLU
M
NA
DD
RE
S SFO
R2
%
!
$
"#
W
"
AN
K #
O
LU
MNA
DD
RE
SSFO
R7
2
)4
%
2$ 2
%
!$
72 7
2)4
%
$%3
$
E
SE
LE
C T
Figure 36
$R
$XR 2
%
!
$$
ATA
FR O
M
"#
$XW 7
2)4
%
$
ATA
FRO
M
"
#
#OM #
O
MMA
ND
!DDR !D
D
RE
S S"
#
$W
$W $W
$ON
gT#A
R E
$1S 4
E
RM
IN
ATIO
NS O
FF
2$1
3 .O
TD
RIVE
N
Read followed by Write
1. Shown with nominal tAC, tDQSQ and tDQSS
2. RDQS will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge
of RDQS
3. The DQ terminations are switched off 1 cycle before the first Read Data and on again 1 cycle after the last
Read data
4. WDQS can only transition when data is applied at the chip input and during pre- and postambles
5. The Write command may be either on the same bank or on another bank
Data Sheet
53
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
3.8.6
Read followed by Precharge on the same Bank
#OM
2$
.$
02%
.$
.$
.$
.$
.$
.$
!DDR "#
#,+
#,+
#!3LA
TE
NCY 2$1
3
$1
$
$
$
$
$
$
#!3LATE
NCY 2$13
$1
T20
#OM #O
M
MAN
D
!DDR !D
D
RE
SS "
#
"#
"A
N
K#
O
LU
MNA
DD
RE
S S
2$ 2
%
!$
02%
0
2
%#
(
!
2
'%
$X $
A
TA
FRO
M"
#
$
$
$ON
gT#
A
R E
$1S 4
ER M
INA
TIO
N
SO
FF
2$1
3 .
O
TD
RIV EN
.$ .
/
0OR $
E
SELEC T
Figure 37
1.
2.
3.
4.
Read followed by Precharge on the same Bank
tRAS requirement must also be met before issuing PRE command
RD and PRE commands are applied to the same bank.
Shown with nominal tAC and tDQSQ
RDQS will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge
of RDQS
Data Sheet
54
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
3.9
Data Termination Disable (DTERDIS)
The Data Termination Disable command is detected by
the device by snooping the bus for Read commands
when CS is high. The terminators are disabled starting
at CL - 1 clocks after the DTERDIS command is
detected and the duration is 4 clocks. The command
and address terminators are always enabled.
#,+
#,+
#+%
DTERDIS may only be applied to the GDDR3 Graphics
memory if it is not in the Power Down or in the Self
Refresh state.
#3
The timing relationship between DTERDIS and other
commands is defined by the constraint to avoid
contention on the RDQS bus (i.e Read to DTERDIS
transistion) or the necessity to have a defined
termination on the data bus during Write (i.e. Write to
DTERDIS transition). ACT and PRE/PREALL may be
applied at any time before or after a DTERDIS
command.
2!3
#!3
7%
!!!
!!
!!
!
"! "!
!0 !
UTO
0R E
CHA
RG
E
$ONgT#
A
RE
Figure 38
Data Termination Disable Command
$4$
.$
.$
.$
.$
.$
.$
.$
.$
.$
#,+
#,+
#OM
!DDR #!3
LATE
NCY $1
4ERM
INATION
$ATA
4E
RMINATIO
NS A
RE
D
ISA
BLED
$4$
$4
%
2$
)3
#OM #
O
MM
AND
!DDR !
D
DR E
S S"
#
Figure 39
Data Sheet
$ON
gT#A
R E
.$
./
0O
R$
E
SELEC T
DTERDIS Timing
55
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
!DD
R
#!3LATE
NC
Y
2$1
3
$1
#OM
.$
$4$
.$
.$
.$
.$
.$
.$
.$
.$
.$
$4$
.$
.$
.$
.$
.$
.$
.$
.$
!DD
R
#!3LATE
NC
Y
2$1
3
$1
#OM
.$
.$
!DD
R
#!3LATE
NC
Y
2$1
3
$1
#OM #
O
MMAN
D
!DD
R !D
DR E
SS"
#
Figure 40
"#
X
"A
N
K#
OLUM
NAD
D
RE
S
SX
2$ 2
%
!
$
$4$ $
4
%2
$
)3
.$ .
/
0OR $
ES
ELEC
T
$X $A
TAFR O
M
"#X
$ON
gT#A
R E
$1S 4
E
RM
IN
ATIO
NS
O
FF
2$1
3 .O
TD
RIVE
N
DTERDIS followed by DTERDIS
1. At least 1NOP is required between 2 DTERDIS commands. This correspond to a Read to Read transistion on
the other memory in a 2 rank system.
2. CAS Latency 5 is used as an example.
3. The DQ terminations are switched off (CL-1) clock periods after the DTERDIS command for a duration of (BL/2
+ 2 ) clocks
4. The dashed lines (RDQS bus) describe the RDQS behavior in the case where the DTERDIS command
corresponds to a Read command applied to the second Graphics DRAM in a 2 rank system. In this case,
RDQS would be driven by the second Graphics DRAM.
Data Sheet
56
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
3.9.1
DTERDIS followed by READ
.$
.$
2$
.$
.$
.$
.$
.$
.$
.$
.$
.$
.$
.$
#,+
#,+
#OM
!DD
R
"#
X
#!3
LATE
NCY
2$1
3
$X $X $X $X
$1
#OM
.$
!DD
R
.$
.$
2$
.$
.$
.$
.$
.$
.$
"#
X
#!3LATENC
Y
2$1
3
$1
$X $X $X $X
#OM
#
O
MMA
ND
!DD
R !
DD
R ES
S"
#
Figure 41
"#
X
"
ANK
#
O
LU
MNA
DDR E
S
SX
2$ 2
%
!$
$4$
$
4
%2
$
)3
.$
.
/
0OR $
E
SE
LEC
T
$X $
A
TA
FRO
M"
#
X
$ON
gT#
A
R E
$1S 4
ERM
INA
TION
S
O
FF
2$1
3 .
O
TD
RIV
EN
DTERDIS Command followed by READ
1. At least 3 NOPs are required between a DTERDIS command and a READ command in order to avoid
contention on the RDQS bus in a 2 rank system.
2. CAS Latency 5 is used as an example.
3. The DQ terminations are switched off (CL-1) clock periods after the DTERDIS command for a duration of 4
clocks.
Data Sheet
57
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
3.9.2
DTERDIS followed by Write
$4$
$%3
$%3
$%3
$%3
$%3
72
$%3
$%3
$%3
$%3
$%3
#,+
#,+
#OM
!DDR "#W
#!3LATE
N
CY
7RITELATENC Y 7$1
3
$W
$W $W $W
$1
$4$
$%3
$%3
$%3
$%3
$%3
72
$%3
$%3
$%3
$%3
$%3
"#W
7RITE
LATE
NC Y #!3LATE
NC Y
7$1
3
$W
$W $W
$1
"#
W
"
AN
K #
O
LU
MN
A
DD
R ES SFO
R 7
2
)4%
72 7
2)4
%
$4$
$
4
%
2$
)3
$%3
$
E
S ELE
CT
Figure 42
$XW 72)4
%
$
A
TA
FRO
M"
#
#OM #
O
MM
AND
!DDR !
D
DR E
S S"
#
$ON
gT#A
R E
$1S 4
E
RM
IN
ATIO
NS O
FF
DTERDIS Command followed by Write
1. Write shown with nominal value of tDQSS
2. WDQS can only transition when data is applied at the chip input and during pre- and postambles
3. The minimum distance between DTERDIS and Write is (CL -WL + 4) clocks.
Data Sheet
58
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
3.10
Precharge (PRE/PREALL)
The Precharge command is used to deactivate the
open row in a particular bank (PRE) or the open rows in
all banks (PREALL). The bank(s) will enter the idle
state and be available again for a new row access after
the time tRP. A8/AP sampled with the PRE command
determines whether one or all banks are to be
precharged. For PRE commands BA0 and BA1 select
the bank. For PREALL inputs BA0 and BA1 are “Don’t
Care”. The PRE/PREALL command may not be given
unless the tRAS requirement is met for the selected bank
(PRE), or for all banks (PREALL).
#,+
#,+
#+%
#3
2!3
#!3
7%
! !
!,,
"! "!
"!
!,,
(IG
HS ELEC TS A
LLB
AN
KS ,OW
S ELEC TS "
AN
K "!
"! "
A
NK !
D
DRE
SS
$ONgT#
A
RE
Figure 43
Precharge Command
Table 26
BA1, BA0 precharge bank selection
A8 / AP
BA1
BA0
precharged bank(s)
0
0
0
Bank 0 only
0
0
1
Bank 1 only
0
1
0
Bank 2 only
0
1
1
Bank 3 only
1
X
X
All banks
Data Sheet
59
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
#,+
#,+
#OMM
AN
D
!#4
!!
2OW
"!
"
!
"8
./0
02%
./0
./0
!#4
2OW
"8
"8
T2!3 T20
02%
0
R EC HA
RG
E
!#4
!
C TIVA
TE
2OW 2
O
W!
D
DRE
S S
"8 "A
N
K8
T2#
$ON
gT#
A
R E
Figure 44
Precharge Timing
Table 27
Precharge Timing Parameters for –1.6, –2.0 and –2.2 speed sorts
Parameter
Symbol
Limit Values
–1.6
Row Precharge Time
Data Sheet
tRP
Unit
–2.0
–2.2
min
max
min
max
min
max
13.2
–
13.2
–
13.2
–
60
Notes
ns
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
3.11
Auto Refresh Command (AREF)
AREF is used to do a refresh cycle on one row in each
bank. The addresses are generated by an internal
refresh controller; external address pins are “DON’T
CARE”. All banks must be idle before the AREF
command can be applied. The delay between the
AREF command and the next ACT or subsequent
AREF must be at least tRFC(min). The refresh period
starts when the AREF command is entered and ends
tRFC later at which time all banks will be in the idle state.
#,+
#,+
#+%
#3
Within a period of tREF=32ms the whole memory has to
be refreshed. The average periodic interval time from
AREF to AREF is then tREFI(max)=7.8µs.
2!3
To improve efficiency bursts of AREF commands can
be used. Such bursts may consist of maximum 8 AREF
commands. tRFC(min) is the minimum required time
between two AREF commands inside one AREF burst.
According to the number of AREF commands in one
burst the average required time from one AREF burst
to the next can be increased. Example: If the AREF
bursts consists of 4 AREF commands, the average
time from one AREF burst to the next is 4 * 7.8µs =
31.2µs.
#!3
7%
!!
"! "!
The AREF command generates an update of the OCD
output impedance and of the addresses, commands
and DQ terminations. The timing parameter tKO ( see
section 2.3.2 ) must be complied with.
"! "
AN
K!D
D
RE
SS
$ONgT#
A
RE
Figure 45
Auto Refresh Command
#,+
#,+
#OMM
AN
D
#+%
02%
!2&
T20
./0
!#
./0
!2&
T2&#
./0
!# !
2%
&
O
R !#
4
#O
M
MAN
D
!2&
!
U
TO
2
E
FR E
SH
T2%& )
$ON
gT#
A
R E
Figure 46
Auto Refresh Cycle
Table 28
Autorefresh Timing Parameters for –1.6, –2.0 and –2.2 speed sorts
Parameter
Symbol
Limit Values
–1.6
Refresh Period (4096 cycles)
Average periodic Auto Refresh interval
Delay from AREF to next ACT/ AREF
Data Sheet
tREF
tREFI
tRFC
Unit
–2.0
–2.2
min
max
min
max
min
max
—
32
—
32
—
32
7.8
54
—
61
7.8
54
—
Notes
7.8
54
—
ms
µs
ns
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
3.12
Self-Refresh
3.12.1
Self-Refresh Entry (SREFEN)
The Self-Refresh mode can be used to retain data in
the GDDR3 Graphics RAM even if the rest of the
system is powered down. When in the Self-Refresh
mode, the GDDR3 Graphics RAM retains data without
external clocking. The Self-Refresh command is
initiated like an Auto-Refresh command except CKE is
disabled (LOW). Self Refresh Entry is only possible if all
banks are precharged and tRP is met.
#,+
#,+
#+%
#3
The GDDR3 Graphics RAM has a build-in timer to
accomodate Self-Refresh operation. The Self-Refresh
command is defined by having CS, RAS, CAS and CKE
held low with WE high at the rising edge of the clock.
Once the command is registered, CKE must be held
LOW to keep the device in Self-Refresh mode. When
the GDDR3 Graphics RAM has entered the SelfRefresh mode, all external control signals, except CKE
are disabled. The address, command and data
terminators remain on. The DLL and the clock are
internally disabled to save power. The user may halt the
external clock while the device is in Self-Refresh mode
the next clock after Self-Refresh entry, however the
clock must be restarted before the device can exit SelfRefresh operation.
2!3
#!3
7%
! !
!!
!
"! "!
$ONgT#
A
RE
Figure 47
Self Refresh Entry Command
#,+
#,+
#OMM
AN
D
0!
32&
#
LOC K
#+%
T20
#,+
#,
+
MAY BE
H
ALTED
0! 0R E
CH
A
RG
E!
,,#
O
MMA
ND
O
RLAS TO
F0
2
%
STO
E
AC HB
AN
K
32&
3
ELF2
E
FR E
SH#
O
MMA
ND
$ON
gT#
A
R E
Figure 48
Data Sheet
Self Refresh Entry
62
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
3.12.2
Self-Refresh Exit (SREFEX)
To exit the Self Refresh Mode, a stable external clock
is needed before setting CKE high asynchronously.
Once the Self-Refresh Exit command is registered, a
delay equal or longer than tXSC (minimum 200 Clock
Cycles) must be satisfied before any command can be
applied. During this time, the DLL is automatically
enabled, reset and calibrated.
#,+
#,+
#+%
#3
CKE must remain HIGH for the entire Self-Refresh exit
period and commands must be gated off with CS held
HIGH. Alternately, NOP commands may be registered
on each positive clock edge during the Self Refresh exit
interval.
2!3
#!3
7%
!!
!!
$ON
gT#
AR E
Figure 49
Self Refresh Exit Command
#,+
#,+
#OM
MA
ND
.$
.$
.$
!#
#+%
T83# #,+#
,
+
M
US T
BESTAB
LE
!# !N
Y #O
M
MAN
D
.$
./
0O
R$
%
3%
,
#
O
MM
AND
$ONgT#
A
RE
Figure 50
Self Refresh Exit
Table 29
Self Refresh Exit Timing Parameter for –1.6, –2.0 and –2.2 speed sorts
Parameter
Symbol
Limit Values
–1.6
Self Refresh Exit time
Data Sheet
tXSC
Units Notes
–2.0
–2.2
min
max
min
max
min
max
200
–
200
–
200
–
63
tCK
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
3.13
Power-Down
burst completion is defined after the rising edge of the
Read Postamble. For Writes, a burst completion is
defined one clock after the rising edge of the Write
Postamble.
#,+
#,+
#+%
For Read with Autoprecharge and Write with
Autoprecharge, the internal Autoprecharge must be
completed before entering Power-Down.
#3
Power-Down is entered when CKE is registered LOW
(no access can be in progress). If Power-Down occurs
when all banks are idle, this mode is referred to as
Precharge Power-Down; if Power-Down occurs when
there is a row active in any bank, this mode is referred
to as Active Power-Down. Entering power-down
deactivates the input and output buffers, excluding
CLK, CLK and CKE. For maximum power saving, the
user has the option of disabling the DLL prior to
entering power-down. In that case the DLL must be
enabled and reset after exiting power-down, and 200
cycles must occur before a READ command can be
issued.
2!3
#!3
7%
!!
In Power-Down mode, CKE low and a stable clock
signal must be maintained at the inputs of the GDDR3
Graphics RAM, all the other input signals are “Don’t
Care”. Power down duration is limited by the refresh
requirements of the device.
"! "!
$
%
3
%,
./
0
$ONgT#
A
RE
Figure 51
Power Down Command
The Power-Down state is synchronously exited when
CKE is registered HIGH (along with a NOP or DESEL
command). A valid executable command may be
applied tXPN later.
Unlike SDR SDRAMs, the GDDR3 Graphics RAM
requires CKE to be active at all times an access is in
progress : From the issuing of a READ or WRITE
command until completion of the burst. For READs, a
#,+
#,+
#OMM
.$
.$
.$
.$
!#
!#
#+%
T)3
0OWE
R $O
WN
-ODE
%N
TR Y
T80.
0OWE
R$
O
WN
-ODE
%X IT
.$
.
/
0O
R $
%
3
%,
%
#
4
#OM
MAND
!# !N
Y #O
M
MAN
D
$ONgT#
A
RE
Figure 52
Power-Down Mode
Table 30
Power Down Exit Timing Parameter for –1.6, –2.0 and –2.2 speed sorts
Parameter
Symbol
Limit Values
–1.6
Precharge power-down exit timing
Data Sheet
tXPN
–2.0
Unit
–2.2
min
max
min
max
min
max
5
—
4
—
4
—
64
Notes
tCK
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Electrical Characteristics
4
Electrical Characteristics
4.1
Absolute Maximum Ratings
Table 31
Absolute Maximum Ratings
Parameter
Symbol
Power Supply Voltage
VDD
VDDQ
VIN
VOUT
TSTG
IOUT
Power Supply Voltage for Output Buffer
Input Voltage
Output Voltage
Storage Temperature
Short Circuit Output Current
Rating
Unit
min.
max.
-0.5
2.5
V
-0.5
2.5
V
-0.5
V
-0.5
VDDQ+0.5
VDDQ+0.5
-55
+150
°C
—
50
mA
V
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage of the
device. This is a stress rating only, and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Table 32
Operation Conditions
Parameter
Symbol
Operation Temperature (Junction)
TJ
TC
PD
Operation Temperature (Case)
Power Dissipation
Data Sheet
65
Range
Unit
min.
max.
0
+90
°C
0
+85
°C
—
3.2
W
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Electrical Characteristics
4.2
Recommended Power & DC Operation Conditions.
All values are recommended operating conditions unless otherwise noted. Tc = 0 to 85 °C.
(0°C ≤ TC ≤ +85°C, VDD = +2.0 V ± 0.10 V, VDDQ = +2.0 V ± 0.10 V, see Table 1)
Table 33
Power & DC Operation Conditions
Parameter
Symbol Speed
sort
Limit Values
min.
typ.
max.
Power Supply Voltage
VDD
–1.6
1.9
2.0
2.1
V
1)
–2.0
1.9
2.0
2.1
V
1)
–2.2
1.9
2.0
2.1
V
1)
–1.6
1.9
2.0
2.1
V
1)
–2.0
1.9
2.0
2.1
V
1)
–2.2
1.9
2.0
2.1
V
1)
–1.6
0.72*VDDQ 0.73*VDDQ 0.74*VDDQ V
2)
–2.0
0.72*VDDQ 0.73*VDDQ 0.74*VDDQ
2)3)
–2.2
0.72*VDDQ 0.73*VDDQ 0.74*VDDQ
2)3)
Power Supply Voltage for I/O Buffer
Reference Voltage
Output Low Voltage
Input leakage current
CLK Input leakage current
Output leakage current
VDDQ
VREF
VOL(DC)
IIL
IILC
IOL
Unit Notes
0.4*VDDQ
V
–5
+5
µA
–5
+5
µA
–5
+5
µA
4)
4)
VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
2) VREF is allowed ± 19mV for DC error and an additionnal ± 28mV for AC noise.
3) VREF is expected to equal 73% of VDDQ for the transmitting device and to track variations in the DC level of the
same. Peak-to-peak noise on VREF may not exceed ±2% VREF (DC). Thus, from 73% of VDDQ.
4) IIL and IOL are measured with ODT disabled.
1)
Data Sheet
66
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Electrical Characteristics
4.3
DC & AC Logic Input Levels.
(0°C ≤ TC ≤ +85°C, VDD = +2.0 V ± 0.10 V, VDDQ = +2.0 V ± 0.10 V, see Table 1)
Table 34
DC & AC Logic Input Levels
Parameter
Symbol
Input logic high voltage, DC
Input logic low voltage, DC
Input logic high voltage, AC
Input logic low voltage, AC
Input logic high, DC, RESET pin
Input logoc low, DC, RESET pin
VIH(DC)
VIL(DC)
VIH (AC)
VIL(AC)
VIHR(DC)
VILR(DC)
Limit Values
Unit Notes
min.
max.
0.7 *VDDQ + 0.15
—
V
1
—
0.7 *VDDQ -0.15
V
1
0.7 *VDDQ +0.4
—
V
2,3
—
0.7 *VDDQ - 0.4
V
2,3
0.8 *VDDQ
VDDQ + 0.3
0.2 *VDDQ
V
-0.3
V
1. The DC values define where the input slew rate requirements are imposed, and the input signal must not
violate these levels in order to maintain a valid level.
2. Input slew rate = 2 V/ns. If the input slew rate is less than 2 V/ns, input timing may be compromised. All slew
rates are measured between VIL(DC) and VIH(DC).
3. VIH overshoot : VIH(MAX) = VDDQ+0.5 V for a pulse width ≤ 500ps and the pulse width cannot be greater than 1/3
of the cycle rate. VIL undershoot: VIL(MIN) = 0 V for a pulse width ≤ 500ps and the pulse width cannot be greater
than 1/3 of the cycle rate.
4.4
Differential Clock DC and AC Levels
(0°C ≤ TC ≤ +85°C, VDD = +2.0 V ± 0.10 V, VDDQ = +2.0 V ± 0.10 V, see Table 1)
Table 35
Differential Clock DC and AC Input conditions
Parameter
Symbol Limit Values
Clock Input Mid-Point Voltage, CLK and CLK VMP(DC)
Unit
Note
s
V
1
min.
max.
VREF - 0.1
V
1
V
1
Clock DC Input Differential Voltage, CLK and VID(DC)
CLK
0.3
VREF + 0.1
VDDQ + 0.3
VDDQ
Clock AC Input Differential Voltage, CLK and VID(AC)
CLK
0.5
VDDQ + 0.5
V
1, 2
AC Differential Crossing Point Input Voltage VIX(AC)
VREF - 0.15
VREF + 0.15
V
1, 3
Clock Input Voltage Level, CLK and CLK
VIN(DC)
0.42
1. All voltages referenced to VSS
2. VID is the magnitude of the difference between the input level on CLK and the input level on CLK.
3. The value of VIX is expected to equal 0.7 x VDDQ of the transmitting device and must track variations in the DC
level of the same.
Data Sheet
67
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Electrical Characteristics
4.5
Output Test Conditions
VDDQ
60 Ohm
DQ
DQS
Figure 53
Test point
Output Test Circuit
Note: VDDQ=2.0 ±0.1 V, Tc=0 °C to 85 °C, see Table 1
4.6
Pin Capacitances
Table 36
Capacitances
Parameter
Symbol
Min
Max
Unit
Input capacitance:
CLK, CLK
CCK
2.0
4.0
pF
Input capacitance delta:
CLK, CLK
CDCK
0.1
pF
Input capacitance:
A0-A11, BA0-1,CKE, CS, CAS, RAS, WE, CKE, RES
CI
4.0
pF
Input capacitance delta:
A0-A11, BA0-1,CKE, CS, CAS, RAS, WE, CKE, RES
DCI
0.6
pF
Input capacitance:
DQ0-DQ31, RDQS0-RDQS3, WDQS0-WDQS3, DM0DM3
CIO
4.5
pF
Input capacitance delta:
DQ0-DQ31, RDQS0-RDQS3, WDQS0-WDQS3, DM0DM3
DCIO
0.6
pF
2.0
2.5
Notes
1
1
2
1. The input capcitance per pin group will not differ by more than this maximum amount for any given device.
2. The IO capacitance per RDQS and DQ byte / group will not differ by more than this maximum amount for any
given device.
Data Sheet
68
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Electrical Characteristics
4.7
Driver current characteristics
4.7.1
Driver IV characteristics at 40 Ohms
Figure 54 represents the driver Pull-Down and Pull-Up IV characteristics under process, voltage and temperature
best and worst case conditions. The actual Driver Pull-Down and Pull-Up current must lie between these two
bounding curves. The value of the external ZQ resistor is 240Ω, setting the nominal driver output impedance to
40Ω.
0ULL5P
#H
A
RA
CT ERS
T ICS
0ULL$
O
WN#H
A
RA
CTE
R ST ICS
)OU
TM!
)OU
TM!
6$$
1
6OU
T6
6OUT6
Figure 54
40 Ohm Driver Pull-Down and Pull-Up characteristics
Table 37 lists the numerical values of the minimum and maximum allowed values of the output driver Pull-Down
and Pull-Up IV characteristics.
Table 37
Voltage (V)
Programmed Driver IV Characteristics at 40 Ohm
Pull-Down Current (mA)
Pull-Up Current (mA)
Minimum
Maximum
Minimum
Maximum
0.1
2.32
3.04
-2.44
-3.27
0.2
4.56
5.98
-4.79
-6.42
0.3
6.69
8.82
-7.03
-9.45
0.4
8.74
11.56
-9.18
-12.37
0.5
10.70
14.19
-11.23
-15.17
0.6
12.56
16.72
-13.17
-17.83
0.7
14.34
19.14
-15.01
-20.37
0.8
16.01
21.44
-16.74
-22.78
0.9
17.61
23.61
-18.37
-25.04
1.0
19.11
26.10
-19.90
-27.17
1.1
20.53
28.45
.21.34
-29.17
1.2
21.92
30.45
-22.72
-31.25
1.3
23.29
32.73
-24.07
-33.00
1.4
24.65
34.95
-25.40
-35.00
1.5
26.00
37.10
-26.73
-37.00
1.6
27.35
39.15
-28.06
-39.14
1.7
28.70
41.01
-29.37
-41.25
1.8
-
42.53
-
-43.29
1.9
-
43.71
-
-45.23
Data Sheet
69
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Electrical Characteristics
4.8
Termination IV Characteristic at 60 Ohms
Figure 55 represents the DQ termination Pull-Up IV characteristic under process, voltage and temperature best
and worst case conditions. The actual DQ termination Pull-Up current must lie between these two bounding
curves. The value of the external ZQ resistor is 240Ω, setting the nominal DQ termination impedance to 60Ω.
(Extended Mode Register programmed to ZQ/4).
/
HM4E
RM
INA
TION
#H
A
RA
CT ERS
TIC
S
)OU
TM
!
6$$
1
6OU
T6
Figure 55
60 Ohm Active Termination Characteristic
Table 38 lists the numerical values of the minimum and maximum allowed values of the output driver termination
IV characteristic.
Table 38
Voltage (V)
Programmed Terminator Characterisitc at 60 Ohm
Terminator Pull-Up Current
(mA)
Minimum
Voltage (V)
Maximum
Terminator Pull-Up Current
(mA)
Minimum
Maximum
1.0
-13.27
-18.11
0.1
-1.63
-2.18
1.1
-14.23
-19.45
0.2
-3.19
-4.28
1.2
-15.14
-20.83
0.3
-4.69
-6.30
1.3
-16.04
-22.00
0.4
-6.12
-8.25
1.4
-16.94
-23.33
0.5
-7.49
-10.11
1.5
-17.82
-24.67
0.6
-8.78
-11.89
1.6
-18.70
-26.09
0.7
-10.01
-13.58
1.7
-19.58
-27.50
0.8
-11.16
-15.19
1.8
-
-28.86
0.9
-12.25
-16.69
1.9
-
-30.15
Data Sheet
70
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Electrical Characteristics
4.9
Termination IV Characteristic at 120 Ohms
Figure 56 represents the DQ or ADD/CMD termination Pull-Up IV characteristic under process, voltage and
temperature best and worst case conditions. The actual termination Pull-Up current must lie between these two
bounding curves. The value of the external ZQ resistor is 240Ω, setting the nominal termination impedance to
120Ω. (Extended Mode Register programmed to ZQ/2 for DQ terminations or CKE = 0 at the RES transition during
Power-Up for ADD/CMD terminations).
/HM
4E
RM
INA
TIO
N#
HA
R AC
TERS
TICS
)OU
TM! 6$$
1
6OU
T 6
Figure 56
120 Ohm Active Termination Characteristic
Table 39 lists the numerical values of the minimum and maximum allowed values of the termination IV
characteristic.
Table 39
Voltage(V)
Programmed Terminator Characterisitics at 120 Ohm
Terminator Pull-Up Current
(mA)
Minimum
Voltage (V)
Maximum
Terminator Pull-Up Current
(mA)
Minimum
Maximum
1.0
-6.63
-9.06
0.1
-0.81
-1.09
1.1
-7.11
-9.72
0.2
-1.60
-2.14
1.2
-7.57
-10.42
0.3
-2.34
-3.15
1.3
-8.02
-11.00
0.4
-3.06
-4.12
1.4
-8.47
-11.67
0.5
-3.74
-5.06
1.5
-8.91
-12.33
0.6
-4.39
-5.94
1.6
-9.35
-13.05
0.7
-5.00
-6.79
1.7
-9.79
-13.75
0.8
-5.58
-7.59
1.8
-
-14.43
0.9
-6.12
-8.35
1.9
-
-15.08
Data Sheet
71
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Electrical Characteristics
4.10
Termination IV Characteristic at 240 Ohms
Figure 57 represents the ADD/CMD termination Pull-Up IV characteristic under process, voltage and temperature
best and worst case conditions. The actual ADD/CMD termination Pull-Up current must lie between these two
bounding curves. The value of the external ZQ resistor is 240Ω, setting the nominal termination impedance to
240Ω. (CKE = 1at the RES transition during Power-Up for ADD/CMD terminations).
/H
M4
E
RM
INA
TION
#H
A
RA
CTER ST ICS
)OU
TM
!
6$$
1
6OU
T6
Figure 57
240 Ohm Active Termination Characteristic
Table 40 lists the numerical values of the minimum and maximum allowed values of the ADD/CMD termination IV
characteristic.
Table 40
Voltage (V)
Programmed Terminator Characterisitc at 240 Ohm
Terminator Pull-Up Current
(mA)
Voltage (V)
Terminator Pull-Up Current
(mA)
Minimum
Maximum
1.0
-3.32
-4.53
0.1
-0.41
-0.55
1.1
-3.56
-4.86
0.2
-0.80
-1.07
1.2
-3.79
-5.21
0.3
-1.17
-1.58
1.3
-4.01
-5.50
0.4
-1.53
-2.06
1.4
-4.23
-5.83
0.5
-1.87
-2.53
1.5
-4.46
-6.17
0.6
-2.20
-2.97
1.6
-4.68
-6.52
0.7
-2.50
-3.40
1.7
-4.90
-6.88
0.8
-2.79
-3.80
1.8
-
-7.21
0.9
-3.06
-4.17
1.9
-
-7.54
Data Sheet
Minimum
72
Maximum
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Electrical Characteristics
4.11
Operating Currents
4.11.1
Operating Current Ratings
(0°C ≤ TC ≤ +85°C, VDD = +2.0 V ± 0.10 V, VDDQ = +2.0 V ± 0.10 V, see Table 1)
Table 41
Operating Current Ratings
Parameter
Symbol –1.6
–2.0
–2.2
typ.
typ.
typ.
Operating Current
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
IDD7
274
238
297
Operating Current
Precharge Power-Down Standby Current
Precharge Floating Standby Current
Precharge Quiet Standby Current
Active Power-Down Standy Current
Active Standby Current
Operating Current Burst Read
Operating Current Burst Write
Auto-Refresh Current (tRC=min(tRFC))
Auto-Refresh Current at tREFI
Self Refresh Current
Operating Current
1)
Unit
Notes
222
mA
1)2)3)
258
241
mA
1)2)3)
99
86
81
mA
1)2)3)
156
136
127
mA
1)2)3)
113
98
92
mA
1)2)3)
99
86
81
mA
1)2)3)
182
158
148
mA
1)2)3)
474
412
385
mA
1)2)3)
320
278
265
mA
1)2)3)
430
374
348
mA
1)2)3)
101
88
83
mA
1)2)3)
11
11
11
mA
1)2)3)4)
630
548
509
mA
1)2)3)
IDD specifications are tested after the device is properly initialized.
2) Input slew rate = 2 V/ns.
3) Mesured with Output open and On Die termination off.
4) Enables on-chip refresh and address counter.
4.12
Operating Current Measurement Conditions
(0°C ≤ TC ≤ +85°C, VDD = +2.0V ± 0.10 V, VDDQ = +2.0 V ± 0.10 V, see Table 1)
Table 42
Operating Current Measurement Conditions
Symbol Parameter/Condition
IDD0
Operating Current - One bank, Activate - Precharge
tCK=min(tCK), tRC=min(tRC)
Databus inputs are SWITCHING; Address and control inputs are SWITCHING, CS = HIGH between
valid commands.
IDD1
Operating Current - One bank, Activate - Read - Precharge
One bank is accessed with tCK=min(tCK), tRC=min(tRC), CL = CL(min), Address and control inputs are
SWITCHING;
CS = HIGH between valid commands. Iout=0mA
IDD2P
Precharge Power-Down Standby Current
All banks idle, power-down mode, CKE is LOW, tCK=min(tCK), Data bus inputs are STABLE.
IDD2F
Precharge Floating Standby Current
All banks idle; CS is LOW, CKE is HIGH, tCK=min(tCK); Address and control inputs are SWITCHING;
Data bus input are STABLE.
Data Sheet
73
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Electrical Characteristics
Table 42
Operating Current Measurement Conditions
Symbol Parameter/Condition
IDD2Q
Precharge Quiet Standby Current
CS is HIGH, all banks idle, CKE is HIGH, tCK=min(tCK), Address and other control inputs STABLE, Data
bus inputs are STABLE.
IDD3P
Active Power-Down Standby Current
All banks active, CKE is LOW, Address and control inputs are STABLE; Data bus inputs are STABLE;
standard active power-down mode.
IDD3N
Active Standby Current
All banks active, CS is HIGH, CKE is HIGH, tRC=max(tRAS), tCK=min(tCK); Address and control inputs
are SWITCHING; Data bus inputs are SWITCHING; Iout = 0 mA.
IDD4R
Operating Current - Burst Read
All banks active; Continuous read bursts, CL = CL(min); tCK=min(tCK); Address and control inputs are
SWITCHING; Data bus inputs are SWITCHING.
IDD4W
Operating Current - Burst Write
All banks active; Continuous write bursts; tCK=min(tCK); Address and control inputs are SWITCHING;
Data bus inputs are SWITCHING.
IDD5B
Burst Auto Refresh Current
Refresh command at tRC=min(tRFC); tCK=min(tCK); CKE is HIGH, CS is HIGH between all valid
commands; Other command and address inputs are SWITCHING; Data bus inputs are SWITCHING.
IDD5D
Distributed Auto Refresh Current
tCK=tCKmin; Refresh command every tREFI; CKE is HIGH, CS is HIGH between valid commands;
Other command and address inputs are SWITCHING; Data bus inputs are SWITCHING.
IDD6
Self Refresh Current
CKE ≤ max(VIL), external clock off, CK and CK LOW; Address and control inputs are STABLE; Data
Bus inputs are STABLE.
IDD7
Operating Bank Interleave Read Current
1. All banks interleaving with CL = CL(min); tRCD = tRCDRD(min); tRRD = tRRD(min); Iout=0mA;
Address and control inputs are STABLE during DESELECT; Data bus inputs are SWITCHING.
2: Timing pattern:
-1.6 (600 MHz, CL=7) : tCK = 2.5ns, tRCDRD = 7. tCK; tRRD = 4. tCK; tRC = 18. tCK
Read: A0 RA3 D D A1 D D RA0 A2 D D RA1 A3 D D RA2 D D TBD TBD TBD
-2.0 (500 MHz, CL7) : tCK = 2.0ns, tRCDRD = 7. tCK; tRRD = 4. tCK; tRC = 18. tCK
Read: A0 RA3 D D A1 D D RA0 A2 D D RA1 A3 D D RA2 D D
-2.2 (455 MHz, CL6) : tCK = 2.2ns, tRCDRD = 7. tCK; tRRD = 4. tCK; tRC = 18. tCK
Read: A0 RA3 D D A1 D D RA0 A2 D D RA1 A3 D D RA2 D D
1. Data Bus consists of DQ, DM, WDQS
2. Definitions for IDD : LOW is defined as VIN = 0.4 x VDDQ; HIGH is defined as VIN = VDDQ;
STABLE is defined as inputs are stable at a HIGH level.
SWITCHING is defined as inputs are changing between HIGH and LOW every clock cycle for address and
control signals, and inputs changing 50% of each data transfer for DQ signals.
3. Legend : A=Activate, RA=Read with Autoprecharge, D=DESELECT
Data Sheet
74
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Electrical Characteristics
4.13
Summary of timing parameters for –1.6, –2.0 and –2.2 ns speed sorts in DLL
on mode
Table 43
Timing Parameters for –1.6, –2.0 and –2.2 speed sorts
Parameter
Read
Symlatency bol
Limit Values
Unit Notes
–1.6
–2.0
–2.2
min
max
min
max
min
max
1.6
3.3
2.0
4.0
2.2
4.0
ns
2.0
3.3
2.0
4.0
2.2
4.0
ns
—
—
—
—
2.7
4.0
ns
300
600
250
500
250
455
MHz
300
500
250
500
250
455
MHz
—
—
—
—
250
370
MHz
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
0.45
—
0.45
—
0.45
—
tCK
tCK
tCK
0.6
—
0.75
—
0.75
—
ns
0.6
—
0.75
—
0.75
—
ns
0.85
—
0.85
—
0.85
—
tCK
5
—
4
—
4
—
15
—
12
—
12
—
tCK
tCK
37.2
—
37.2
—
39.6
—
ns
24.0
8 x tREFI
24.0
8 x tREFI 26.2
8 x tREFI ns
8.0
—
8.0
—
8.8
—
ns
13.2
—
13.2
–
13.2
–
ns
16.0
—
16.0
–
17.5
–
ns
Clock and Clock Enable
Clock Cycle Time
7
6
5
System frequency
7
6
5
Clock high level width
Clock low-level width
Minimum clock half period
tCK7
tCK6
tCK5
fCK7
fCK6
fCK5
tCH
tCL
tHP
1)
Command and Address Setup and Hold Timing
Address/Command input setup time tIS
Address/Command input hold time
Address/Command input pulse
width
tIH
tIPW
Mode Register Set Timing
tMRD
Mode Register Set to READ timing tMRDR
Mode Register Set cycle time
Row Timing
tRC
Row Active Time
tRAS
ACT(a) to ACT(b) Command period tRRD
Row Precharge Time
tRP
Row to Column Delay Time for
tRCDRD
Row Cycle Time
Reads
Row to Column Delay Time for
Writes
tRCDWR
tRCDWR(min) = tRCDRD(min) - (WL + 1) x tCK(min)
ns
Column Timing
CAS(a) to CAS(b) Command period tCCD
Write to Read Command Delay
Read to Write command delay
tWTR
tRTW
2
—
2
—
2
—
tCK
2)
6.0
—
6.0
—
6.6
—
ns
3)
tCK
4)
tRTW(min)= (CL+4-WL)
Write Cycle Timing Parameters for Data and Data Strobe
Write command to first WDQS
latching transition
tDQSS
WL 0.25
WL
+0.25
WL 0.25
WL
+0.25
WL 0.25
WL
+0.25
tCK
Data-in and Data Mask to WDQS
Setup Time
tDS
0.35
—
0.375
—
0.375
—
ns
Data Sheet
75
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Electrical Characteristics
Table 43
Timing Parameters for –1.6, –2.0 and –2.2 speed sorts
Parameter
Read
Symlatency bol
Limit Values
Unit Notes
–1.6
–2.0
–2.2
min
max
min
max
min
max
Data-in and Data Mask to WDQS
Hold Time
tDH
0.35
—
0.375
—
0.375
—
ns
Data-in and DM input pulse width
(each input)
tDIPW
0.45
—
0.45
—
0.45
—
tCK
DQS input low pulse width
tDQSL
tDQSH
tWPRE
tWPST
tWR
0.45
—
0.45
—
0.45
—
0.45
—
0.45
—
0.45
—
0.75
1.25
0.75
1.25
0.75
1.25
0.75
1.25
0.75
1.25
0.75
1.25
tCK
tCK
tCK
tCK
11.0
—
11.0
—
11.0
—
ns
DQS input high pulse width
DQS Write Preamble Time
DQS Write Postamble Time
Write Recovery Time
3
Read Cycle Timing Parameters for Data and Data Strobe
tAC
Read Preamble
tRPRE
Read Postamble
tRPST
Data-out high impedance time from tHZ
Data Access Time from Clock
–0.4
0.4
–0.4
0.4
–0.45
0.45
ns
0.75
1.25
0.75
1.25
0.75
1.25
0.75
1.25
0.75
1.25
0.75
1.25
tCK
tCK
tACmin
tACmax
tACmin
tACmax
tACmin
tACmax
ns
tACmin
tACmax
tACmin
tACmax
tACmin
tACmax
ns
–0.4
0.4
–0.4
0.4
–0.45
0.45
ns
—
0.225
—
0.225
—
0.25
ns
0
0.225
0
0.225
0
0.25
ns
CLK
Data-out low impedance time from
CLK
tLZ
tDQSCK
DQS edge to output data edge skew tDQSQ
Data hold skew factor
tQHS
Data output hold time from DQS
tQH
DQS edge to Clock edge skew
tHP–tQHS
tHP–tQHS
tHP–tQHS
tREF
tREFI
—
—
Delay from AREF to next ACT/
AREF
tRFC
54
—
54
—
54
—
ns
Self Refresh Exit time
tXSC
tXPN
t XARD
200
—
200
—
200
—
5
—
4
—
4
—
8
—
6
—
6
—
tCK
tCK
tCK
tATS
tATH
tKO
10
—
10
—
10
—
ns
10
—
10
—
10
—
ns
10
—
10
—
10
—
ns
tRIDon
tRIDoff
—
20
—
20
—
20
ns
—
20
—
20
—
20
ns
ns
Refresh/Power Down Timing
Refresh Period (4096 cycles)
Average periodic Auto Refresh
interval
Precharge Power Down Exit time
Active Power Down Exit time
32
7.8
32
7.8
—
32
7.8
ms
µs
Other Timing Parameters
RES to CKE setup timing
RES to CKE hold timing
Termination update Keep Out
timing
Rev. ID EMRS to DQ on timing
Rev. ID EMRS to DQ off timing
tHP is the lesser of tCL minimum and tCH minimum actually applied to the device CLK, CLK inputs
tCCD is either for gapless consecutive reads or gapless consecutive writes.
3) tWTR and tWR start at the first rising edge of CLK after the last valid (falling) WDQS edge of the slowest WDQS signal.
4) Please round up tRTW to the next integer of tCK.
1)
2)
Data Sheet
76
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Electrical Characteristics
4.14
AC Characteristics and Settings
The following tables are meant as a guideline to correctly set the most important timing parameters depending on
speed sort and clock frequency.
Table 44
HYB18T256324F–16
Frequency / tCK
CAS
tRC
Latency
tRFC
tRAS
tRP
tWR
tRRD
tRCDRD
tRCDWR Unit
600 MHz / 1.6ns
7
23
33
15
8
7
5
10
7
500 MHz / 2.0ns
7
19
27
12
7
6
4
8
6
455 MHz / 2.2ns
7
17
25
11
6
5
4
8
6
400 MHz / 2.5ns
6
15
22
10
6
5
4
7
5
370 MHz / 2.7ns
6
14
20
9
5
5
3
6
5
300 MHz / 3.0ns
6
12
17
8
4
4
3
5
4
CAS
tRC
Latency
tRFC
tRAS
tRP
tWR
tRRD
tRCDRD
tRCDWR Unit
500 MHz / 2.0ns
7
19
27
12
7
6
4
8
5
455 MHz / 2.2ns
7,6
17
25
11
6
5
4
8
5
400 MHz / 2.5ns
7,6
15
22
10
6
5
4
7
4
370 MHz / 2.7ns
6
14
20
9
5
5
3
6
4
300 MHz / 3.0ns
6
12
17
8
4
4
3
5
3
Table 45
HYB18T256324F–20
Frequency / tCK
Table 46
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
HYB18T256324F–22
Frequency / tCK
CAS
tRC
Latency
tRFC
tRAS
tRP
tWR
tRRD
tRCDRD
tRCDWR Unit
455 MHz / 2.2ns
7
18
25
12
6
5
4
8
5
400 MHz / 2.5ns
7,6
16
22
11
6
5
4
7
5
370 MHz / 2.7ns
7,6
15
20
10
5
5
4
7
4
300 MHz / 3.0ns
5
12
17
8
4
4
3
6
4
266 MHz / 3.8ns
5
11
15
7
4
3
3
5
3
250MHZ / 4.0ns
5
10
14
7
4
3
3
5
3
Data Sheet
77
tCK
tCK
tCK
tCK
tCK
tCK
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Package Outlines
5
Package Outlines
11.00 ± 0.10
0.10
C
11.00 ± 0.10
BALL A1
INDICATOR
1.20 MAX
TOP VIEW
C
1
2
3
4
5
6
7
8
9 10 11 12
M
0.40
J
H
0.80 (11X)
L
K
G
F
0.12
E
C
D
C
B
A
0.40
0.80 (11X)
BALLS VIEW
All dimensions in mm.
Figure 58
Package Outline FBGA
1. The package is conforming with JEDEC MO216
2. The inner matrix of 4x4 balls is reserved for thermal contacts
Data Sheet
78
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Package Outlines
5.1
Package Thermal Characteristics
Table 47
P-FBGA 144 Package Thermal Resitances
Theta_jA
JEDEC Board
1s0p
Theta_jB
Theta_jC
2s0p
Air Flow
0 m/s
1 m/s
3 m/s
0 m/s
1 m/s
3 m/s
-
-
K/W
48.8
40.2
35.1
27.0
23.5
22.0
6.0
3.9
1. Theta_jA : Junction to Ambient thermal resistance. The values have been obtained by simulation using the
conditions stated in the JEDEC JESD-51 standard.
2. Theta_jB : Junction to Board thermal resistance. The value has been obtained by simulation.
3. Theta_jC : Junction to Case thermal resistance. The value has been obtainned by simulation.
Data Sheet
79
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
www.infineon.com
Published by Infineon Technologies AG