INFINEON PXB4340E

ICs for Communications
Content Addressable Memory Element
CAME
PXB 4360 F Version 1.1
Data Sheet 07.2000
Version 1.1
3;%)
5HYLVLRQ+LVWRU\&XUUHQW9HUVLRQ
Previous Version: Preliminary Data Sheet 11.97 (DS 2)
Page
Page
Subjects (major changes since last revision)
(in previous (in current
Version)
Version)
The Data Sheet has been reorganized.
For questions on technology, delivery and prices please contact the Infineon Technologies
Offices in Germany or the Infineon Technologies Companies and Representatives worldwide:
see our webpage at http://www.Infineon.com.
IOM®, IOM®-1, IOM®-2, SICOFI®, SICOFI®-2, SICOFI®-4, SICOFI®-4µC, SLICOFI®, ARCOFI® , ARCOFI®-BA,
ARCOFI®-SP, EPIC®-1, EPIC®-S, ELIC®, IPAT®-2, ITAC®, ISAC®-S, ISAC®-S TE, ISAC®-P, ISAC®-P TE, IDEC®,
SICAT®, OCTAT®-P, QUAT®-S are registered trademarks of Infineon Technologies AG.
MUSAC™-A, FALC™54, IWE™, SARE™, UTPT™, DigiTape™ are trademarks of Infineon Technologies AG.
All other brand or product names, Hardware or Software names are trademarks or registered trademarks of their
respective companies or organizations.
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This edition was realized using the software system FrameMaker.
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© Infineon Technologies AG 2000.
All Rights Reserved.
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As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or
the Infineon Technologies Companies and Representatives worldwide (see address list).
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies AG is an approved CECC manufacturer.
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Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office.
By agreement we will take packing material back, if it is sorted. You must bear the costs of transport.
For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice
you for any costs incurred.
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Critical components1 of Infineon Technologies AG, may only be used in life-support devices or systems2 with the
express written approval of Infineon Technologies AG.
1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device
or system.
2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
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3DJH
1.1
1.2
1.3
2YHUYLHZ Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6\VWHP,QWHJUDWLRQ )XQFWLRQDO2YHUYLHZ 4.1
4.2
4.3
4.4
4.4.1
4.4.2
'DWD)ORZDQG)XQFWLRQDO'HVFULSWLRQRIWKH&$0( Programming of the Search and Search Result Pattern . . . . . . . . . . . . . . . . . . . . 20
Reading the Search Pattern for a Predefined LCI Value . . . . . . . . . . . . . . . . . . . 21
Configuration and Testing of the CAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Search Operation for Cell Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Data Structure of Request Commands for 16-Bit Mode . . . . . . . . . . . . . . . . . . . . 23
Data Structure of the Request Commands for 32-Bit Mode . . . . . . . . . . . . . . . . . 25
5.1
5.2
5.3
5.4
5.5
5.6
5.6.1
5.7
5.7.1
5.7.2
5.7.3
5.7.4
5.7.5
5.7.6
5.7.7
5HJLVWHUV Write Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Search Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Address Register (DLCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Search Result Data Register (SLCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Read Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Description of Status Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Testmode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Data Field of Testmode Register (Selection is MODE) . . . . . . . . . . . . . . . . . . . . 39
Data Field of Testmode Register (Selection is TMODE) . . . . . . . . . . . . . . . . . . . 41
Data Field of Testmode Register (Selection is TMUX) . . . . . . . . . . . . . . . . . . . . . 42
Data Field of Testmode Register (Selection is VER0) . . . . . . . . . . . . . . . . . . . . . 42
Data Field of Testmode Register (Selection is VER1) . . . . . . . . . . . . . . . . . . . . . 43
Data Field of Testmode Register (Selection is VER2) . . . . . . . . . . . . . . . . . . . . . 43
Data Field of Testmode Register (Selection is VER3) . . . . . . . . . . . . . . . . . . . . . 44
6.1
6.2
6.2.1
6.3
6.4
6.5
6.6
,QWHUIDFH'HVFULSWLRQ Data Bus and Address Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Cascade Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Cascade Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Clock and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Boundary Scan Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Microprocessor and Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Reference for Internal Current Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Data Sheet
0-3
07.2000
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7DEOHRI&RQWHQWV
3DJH
7.1
7.2
7.3
7.4
7.5
7.5.1
7.5.2
7.5.3
(OHFWULFDO&KDUDFWHULVWLFV Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
DC Characteristics for all Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Boundary-Scan Test Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
AC Characteristics of CAME Data Interface to the ALP . . . . . . . . . . . . . . . . . . . . 61
AC Characteristics of CAME Cascade Interface . . . . . . . . . . . . . . . . . . . . . . . . . 63
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0-4
07.2000
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/LVWRI)LJXUHV
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Data Sheet
3DJH
Chipset Configuration for Main ATM Layer Functionality . . . . . . . . . . . . . . . . . . . 7
Chipset Configuration for Main ATM Layer Functionality Plus Full OAM . . . . . . . 8
Chipset Configuration for Main ATM Layer Functionality Plus Full OAM
and Arbitrary Header Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Miniswitch Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Line Card Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CAME Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
CAME Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
ALP and CAME Application for 8k Connections . . . . . . . . . . . . . . . . . . . . . . . . . 17
ALP and CAME Application for 16k Connections . . . . . . . . . . . . . . . . . . . . . . . . 18
Block Diagram of the CAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
State Diagram of Status Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Cascade Interface - Interconnection of 2 CAME Chips . . . . . . . . . . . . . . . . . . . . 46
Clock Interface of the CAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Example for VBIAS Reference Voltage Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Input/Output Waveform for AC Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Boundary-Scan Test Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 60
Example of Execution Timing for Write Command (Request #4) . . . . . . . . . . . . 61
CAME Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
CAME Write Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Timing of Cascade Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Sorts of Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
0-5
07.2000
3;%)
/LVWRI7DEOHV
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10:
Table 11:
Table 12:
Table 13:
Table 14:
Table 15:
Data Sheet
3DJH
Data Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cascade Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Selection Criteria for Different Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Responding Device and Overall Result after Search Operation . . . . . . . . . . . .
Overall Status in Case of Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boundary Scan Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CAME Boundary Scan Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boundary-Scan Test Interface AC Timing Characteristics . . . . . . . . . . . . . . . . .
Duration of Command Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parameters for Read/Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cascade Interface Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0-6
45
47
48
49
50
52
52
57
57
58
59
60
61
63
64
07.2000
3;%)
2YHUYLHZ
2YHUYLHZ
The PXB 4360 F ATM Content Addressable Memory Element (CAME) is a member of the
Infineon ATM622 chip set. The entire chip set consists of:
• PXB 4330 E ATM Buffer Manager (ABM)
• PXB 4340 E ATM OAM Processor (AOP)
• PXB 4350 E ATM Layer Processor (ALP)
• PXB 4360 F Content Addressable Memory Element (CAME)
Main ATM Layer functionality is achieved with only two chips, ALP and ABM. The combination
of these two devices provides elementary ATM functionality such as header translation, policing,
OAM support, multicast, and traffic management (see ILJXUH). The functionality is upgradeable
to full OAM support by the AOP (see ILJXUH) and to arbitrary header translation by the CAME
(see ILJXUH).
Pol.
RAM
UTOPIA
P H Ys
UTOPIA
UTOPIA
PXB 4350 E
PXB 4330 E
ALP
ABM
Cell
RAM
Conn.
RAM
)LJXUH
Data Sheet
Cell
RAM
Pointer
RAM
Switch (Loop)
Conn.
RAM
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Pol.
RAM
UTOPIA
UTOPIA
PHYs
PXB 4340 E
PXB 4330 E
ALP
AOP
ABM
CAME
Pointer
RAM
Conn.
RAM
UTOPIA
Cell
RAM
UTOPIA
PXB 4350 E
PXB 4340 E
PXB 4330 E
ALP
AOP
ABM
Conn.
RAM
Data Sheet
S
wit
ch
Cell
RAM
Conn.
RAM
Conn.
RAM
Switch (Loop)
Pol.
RAM
UTOPIA
)LJXUH
UTOPIA
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Conn.
RAM
PHYs
Cell
RAM
PXB 4350 E
Conn.
RAM
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Pointer
RAM
Conn.
RAM
Switch (Loop)
Conn.
RAM
S
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ch
Cell
RAM
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The ATM 622 Layer devices can be used as ....
...a full switch in:
ADSL Concentrators / Multiplexers (DSLAM)
Access Multiplexers
Access Concentrators
Multiservice switches
...Line card in:
Workgroup Switches
Edge Switches
Core Switches
UTOPIA
UTOPIA
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Data Sheet
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UTOPIA
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Due to their immensely flexible scaling facilities, feature set, and throughput, the Infineon
ATM622 layer chips are ideal devices for almost any ATM system solution.
Data Sheet
1-10
07.2000
3;%)
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• ALP Co-processor for Address Reduction to search for a
Port Number PN, VPI and VCI the corresponding Local
Connection Identifier LCI
• Delivers search result during one cell cycle for
Bit rates up to 686 MBit/s
• CAME supports up to 8192 search entries
• Master or Slave mode is selectable to cascade 2 CAME
P-TQFP-144-2 / -3
chips to support up to 16384 search entries
• 16-bit or 32-Bit Data Interface is selectable; ALP uses the
16-Bit interface
• Microprocessor Interface is not necessary as CAME is configurated via Address and Data Bus
• Three search modes are supported:
- Search for LCI and the corresponding PN, VPI and VCI
- Search for PN, VPI and VCI the corresponding LCI
- Search for PN and VPI the corresponding first valid LCI for F4 OAM cells
• Status Report provides:
- Information on search result: single match, mismatch or multimatch
- Information on whether the connection is valid or invalid for a given LCI, PN, VPI and VCI
- Information on whether the VP is terminated or not for a given LCI, PN, VPI and VCI
• Parity error indication for Data Bus and CAME cascade error indication
• Boundary Scan support according to JTAG
• Technology:
- TQFP-144 package
- 3.3 V Power Supply
- typical Power dissipation 0.3 W
- Temperature range from 0°C to +70°C
7\SH
3DFNDJH
PXB 4360 F
P-TQFP-144-2/-3
Data Sheet
1-11
07.2000
3;%)
/RJLF6\PERO
Test/JTAG Interface
PXB 4360 F
CAME
Cascade
Interface
CAME
ALP - Data
Interface
)LJXUH
Data Sheet
ALP - Address
Interface
&$0(/RJLF6\PERO
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108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
VCC
GND
EN16
VCC
CA
GND
VCC
GND
VCC
DAT32
GND
DAT31
VCC
DAT30
GND
DAT29
VCC
DAT28
GND
DAT27
VCC
DAT26
GND
DAT25
VCC
DAT24
GND
DAT23
VCC
GND
VCC
DAT22
DAT21
GND
DAT20
VCC
3LQ&RQILJXUDWLRQ
(Top view)
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
CAME
PXB 4360 F
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
DAT19
VCC
DAT18
GND
DAT17
VCC
DAT16
GND
DAT15
VCC
DAT14
GND
DAT13
VCC
DAT12
GND
DAT11
VCC
CLK
GND
DAT10
VCC
DAT9
GND
DAT8
VCC
DAT7
GND
DAT6
VCC
DAT5
GND
DAT4
VCC
DAT3
GND
VCC
GND
TDI
VCC
TMS
GND
TCK
VCC
TRST
GND
VCC
ADR0
GND
ADR1
VCC
ADR2
GND
ADR3
VCC
RES
GND
WE
VCC
OE
GND
CS
VCC
GND
VCC
GND
VCC
DAT0
GND
DAT1
VCC
DAT2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
TMD0
GND
VCC
GND
TMD1
VCC
TMD2
GND
TMD3
VCC
TMD4
GND
TMD5
VCC
TMD6
GND
TMD7
VCC
CO0
GND
CO1
VCC
CO2
GND
CI0
VCC
CI1
GND
CI2
VCC
VBIAS
RBIAS
GND
VCC
GND
TDO
)LJXUH
Data Sheet
ITP09962
&$0(3LQ&RQILJXUDWLRQ
1-13
07.2000
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3LQ'HILQLWLRQVDQG)XQFWLRQV
The following explanations apply to all pins within a field in the following table:
Pins with a 1) attached are connected with an internal pull up resistor.
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3LQ1R
6\PERO
,QSXW,
2XWSXW2
)XQFWLRQ
*HQHUDOSLQV
20
RES
I
Hardware reset signal
Active low
54
CLK
I
Clock input of bus interface
'DWDDQG$GGUHVV%XV,QWHUIDFHEHWZHHQ&$0(DQG$/3SLQV
99, 97, 95, 93, 91, DAT
89, 87, 85, 83, 81, (32:0)
77, 76, 74, 72, 70,
68, 66, 64, 62, 60,
58, 56, 52, 50, 48,
46, 44, 42, 40, 38,
36, 34, 32
I/O
Data bus of bus interface including parity bit
(DAT(0)).
18, 16, 14, 12
ADR
(3:0)
I
Address bus of the bus interface
26
CS
I
Chip enable signal of the bus interface.
Active low
24
OE
I
Output enable signal of the bus interface.
Active low
22
WE
I
Write enable signal of the bus interface.
Active low
106
EN16
I
16-Bit mode enable signal of the bus
interface.
If 0, then DAT(16:0) are used.
If 1, then DAT(32:0) are used.
With ALP, this pin should be 0 for use with the
16-bit data bus.
&$0(&DVFDGH,QWHUIDFHSLQV
Data Sheet
1-14
07.2000
3;%)
3LQ'HILQLWLRQVDQG)XQFWLRQV(cont’d)
3LQ1R
6\PERO
,QSXW,
2XWSXW2
)XQFWLRQ
104
CA
I
Cascade interface address input
137, 135, 133
CI
(2:0)
I
Cascade interface communication channel
131, 129, 127
CO
(2:0)
O
Cascade interface communication channel.
Do not connect in single CAME application.
-7$*,QWHUIDFHSLQV
9 1)
TRST
I
Boundary scan test reset
Active low
3 1)
TDI
I
Boundary scan test data input
7 1)
TCK
I
Boundary scan test clock input
5 1)
TMS
I
Boundary scan test mode select
144
TDO
O
Boundary scan test data output
O
Test Interface. Only for test purpose. Do not
connect.
$GGLWLRQDO7HVWSLQVSLQV
125, 123, 121,
119, 117, 115,
113, 109
TMD
(7:0)
0LVFHOODQHRXVSLQV
139
VBIAS
I
Analog reference voltage input, used for a
precise adjustment of the internal current
sources. VBIAS value: 1.2 V ±10%.
VBIAS = 1 switches into “powerdown” and
disables CAME functionality.
140
RBIAS
O
Calibration output, used to define the bias
current of the internal current sources. A
resistor (12.1 kΩ ±1%) must be connected
between the RBIAS pin and ground.
Data Sheet
1-15
07.2000
3;%)
3LQ'HILQLWLRQVDQG)XQFWLRQV(cont’d)
3LQ1R
6\PERO
,QSXW,
2XWSXW2
)XQFWLRQ
6XSSO\DQG*1'SLQV
1, 4, 8, 11, 15, 19, 23, 27, 29, 31, 35, 39, 43, 47, VCC
51, 55, 59, 63, 67, 71, 73, 78, 80, 84, 88, 92, 96, (P3V3)
100, 102, 105, 108, 111, 114, 118, 122, 126,
Supply Voltage (nominal 3.3 V)
130, 134, 138, 142
2, 6, 10, 13, 17, 21, 25, 28, 30, 33, 37, 41, 45, GND
49, 53, 57, 61, 65, 69, 75, 79, 82, 86, 90, 94, 98, Digital ground (0 V)
101, 103, 107, 110, 112, 116, 120, 124, 128,
132, 136, 141, 143
8QFRQQHFWHG3LQVSLQV
unconnected pins
Data Sheet
1-16
07.2000
3;%)
6\VWHP,QWHJUDWLRQ
6\VWHP,QWHJUDWLRQ
One CAME chip is connected to the ALP if only 8k connections are supported. For 16k
connections, a second CAME is cascaded to the first CAME. The ALP is the master device that
controls the CAME. If two CAME chips are cascaded, the second CAME must be configured as
a slave device to be controlled by the first CAME, which is operated in master mode. The two
configurations are illustrated in ILJXUH and ILJXUH.
.
ALP
ARCCLK
CLK
ARCCS
CS
ARCWE
WE
ARCOE
OE
ARCRES
RES
ARCADR(3:0)
CAME
(Master)
ADR(3:0)
1kΩ
EN16
GND
ARCDAT(16:0)
DAT(16:0)
+ 3.3 V
10 kΩ
DAT(32:17)
1k Ω
CI(2:0) CO(2:0) CA
GND
)LJXUH
Data Sheet
$/3DQG&$0($SSOLFDWLRQIRUN&RQQHFWLRQV
2-17
07.2000
3;%)
6\VWHP,QWHJUDWLRQ
ARCCLK
CLK
ARCCS
CS
ARCWE
WE
ARCOE
OE
CAME
(Master)
RES
ARCRES
ADR(3:0)
ARCADR(3:0)
1 kΩ
EN16
GND
DAT(16:0)
ARCDAT(16:0)
+ 3.3 V
10 kΩ
DAT(32:17)
CI(2:0) CO(2:0) CA
ALP
10 kΩ
1 kΩ
+ 3.3 V
GND
CO(2:0) CI(2:0) CA
CLK
CS
WE
CAME
(Slave)
OE
RES
ADR(3:0)
1 kΩ
EN16
GND
DAT(16:0)
+ 3.3 V
)LJXUH
Data Sheet
10 kΩ
DAT(32:17)
$/3DQG&$0($SSOLFDWLRQIRUN&RQQHFWLRQV
2-18
07.2000
3;%)
)XQFWLRQDO2YHUYLHZ
)XQFWLRQDO2YHUYLHZ
The PXB 4360 F is a Content Addressable Memory Element (CAME) that searches for a
programmable 32-bit pattern the corresponding programmable 14-bit pattern; or vice versa.
Additionally, two search bits are provided to support the search for unused entries and to support
the search for F4-OAM connections in ATM. One CAME supports up to 8192 entries. This can
be extended up to 16384 entries by adding a second, cascaded CAME, without the need for
additional glue logic.
The target application of the CAME is the Address Reduction mechanism for ATM cells
performed by the Infineon ATM layer chip ALP PXB 4350. The ALP extracts the Virtual Path
Identifier of a standardized ATM cell (VPI) and the Virtual Channel Identifier of a standardized
ATM cell (VCI) from the ATM Cell Header and sends them together with the Port Number as a
32-bit pattern to the CAME. After the search procedure of the CAME, the corresponding 14-Bit
pattern is sent back to the ALP. The 14-bit pattern is used as a Local Connection Identifier (LCI)
inserted into the ATM Cell Header. Herewith, the CAME translates any arbitrary address, within
the address range of 232, into another arbitrary address within the address range of 213 (or 214 if
two CAME chips are cascaded). The entire search process is completed during one ATM cell
cycle with a bit rate of 686 MBit/s.
Data Sheet
3-19
07.2000
3;%)
'DWD)ORZDQG)XQFWLRQDO'HVFULSWLRQRIWKH&$0(
'DWD)ORZDQG)XQFWLRQDO'HVFULSWLRQRIWKH&$0(
The CAME can be configured, operated, and tested using six Request Commands. Each
Request Command is a combination of various write and read commands transmitted via the
Data bus of the CAME. The Address bus selects the Request Commands. The data flow for
writing the search pattern into the CAME is such that the Local Connection Identifier (LCI)
defines the address of the memory where the Port Number (PN), VPI, VCI, and the two auxiliary
bits P_IP and VCON are stored. The CAME is operated inversely for cell processing. In the case
of cell processing, the PN, VPI, and VCI address the memory in which the LCI is stored. As well
as the LCI being transmitted to the ALP, a search report is also transmitted. Request Commands
1 and 2 are activated by the ALP during cell processing. Request Commands 3 through 6 are
activated by the microprocessor via the ALP because the CAME has no microprocessor
interface. All six Request Commands are described in the following sections.
Data
Address & WEN
&$0(
Write Data Register (0:33)
Read Data Register (0:33)
Address Register (0:13)
Conf. Register (13:0)
Configuration control
logic
PN(3:0), VPI(11:0), VCI(15:0), VCON, P_IP
Memory
LCI(13:0)
Search Control
logic
Search Address Register (0:31)
)LJXUH
Search Data Register (0:13)
Status Register (3:0)
%ORFN'LDJUDPRIWKH&$0(
3URJUDPPLQJRIWKH6HDUFKDQG6HDUFK5HVXOW3DWWHUQ
Request Command number 4 should be used for the set up and release of a connection. First,
the LCI (14 bits) and the two auxiliary bits VCON and P_IP are written into the Write Data
Register and Address Register via the Data bus. Subsequently, the PN, VPI, and the VCI are
written into the Write Data Register. Within the 16-bit word, any subdivision by the PN and VPI
is allowed. The LCI of the Address Register defines the address of the memory in which the
contents of the Write Data Register are written. After writing the entry into memory, status
information on the current request is stored in the Status Register. The Status Register is read
out at the end of each request.
Data Sheet
4-20
07.2000
3;%)
'DWD)ORZDQG)XQFWLRQDO'HVFULSWLRQRIWKH&$0(
The auxiliary bit VCON defines whether an entry is valid or invalid. This mechanism is used to
prevent overwriting a valid connection, if the corresponding configuration bit CEE1) in the
TESTMODE register is set. A second configuration bit, CLE1) of the TESTMODE register, is
available to prevent a multimatch entry. If CLE and CEE are set, the CAME checks whether the
PN, VPI, and VCI already exist. For the case that an entry exists (single or multimatch), the
CAME prevents the writing and outputs a failure report to the Status Register. For the case that
no entry exists (mismatch), the CAME writes the entry into memory if the LCI entry is invalid;
otherwise, the writing is also prevented. If CEE and CLE are not set, there is no checking
whether both a valid connection is changed and a multimatch condition is generated. The CEE
and CLE have an influence on the execution time of Request Command number 4.
The auxiliary bit P_IP defines whether the connection point is a Path Intermediate Point. If the
P_IP is set, the VCI values are ignored during the search process.
In the TESTMODE register, the TWE bit is provided for testing the memory. If it is set, the write
request is converted into a test write request and all memory banks are written simultaneously.
5HDGLQJWKH6HDUFK3DWWHUQIRUD3UHGHILQHG/&,9DOXH
Request Command number 5 should be used to check the Search Pattern PN, VPI, and VCI and
the Search result pattern VCON and P_IP for a given LCI. First, the LCI (14 bits) is written into
the Address Register, via the Data bus. Then the PN, VPI, VCI, VCON, and P_IP are written
from memory to the Read Data Register. The Read Data Register and the Status Register are
read out via the data bus of the CAME.
In the TESTMODE register, the TRE bit is provided for testing the memory. If it is set, the read
request is converted into a test read request and all memory banks are read simultaneously.
&RQILJXUDWLRQDQG7HVWLQJRIWKH&$0(
Request Command number 3 should be used to search for a Search Pattern with deactivated
search fields, as defined in the TESTMODE register. This Request Command should be
activated by the microprocessor via the ALP and the CAME Interface. It is not used during
normal cell processing. First, the PN, VPI, and VCI are written into the Search Address Register,
via the Data bus. After a predefined search period, the search results (LCI and the two auxiliary
bits VCON and P_IP) are written into the Search Data Register. The status information in the
Status Register and the contents of the Search Data Register are read out via the Data bus of
the CAME.
In the TESTMODE register, the bits VCEN, VPEN, and VSET are provided to define whether the
VCI or the PN and VPI are ignored. Furthermore, it is possible to search for invalid and free
entries, identified by VCON as equal to zero. Additionally, a TSE bit is implemented to convert
the search request into a test search request which compares all memory banks in parallel.
Request Command number 6 is implemented to configure the CAME for operation and test. This
request is a substitute for the microprocessor interface. The configuration and test mode
commands are written into the TESTMODE register via the Data bus of the CAME. Herewith it
is possible to:
• Check the cascade interface between the Master and Slave CAME devices
• Check the parity of the Data bus and Address bus of the CAME
• Read the version number of the CAME
1)
Note that CEE and CLE are not supported by the ALP
Data Sheet
4-21
07.2000
3;%)
'DWD)ORZDQG)XQFWLRQDO'HVFULSWLRQRIWKH&$0(
• Configure the response on Write Request Command number 4
• Configure the response on Search Request Command number 3
• Configure the test functions of the CAME.
6HDUFK2SHUDWLRQIRU&HOO3URFHVVLQJ
Two Search Request Commands are supported by the CAME. Search Request Command
number 1 is used for search processing of F4-OAM cells at the VP termination point. Normally,
the F4-OAM cells are identified by VCI value 3 or 4 for segment or end-to-end flow. The ALP
identifies the F4-OAM cells and uses Search Request Command number 1. Herewith, the PN
and VPI are written into the Search Address Register via the Data bus of the CAME. After a
predefined search period, the search results (LCI and the two auxiliary bits VCON and P_IP) are
written into the Search Data Register. Subsequently, the search data and status information are
read from the ALP. In the case of a valid search result, the LCI value is written into the GFC, VPI
and UDF1 fields of the ATM cell. Herewith, the CAME and ALP borrow a VCI from the user cell
which identifies the F4-OAM cells as VCI value 3 or 4 in order to transmit the F4-OAM cell to the
AOP. This mechanism reduces the number of LCI needed for to transport F4-OAM cells
between the ALP and the AOP. The ALP ignores the multimatch alarm from the CAME for the
F4-OAM cells as it is obvious that a terminated VP delivers a match for all VCIs if only the PN
and VPI value are used as a search pattern. The LCI value used is the lowest LCI.
Search request number 2 is used for search processing of cells belonging to a VC or VP
connection. This search request is identical to Search Request Command 1 except that the VCI
value is also written into the Search Address Register. For VP connections, the auxiliary bit P_IP
must be set which suppresses the VCI search pattern. Herewith, only the PN and VPI values are
considered.
The data structures of the six Request Commands and the corresponding write and read
commands for the 16-bit and 32 bit modes are described in the following sections.
Data Sheet
4-22
07.2000
3;%)
'DWD)ORZDQG)XQFWLRQDO'HVFULSWLRQRIWKH&$0(
'DWD6WUXFWXUHRI5HTXHVW&RPPDQGVIRU%LW0RGH
CAME Data bit (16) is used as parity line and completes the ARCDAT(1:15) and ACRADR(0:3)
to odd parity. Note: Shaded fields represent unused bits.
5HTXHVW1XPEHU
6HDUFK3URFHVVLQJIRU2$0))ORZ
bit: 15 14 13 12 11 10
Write to address CH
9
8
7
PN(3:0)
6
5
4
3
2
1
0
VPI(11:0)
Wait for command
execution
Read from address 6H
V
I
LCI(13:0)
Read from address EH
S3 S2 S1 S0
5HTXHVW1XPEHU
6HDUFKSURFHVVLQJIRU$70&HOOVEHORQJLQJWR93&DQG9&&
bit: 15 14 13 12 11 10
Write to address DH
9
8
7
PN(3:0)
6
5
4
3
2
1
0
VPI(11:0)
Write to address 5H
VCI(15:0)
Wait for command
execution
Read from address 6H
V
I
LCI(13:0)
Read from address EH
S3 S2 S1 S0
5HTXHVW1XPEHU
6HDUFK3URFHVVLQJDFWLYDWHGE\WKH0LFURSURFHVVRU
bit: 15 14 13 12 11 10
Write to address EH
PN(3:0)
9
8
7
6
5
4
3
2
1
0
VPI(11:0)
Write to address 6H
VCI(15:0)
Wait for command
execution
Read from address 6H
V
I
LCI(13:0)
Read from address EH
1)
S3 S2 S1 S0
Structure applies to 4-bit PN and 12-bit VPI. If 6-bit PN and 10-bit VPI are selected, the structure of the first dword
is bit 15..10 = PN(5:0), bit 9..0 = VPI(9:0) for all requests.
Data Sheet
4-23
07.2000
3;%)
'DWD)ORZDQG)XQFWLRQDO'HVFULSWLRQRIWKH&$0(
5HTXHVW1XPEHU
:ULWH&RPPDQGIRU6HWXSDQG5HOHDVHRI&RQQHFWLRQVE\WKH0LFURSURFHVVRU
bit: 15 14 13 12 11 10
Write to address 2H
V
Write to address BH
9
8
I
7
6
5
4
3
2
1
0
LCI(13:0)
PN(3:0)
VPI(11:0)
VCI(15:0)
Write to address 3H
Wait for command
execution
Read from address 6H
Read from address EH
S3 S2 S1 S0
5HTXHVW1XPEHU
5HDG&RPPDQGIRU9HULILFDWLRQRIWKH&RQQHFWLRQ(QWU\E\WKH0LFURSURFHVVRU
bit: 15 14 13 12 11 10
9
8
Write to address 0H
7
6
5
4
3
2
1
0
LCI(13:0)
Wait for command
execution
Read from address 1H
PN(3:0)
VPI(11:0)
Read from address 9H
Read from address 6 H
VCI(15:0)
V
I
Read from address EH
S3 S2 S1 S0
5HTXHVW1XPEHU
&$0(7HVWDQG&RQILJXUDWLRQ&RPPDQGE\WKH0LFURSURFHVVRU
bit: 15 14 13 12 11 10
Write to address 7H
9
8
7
6
5
4
3
2
1
0
Testmode(13:0)
Wait for command
execution
Read from address 7H
Testmode(13:0)
Read from address FH
Data Sheet
S3 S2 S1 S0
4-24
07.2000
3;%)
'DWD)ORZDQG)XQFWLRQDO'HVFULSWLRQRIWKH&$0(
'DWD6WUXFWXUHRIWKH5HTXHVW&RPPDQGVIRU%LW0RGH
Note: Shaded fields represent unused bits.
5HTXHVW1XPEHU1)
6HDUFK3URFHVVLQJIRU2$0))ORZ
bit: Write to address 4H of CAME
PN(3:0)
VPI(11:0)
Wait for command execution
Read from address 6H of CAME
S3S2S1S0 V I
LCI(13:0)
5HTXHVW1XPEHU
6HDUFKSURFHVVLQJIRU$70&HOOVEHORQJLQJWR93&DQG9&&
bit: Write to address 5H of CAME
PN(3:0)
VPI(11:0)
VCI(15:0)
Wait for command execution
Read from address 6H of CAME
S3S2S1S0 V I
LCI(13:0)
5HTXHVW1XPEHU
6HDUFK3URFHVVLQJDFWLYDWHGE\WKH0LFURSURFHVVRU
bit: Write to address 6H of CAME
PN(3:0)
VPI(11:0)
VCI(15:0)
Wait for command execution
Read from address 6H of CAME
S3S2S1S0 V I
1)
LCI(13:0)
Structure applies to 4-bit PN and 12-bit VPI. If 6-bit PN and 10-bit VPI are selected, the structure of the first dword
is bit 31..26 = PN(5:0), bit 25..16 = VPI(9:0) for all requests.
Data Sheet
4-25
07.2000
3;%)
'DWD)ORZDQG)XQFWLRQDO'HVFULSWLRQRIWKH&$0(
5HTXHVW1XPEHU
:ULWH&RPPDQGIRU6HWXSDQG5HOHDVHRI&RQQHFWLRQVE\WKH0LFURSURFHVVRU
bit: Write to address 2H of CAME
V I
LCI(13:0)
Write to address 3H of CAME
PN(3:0)
VPI(11:0)
VCI(15:0)
Wait for command execution
Read from address 6H of CAME
S3S2S1S0
5HTXHVW1XPEHU
5HDG&RPPDQGIRU9HULILFDWLRQRIWKH&RQQHFWLRQ(QWU\E\WKH0LFURSURFHVVRU
bit: Write to address 0H of CAME
LCI(13:0)
Wait for command execution
Read from address 1H of CAME
PN(3:0)
VPI(11:0)
VCI(15:0)
Read from address 6H of CAME
S3S2S1S0 V I
5HTXHVW1XPEHU
&$0(7HVWDQG&RQILJXUDWLRQ&RPPDQGE\WKH0LFURSURFHVVRU
bit: Write to address 7H of CAME
TESTMODE(13:0)
Wait for command execution
Read from address 7H of CAME
S3S2S1S0
1RWH
TESTMODE(13:0)
7KH,ELWUHSUHVHQWVWKH3B,3IODJWKH9ELWUHSUHVHQWVWKH9&21IODJ
Data Sheet
4-26
07.2000
3;%)
5HJLVWHUV
5HJLVWHUV
A request command is a sequence of write and read commands at different addresses. The
address selects the register and the consequent action performed by the CAME. Therefore,
different request commands can write to or read from the same register.
:ULWH'DWD5HJLVWHUV
Each of these registers contains a complete entry consisting of PN/VPI/VCI, the P_IP flag and
the VCON flag. The registers are loaded from the bus interface at the beginning of write request
#4. During request #4, their contents are transferred to the line in CAME memory which is
selected with the Address Register (DLCI).
Write Address 2H, 3H, BH
Value after reset undefined
VCON
P_IP
PN(3:0)
VPI(11:8)
VPI(7:0)
VCI(15:8)
VCI(7:0)
16-Bit Mode
request 4:
2H for VCON, P_IP
3H for VCI(15:0)
BH for PN(3:0), VPI(11:0)
32-Bit Mode
request 4:
2H for VCON, P_IP
3H for PN(3:0), VPI(11:0), VCI(15:0)
1RWH
6WUXFWXUHDSSOLHVWRELW31DQGELW93,,IELW31DQGELW93,DUHVHOHFWHGWKHVWUXFWXUHLVELW
31DQGELW 93,IRUDOOUHJLVWHUVZLWK31DQG93,
Data Sheet
5-27
07.2000
3;%)
5HJLVWHUV
9&21
3B,3
31
Valid Connection flag:
0
Connection not valid.
1
Connection valid.
Path Intermediate point flag:
0
Address reduction is performed over PN, VPI and VCI.
1
Path intermediate point; address reduction is performed only over PN and
VPI.
Port Number
93, VPI value of the ATM Header. PN and VPI are in a 16-bit field. Within the 16 bits,
any subdivision into the PN and VPI is allowed.
9&, VCI value of the ATM Header.
Data Sheet
5-28
07.2000
3;%)
5HJLVWHUV
6HDUFK$GGUHVV5HJLVWHU
These registers contain the PN, VPI, VCI combination which will be compared to all lines in
CAME during search requests #1,#2 and #3. The registers are loaded from the bus interface at
the beginning of the respective search request.
Write Address 4H, 5H, 6H, CH, DH, EH
Value after reset undefined
PN(3:0)
VPI(11:8)
VPI(7:0)
VCI(15:8)
VCI(7:0)
16-Bit Mode
32-Bit Mode
31
request 1:
CH for PN (3:0), VPI (11:0)
request 2:
5H for VCI (15:0)
DH for PN (3:0), VPI (11:0)
request 3:
6H for VCI (15:0)
EH for PN (3:0), VPI (11:0)
request 1:
4H for PN (3:0), VPI (11:0)
request 2:
5H for PN (3:0), VPI (11:0), VCI (15:0)
request 3:
6H for PN (3:0), VPI (11:0), VCI (15:0)
Port Number
93, Virtual Path Identifier value of the ATM Header. PN and VPI are in a 16-bit field.
Any subdivision within the 16-bits for the PN and VPI is allowed.
9&, Virtual Channel Identifier value of the ATM Header.
Data Sheet
5-29
07.2000
3;%)
5HJLVWHUV
$GGUHVV5HJLVWHU'/&,
This register contains the address of the line to which data is written in a write request #4, or
from which data is read in a read request #5. The DLCI register is loaded from the bus interface
at the beginning of the respective read or write request.
Write Address 0H, 2H
Value after reset undefined
LCI(13:8)
LCI(7:0)
16-Bit Mode
32-Bit Mode
request 4:
2H for LCI (13:0)
request 5:
0H for LCI (13:0)
request 4
2H for LCI (13:0)
request 5:
0H for LCI (13:0)
/&, Local Connection Identifier
Data Sheet
5-30
07.2000
3;%)
5HJLVWHUV
6HDUFK5HVXOW'DWD5HJLVWHU6/&,
The result of searching in the memory array is the LCI value of the first line that matches the data
in the SPN/SVPI/SVCI registers. This result is stored in the SLCI register. At the end of all search
requests (#1..3), the ALP can read the resulting LCI from the SLCI register. For the other
requests (# 4 & #5), the LCI value is set to zero.
Read Address 6H
Value after reset undefined
LCI(13:8)
LCI(7:0)
16-Bit Mode
32-Bit Mode
request 1, 2, 3:
request 1, 2, 3:
6H for LCI (13:0)
6 H for LCI 13:0)
/&, Local Connection Identifier
Data Sheet
5-31
07.2000
3;%)
5HJLVWHUV
5HDG'DWD5HJLVWHU
These registers contain a complete entry consisting of PN/VPI/VCI, the P_IP flag and the VCON
flag. The read data contained in the CAME memory line, selected with the DLCI register
contents, is transferred to these registers. At the end of a read request #5, the ALP can read the
resulting data from the RPN,RVPI,RVCI,RI,RV registers.
Read Address 1H, 6H, 9H
Value after reset undefined
VCON
P_IP
PN(3:0)
VPI(11:8)
VPI(7:0)
VCI(15:8)
VCI(7:0)
16-Bit Mode
request 5:
32-Bit Mode
request 5:
9&21
3B,3
Data Sheet
1H for PN(3:0), VPI(11:0)
6H for VCON, P_IP
9H for VCI(15:0)
1H for PN(3:0), VPI(11:0), VCI(15:0)
6H for VCON, P_IP
Valid Connection flag:
0
Connection not valid.
1
Connection valid.
Path Intermediate Point flag:
0
Address reduction is performed over PN / VPI / VCI.
1
Path Intermediate Point; address reduction is performed only over
PN / VPI.
5-32
07.2000
3;%)
5HJLVWHUV
31
Port Number
93, Virtual Path Identifier value of the ATM Header. PN and VPI are in a 16-bit field.
Any subdivision within the 16 bits for the PN and VPI is allowed.
9&, Virtual Channel Identifier
Data Sheet
5-33
07.2000
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Status information generated by the control logic in the CAME indicates the success of
commands or detected failures. At the end of each command cycle, status information about the
current operation is transferred from the CAME to the ALP. The 4-bit status field consists of two
bits (S3,S2) with command independent information and two bits (S1,S0) with command related
details.
The data bus parity error is returned if a parity error at the data bus interface was detected by
the CAME since the last completed request. In all requests, the master CAME checks whether
the slave also accepted a request. This information is transferred at the Cascade Interface. If the
slave signals at CO(1..0) that it has recognized no request the “cascade error” status is
generated in the master (Note: if LCI 2000..3FFFH is accessed in a single CAME configuration,
“cascade error” is also indicated because this case cannot be distinguished from a two-chip
configuration with a defect on the second chip). A “command cycle error” is internally set after
reading the status at the end of a request, or if a write access was performed while a command
cycle was running.
If a parity error is detected in one of the write accesses at the start of a command, the command
is discarded, internal status information is set to “parity error”, and the control logic waits for one
of the two possible final bus read accesses (address #6 or #7). After the final bus read access,
the CAME is ready for the next command cycle. After a command cycle is finished, the internal
status contains a “command cycle error”. This status is changed with the start of a new
command cycle. If the start of a command cycle is not recognized by the CAME, the error status
above is still present at the next status read access.
For S3/S2 = 1/0, coding of S1/S0 depends on the command just finished in the following way:
Status information can be read any time at address 6 and address 7. ILJXUH at page 35
shows the conditions under which the status information changes. The five states, named as
OK, Busy, Alarm, Error(cmd), Error(parity) and shown in this figure, are coded by the status bits
S3..0. The start of a request can take place in the “OK”, “Alarm”, or “Error (cascade or command
cycle)” state. If a parity error is detected, the “Parity Error” state is entered. This state is left only
on reading of the status information. All write accesses are ignored while the status is in “Parity
Error” state. If no parity error has occurred, the command is processed. This is indicated by the
“Busy” state. In this state, writing generates a “command cycle error” and no internal register is
changed by the write access. Reading is allowed in “Busy” state. Depending on the result of the
request, either the “OK”, “Alarm”, or “Error (cascade or command cycle)” status is entered. After
reading the status once, the “Error (command cycle)” is entered. This supports the recognition
of a missing command cycle start.
Data Sheet
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5HJLVWHUV
OK
6)
3)
Error
(parity)
2)
6)
1)
4) or
any write
Error
(cmd cyc.
or casc.)
Busy
5)
6)
Alarm
Transition conditions:
)LJXUH
1)
2)
3)
4)
5)
6)
Start of a request (write access)
Parity error occurred at start of a request
Internal processing of request finished
Error occurred during internal processing
Alarm occurred during internal processing
Status read access
6WDWH'LDJUDPRI6WDWXV*HQHUDWLRQ
6WDWXV5HJLVWHU
Read Address 6H, 7H, EH, FH
Value after reset 0000H
S3
16-Bit Mode
32-Bit Mode
Data Sheet
request 1, 2, 3, 4, 5:
EH for S3, S2, S1, S0
request 6:
FH for S3, S2, S1, S0
request 1, 2, 3, 4, 5:
6H for S3, S2, S1, S0
request 6:
7H for S3, S2, S1, S0
5-35
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S1
S0
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6
S3 / S2 :S1/S0
00
Ok
Command was executed without problems.
Indication in S1/S0:
S1/S0 = 0/0.
01
Busy
Command execution is still in progress.
Indication in S1/S0:
S1/S0 = 0/0.
10
Alarm
Operation was not successful for CAME memory content
dependent reasons. Indication in S1 / S0:
00
Mismatch (at search requests #1..3).
The search pattern was not found in any line. The LCI returned
is invalid (01FFH).
01
Multimatch (at search requests #1..3).
The search pattern was found in more than one line. The LCI
of the lowest matching line is returned.
10
Test search fault (at search requests #1..3).
After “test search,” the search pattern was not found in all 16
blocks at the same line offset and nowhere else. The LCI
returned is invalid.
00
Refused entry (at write request #4).
Attempt to write an entry to CAME which is already stored in a
line of this chip (or the second CAME). This mode can be
activated with MODE register bit CEE.
01
Refused line (at write request #4).
Attempt to write a valid entry in a line already containing valid
information. This mode can be activated with MODE register
bit CLE.
00
Test read fault (at read request #5).
The contents read from all 16 blocks at the same line offset
were not equal. The read result returned is invalid.
Error
A hardware error was detected.
Indication in S1 / S0:
00
Data bus parity error.
01
Cascade error.
10
Command cycle error.
11
Data Sheet
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5HJLVWHUV
7HVWPRGH5HJLVWHU
The testmode register is used in the test request #6. The testmode register acts as an
intermediate stage for access to the configuration (MODE, TMODE), test (TMUX) and version
(VER0..3) registers which are selected by the selection field. The control field defines the read
and modify-and-read operation as well as access to the master or slave device. The data field
is used as MODE, TMODE, and TMUX registers as well as Version register (VER0..3) selected
by the selection register.
Read/write Address 7H
Value after reset undefined
Selection(2:0)
Control(1:0)
Data(8)
Data(7:0)
16-Bit Mode
request 6: 7H for TESTMODE(13:0)
3-Bit Mode
request 6: 7H for TESTMODE(13:0)
6HOHFWLRQ
Selection field defines which one of the eight registers is selected
Data Sheet
000
MODE register used for Cascade Interface test, configuration of
the request #3 and #4
001
TMODE register used for checking of the internal memory
010
TMUX register for test purposes only.
011
Reserved
100
Read Version number Octet 0; VER0 register used for reading
101
Read Version number Octet 1; VER1 register used for reading
110
Read Version number Octet 2; VER2 register used for reading
111
Read Version number Octet 3; VER3 register used for reading
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&RQWURO
&RQWURO
'DWD
Data Sheet
Control field
0
Modify and Read; not usable for selection (100:111)
1
Read
Control field
0
Master is accessed
1
Slave is accessed
Data field
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'DWD)LHOGRI7HVWPRGH5HJLVWHU6HOHFWLRQLV02'(
For request #1, the VSET portion for comparison is LQWHUQDOO\ set to 1, VPED is set to 0 and
VCED set to 1. In request #2, the settings VSET = 1, VCED = 0 and VPED = 0 are used. For
request #3, all three VSET, VCED and VPED DUHSURJUDPPDEOH in the MODE register. Both
modes of searching as well as searching for invalid lines are possible under microprocessor
control during cell processing.
For SW convenience and acceleration of the connection data update, write request #4 may be
extended by using the CEE and CLE bits in the MODE register. If CEE is set to 1 before writing
a pattern to a line, searching for this pattern in the CAME (and the optional second CAME) is
performed. If this pattern is already present, the command cycle is finished without writing to the
line. This failure is reported in the status register. Next, if enabled, prior to writing with CLE set
to 1, the destination line is checked to determine if it already contains a valid entry (with VCON
= 1). Writing is prevented only if a valid pattern (VCON =1) is intended to be written over a valid
entry and the failure is reported in the status field.
1RWH
&RPPDQG H[HFXWLRQ WLPH YDULHV ZLWK &(( DQG &/( XVDJH 7KH QXPEHU RI FORFN F\FOHV UHTXLUHG IRU
UHTXHVWSURFHVVLQJSURKLELWVWKHLUXVDJHLQ 0ELWVV\VWHPV7KHFRPPDQGH[HFXWLRQWLPHVDUHOLVWHG
LQWDEOH RQ SDJH VCED
VPED
9&('
93('
96(7
Data Sheet
VSET
DPG
CIO2
CIO1
CIO0
CLE
CEE
VCI Evaluation Disable.
This bit has no influence on any requests except request #3:
0
Default
1
VCI is ignored in search requests of type #3.
VPI Evaluation Disable.
This bit has no influence on any requests except request #3:
0
Default
1
PN / VPI is ignored in search requests of type #3.
For VCON comparison internally Set value for search request #3:
0
Free empty lines are localized.
1
Default
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5HJLVWHUV
'3*
Disturbed Parity Generation.
Generate a bus parity error in the read access at the end of this command cycle.
This bit is automatically reset. DPG is not supported by the ALP!
0
&,2
CI(2) / CO(2) data
If this bit is written, it determines the setting of the CO(2) output while it is used for
Cascade Interface check. If it is read, it reflects the level at the CI(2) input.
y
&,2
Default
Check of an Entry before write Enable.
Search is performed for occurrence of write pattern in the CAME (and a cascaded
CAME, if connected). If the pattern is already present, the related line will not be
updated and an alarm is returned in the status field. Activation of this bit prolongs
the write request (restricted usage in 622 Mbit/s systems). CEE is not supported by
the ALP!
0
Data Sheet
Default
y depends on the CI input with the same index
Check of a Line before write Enable.
This means writing of a valid entry (with its VCON bit set to 1) over a valid entry in
memory (also with VCON bit contained in this line set to 1) is not performed;
instead, in the status field, an alarm is returned. Activation of this bit prolongs the
write request (restricted usage in 622 Mbit/s systems). CLE is not supported by the
ALP!
0
&((
Default
y depends on the CI input with the same index
CI(0) / CO(0) data
If this bit is written, it determines the setting of the CO(0) output while it is used for
Cascade Interface check. If it is read, it reflects the level at the CI(0) input.
y
&/(
Default
y depends on the CI input with the same index
CI(1) / CO(1) data
If this bit is written, it determines the setting of the CO(1) output while it is used for
cascade interface check. If it is read, it reflects the level at the CI(1) input.
y
&,2
Default
Default
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5HJLVWHUV
'DWD)LHOGRI7HVWPRGH5HJLVWHU6HOHFWLRQLV702'(
TMODE register use is allowed only if the MODE register is set to the default values mentioned
in VHFWLRQ on page 39. The TMODE register bits cause the following functional changes:
reserved(5)
reserved(4:0)
TWE
TRE
TSE
UHVHUYHG Reserved, do not activate.
000000
7:(
Test Write Enable.
Enables writing to all memory banks in parallel. This bit changes a write
request #4 to a “test write” request.
0
75(
Default
Test Search Enable.
Enables parallel comparing in all banks. This bit changes a search request #3
to a “test search” request.
0
Data Sheet
Default
Test Read Enable.
Enables parallel reading from all banks at the same offset. This bit changes a
read request #5 to a “test read” request.
0
76(
Default
Default
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5HJLVWHUV
'DWD)LHOGRI7HVWPRGH5HJLVWHU6HOHFWLRQLV708;
TMUX(8)
TMUX(7:0)
708; For test only. This register should be set to 0 for normal operation (TMUX
disabled):
000000000
Default
'DWD)LHOGRI7HVWPRGH5HJLVWHU6HOHFWLRQLV9(5
VER0(8)
VER0(7:0)
9(5
0
9(5
Data Sheet
Value
Version number, octet 0.
Version number bits 7..0 contain 2FH.
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5HJLVWHUV
'DWD)LHOGRI7HVWPRGH5HJLVWHU6HOHFWLRQLV9(5
VER1(8)
VER1(7:0)
9(5
0
9(5
Value
Version number, octet 1.
Version number bits 15..8 contain 70H.
'DWD)LHOGRI7HVWPRGH5HJLVWHU6HOHFWLRQLV9(5
VER2(8)
VER2(7:0)
9(5
0
9(5
Data Sheet
Value
Version number, octet 2.
Version number bits 23..16 contain 0BH.
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5HJLVWHUV
'DWD)LHOGRI7HVWPRGH5HJLVWHU6HOHFWLRQLV9(5
VER3(8)
VER3(7:0)
9(5
0
9(5
Data Sheet
Value
Version number, octet 3.
Version number bits 31..24 contain 0BH.
5-44
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,QWHUIDFH'HVFULSWLRQ
,QWHUIDFH'HVFULSWLRQ
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All communication with ALP is done using the data interface. The data interface consists of the
following signals, as shown in WDEOH:
7DEOH
'DWD,QWHUIDFH6LJQDOV
6LJQDO1DPH
([SODQDWLRQ
DAT(0)
Odd parity. Selected to create parity over ADR and DAT bidirectional
DAT(31..1)1)
Data Bus
bidirectional
DAT(32)
Data Bus
bidirectional
ADR(2..0)
Address Bus
input
ADR(3)
Address Bus
input
WE
Write Enable
input
OE
Output Enable
input
CE
Chip Enable
input
CLK
Clock
input
EN16
Selection of bus width
input
1)
7\SH
DAT(15:1) are needed with ALP V1.1. DAT(32:17) are reserved for future use.
CAME will be accessed only if CE is low at the rising edge of CLK. If WE is low at the time, a
write cycle will be executed; if WE is high, a read cycle will be executed. The OE signal controls
the CAME output buffers for read accesses only. The EN16 signal determines data bus width,
which is 16-bit for EN16 at low level, and 32-bit otherwise. This signal is intended for static
adjustment of bus width.
Parity generation in 16-bit Mode extends over DAT(16..0) and ADR(3..0). In 32-bit Mode, it
extends over DAT(32..0) and ADR(3..0). In 32-bit interface mode, ADR(3) is not needed and
must be connected to ground; thus, parity generated over DAT(32..0) and ADR(2..0) is accepted
correctly. In both cases, DAT(0) is used as a parity line and completes the corresponding DAT
and ADR lines to odd parity. In 16-bit Mode, only the lower part of the data bus is used. The
upper bus half (index 17..32) is ignored during write accesses to CAME and is 0 during read
accesses.
Data Sheet
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,QWHUIDFH'HVFULSWLRQ
&DVFDGH,QWHUIDFH
For more demanding applications, two CAME chips can be cascaded to build up one virtual
device with double capacity and the identical physical bus interface to an external controller. The
Cascade Interface is used for this purpose and consists of the CO(2..0) outputs and the CI(2..0)
and CA inputs as shown in ILJXUH.
CAME
(Master)
ALP
Bus
interface
CA
1k Ω
GND
CI(2:0)
CO(2:0)
CAME
ALP
Bus
interface
CA
CI( 0)
CI( 1)
CI( 2)
CO(0)
CAME
(Slave)
1kΩ
GND
Bus
interface
CO(1)
CA
CO(2)
10kΩ
+ 3.3 V
CI(2:0)
CO(2:0)
a) Single CAME application
)LJXUH
a) 2 CAME application
&DVFDGH,QWHUIDFH,QWHUFRQQHFWLRQRI&$0(&KLSV
Both CAME chips receive the same requests from ALP. Depending on the request, the
determination of which chip may answer at the end of the request is either known in advance
(read, write and test requests #4..6) or results from the operation (search requests #1..3). In the
second case, the master must inform the slave of its search result and indicate whether or not it
processes the search request. The same report takes place from the slave to the master. This
is done with the signals CO(1..0). Processing the crosswise transferred status information is
done according to WDEOH . The timing of this transfer is defined in WDEOH . The interpretation of
the CO(1..0) signals at this time is done according to WDEOH .
In order to avoid bus conflicts on reading of cascaded CAME chips, the master has the
opportunity to disable data output of the slave CAME using the CO(2) signal. This signal is
important in case of a parity error, for example.
The CO(2..0) outputs must be connected to the CI(2..0) inputs of the opposite CAME.
Data Sheet
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,QWHUIDFH'HVFULSWLRQ
For single chip applications, the CAME device must be configured as master by CA and the
CI(1..0) inputs must be supplied with low level, pretending an “always mismatch” condition of the
non-existent slave. The CI(2) input is not evaluated by a chip configured as master, but it needs
connection to ground.
7DEOH
&DVFDGH,QWHUIDFH6LJQDOV
6LJQDO
1DPH
&RGH
)XQFWLRQ
7\SH
CA
0
Device is master, its LCI range is 0..8191
input
1
Device is slave, its LCI range is 8192..16383
00
A search request (#1..3 or #4 with MODE.CEE= 1) is running
with the result mismatch on the opposite chip
01
A search request (#1..3 or #4 with MODE.CEE= 1) is running
with the result of single match or multimatch on the opposite chip
10
No request is processed by the opposite chip
11
Request #4..6 is processed by the opposite chip
0
CI(2) is ignored by a master.
A slave interprets CI(2) as follows:
Data output at DAT is prohibited in read cycles
1
Data output at DAT is allowed in read cycles
CI(1..0)
CI(2)
CO(1..0) 00
A search request (#1..3 or #4 with MODE.CEE= 1) is running
with the result mismatch
01
A search request (#1..3 or #4 with MODE.CEE= 1) is running
with the result of single match or multimatch
10
No request is processed
11
Request #4..6 is processed
0
CO(2) of a slave is undefined.A master outputs CO(2) as
follows:
Prohibit data output of a slave in read cycles
1
Allow data output of a slave in read cycles
CO(2)
input
input
output
output
&DVFDGH/RJLF
If two CAME chips are cascaded, the selection of which device will react and may respond is
made based on the command started. No additional preparation at the bus interface is
necessary. In read or write command cycles, the LCI - at least part of the command word Data Sheet
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,QWHUIDFH'HVFULSWLRQ
determines which chip performs the operations and may send back the results to ALP.
Therefore, the chip not selected chip must also wait for the end of the current request before a
new request may be started. In search cycles, both CAME chips start searching in parallel. Only
one chip will respond to ALP, determined by the search result. Only for test request #6 must an
extra bit, TESTMODE(9), be spent in the instruction word for selection between master and
slave.
7DEOH
6HOHFWLRQ&ULWHULDIRU'LIIHUHQW,QVWUXFWLRQV
&RPPDQG7\SH
6HOHFWLRQRI0DVWHU
6HOHFWLRQRI6ODYH
Search - Requests #1..3
Refer to table 4
Write - Request #4
0 ≤ LCI ≤ 8191
8192 ≤ LCI ≤ 16383
Read - Request #5
0 ≤ LCI ≤ 8191
8192 ≤ LCI ≤ 16383
Test - Request #6
TESTMODE(9) = 0
TESTMODE(9) = 1
With two cascaded CAME chips, each CAME first searches alone. When the match state of
master and slave is known, the master reports his local result to the slave. It is only necessary
to report “mismatch” or “not mismatch” conditions. The same is done by the slave. Both chips
determine their reaction and the overall status according to WDEOH , which includes all
combinations of local master and slave search results. The fields of this table contain the overall
status of the result for which device returns the result to ALP and which stays inactive.
For example, if both chips detect a single match, the slave knows about its own state and the
detection of at least an additional match in the master (Master.CO(2..0) = Slave.CI(2..0)) and
knows that a global multimatch results. As the slave in this case, it must not respond to ALP. The
master also detects a global multimatch the same way (Slave.CO(2..0) = Master.CI(2..0)) and
responds to ALP.
Data Sheet
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7DEOH
5HVSRQGLQJ'HYLFHDQG2YHUDOO5HVXOWDIWHU6HDUFK2SHUDWLRQ
0DVWHU'HYLFH
Mismatch
Master.CO(1..0) = 00
Single Match
Master.CO(1..0) = 01
Multimatch
Master.CO(1..0) = 01
Mismatch
Slave.CO(1..0) = 00
Master: Mismatch
Slave: inactive
Master: Single Match
Slave: inactive
Master: Multimatch
Slave: inactive
Single Match
Slave.CO(1..0) = 01
Master: inactive
Slave: Single Match
Master: Multimatch
Slave: inactive
Master: Multimatch
Slave: inactive
Multimatch
Slave.CO(1..0) = 01
Master: inactive
Slave: Multimatch
Master: Multimatch
Slave: inactive
Master: Multimatch
Slave: inactive
6ODYH'HYLFH
In summary, the condition for the CAME to become active at the end of an error-free search
cycle is:
If the Slave receives 00 for “Mismatch” on CI(1..0) and recognizes an internal “Single Match” or
“Multimatch” condition it may respond to the master; it must not respond in all other cases.
A master will not respond at the end of the current command cycle only if it detects an internal
“Mismatch” condition and the slave reports at CI(1..0) with 01 no “Mismatch”; in all other cases
the master responds.
In the case of a communication fault at the beginning of a request, the determination of which
chip may respond is not performed. The reason may be a parity error. To avoid bus conflicts, the
slave always must be controlled by the master chip for data output in case of reading. This is
done by the master with the CO(2) signal.
If the slave outputs the codes 10 (no request processed) or 11 (request #4..6 processed) at
CO(1..0) while the master processes a search request, the overall status “cascade error” is
reported by the master.
If the master processes one of the requests without searching, then only if the slave outputs the
code 10 (no request processed) is the overall status “cascade error”. In the other cases, no error
is recognized. The code 00 from a slave is accepted intentionally, even if it pretends a search
operation, because, for non-cascaded applications, the CI(2..0) inputs are connected to ground.
Finally, if the master holds the internal status “data bus parity error” or “command cycle error,”
no request is processed by the master. In this case, the slave status is ignored.
This behavior is summarized in WDEOH . The master will always report the cascade, parity, and
command cycle errors.
Data Sheet
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,QWHUIDFH'HVFULSWLRQ
7DEOH
2YHUDOO6WDWXVLQ&DVHRI(UURUV
0DVWHU
CO(1..0) = 00 or 01
(requests with
searching)
CO(1..0) = 11
(requests without
searching)
CO(1..0) = 10
(No request
processed)
6ODYH
CO(1..0) = 00 or 01
See table 4
Status of read, write
and test requests
Parity or command
cycle error
CO(1..0) = 11
Cascade error
Reported by the preselected device
Parity or command
cycle error
CO(1..0) = 10
Cascade error
Cascade error
Parity or command
cycle error
Data Sheet
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&ORFNDQG5HVHW
The system clock is passed to CAME at the CLK input. For typical applications, it will be equal
to ALP SYS_CLK/2 = 25.92 MHz. This is the only clock supply for the CAME (if the BSCAN
interface clock is ignored). It determines operation of the bus interface and the timing of all
clocked internal functions. The ALP delivers the CLK signal for the CAME without any glue logic,
as depicted in ILJXUH.
&$0(
&$0(&ORFN 6<6&ORFN
8WRSLD3+<&ORFN
≤ 6<6&ORFN
8WRSLD$70&ORFN
≤ 6<6&ORFN
1:2
3+<
$/3
$23
$%0
6<6&ORFN
0+]
)LJXUH
&ORFN,QWHUIDFHRIWKH&$0(
The RESET signal is an active low input. As long as it is connected to a low level, the data bus
DAT(32..0) will be forced to a high-impedance state, CO(2..0) are set to 000. TDO and
TMD(7..0) are not influenced.
When the transition low → high is detected at RESET, the internal control logic is reset, the
internal status is “ok” and all test function registers are set to their default values as outlined in
section 5.7 on page 37. Thus, test multiplexer selection and the CO(2..0) outputs are
influenced. Internal registers around the memory array are also cleared. The contents of the
memory array are not changed intentionally, but memory protection during reset is not
implemented.
As long as RESET stays at a high level, normal operation will occur.
Data Sheet
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Factory test is supported by the Boundary Scan Interface. It consists of four inputs for control of
the TAP-controller and one output described in table 6. The TAP-controller is a part of the
BSCAN logic.
7DEOH
%RXQGDU\6FDQ,QWHUIDFH
6LJQDO
([SODQDWLRQ
TCK
Clock input
TDI
Serial Data Input, accepted with rising TCK edge
TDO
Serial Data Output, changes with falling TCK edge
TMS
Test Mode Select signal, accepted with rising TCK edge, defines TAP controller
operation mode.
TRST
Test interface Reset signal, low level initializes the TAP-controller
asynchronously
According to IEEE-Standard 1149.1, boundary scan also provides a 32-bit identification register.
In CAME, it contains the boundary scan ID number 0B0B702FH.
7DEOH
&$0(%RXQGDU\6FDQ7DEOH
%RXQGDU\
6FDQ1XPEHU
3,11U
6LJQDO1DPH
7\SH
1
12
ADR(0)
I
2
14
ADR(1)
I
3
16
ADR(2)
I
4
18
ADR(3)
I
5
20
RES
I
6
22
WE
I
7
24
OE
I
8
26
CS
I
9
32
DAT(0)
O
10
32
DAT(0)
I
11
34
DAT(1)
O
12
34
DAT(1)
I
Data Sheet
6-52
07.2000
3;%)
,QWHUIDFH'HVFULSWLRQ
7DEOH
&$0(%RXQGDU\6FDQ7DEOH(cont’d)
%RXQGDU\
6FDQ1XPEHU
3,11U
6LJQDO1DPH
7\SH
13
36
DAT(2)
O
14
36
DAT(2)
I
15
38
DAT(3)
O
16
38
DAT(3)
I
17
40
DAT(4)
O
18
40
DAT(4)
I
19
42
DAT(5)
O
20
42
DAT(5)
I
21
44
DAT(6)
O
22
44
DAT(6)
I
23
46
DAT(7)
O
24
46
DAT(7)
I
25
48
DAT(8)
O
26
48
DAT(8)
I
27
50
DAT(9)
O
28
50
DAT(9)
I
29
52
DAT(10)
O
30
52
DAT(10)
I
31
54
CLK
I
32
-
Control pad for DAT(32:0)
-
33
56
DAT(11)
O
34
56
DAT(11)
I
35
58
DAT(12)
O
36
58
DAT(12)
I
37
60
DAT(13)
O
38
60
DAT(13)
I
Data Sheet
6-53
07.2000
3;%)
,QWHUIDFH'HVFULSWLRQ
7DEOH
&$0(%RXQGDU\6FDQ7DEOH(cont’d)
%RXQGDU\
6FDQ1XPEHU
3,11U
6LJQDO1DPH
7\SH
39
62
DAT(14)
O
40
62
DAT(14)
I
41
64
DAT(15)
O
42
64
DAT(15)
I
43
66
DAT(16)
O
44
66
DAT(16)
I
45
68
DAT(17)
O
46
68
DAT(17)
I
47
70
DAT(18)
O
48
70
DAT(18)
I
49
72
DAT(19)
O
50
72
DAT(19)
I
51
74
DAT(20)
O
52
74
DAT(20)
I
53
76
DAT(21)
O
54
76
DAT(21)
I
55
77
DAT(22)
O
56
77
DAT(22)
I
57
81
DAT(23)
O
58
81
DAT(23)
I
59
83
DAT(24)
O
60
83
DAT(24)
I
61
85
DAT(25)
O
62
85
DAT(25)
I
63
87
DAT(26)
O
64
87
DAT(26)
I
Data Sheet
6-54
07.2000
3;%)
,QWHUIDFH'HVFULSWLRQ
7DEOH
&$0(%RXQGDU\6FDQ7DEOH(cont’d)
%RXQGDU\
6FDQ1XPEHU
3,11U
6LJQDO1DPH
7\SH
65
89
DAT(27)
O
66
89
DAT(27)
I
67
91
DAT(28)
O
68
91
DAT(28)
I
69
93
DAT(29)
O
70
93
DAT(29)
I
71
95
DAT(30)
O
72
95
DAT(30)
I
73
97
DAT(31)
O
74
97
DAT(31)
I
75
99
DAT(32)
O
76
99
DAT(32)
I
77
104
CA
I
78
106
EN16
I
79
109
TMD(0)
O
80
113
TMD(1)
O
81
115
TMD(2)
O
82
117
TMD(3)
O
83
119
TMD(4)
O
84
121
TMD(5)
O
85
123
TMD(6)
O
86
125
TMD(7)
O
87
127
CO(0)
O
88
129
CO(1)
O
89
131
CO(2)
O
90
133
CI(0)
I
Data Sheet
6-55
07.2000
3;%)
,QWHUIDFH'HVFULSWLRQ
7DEOH
&$0(%RXQGDU\6FDQ7DEOH(cont’d)
%RXQGDU\
6FDQ1XPEHU
3,11U
6LJQDO1DPH
7\SH
91
135
CI(1)
I
92
137
CI(2)
I
0LFURSURFHVVRUDQG&RQWURO,QWHUIDFH
No Microprocessor Interface is implemented in the CAME. In the CAME, data and control
interfaces are identical. For the interface description, refer to "Data Bus and Address Bus
Interface" on page 6-45.
The CAME mode register access takes place with request #6. For details about command
transfer, refer to VHFWLRQpage 37.
5HIHUHQFHIRU,QWHUQDO&XUUHQW6RXUFHV
Adjustment of internal current sources is done using the RBIAS and VBIAS pins. VBIAS must
be connected to a precision voltage reference with 1.2 V ± 10%. Additionally, between the
RBIAS pin and ground, a resistor with 12.1 kΩ ± 1% is necessary.
VBIAS= 1 is interpreted as “powerdown” and disables the CAME functionality.
.
V33
R=10k
REF
VBIAS
1.2V
GND
LM4041EIM3-1.2
C=100nF
GND
)LJXUH
Data Sheet
([DPSOHIRU9%,$65HIHUHQFH9ROWDJH&LUFXLW
6-56
07.2000
3;%)
(OHFWULFDO&KDUDFWHULVWLFV
(OHFWULFDO&KDUDFWHULVWLFV
$EVROXWH0D[LPXP5DWLQJV
7DEOH
$EVROXWH0D[LPXP5DWLQJV
3DUDPHWHU
6\PERO
Supply Voltage
9CC
-0.5 to 4.6
V
Input Voltage
9IN
-0.5 to 9CC+0.5
V
Output Voltage
9OUT
Power Dissipation
3V
<0.3
W
Storage Temperature
7S
-65 to 150
°C
1RWH
/LPLW9DOXHV
8QLW
V
6WUHVVHV DERYH WKRVH OLVWHG KHUH PD\ FDXVH SHUPDQHQW GDPDJH WR WKH GHYLFH ([SRVXUH WR DEVROXWH
PD[LPXPUDWLQJFRQGLWLRQVIRUH[WHQGHGSHULRGVPD\DIIHFWGHYLFHUHOLDELOLW\
2SHUDWLQJ&RQGLWLRQV
7DEOH
2SHUDWLQJ&RQGLWLRQV
3DUDPHWHU
Supply Voltage
6\PERO
9CC
3.135 to 3.465
V
Ground
*1'
0
V
Input Voltage
9IN
0 to 9CC
V
Output Voltage
9OUT
0 to 9CC
V
Input low Voltage
9IN
0 to 0.8
V
Input high Voltage
9IN
2.0 to 9CC
V
Ambient Temperature
7A
0 to 70
°C
Junction Temperature
7J
max. 100
°C
Data Sheet
7-57
/LPLW9DOXHV
8QLW
07.2000
3;%)
(OHFWULFDO&KDUDFWHULVWLFV
'&&KDUDFWHULVWLFVIRUDOO,QWHUIDFHV
7DEOH
'&&KDUDFWHULVWLFV
3DUDPHWHU
6\PERO
/LPLW9DOXHV
PLQ
W\S
PD[
8QLW
7HVW&RQGLWLRQ
Input Low Voltage
9IL
0
0.8
V
Input High Voltage
9IH
2.0
9CC
V
Output Low Voltage
9OL
0.4
V
Output High Voltage
9OH
2.4
V
9OH=9DD or9SS
Output Current at high
Voltage
,OH
-8
mA
9IN=9CC or 0 V
8
mA
9IN=9CC or 0 V
Output Current at low Volt- ,OL
age
Input Leakage Current at
low Voltage
(all inputs except TCK,
TMS, TDI, TRSTN)
,IL
-1
1
mA
9IN=9CC or 0 V
Input Leakage Current at
high Voltage
(all inputs except TCK,
TMS, TDI, TRSTN)
,IH
-1
1
mA
9IN=9CC or 0 V
Input Leakage Current at
low Voltage
(inputs TCK, TMS, TDI,
TRSTN)
,IL
-1
-14
mA
9IN=0 V
Input Leakage Current at
high Voltage
(inputs TCK, TMS, TDI,
TRSTN)
,IH
-1
1
mA
9IN=9CC
Data Sheet
7-58
07.2000
3;%)
(OHFWULFDO&KDUDFWHULVWLFV
&DSDFLWDQFHV
7DEOH
&DSDFLWDQFHV
3DUDPHWHU
6\PERO
PLQ
Input Capacitance
Input/Output Capacitance
/LPLW9DOXHV
PD[
8QLW
&IN
5
pF
&IN/OUT
7
pF
$&&KDUDFWHULVWLFV
7A = 0 to 70 °C, 9CC = 3.3 V ± 5%, 9SS = 0 V
All inputs are driven to 9IH = 2.4 V for a logical 1
and to 9IL = 0.4 V for a logical 0
All outputs are measured at 9H = 2.0 V for a logical 1
and at
9L = 0.8 V for a logical 0
The AC testing input/output waveforms are shown in ILJXUH .
)LJXUH
Data Sheet
,QSXW2XWSXW:DYHIRUPIRU$&0HDVXUHPHQWV
7-59
07.2000
3;%)
(OHFWULFDO&KDUDFWHULVWLFV
%RXQGDU\6FDQ7HVW,QWHUIDFH
)LJXUH
%RXQGDU\6FDQ7HVW,QWHUIDFH7LPLQJ'LDJUDP
7DEOH
%RXQGDU\6FDQ7HVW,QWHUIDFH$&7LPLQJ&KDUDFWHULVWLFV
1R
3DUDPHWHU
/LPLW9DOXHV
0LQ
7\S
0D[
8QLW
1
7TCK: Period TCK
160
1A
)TCK: Frequency TCK
0
2
Set up time TMS, TDI before TCK rising
10
ns
3
Hold time TMS, TDI after TCK rising
10
ns
4
Delay TCK falling to TDO valid
0
30
ns
5
Delay TCK falling to TDO high impedance 0
30
ns
6
Pulse width TRST low
Data Sheet
100
7-60
ns
6.25
MHz
ns
07.2000
3;%)
(OHFWULFDO&KDUDFWHULVWLFV
$&&KDUDFWHULVWLFVRI&$0('DWD,QWHUIDFHWRWKH$/3
1
2
n-1
n
CLK
CS
OE
WE
ADR(3:0)
DAT(16:0)
Start (first write)
)LJXUH
End (last read)
([DPSOHRI([HFXWLRQ7LPLQJIRU:ULWH&RPPDQG5HTXHVW
7DEOH
'XUDWLRQRI&RPPDQG([HFXWLRQ
3DUDPHWHU
0D[H[HFXWLRQWLPH 8QLW
IRUELW IRUELW
LQWHUIDFH LQWHUIDFH
Request number 1:
Cell processing search for PN/VPI reduction
12
13
clock cycles
Request number 2:
Cell processing search for, PN/VPI/VCI reduction
12
14
clock cycles
Request number 3:
Search request by the microprocessor
12
14
clock cycles
Request number 4: CAME Write command
8
101)
clock cycles
MODE.CEE = 0, MODE.CLE = 1
12
14
clock cycles
MODE.CEE = 1, MODE.CLE = 0
14
16
clock cycles
MODE.CEE = 1, MODE.CLE = 1
16
18
clock cycles
Request number 5: CAME Read command
11
13
clock cycles
Request number 6:
Test and configuration of the CAME
8
9
clock cycles
Extended modes:
1)
Only this mode is selected by the ALP PXB 4350 E.
Data Sheet
7-61
07.2000
3;%)
(OHFWULFDO&KDUDFWHULVWLFV
2
1
CLK
3
6
4
CS
5
OE
WE
ADR(3:0)
DAT(16:0)
8
7
)LJXUH
&$0(5HDG&\FOH
CLK
3
4
CS
OE
WE
ADR(3:0)
DAT(16:0)
)LJXUH
Data Sheet
&$0(:ULWH&\FOH
7-62
07.2000
3;%)
(OHFWULFDO&KDUDFWHULVWLFV
7DEOH
3DUDPHWHUVIRU5HDG:ULWH$FFHVV
1R
3DUDPHWHU
8QLW
PLQ
/LPLW9DOXHV
W\S
PD[
1
CLK frequency
0.01
25.92
MHz
2
CLK duty cycle
40
60
%
3
Set up time of CS, WE, ADR and DAT in 4
read and write cycle to CLK ↑
ns
4
Hold time of CS, WE, ADR and DAT in 4
read and write cycle from CLK ↑
ns
5a1)
Data access of DAT in read cycle from
CLK ↑ (32-bit access)
35
ns
5b1)
Data access of DAT in read cycle from
CLK ↑ (16-bit access)
19
ns
6
Data hold of DAT in read cycle from
CLK ↑
7
OE low of DAT in read cycle to Output
active
21
ns
8
OE high of DAT in read cycle to Output Z
21
ns
1)
4
ns
The ALP PXB 4350 E uses only the 16-bit access
$&&KDUDFWHULVWLFVRI&$0(&DVFDGH,QWHUIDFH
Transfer of status information
1
CLK
2
2
valid
CO(2:0)
3
CI(2:0)
)LJXUH
Data Sheet
4
valid
7LPLQJRI&DVFDGH,QWHUIDFH
7-63
07.2000
3;%)
(OHFWULFDO&KDUDFWHULVWLFV
7DEOH
&DVFDGH,QWHUIDFH7LPLQJ3DUDPHWHUV
1R
3DUDPHWHU
PLQ
8QLW
25.92
MHz
22
ns
1
CLK frequency
2
CO change from CLK ↓
3
Set up time to CLK ↑
17
ns
4
Hold time from CLK ↑
2
ns
Data Sheet
0.01
/LPLW9DOXHV
W\S
PD[
7-64
07.2000
3;%)
3DFNDJH2XWOLQHV
3DFNDJH2XWOLQHV
GPP05616
74)3
(144 pin Thin Plastic Quad Flatpack)
)LJXUH
6RUWVRI3DFNLQJ
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
Dimensions in mm
SMD = Surface Mounted Device
Data Sheet
8-65
07.2000
3;%)
5HIHUHQFHV
1.
5HIHUHQFHV
Joint Test Action Group JTAG standard IEEE Std. 1149.1
$FURQ\PV
ABM
ALP
AOP
ARC
byte
CAME
double word
F4
F5
HT
I/O
IP
LCI
LSB
octet
OAM
PN
SSRAM
tbd
TEP
VCC
VCI
VPVPC
VPI
word
Data Sheet
PXB 4330 E $TM %uffer 0anager
PXB 4350 E $TM /ayer 3rocessor
PXB 4340 E $TM 2AM 3rocessor
$ddress 5eduction &ircuit
octet = 8 bits
&ontent $ddressable 0emory (lement
32 bits
Virtual Path Layer
Virtual Channel Layer
+eader 7ranslation
,nput/2utput
,ntermediate 3oint
/ocal &onnection ,dentifier
/east 6ignificant %it
byte = 8 bits
2peration $nd 0aintenance
3ort 1umber
6ynchronous 6tatic 5andom$ccess0emory
Wo Ee Gefined
7erminating (nd 3oint
9irtual &hannel &onnection
9irtual &hannel ,dentifier of standardized ATM cell
9irtual 3ath specific
9irtual 3ath &onnection
9irtual 3ath ,dentifier of standardized ATM cell
16 bits
9-66
07.2000