14-Bit, 80 MSPS/105 MSPS A/D Converter AD6645 generation in a wideband ADC family, preceded by the AD9042 (12-bit, 41 MSPS), the AD6640 (12-bit, 65 MSPS, IF sampling), and the AD6644 (14-bit, 40 MSPS/65 MSPS). FEATURES SNR = 75 dB, fIN 15 MHz, up to 105 MSPS SNR = 72 dB, fIN 200 MHz, up to 105 MSPS SFDR = 89 dBc, fIN 70 MHz, up to 105 MSPS 100 dBFS multitone SFDR IF sampling to 200 MHz Sampling jitter: 0.1 ps 1.5 W power dissipation Differential analog inputs Pin compatible to AD6644 Twos complement digital output format 3.3 V CMOS compatible Data-ready for output latching Designed for multichannel, multimode receivers, the AD6645 is part of the Analog Devices, Inc., SoftCell® transceiver chipset. The AD6645 maintains 100 dB multitone, spurious-free dynamic range (SFDR) through the second Nyquist band. This breakthrough performance eases the burden placed on multimode digital receivers (software radios) that are typically limited by the ADC. Noise performance is exceptional; typical signal-to-noise ratio (SNR) is 74.5 dB through the first Nyquist band. The AD6645 is built on the Analog Devices extra fast complementary bipolar (XFCB) process and uses an innovative, multipass circuit architecture. Units are available in thermally enhanced 52-lead PowerQuad 4 (LQFP_PQ4) and 52-lead exposed pad (TQFP_EP) packages specified from −40°C to +85°C at 80 MSPS and −10°C to +85°C at 105 MSPS. APPLICATIONS Multichannel, multimode receivers Base station infrastructures AMPS, IS-136, CDMA, GSM, W-CDMA Single channel digital receivers Antenna array processing Communications instrumentation Radars, infrared imaging Instrumentation PRODUCT HIGHLIGHTS 1. 2. GENERAL DESCRIPTION 3. The AD6645 is a high speed, high performance, monolithic 14-bit analog-to-digital converter (ADC). All necessary functions, including track-and-hold (T/H) and reference, are included on the chip to provide a complete conversion solution. The AD6645 provides CMOS-compatible digital outputs. It is the fourth IF Sampling. The AD6645 maintains outstanding ac performance up to input frequencies of 200 MHz, suitable for multicarrier 3G wideband cellular IF sampling receivers. Pin Compatibility. The ADC has the same footprint and pin layout as the AD6644 14-bit, 40 MSPS/65 MSPS ADC. SFDR Performance and Oversampling. Multitone SFDR performance of 100 dBFS can reduce the requirements of high end RF components and allows the use of receive signal processors, such as the AD6620, AD6624/AD6624A, or AD6636. FUNCTIONAL BLOCK DIAGRAM AVCC DVCC AD6645 AIN VREF A1 TH1 TH2 A2 ADC1 TH3 TH4 DAC1 TH5 ADC2 ENCODE 6 DAC2 2.4V 5 ENCODE ADC3 5 INTERNAL TIMING GND DIGITAL ERROR CORRECTION LOGIC DMID OVR DRY D13 MSB D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB 02647-001 AIN Figure 1. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2002–2008 Analog Devices, Inc. All rights reserved. AD6645 TABLE OF CONTENTS Features .............................................................................................. 1 Explanation of Test Levels ............................................................7 Applications ....................................................................................... 1 ESD Caution...................................................................................7 General Description ......................................................................... 1 Pin Configuration and Function Descriptions..............................8 Product Highlights ........................................................................... 1 Typical Performance Characteristics ..............................................9 Functional Block Diagram .............................................................. 1 Equivalent Circuits ......................................................................... 14 Revision History ............................................................................... 2 Terminology .................................................................................... 15 Specifications..................................................................................... 3 Theory of Operation ...................................................................... 17 DC Specifications ......................................................................... 3 Applying the AD6645 ................................................................ 17 Digital Specifications ................................................................... 4 Layout Information ........................................................................ 19 AC Specifications.......................................................................... 4 Jitter Considerations .................................................................. 19 Switching Specifications .............................................................. 5 Outline Dimensions ....................................................................... 24 Absolute Maximum Ratings............................................................ 7 Ordering Guide .......................................................................... 24 Thermal Resistance ...................................................................... 7 REVISION HISTORY 10/08—Rev. C to Rev. D Added TQFP_EP Package ............................................ Throughout Renamed Thermal Characteristics Section Thermal Resistance Section ................................................................................................ 7 Added Table 6; Renumbered Sequentially .................................... 7 Moved Equivalent Circuits Section .............................................. 14 Moved Terminology Section ......................................................... 15 Changes to Table 9 .......................................................................... 20 Updated Outline Dimensions ....................................................... 24 Changes to Ordering Guide .......................................................... 24 7/03—Rev. A to Rev. B. Changes to Title ................................................................................1 Changes to Features ..........................................................................1 Changes to Product Description .....................................................1 Changes to Specifications .................................................................3 Changes to Absolute Maximum Ratings ........................................7 Changes to Ordering Guide .......................................................... 24 Updated Outline Dimensions ....................................................... 20 6/02—Rev. 0 to Rev. A. Change to DC Specifications ...........................................................3 12/06—Rev. B to Rev. C Updated Format .................................................................. Universal Changes to Specifications ................................................................ 3 Changes to Jitter Considerations Section .................................... 19 Changes to Table 8, Bill of Materials ............................................ 20 Changes to Figure 43, Evaluation Board Schematic .................. 21 Changes to Figure 44 and Figure 46 ............................................. 22 Updated Outline Dimensions ....................................................... 23 Changes to Ordering Guide .......................................................... 23 Rev. D | Page 2 of 24 AD6645 SPECIFICATIONS DC SPECIFICATIONS AVCC = 5 V, DVCC = 3.3 V; TMIN and TMAX at rated speed grade, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error POWER SUPPLY REJECTION RATIO (PSRR) REFERENCE OUT (VREF) 1 ANALOG INPUTS (AIN, AIN) Differential Input Voltage Range Differential Input Resistance Differential Input Capacitance POWER SUPPLY Supply Voltages AVCC DVCC Supply Current IAVCC (AVCC = 5.0 V) IDVCC (DVCC = 3.3 V) Rise Time 2 AVCC POWER CONSUMPTION Temp Test Level AD6645ASQ-80/AD6645ASV-80 Min Typ Max 14 Full Full Full Full Full II II II II V −10 −10 −1.0 Full Full 25°C V V V 1.5 48 ±1.0 1.5 48 ±1.0 ppm/°C ppm/°C mV/V Full V 2.4 2.4 V Full Full 25°C V V 2.2 1 1.5 2.2 1 1.5 V p-p kΩ pF Full Full II II Full Full Full Full 4.75 3.0 Guaranteed +1.2 +10 0 +10 ±0.25 +1.5 ±0.5 5.0 3.3 5.25 3.6 II II 275 32 IV II 1.5 1 AD6645ASQ-105/AD6645ASV-105 Min Typ Max 14 −10 −10 −1.0 4.75 3.0 Guaranteed +1.2 +10 0 +10 ±0.5 +1.5 ±1.5 Unit Bits mV % FS LSB LSB 5.0 3.3 5.25 3.6 V V 320 45 275 32 320 45 mA mA 250 1.75 5.0 1.5 250 1.75 ms W VREF is provided for setting the common-mode offset of a differential amplifier, such as the AD8138, when a dc-coupled analog input is required. VREF should be buffered if used to drive additional circuit functions. 2 Specified for dc supplies with linear rise time characteristics. Rev. D | Page 3 of 24 AD6645 DIGITAL SPECIFICATIONS AVCC = 5 V, DVCC = 3.3 V; TMIN and TMAX at rated speed grade, unless otherwise noted. Table 2. Parameter ENCODE INPUTS (ENCODE, ENCODE) Differential Input Voltage 1 Differential Input Resistance Differential Input Capacitance LOGIC OUTPUTS (D13 to D0, DRY, OVR) Logic Compatibility Logic 1 Voltage (DVCC = 3.3 V) 2 Logic 0 Voltage (DVCC = 3.3 V)2 Output Coding DMID 1 2 Temp Test Level AD6645ASQ-80/AD6645ASV-80 Min Typ Max AD6645ASQ-105/AD6645ASV-105 Min Typ Max Full 25°C 25°C IV V V 0.4 0.4 Full Full II II 2.85 Full V 10 2.5 V p-p kΩ pF 10 2.5 CMOS DVCC − 2 0.2 Twos complement DVCC/2 2.85 0.5 Unit CMOS DVCC − 2 0.2 Twos complement DVCC/2 0.5 V V V All ac specifications tested by driving ENCODE and ENCODE differentially. Digital output logic levels: DVCC = 3.3 V, CLOAD = 10 pF. Capacitive loads >10 pF degrades performance. AC SPECIFICATIONS All ac specifications tested by driving ENCODE and ENCODE differentially. AVCC = 5 V, DVCC = 3.3 V; ENCODE, ENCODE, TMIN and TMAX at rated speed grade, unless otherwise noted. Table 3. Parameter SNR Analog Input @ −1 dBFS SINAD Analog Input @ −1 dBFS WORST HARMONIC (SECOND OR THIRD) Analog Input @ −1 dBFS Temp Test Level 25°C Full 25°C Full 25°C 25°C V II I II V V 25°C Full 25°C Full 25°C 25°C V II I V V V 25°C Full 25°C Full 25°C 25°C V II I V V V AD6645ASQ-80/ AD6645ASV-80 Min Typ Max AD6645ASQ-105/ AD6645ASV-105 Min Typ Max 75.0 74.5 75.0 72.5 72.0 72.5 73.5 73.0 72.0 72.5 72.0 75.0 74.5 75.0 72.5 73.0 68.5 62.5 85.0 93.0 93.0 Rev. D | Page 4 of 24 74.5 73.0 67.5 62.5 93.1 85.0 89.0 70.0 63.5 74.5 73.5 73.0 72.0 93.0 87.0 70.0 63.5 Unit Conditions dB dB dB dB dB dB At 15.5 MHz At 30.5 MHz At 37.7 MHz At 70.0 MHz At 150.0 MHz At 200.0 MHz dB dB dB dB dB dB At 15.5 MHz At 30.5 MHz At 37.7 MHz At 70.0 MHz At 150.0 MHz At 200.0 MHz dBc dBc dBc dBc dBc dBc At 15.5 MHz At 30.5 MHz At 37.7 MHz At 70.0 MHz At 150.0 MHz At 200.0 MHz AD6645 Parameter WORST HARMONIC (FOURTH OR HIGHER) Analog Input @ −1 dBFS TWO-TONE SFDR TWO-TONE IMD REJECTION2, 3 F1, F2 @ −7 dBFS ANALOG INPUT BANDWIDTH Temp Test Level 25°C Full 25°C Full 25°C 25°C 25°C 25°C 25°C V II I V V V V V V 25°C 25°C V V AD6645ASQ-80/ AD6645ASV-80 Min Typ Max AD6645ASQ-105/ AD6645ASV-105 Min Typ Max 96.0 95.0 96.0 85.0 Unit Conditions At 15.5 MHz At 30.5 MHz At 37.7 MHz At 70.0 MHz At 150.0 MHz At 200.0 MHz At 30.5 MHz 1, 2 At 55.0 MHz1, 3 At 70.0 MHz1, 4 90.0 90.0 88.0 100 100 95.0 90.0 90.0 88.0 98.0 98.0 98.0 dBc dBc dBc dBc dBc dBc dBFS dBFS dBFS 90 270 90 270 dBc MHz 86.0 1 Analog input signal power swept from −10 dBFS to −100 dBFS. F1 = 30.5 MHz, F2 = 31.5 MHz. 3 F1 = 55.25 MHz, F2 = 56.25 MHz. 4 F1 = 69.1 MHz, F2 = 71.1 MHz. 2 SWITCHING SPECIFICATIONS AVCC = 5 V, DVCC = 3.3 V; ENCODE, ENCODE, TMIN and TMAX at rated speed grade, unless otherwise noted. Table 4. Parameter ENCODE INPUT PARAMETERS 1 Maximum Conversion Rate Minimum Conversion Rate ENCODE Pulse Width High, tENCH 2 Symbol Temp Test Level tENC Full Full Full Full Full Full Full II IV IV V IV V V Full Full Full V V V Full Full Full Full V V V V ENCODE Pulse Width Low, tENCL2 ENCODE Period1 ENCODE/DATA-READY ENCODE Rising to Data-Ready Falling ENCODE Rising to Data-Ready Rising 50% Duty Cycle ENCODE/DATA (D13:0), OVR ENCODE to DATA Falling Low ENCODE to DATA Rising Low 3 ENCODE to DATA Delay3 (Hold Time) ENCODE to DATA Delay (Setup Time) tDR tE_DR tE_FL tE_RL tH_E tS_E AD6645ASQ-80/ AD6645ASV-80 Min Typ Max AD6645ASQ-105/ AD6645ASV-105 Min Typ Max 80 105 30 5.625 30 4.286 6.25 4.75 5.625 4.286 6.25 12.5 1.0 7.3 2.4 1.4 1.4 tENC − tE_FL(max) 4.75 9.5 2.0 tENCH + tDR 8.3 3.1 1.0 9.4 5.7 4.7 3.0 3.0 7.0 4.7 4.7 2.4 1.4 1.4 tENC − tE_FL(max) tENC − tE_FL(typ) 50% Duty Cycle Full V 5.3 Rev. D | Page 5 of 24 7.6 2.0 tENCH + tDR 6.75 3.1 7.9 4.7 3.0 3.0 7.0 4.7 4.7 2.3 4.8 MSPS MSPS ns ns ns ns ns ns ns ns ns ns ns ns ns tENC − tE_FL(typ) tENC − tE_FL(min) 10.0 Unit tENC − tE_FL(min) 7.0 ns ns AD6645 Parameter DATA-READY (DRY 4 )/DATA(D13:0),, OVR Data-Ready to DATA Delay (Hold Time) 50% Duty Cycle Data-Ready to DATA Delay (Setup Time) 50% Duty Cycle APERTURE DELAY APERTURE UNCERTAINTY (JITTER) Symbol Temp Test Level tH_DR Full Full Full Full 25°C 25°C V V V V V V tS_DR tA tJ AD6645ASQ-80/ AD6645ASV-80 Min Typ Max AD6645ASQ-105/ AD6645ASV-105 Min Typ Max Note 5 5 7.2 Note 55 3.6 −500 0.1 Note 55 5.7 Note 55 2.1 −500 6.6 2.1 7.9 5.1 5.1 0.6 6.4 ns 3.5 ns ps ps rms 0.1 1 Several timing parameters are a function of tENC and tENCH. Several timing parameters are a function of tENCL and tENCH. ENCODE TO DATA Delay (Hold Time) is the absolute minimum propagation delay through the ADC, tE_RL = tH_E. 4 DRY is an inverted and delayed version of the encode clock. Any change in the duty cycle of the clock will correspondingly change the duty cycle of DRY. 5 Data-ready to DATA Delay (tH_DR and tS_DR) is calculated relative to rated speed grade and is dependent on tENC and duty cycle. 2 3 tA N+3 N AIN N+1 N+2 tE_RL D[13:0], OVR tENCH tENC N tENCL N+1 N+4 N+2 tE_FL N+3 tE_DR N–3 N–2 N–1 tS_DR DRY tDR Figure 2. Timing Diagram Rev. D | Page 6 of 24 N+4 tS_E tH_E N tH_DR 02647-002 ENCODE, ENCODE Unit AD6645 ABSOLUTE MAXIMUM RATINGS Values of θJA are provided for package comparison and PCB design considerations. θJA can be used for a first-order approximation of TJ by the equation Table 5. Parameter Electrical AVCC Voltage DVCC Voltage Analog Input Voltage Analog Input Current Digital Input Voltage Digital Output Current Environmental Operating Temperature Range (Ambient) AD6645-80 AD6645-105 Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Storage Temperature Range (Ambient) Rating TJ = TA + (θJA × PD) 0 V to 7 V 0 V to 7 V 0 V to AVCC 25 mA 0 V to AVCC 4 mA where: TA is the ambient temperature (°C). PD is the power dissipation (W). EXPLANATION OF TEST LEVELS −40°C to +85°C −10°C to +85°C 150°C 300°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. I. 100% production tested. II. 100% production tested at 25°C and guaranteed by design and characterization at temperature extremes. III. Sample tested only. IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only. ESD CAUTION THERMAL RESISTANCE The heat sink of the AD6645ASVZ, 52-lead TQFP_EP (SV-52-1) package must be soldered to the PCB GND plane to meet thermal specifications. Table 6. Thermal Characteristics Package Type 52-Lead TQFP_EP θJA (0 m/sec airflow)1, 2, 3 θJMA (1.0 m/sec airflow)2, 3, 4, 5 θJC6, 7 52-Lead LQFP_PQ4 θJA (0 m/sec airflow)1, 2, 3 θJMA (1.0 m/sec airflow)2, 3, 4, 5 θJA (0 m/sec airflow)1, 2, 3 θJMA (1.0 m/sec airflow)2, 3, 4, 5 θJC6, 7 Rating 23°C/W, soldered heat sink 17°C/W, soldered heat sink 2°C/W, soldered heat sink 30°C/W, unsoldered heat sink 24°C/W, unsoldered heat sink 23°C/W, soldered heat sink 17°C/W, soldered heat sink 2°C/W 1 Per JEDEC JESD51-2 (heat sink soldered to PCB). 2S2P JEDEC test board. Values of θJA are provided for package comparison and PCB design considerations. 4 Per JEDEC JESD51-6 (heat sink soldered to PCB). 5 Airflow increases heat dissipation, effectively reducing θJA. Furthermore, the more metal that is directly in contact with the package leads from metal traces, throughholes, ground, and power planes, the more θJA is reduced. 6 Per MIL-STD-883, Method 1012.1. 7 Values of θJC are provided for package comparison and PCB design considerations when an external heat sink is required. 2 3 Rev. D | Page 7 of 24 AD6645 D4 D5 GND DVCC D6 D7 D8 D9 D10 D11 D12 D13 (MSB) DRY PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 52 51 50 49 48 47 46 45 44 43 42 41 40 DVCC 1 39 D3 PIN 1 IDENTIFIER GND 2 38 D2 VREF 3 37 D1 GND 4 36 D0 (LSB) ENCODE 5 35 DMID AD6645 ENCODE 6 AVCC 8 AVCC 34 GND TOP VIEW (Not to Scale) GND 7 33 DVCC 32 OVR 31 DNC 9 GND 10 30 AVCC AIN 11 29 GND AIN 12 28 AVCC GND 13 27 GND NOTES 1. DNC = DO NOT CONNECT. 2. EXPOSED PAD. CONNECT THE EXPOSED PAD TO GND. 02647-003 AVCC GND C2 GND AVCC GND C1 GND AVCC GND AVCC GND AVCC 14 15 16 17 18 19 20 21 22 23 24 25 26 Figure 3. Pin Configuration Table 7. Pin Function Descriptions Pin Number 1, 33, 43 2, 4, 7, 10, 13, 15, 17, 19, 21, 23, 25, 27, 29, 34, 42 3 5 6 8, 9, 14, 16, 18, 22, 26, 28, 30 11 12 20 24 31 32 35 36 37 to 41, 44 to 50 51 52 53 (EPAD) Mnemonic DVCC GND Description 3.3 V Power Supply (Digital) Output Stage Only. Ground. VREF ENCODE ENCODE AVCC AIN AIN C1 C2 DNC OVR DMID D0 (LSB) D1 to D5, D6 to D12 D13 (MSB) DRY Exposed Paddle (EPAD) 2.4 V Reference. Bypass to ground with a 0.1 μF microwave chip capacitor. Encode Input. Conversion initiated on rising edge. Complement of ENCODE, Differential Input. 5 V Analog Power Supply. Analog Input. Complement of AIN, Differential Analog Input. Internal Voltage Reference. Bypass to ground with a 0.1 μF chip capacitor. Internal Voltage Reference. Bypass to ground with a 0.1 μF chip capacitor. Do not connect this pin. Overrange Bit. A logic level high indicates analog input exceeds ±FS. Output Data Voltage Midpoint. Approximately equal to (DVCC)/2. Digital Output Bit (Least Significant Bit); Twos Complement. Digital Output Bits in Twos Complement. Digital Output Bit (Most Significant Bit); Twos Complement. Data-Ready Output. Exposed Pad. Connect the exposed pad to GND. Rev. D | Page 8 of 24 AD6645 TYPICAL PERFORMANCE CHARACTERISTICS 0 0 ENCODE = 80MSPS AIN = 2.2MHz @ –1dBFS SNR = 75.0dB SFDR = 93.0dBc –10 –20 –30 –30 –40 –40 AMPLITUDE (dBFS) –50 –60 –70 –80 –90 3 2 5 –100 6 4 –110 –60 –70 –80 –90 6 5 10 15 20 25 FREQUENCY (MHz) 30 35 40 –130 0 5 –20 –30 –30 –40 –40 –50 –60 –70 –80 3 5 –100 6 –110 40 –60 3 –70 2 –80 –90 4 5 6 –110 –120 5 10 15 20 25 FREQUENCY (MHz) 30 35 40 –130 0 5 –20 –40 AMPLITUDE (dBFS) –30 –40 –50 –60 –70 –80 3 2 5 –100 35 40 40 ENCODE = 80MSPS AIN = 200MHz @ –1dBFS SNR = 72.0dB SFDR = 64.0dBc –10 –30 –90 30 0 ENCODE = 80MSPS AIN = 29.5MHz @ –1dBFS SNR = 74.5dB SFDR = 93.0dBc –20 15 20 25 FREQUENCY (MHz) Figure 8. Single Tone @ 150 MHz 0 –10 10 02647-014 0 02647-011 –120 Figure 5. Single Tone @ 15.5 MHz AMPLITUDE (dBFS) 35 –50 –100 2 4 30 ENCODE = 80MSPS AIN = 150MHz @ –1dBFS SNR = 73.0dB SFDR = 70.0dBc –10 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 0 ENCODE = 80MSPS AIN = 15.5MHz @ –1dBFS SNR = 75.0dB SFDR = 93.0dBc –90 15 20 25 FREQUENCY (MHz) Figure 7. Single Tone @ 69.1 MHz 0 –20 10 02647-013 0 02647-010 –120 –10 6 –50 –60 3 –70 2 –80 4 –90 6 5 –100 4 –110 –110 –120 –120 0 5 10 15 20 25 FREQUENCY (MHz) 30 35 40 –130 02647-012 –130 4 5 –110 Figure 4. Single Tone @ 2.2 MHz –130 3 2 –100 –120 –130 –50 02647-015 AMPLITUDE (dBFS) –20 ENCODE = 80MSPS AIN = 69.1MHz @ –1dBFS SNR = 73.5dB SFDR = 89.0dBc –10 0 5 10 15 20 25 FREQUENCY (MHz) 30 Figure 9. Single Tone @ 200 MHz Figure 6. Single Tone @ 29.5 MHz Rev. D | Page 9 of 24 35 AD6645 100 75.5 95 75.0 T = –40°C HARMONICS (dBc) T = +85°C T = +25°C 73.5 73.0 85 80 HARMONICS (SECOND, THIRD) 75 70 72.5 65 10 20 30 40 FREQUENCY (MHz) 50 60 70 02647-016 0 60 ENCODE = 80MSPS @ AIN = –1dBFS TEMP = 25°C 0 20 Figure 10. Signal-to-Noise Ratio (SNR) vs. Frequency 180 200 T = –40°C, +85°C 88 86 84 ENCODE = 80MSPS @ AIN = –1dBFS TEMP = –40°C, +25°C, +85°C 10 20 30 40 50 ANALOG INPUT FREQUENCY (MHz) 60 70 dBFS 100 90 80 ENCODE = 80MSPS AIN = 30.5MHz 70 dBc 60 50 SFDR = 90dB REFERENCE LINE 40 30 20 10 0 –90 02647-017 0 110 –80 Figure 11. Worst-Case Harmonics vs. Analog Input Frequency –70 –60 –50 –40 –30 –20 ANALOG INPUT POWER LEVEL (dBFS) –10 0 02647-020 WORST-CASE SPURIOUS (dBFS AND dBc) WORST-CASE HARMONIC (dBc) T = +25°C 90 82 Figure 14. Single-Tone SFDR @ 30.5 MHz 76 WORST CASE SPURIOUS (dBFS AND dBc) 120 75 74 73 72 71 ENCODE = 80MSPS @ AIN = –1dBFS TEMP = 25°C 0 20 40 60 80 100 120 140 ANALOG FREQUENCY (MHz) 160 180 200 110 dBFS 100 90 80 ENCODE = 80MSPS AIN = 69.1MHz 70 Figure 12. Signal-to-Noise Ratio (SNR) vs. Analog Frequency (IF) dBc 60 50 SFDR = 90dB REFERENCE LINE 40 30 20 10 0 –90 02647-018 SNR (dB) 160 120 92 70 60 80 100 120 140 ANALOG FREQUENCY (MHz) Figure 13. Harmonics vs. Analog Frequency (IF) 94 80 40 02647-019 ENCODE = 80MSPS @ AIN = –1dBFS TEMP = –40°C, +25°C, +85°C –80 –70 –60 –50 –40 –30 –20 ANALOG INPUT POWER LEVEL (dBFS) Figure 15. Single-Tone SFDR @ 69.1 MHz Rev. D | Page 10 of 24 –10 0 02647-021 SNR (dB) 74.0 72.0 WORST OTHER SPUR 90 74.5 0 ENCODE = 80MSPS –10 AIN = 30.5MHz, 31.5MHz (–7dBFS) –20 NO DITHER –30 0 ENCODE = 80MSPS –10 AIN = 55.25MHz, 56.25MHz (–7dBFS) –20 NO DITHER –40 –40 –50 –110 –120 –120 5 10 15 20 25 FREQUENCY (MHz) 30 35 40 –130 02647-022 0 Figure 16. Two-Tone SFDR @ 30.5 MHz and 31.5 MHz dBc 60 SFDR = 90dB REFERENCE LINE 50 40 30 20 10 30 35 40 –67 –57 –47 –37 –27 –17 INPUT POWER LEVEL (F1 = F2 dBFS) –7 100 dBFS 90 80 ENCODE = 80MSPS F1 = 55.25MHz F2 = 56.25MHz 70 dBc 60 SFDR = 90dB REFERENCE LINE 50 40 30 20 10 0 –77 –67 –57 –47 –37 –27 –17 INPUT POWER LEVEL (F1 = F2 dBFS) –7 Figure 20. Two-Tone SFDR @ 55.25 MHz and 56.25 MHz Figure 17. Two-Tone SFDR @ 30.5 MHz and 31.5 MHz 95 SNR, WORST-CASE SPURIOUS (dB AND dBc) 100 WORST SPUR @ AIN = 2.2MHz 95 90 85 80 SNR @ AIN = 2.2MHz 75 30 45 60 75 ENCODE FREQUENCY (MHz) 90 105 02647-024 70 WORST SPUR @ AIN = 69.1MHz 90 85 80 75 SNR @ AIN = 69.1MHz 70 65 15 30 45 60 75 ENCODE FREQUENCY (MHz) 90 105 Figure 21. SNR, Worst-Case Spurious vs. Encode @ 69.1 MHz Figure 18. SNR, Worst-Case Spurious vs. Encode @ 2.2 MHz Rev. D | Page 11 of 24 02647-027 0 –77 SNR, WORST-CASE SPURIOUS (dB AND dBc) 15 20 25 FREQUENCY (MHz) 02647-026 WORST-CASE SPURIOUS (dBFS AND dBc) ENCODE = 80MSPS F1 = 30.5MHz F2 = 31.5MHz 02647-023 WORST-CASE SPURIOUS (dBFS AND dBc) dBFS 70 65 15 10 110 100 80 5 Figure 19. Two-Tone SFDR @ 55.25 MHz and 56.25 MHz 110 90 0 02647-025 –90 –100 2F1 – F2 –80 –110 –130 2F1 + F2 2F2 + F1 –70 2F2 – F1 –60 F1 + F2 –100 2F1 – F2 –90 F1 + F2 –80 2F1 + F2 2F2 + F1 –70 2F2 – F1 –60 F2 – F1 AMPLITUDE (dBFS) –30 –50 F2 – F1 AMPLITUDE (dBFS) AD6645 AD6645 –20 –30 –30 –40 –40 AMPLITUDE (dBFS) –50 –60 –70 –80 2 –90 6 –100 –110 –60 –70 –80 –90 –100 4 3 5 –50 0 5 10 15 20 25 FREQUENCY (MHz) 30 35 40 –130 02647-028 0 5 110 ENCODE = 80.0MSPS AIN = 30.5MHz NO DITHER 100 90 WORST-CASE SPURIOUS (dBc) WORST-CASE SPURIOUS (dBc) 100 80 70 60 50 40 SFDR = 90dB REFERENCE LINE 30 20 10 30 35 40 –10 0 ENCODE = 80.0MSPS AIN = 30.5MHz WITH DITHER @ –19.2dBm 90 80 70 60 SFDR = 100dB REFERENCE LINE 50 40 SFDR = 90dB REFERENCE LINE 30 20 80 70 60 50 40 30 20 ANALOG INPUT LEVEL (dBFS) 10 0 02647-029 10 0 90 0 –90 –80 Figure 23. SFDR Without Dither 0 –20 0 –40 AMPLITUDE (dBFS) –30 –50 –60 –70 –80 3 5 2 6 –110 –50 –60 –70 –80 –90 –100 4 2 –110 –120 3 6 4 5 –120 0 5 10 15 20 25 FREQUENCY (MHz) 30 35 40 02647-030 –130 ENCODE = 76.8MSPS AIN = W-CDMA @ 69.1MHz –20 –40 –100 –60 –50 –40 –30 –20 ANALOG INPUT LEVEL (dBFS) –10 –30 –90 –70 Figure 26. SFDR with Dither ENCODE = 76.8MSPS AIN = 69.1MHz @ –1dBFS SNR = 73.5dB SFDR = 89.0dBc –10 AMPLITUDE (dBFS) 15 20 25 FREQUENCY (MHz) Figure 25. 1 M Sample FFT with Dither Figure 22. 1 M Sample FFT Without Dither 110 10 02647-032 –130 6 3 5 –120 –120 4 2 –110 Figure 24. Single Tone @ 69.1 MHz, Encode = 76.8 MSPS –130 0 5 10 15 20 25 FREQUENCY (MHz) 30 35 40 Figure 27. W-CDMA Tone @ 69.1 MHz, Encode = 76.8 MSPS Rev. D | Page 12 of 24 02647-033 AMPLITUDE (dBFS) 0 ENCODE = 80.0MSPS –10 AIN = 30.5MHz @ –29.5dBFS WITH DITHER @ –19.2 dBm –20 ENCODE = 80.0MSPS AIN = 30.5MHz @ –29.5dBFS NO DITHER 02647-031 0 –10 AD6645 –20 –30 –30 –40 –40 AMPLITUDE (dBFS) –20 –50 –60 –70 –80 –90 –60 –70 –80 –90 –100 –110 –110 –120 –120 5 10 15 20 25 FREQUENCY (MHz) 30 35 40 –130 0 –30 –40 –40 AMPLITUDE (dBFS) –20 –50 –60 –70 –80 –90 15 20 25 FREQUENCY (MHz) 30 35 40 ENCODE = 61.44MSPS AIN = W-CDMA @ 190MHz –70 –80 –90 –110 –120 –120 02647-035 –110 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 FREQUENCY (MHz) 3 –60 –100 5.0 2 –50 –100 2.5 10 0 –30 0 5 4 –10 –20 –130 5 Figure 30. W-CDMA Tone @ 140 MHz, Encode = 76.8 MSPS ENCODE = 61.44MSPS AIN = 4W-CDMA @ 46.08MHz –10 0 6 Figure 29. Four W-CDMA Carriers @ 46.08 MHz, Encode = 61.44 MSPS Rev. D | Page 13 of 24 –130 2 0 2.5 5.0 3 6 4 5 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 FREQUENCY (MHz) Figure 31. W-CDMA Tone @ 190 MHz, Encode = 61.44 MSPS 02647-037 0 Figure 28. Two W-CDMA Carriers @ 59.6 MHz, Encode = 76.8 MSPS AMPLITUDE (dBFS) –50 –100 –130 ENCODE = 76.8MSPS AIN = W-CDMA @ 140MHz –10 02647-034 AMPLITUDE (dBFS) 0 ENCODE = 76.8MSPS AIN = 2W-CDMA @ 59.6MHz 02647-036 0 –10 AD6645 EQUIVALENT CIRCUITS DVCC VCH AVCC AIN BUF CURRENT MIRROR T/H 500Ω VCL VREF BUF VCH AVCC 500Ω BUF DVCC T/H 02647-004 AIN VCL D0 TO D13, OVR, DRY VREF Figure 32. Analog Input Stage LOADS AVCC AVCC AVCC AVCC 10kΩ 10kΩ CURRENT MIRROR ENCODE 10kΩ 02647-007 ENCODE 10kΩ Figure 35. Digital Output Stage AVCC 02647-005 LOADS Figure 33. Encode Inputs AVCC 2.4V VREF AVCC 02647-008 100µA Figure 36. 2.4 V Reference VREF AVCC AVCC DVCC 10kΩ CURRENT MIRROR Figure 34. Compensation Pin, C1 or C2 10kΩ 02647-009 C1, C2 02647-006 DMID Figure 37. DMID Reference Rev. D | Page 14 of 24 AD6645 TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point of the rising edge of the encode command and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Differential Analog Input Resistance, Differential Analog Input Capacitance, and Differential Analog Input Impedance The real and complex impedances measured at each analog input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer. Differential Analog Input Voltage Range The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. The peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180° out of phase. The peak-to-peak differential is computed by rotating the inputs’ phase 180°and taking the peak measurement again. The difference is then computed between both peak measurements. Differential Nonlinearity The deviation of any code width from an ideal 1 LSB step. Encode Pulse Width/Duty Cycle Pulse width high is the minimum amount of time that the encode pulse should be left in a high state to achieve rated performance; pulse width low is the minimum time that the encode pulse should be left in a low state. See timing implications of changing tENCH in Table 4. At a given clock rate, these specifications define an acceptable encode duty cycle. Full-Scale Input Power The full-scale input power is expressed in dBm and can be calculated by using the following equation: ⎡ V 2Full − Scale rms ⎢ ⎢ Z Input Power = 10 log ⎢ Full − Scale 0.001 ⎢ ⎢ ⎢ ⎣ ⎤ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎦ Harmonic Distortion, Second The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dBc. Harmonic Distortion, Third The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dBc. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a best straight line determined by a least square curve fit. Maximum Conversion Rate The encode rate at which parametric testing is performed. Minimum Conversion Rate The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Noise (for Any Range Within the ADC) VNOISE = − SNRdBc − SignaldBFS ⎞ ⎛ FS Z × 0.001 × 10⎜ dBm ⎟ 10 ⎝ ⎠ where: Z is the input impedance. FS is the full scale of the device for the frequency in question. SNR is the value for the particular input level. Signal is the signal level within the ADC reported in dB below full scale. This value includes both thermal noise and quantization noise. Output Propagation Delay The delay between a differential crossing of ENCODE and ENCODE and the time when all output data bits are within valid logic levels. Power Supply Rejection Ratio (PSSR) The ratio of a change in input offset voltage to a change in power supply voltage. Power Supply Rise Time The time from when the dc supply is initiated until the supply output reaches the minimum specified operating voltage for the ADC. The dc level is measured at the supply pin(s) of the ADC. Signal-to-Noise-and-Distortion (SINAD) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics, but excluding dc. Signal-to-Noise Ratio (Without Harmonics) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. Rev. D | Page 15 of 24 AD6645 Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc (that is, degrades as signal level is lowered) or dBFS (always related back to converter full scale). Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product, and may be reported in dBc (that is, degrades as signal level is lowered) or in dBFS (always related back to converter full scale). Two-Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product, reported in dBc. Worst Other Spur The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonics), reported in dBc. Rev. D | Page 16 of 24 AD6645 THEORY OF OPERATION CLOCK SOURCE The AD6645 ADC employs a three-stage subrange architecture. This design approach achieves the required accuracy and speed while maintaining low power and small die size. Both analog inputs are buffered prior to the first track-and-hold, TH1. The high state of the encode pulse places TH1 in hold mode. The held value of TH1 is applied to the input of a 5-bit coarse ADC1. The digital output of ADC1 drives a 5-bit digitalto-analog converter, DAC1. DAC1 requires 14 bits of precision that is achieved through laser trimming. The output of DAC1 is subtracted from the delayed analog signal at the input of TH3 to generate a first residue signal. TH2 provides an analog pipeline delay to compensate for the digital delay of ADC1. The first residual signal is applied to a second conversion stage consisting of a 5-bit ADC2, a 5-bit DAC2, and a pipeline TH4. The second DAC requires 10 bits of precision, which is met by the process with no trim. The input to TH5 is a second residual signal generated by subtracting the quantized output of DAC2 from the first residual signal held by TH4. TH5 drives a final 6-bit ADC3. The digital outputs from ADC1, ADC2, and ADC3 are added together and corrected in the digital error correction logic to generate the final output data. The result is a 14-bit parallel digital CMOS-compatible word, coded as twos complement. APPLYING THE AD6645 Encoding the AD6645 The AD6645 encode signal must be a high quality, extremely low phase noise source to prevent degradation of performance. Maintaining 14-bit accuracy places a premium on encode clock phase noise. SNR performance can easily degrade by 3 dB to 4 dB with 70 MHz analog input signals when using a high jitter clock source. See the AN-501 application note, Aperture Uncertainty and ADC System Performance, for complete details. For optimum performance, the AD6645 must be clocked differentially. The encode signal is usually ac-coupled into the ENCODE and ENCODE pins via a transformer or capacitors. These pins are biased internally and require no additional bias. Figure 38 shows one preferred method for clocking the AD6645. The clock source (low jitter) is converted from single-ended to differential using an RF transformer. The back-to-back Schottky diodes across the transformer secondary limit excessive amplitude swings from the clock into the AD6645 to approximately 0.8 V p-p differential. This helps to prevent the large voltage swings of the clock from feeding through to other portions of the AD6645 and limits the noise presented to the encode inputs. ENCODE AD6645 02647-038 ENCODE HSMS2812 DIODES Figure 38. Crystal Clock Oscillator, Differential Encode If a low jitter clock is available, another option is to ac-couple a differential ECL/PECL signal to the encode input pins, as shown in Figure 39. The MC100EL16 (or same family) from ON Semiconductor offers excellent jitter performance. VT 0.1µF ENCODE ECL/ PECL AD6645 ENCODE 0.1µF VT 02647-039 As shown in the functional block diagram (see Figure 1), the AD6645 has complementary analog input pins, AIN and AIN. Each analog input is centered at 2.4 V and should swing ±0.55 V around this reference (see Figure 32). Because AIN and AIN are 180° out of phase, the differential analog input signal is 2.2 V p-p. T1-4T 0.1µF Figure 39. Differential ECL for Encode Driving the Analog Inputs As with most new high speed, high dynamic range ADCs, the analog input to the AD6645 is differential. Differential inputs improve on-chip performance as signals are processed through attenuation and gain stages. Most of the improvement is a result of differential analog stages having high rejection of even-order harmonics. There are also benefits at the PCB level. First, differential inputs have high common-mode rejection of stray signals, such as ground and power noise. Second, they provide good rejection of common-mode signals, such as local oscillator feedthrough. The AD6645 analog input voltage range is offset from ground by 2.4 V. Each analog input connects through a 500 Ω resistor to the 2.4 V bias voltage and to the input of a differential buffer (see Figure 32). The resistor network on the input properly biases the followers for maximum linearity and range. Therefore, the analog source driving the AD6645 should be ac-coupled to the input pins. Because the differential input impedance of the AD6645 is 1 kΩ, the analog input power requirement is only −2 dBm, simplifying the driver amplifier in many cases. To take full advantage of this high input impedance, a 20:1 RF transformer is required. This is a large ratio and can result in unsatisfactory performance. In this case, a lower step-up ratio can be used. The recommended method for driving the differential analog input of the AD6645 is to use a 4:1 RF transformer. For example, if RT is set to 60.4 Ω and RS is set to 25 Ω, along with a 4:1 impedance ratio transformer, the input would match to a 50 Ω source with a full-scale drive of 4.8 dBm. Series resistors (RS) on the secondary side of the transformer should be used to isolate the transformer from the A/D. Rev. D | Page 17 of 24 AD6645 This limits the amount of dynamic current from the A/D flowing back into the secondary of the transformer. The 50 Ω impedance matching can also be incorporated on the secondary side of the transformer, as shown in the evaluation board schematic (see Figure 43). AIN RT RS AD6645 AIN 0.1µF 02647-040 RS ADT4-1WT ANALOG INPUT SIGNAL Figure 40. Transformer-Coupled Analog Input Circuit In applications where dc coupling is required, a differential output op amp, such as the AD8138, can be used to drive the AD6645 (see Figure 41). The AD8138 op amp provides singleended-to-differential conversion, which reduces overall system cost and minimizes layout requirements. CF Grounding 5V 499Ω VIN 499Ω VOCM To minimize capacitive loading, there should be only one gate on each output pin. An example of this is shown in the evaluation board schematic of Figure 43. The digital outputs of the AD6645 have a constant output slew rate of 1 V/ns. A typical CMOS gate combined with a PCB trace have a load of approximately 10 pF. Therefore, as each bit switches, 10 mA (10 pF × 1 V ÷ 1 ns) of dynamic current per bit flow in or out of the device. A full-scale transition can cause up to 140 mA (14 bits × 10 mA/bit) of current to flow through the output stages. Place the series resistors as close to the AD6645 as possible to limit the amount of current that can flow into the output stage. These switching currents are confined between ground and DVCC. Standard TTL gates should be avoided because they can add appreciably to the dynamic switching currents of the AD6645. Note that extra capacitive loading increases output timing and invalidates timing specifications. Digital output timing is guaranteed for output loads up to 10 pF. Digital output states for given analog input levels are shown in Table 8. 25Ω AD8138 AD6645 25Ω 499Ω AIN AIN VREF DIGITAL OUTPUTS 02647-041 499Ω CF Figure 41. DC-Coupled Analog Input Circuit Power Supplies Care should be taken when selecting a power source. The use of linear dc supplies with rise times of <45 ms is highly recommended. Switching supplies tend to have radiated components that can be received by the AD6645. Decouple each of the power supply pins as close to the package as possible using 0.1 μF chip capacitors. The AD6645 has separate digital and analog power supply pins. The analog supplies are AVCC and the digital supply pins are DVCC. Although analog and digital supplies can be tied together, the best performance is achieved when the supplies are separate because the fast digital output swings can couple switching currents back into the analog supplies. Note that AVCC must be held within 5% of 5 V. The AD6645 is specified for DVCC = 3.3 V, a common supply for digital ASICs. Digital Outputs Care must be taken when designing the data receivers for the AD6645. It is recommended that the digital outputs drive a series resistor followed by a gate, such as the 74LCX574. For optimum performance, it is highly recommended that a common ground be used between the analog and digital power planes. The primary concern with splitting grounds is that dynamic currents may be forced to travel significant distances in the system before recombining back at the common source ground. This can result in a large, undesirable ground loop. The most common place for this to occur is on the digital outputs of the ADC. Ground loops can contribute to digital noise being coupled back onto the ADC front end. This can manifest itself as either harmonic spurs, or very high-order spurious products that can cause excessive spikes on the noise floor. This noise coupling is less likely to occur at lower clock speeds because the digital noise has more time to settle between samples. In general, splitting the analog and digital grounds can frequently contribute to undesirable EMI-RFI and should, therefore, be avoided. Conversely, if not properly implemented, common grounding can actually impose additional noise issues because the digital ground currents ride on top of the analog ground currents in close proximity to the ADC input. To further minimize the potential for noise coupling, it is highly recommended that multiple ground return traces/vias be placed such that the digital output currents do not flow back toward the analog front end but are routed quickly away from the ADC. This does not require a split in the ground plane and can be accomplished by simply placing substantial ground connections directly back to the supply at a point between the analog front end and the digital outputs. In addition, the judicious use of ceramic chip capacitors between the power supply and ground planes helps to suppress digital noise. The layout should incorporate enough bulk capacitance to supply the peak current requirements during switching periods. Rev. D | Page 18 of 24 AD6645 LAYOUT INFORMATION The schematic of the evaluation board (see Figure 43) represents a typical implementation of the AD6645. A multilayer board is recommended to achieve best results. It is highly recommended that high quality, ceramic chip capacitors be used to decouple each supply pin to ground directly at the device. The pinout of the AD6645 facilitates ease of use in the implementation of high frequency, high resolution design practices. All of the digital outputs are segregated to two sides of the chip, with the inputs on the opposite side for isolation purposes. Care should be taken when routing the digital output traces. To prevent coupling through the digital outputs into the analog portion of the AD6645, minimal capacitive loading should be placed on these outputs. It is recommended that a fanout of only one gate should be used for all AD6645 digital outputs. The layout of the encode circuit is equally critical. Any noise received on this circuitry results in corruption in the digitization process and lower overall performance. The encode clock must be isolated from the digital outputs and the analog inputs. Table 8. Twos Complement Output Coding AIN Level AIN Level Output State Output Code VREF + 0.55 V VREF VREF − 0.55 V VREF − 0.55 V VREF VREF + 0.55 V Positive FS Midscale Negative FS 01 1111 1111 1111 00 … 0/11 … 1 10 0000 0000 0000 JITTER CONSIDERATIONS The SNR for an ADC can be predicted. When normalized to ADC codes, the following equation accurately predicts the SNR based on three terms: jitter, average DNL error, and thermal noise. Each of these terms contributes to the noise within the converter. SNR = 1.76 − ( ⎡ 20 log ⎢ 2π × f ANALOG × t j rms ⎣ ) 2 1 + ε 2 ⎛ 2 × 2 × VNOISE rms ⎞⎟ + ⎛⎜ n ⎞⎟ + ⎜ ⎟ 2n ⎝ 2 ⎠ ⎜⎝ ⎠ 2 1/ 2 ⎤ ⎥ ⎥ ⎦ where: fANALOG is the analog input frequency. tj rms is the rms jitter of the encode (rms sum of encode source and internal encode circuitry). ε is the average DNL of the ADC (typically 0.41 LSB). n is the number of bits in the ADC. VNOISE rms is the voltage rms thermal noise that refers to the analog input of the ADC (typically 0.9 LSB rms). For a 14-bit ADC, such as the AD6645, aperture jitter can greatly affect the SNR performance as the analog frequency is increased. Figure 42 shows a family of curves that demonstrate the expected SNR performance of the AD6645 as jitter increases. The chart is derived from the preceding equation. For a complete discussion of aperture jitter, see the AN-756 application note, Sampled Systems and the Effects of Clock Phase Noise and Jitter. The AN-756 application note can be found on www.analog.com. 80 AIN = 30MHz 75 SNR (dBFS) AIN = 70MHz 70 AIN = 110MHz 65 AIN = 150MHz 55 0 0.1 0.2 0.3 JITTER (ps) 0.4 Figure 42. SNR vs. Jitter Rev. D | Page 19 of 24 0.5 0.6 02647-042 AIN = 190MHz 60 AD6645 Table 9. AD6645/PCB Bill of Materials Quantity 80 MSPS 1 Quantity 105 MSPS 1 Reference ID PCB 4 4 C1, C2, C31, C38 8 8 9 9 0 0 C3, C7 to C10, C16, C30 1 , C32 C4, C15, C22 to C26, C29, (C33) 2, 3 , (C34)2, 3, C39 (C5, C6)2, 3 10 10 0 0 C11 to C14, C17 to C21, C40 (C27, C28)2 1 1 CR13 1 1 E1 5 1 1 1 2 5 1 1 1 2 F1 to F5 J1 J1 J2 (J3)2, J4, J5 1 0 1 0 L1 (R1)2, 3 0 0 (R2)2 2 2 2 2 (R3 to R5)1, 2, (R8)1, 2, R9, R10 R6, R7 0 0 (R11)2, 3, (R13)2, 3 0 0 (R12)2, 3, (R14)2, 3 1 1 R151 1 1 R35 4 4 RN1 to RN4 2 2 T23, T31 1 0 2 0 0 1 2 0 U1 U1 U2, U7 (U3)1, 2 2 2 U4, U6 Description Printed circuit board, AD6645 engineering evaluation board Capacitor, tantalum, SMT BCAPTAJC, 10 μF, 16 V, 10% Capacitor, ceramic, SMT 0508, 0.1 μF, 16 V, 10% Capacitor, ceramic, SMT 0805, 0.1 μF, 25 V, 10% Manufacturer PCSM Supplier Part No. 6645EE01D REV D Kemet T491C106K016AS Presidio Components 0508X7R104K16VP3 Panasonic ECJ-2VB1E104K Capacitor, ceramic, SMT 0805, 0.01 μF, 50 V, 10% Capacitor, ceramic, SMT 0508, 0.01 μF, 50 V, 0.2% Capacitor, ceramic, SMT 0805, limits amp bandwidth as warranted Diode, dual Schottky HSMS2812, SOT-23, 30 V, 20 mA Install jumper wire (across OPT_LAT and BUFLAT) EMI suppression ferrite chip, SMT 0805 Header, 6-pin, pin strip, 5 mm pitch Pin strip, 6-pin, 5 mm pitch Header, 40-pin, male, right angle Connector, gold, female, coax., SMA, vertical Inductor, SMT, 1008-ct package, 4.7 nH Resistor, thick film, SMT 0402, 100 Ω, 1/16 W, 1% Resistor, thick film, SMT 1206, 60.4 Ω, 1/4 W, 1% Resistor, thick film, SMT 0805, 500 Ω, 1/8 W, 1% Resistor, thick film, SMT 0805, 25.5 Ω, 1/8 W, 1% Resistor, thick film, SMT 0805, 66.5 Ω, 1/8 W, 1% Resistor, thick film, SMT 0805, 100 Ω, 1/8W, 1% Resistor, thick film, SMT 0402, 178 Ω, 1/16 W, 1% Resistor, thick film, SMT 0805, 49.9 Ω, 1/8 W, 1% Resistor array, SMT 0402; 100 Ω; 8 ISO RES.,1/4 W; 5% Transformer, ADT4-1WT, CD542, 2 MHz to 775 MHz IC, 14-bit, 80 MSPS ADC IC, 14-bit, 105 MSPS ADC IC, SOIC-20, Octal D-type flip-flop IC, SOIC-8, low distortion differential ADC driver IC, SOT-23, tiny logic UHS 2 input OR gate Panasonic ECJ-2YB1H103K Presidio Components 0508X7R103M2P3 Panasonic MA716-(TX) Steward Wieland Wieland Samtec Johnson Components HZ0805E601R-00 Z5.530.0625.0 25.602.2653.0 TSW-120-08-T-D-RA 142-0701-201 Coilcraft Panasonic 1008CT-040X-J ERJ-2RKF1000 Panasonic ERJ-8ENF60R4V Panasonic ERJ-6ENF4990V Panasonic ERJ-6ENF25R5V Panasonic ERJ-6ENF66R5V Panasonic ERJ-6ENF1000V Panasonic ERJ-2RKF1780X Panasonic ERJ-6ENF49R9V Panasonic EXB2HV101JV Mini-Circuits ADT4-1WT Analog Devices Analog Devices Fairchild Analog Devices AD6645ASQ/ASV-80 AD6645ASQ/ASV-105 74LCX574WM AD8138AR Fairchild NC7SZ32 Rev. D | Page 20 of 24 AD6645 Quantity 80 MSPS 0 1 4 4 Quantity 105 MSPS 0 0 4 4 Reference ID (U8)2, 3 Y1 Y1 Description IC, SOIC-8, differential receiver Clock oscillator, 80 MHz Pin sockets, closed end Circuit board support 1 Manufacturer Motorola CTS Reeves AMP/Tyco Electronics Richco, Inc. Supplier Part No. MC100LVEL16 MXO45-80 5-330808-3 CBSB-14-01 AC-coupled AIN is standard: R3, R4, R5, R8, and U3 are not installed. If dc-coupled AIN is required, C30, R15, and T3 are not installed. Reference designators in parentheses are not installed on standard units. 3 AC-coupled encode is standard: C5, C6, C33, C34, R1, R11 to R14, and U8 are not installed. If PECL encode is required, CR1 and T2 are not installed. 2 Rev. D | Page 21 of 24 J5 J3 AIN 49.9 R35 (SEE NOTE 1) DO NOT INSTALL 60.4 R2 DO NOT INSTALL OPT_CLK J4 ENC R1 C3 0.1U C4 C5 0.01U 100 0.1U VCC' VCC OUT L1 4.7NH R10 500 8 10 12 6 5 2 1 R3 4 1 R12 100 R11 66.5 500 500 T3 2 4 5 6 7 NC R5 C28 3 V+ 500 U3 VAL 4 VREF DR_OUT BUFLAT 1 F5 F3 2 +3P3V_XTL 2 5 0.1U C30 E1 R15 178 AIN AIN R14 100 R13 66.5 (SEE NOTE 1) R6 25.5 25.5 R7 ENC ENC C34 0.1U +5VA INSTALL JUMPER C15 0.1U C22 0.1U 2 1 C33 0.1U CR1 OPT_LAT 3 VOCM AD8138ARM V− 6 ADT4-1WT 4:1 IMPEDANCE RATIO 3 1 +5VA 8 1 -5V 500 R4 C27 DC-COUPLED AIN OPTION (SEE NOTE 2) GND 3 U4 5 0.1U C29 5 +V DO NOT INSTALL R8 7 6 +3P3VD 14 NC7SZ32 66.66MHz (AD6644) 80MHz (AD6645) GN D GND' OUT' OE' OE Y1 +3P3V 7 R9 500 5 3 1 T2 OPTIONAL 4 VEE Q Q VCC MC100LVEL16 VBB D D NC ADT4-1WT 4:1 IMPEDANCE RATIO 1 3 4 3 2 8 +5VA +5VA 1 13 12 11 10 9 8 7 6 5 4 3 2 GND AIN AIN GND AVCC AVCC GND ENC ENC GND VREF GND DVCC U1 52 14 51 50 15 16 48 47 46 45 17 AD6644/AD6645 49 18 19 0.1U C8 20 21 44 22 43 23 42 0.1U C7 24 41 25 40 GND AVCC GND AVCC DNC OVR DVCC GND DMID D0 D1 D2 D3 26 27 28 29 30 31 32 33 34 35 36 37 38 39 3. AC-COUPLED ENCODE IS STANDARD. C5, C6, C33, C34, R1, R11−R14 IF PECL ENCODE IS REQUIRED, CR1 AND T2 ARE NOT INSTALLED. 2. AC-COUPLED AIN IS STANDARD, R3, R4, R5, R8 AND U3 ARE NOT INSTALLED. IF DC-COUPLED AIN IS REQUIRED, C30, R15 AND T3 ARE NOT INSTALLED. 1. R2 IS INSTALLED FOR INPUT MATCHING ON THE PRIMARY OF T3. R1 R15 IS INSTALLED FOR INPUT MATCHING ON THE SECONDARY OF T3, R2 NOTES: +3P3V 0.1U C32 VREF D13 1 D12 GN D U8 +5VA D11 GN D +5VA D9 GN D DO NOT INSTALL DC-COUPLED ENCODE OPTION (SEE NOTE 3) D8 C1 +5VA 0 .0 0 .0 D7 GN D +3P3 V D VC C GN D GN D GN D C2 DR _ OU T DR Y AVC C +5V A AVC C +5V A D10 AVC C +5V A D6 AVC C +5V A D5 GN D D4 AVC C Rev. D | Page 22 of 24 +5V A Figure 43. Evaluation Board Schematic 8 7 6 5 4 3 2 1 J1 100 RN3 6 5 4 3 2 1 PREF +3P3V 10 11 12 13 14 15 10 9 8 7 6 5 4 3 2 1 10 9 8 7 6 5 4 3 2 1 -5V +5V AND U8 ARE NOT INSTALLED. 10U C31 +3P3VIN F1 CP O7 O6 O5 O4 O3 O2 O1 O0 VCC CP O7 O6 O5 O4 O3 O2 O1 O0 VCC F2 11 12 13 14 15 16 17 18 19 20 11 12 13 14 15 16 17 18 19 20 +3P3V_XTL +3P3VIN 74LCX574 GND D7 D6 D5 D4 D3 D2 D1 D0 OE U2 74LCX574 GND D7 D6 D5 D4 D3 D2 D1 D0 OE 5 IS NOT INSTALLED. IS NOT INSTALLED. +5VA 10 7 +5VA 11 6 9 12 5 16 13 4 100 14 3 9 15 2 8 16 RN1 1 U7 +3P3VD +3P3VD +3P3V 0.01U C4 0 10U C2 10U C1 9 0.1U C39 0.1U C16 0.1U C9 100 RN4 100 RN2 BUFLAT 8 7 6 5 4 3 2 1 BUFLAT 8 7 6 5 4 3 2 1 BUFLAT 9 5 U6 +V 10 11 12 13 14 15 1 10U C38 2 E2 0.01U C17 0.1U C10 F4 GND 3 16 10 11 12 13 14 15 16 2 1 +3P3VD 0 .0 1 U C18 0.01U C11 0.1U C23 NC7SZ32 4 B00 B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 J2 0.01U C19 0.01U C12 0.1U C24 OVR 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 0.01U C20 +5VA 0.01U C13 0.1U C25 +3P3VD E6 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 37 35 40 39 HEADER40 0 .0 1 U C21 0.01U C14 0.1U C26 02 64 7-04 3 C6 0.01U AD6645 02647-046 02647-044 AD6645 Figure 46. Ground Plane Layer 2 and Ground Plane Layer 5 02647-045 02647-047 Figure 44. Top Signal Level Figure 47. Bottom Signal Layer Figure 45. 5.0 V Plane Layer 3 and 3.3 V Plane Layer 4 Rev. D | Page 23 of 24 AD6645 OUTLINE DIMENSIONS 0.75 0.60 0.45 1.60 MAX 12.20 12.00 SQ 11.80 2.35 2.20 (4 PLCS) 2.05 2.65 2.50 (4 PLCS) 2.35 52 40 1 40 39 52 1 39 PIN 1 (PINS DOWN) 1.45 1.40 1.35 13 10.00 SQ 9.80 26 VIEW A 0.10 MAX COPLANARITY 0.65 BSC LEAD PITCH (PINS UP) 27 27 14 7° 0° SEATING PLANE (CENTERED) BOTTOM VIEW 0.20 0.08 0.15 0.05 6.05 5.90 SQ 5.75 10.20 EXPOSED HEAT SINK TOP VIEW 26 13 14 0.38 0.32 0.22 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. VIEW A 082108-A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BCC-HD Figure 48. 52-Lead Low Profile Quad Flat Package, PowerQuad [LQFP_PQ4] (SQ-52-1) Dimensions shown in millimeters 1.20 MAX 12.00 BSC SQ 52 0.15 0.05 1 PIN 1 10.00 BSC SQ TOP VIEW 0° MIN 39 39 (PINS DOWN) 1.05 1.00 0.95 52 40 40 1 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 MAX COPLANARITY 6.50 BSC SQ EXPOSED PAD BOTTOM VIEW 13 27 14 26 VIEW A (PINS UP) 27 26 0.65 BSC LEAD PITCH 0.38 0.32 0.22 VIEW A ROTATED 90° CCW 13 14 COMPLIANT TO JEDEC STANDARDS MS-026-ACC FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 072408-A 0.75 0.60 0.45 Figure 49. 52-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-52-1) Dimensions shown in millimeters ORDERING GUIDE Model AD6645ASQ-80 AD6645ASQZ-80 1 AD6645ASVZ-801 AD6645ASQ-105 AD6645ASQZ-1051 AD6645ASVZ-1051 AD6645-80/PCBZ1 AD6645-105/PCBZ1 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −10°C to +85°C −10°C to +85°C −10°C to +85°C Package Description 52-Lead Low Profile Quad Flat Package, PowerQuad (LQFP_PQ4) 52-Lead Low Profile Quad Flat Package, PowerQuad (LQFP_PQ4) 52-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] 52-Lead Low Profile Quad Flat Package, PowerQuad (LQFP_PQ4) 52-Lead Low Profile Quad Flat Package, PowerQuad (LQFP_PQ4) 52-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] Evaluation Board Evaluation Board Z = RoHS Compliant Part. ©2002–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02647-0-10/08(D) Rev. D | Page 24 of 24 Package Option SQ-52-1 SQ-52-1 SV-52-1 SQ-52-1 SQ-52-1 SV-52-1