INFINEON SAK-XC161CJ

Da ta S heet, V1.0, Mar. 2002
XC161CJ
1 6 -B it S in g l e -C h i p M i c r o c o n t ro l l e r
Preliminary
M i c r o c o n t ro l le r s
N e v e r
s t o p
t h i n k i n g .
Edition 2002-03
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
© Infineon Technologies AG 2002.
All Rights Reserved.
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The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
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Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
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list).
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Da ta S heet, V1.0, Mar. 2002
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XC161CJ
1 6 -B it S in g l e -C h i p M i c r o c o n t ro l l e r
P
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Preliminary
M i c r o c o n t ro l le r s
N e v e r
s t o p
t h i n k i n g .
XC161
Preliminary
Revision History:
2002-03
Previous Version:
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Page
V1.0
Subjects (major changes since last revision)
Controller Area Network (CAN): License of Robert Bosch GmbH
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Preliminary
16-Bit Single-Chip Microcontroller
XC166 Family
XC161
XC161
1
Summary of Features
• High Performance 16-bit CPU with 5-Stage Pipeline
– 25 ns Instruction Cycle Time at 40 MHz CPU Clock (Single-Cycle Execution)
– 1-Cycle Multiplication (16 × 16 bit), Background Division (32 / 16 bit) in 21 Cycles
– 1-Cycle Multiply-and-Accumulate (MAC) Instructions
– Enhanced Boolean Bit Manipulation Facilities
– Zero-Cycle Jump Execution
– Additional Instructions to Support HLL and Operating Systems
– Register-Based Design with Multiple Variable Register Banks
– Fast Context Switching Support with Two Additional Local Register Banks
– 16 MBytes Total Linear Address Space for Code and Data
– 1024 Bytes On-Chip Special Function Register Area (C166 Family Compatible)
• 16-Priority-Level Interrupt System with 74 Sources, Sample-Rate down to 50 ns
• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via
Peripheral Event Controller (PEC), 24-Bit Pointers Cover Total Address Space
• Clock Generation via on-chip PLL (factors 1:0.15 … 1:10), or
via Prescaler (factors 1:1 … 60:1)
• On-Chip Memory Modules
– 2 KBytes On-Chip Dual-Port RAM (DPRAM)
– 4 KBytes On-Chip Data SRAM (DSRAM)
– 2 KBytes On-Chip Program/Data SRAM (PSRAM)
– 128 KBytes On-Chip Program Memory (Flash Memory)
• On-Chip Peripheral Modules
– 12/16-Channel A/D Converter with Programmable Resolution (10-bit or 8-bit) and
Conversion Time (down to 2.85 µs)
– Two 16-Channel General Purpose Capture/Compare Units (32 Input/Output Pins)
– Multi-Functional General Purpose Timer Unit with 5 Timers
– Two Synchronous/Asynchronous Serial Channels (USARTs)
– Two High-Speed-Synchronous Serial Channels
– On-Chip TwinCAN Interface (Rev. 2.0B active) with 32 Message Objects
(Full CAN/Basic CAN) on Two CAN Nodes, and Gateway Functionality
– Serial Data Link Module (SDLM), compliant with J1850, supporting Class 2
– IIC Bus Interface (10-bit addressing, 400 kbit/s) with 3 Channels (multiplexed)
– On-Chip Real Time Clock, Driven by Dedicated Oscillator
• Idle, Sleep, and Power Down Modes with Flexible Power Management
• Programmable Watchdog Timer and Oscillator Watchdog
Data Sheet
1
V1.0, 2002-03
XC161
Derivatives
Summary of Features
Preliminary
• Up to 16 MBytes External Address Space for Code and Data
– Programmable External Bus Characteristics for Different Address Ranges
– Multiplexed or Demultiplexed External Address/Data Buses
– Selectable Address Bus Width
– 16-Bit or 8-Bit Data Bus Width
– Five Programmable Chip-Select Signals
– Hold- and Hold-Acknowledge Bus Arbitration Support
• Up to 103 General Purpose I/O Lines,
partly with Selectable Input Thresholds and Hysteresis
• On-Chip Bootstrap Loader
• Supported by a Large Range of Development Tools like C-Compilers,
Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers,
Simulators, Logic Analyzer Disassemblers, Programming Boards
• On-Chip Debug Support via JTAG Interface
• 144-Pin TQFP Package, 0.5 mm (19.7 mil) pitch
Ordering Information
The ordering code for Infineon microcontrollers provides an exact reference to the
required product. This ordering code identifies:
• the derivative itself, i.e. its function set, the temperature range, and the supply voltage
• the package and the type of delivery.
For the available ordering codes for the XC161 please refer to the “Product Catalog
Microcontrollers”, which summarizes all available microcontroller variants.
Note: The ordering codes for Mask-ROM versions are defined for each product after
verification of the respective ROM code.
This document describes several derivatives of the XC161 group. Table 1 enumerates
these derivatives and summarizes the differences. As this document refers to all of these
derivatives, some descriptions may not apply to a specific product.
For simplicity all versions are referred to by the term XC161 throughout this document.
Data Sheet
2
V1.0, 2002-03
XC161
Derivatives
Summary of Features
Preliminary
Table 1
Derivative
XC161 Derivative Synopsis
1)
Program
Memory
On-Chip RAM
ADC
Channels
Interfaces
SAK-XC161CJ-16F40F,
SAK-XC161CJ-16F20F
128 KBytes 2 KBytes DPRAM, 12
Flash
2 KBytes DSRAM,
4 KBytes PSRAM
ASC0/1,
SSC0/1,
CAN0/1,
SDLM
SAF-XC161CJ-16F40F,
SAF-XC161CJ-16F20F
128 KBytes 2 KBytes DPRAM, 12
Flash
2 KBytes DSRAM,
4 KBytes PSRAM
ASC0/1,
SSC0/1,
CAN0/1,
SDLM
1)
This Data Sheet is valid for devices starting with and including design step AA.
Data Sheet
3
V1.0, 2002-03
XC161
Derivatives
General Device Information
Preliminary
2
General Device Information
2.1
Introduction
The XC161 derivatives are high-performance members of the Infineon XC166 Family of
full featured single-chip CMOS microcontrollers. These devices extend the functionality
and performance of the C166 Family in terms of instructions (MAC unit), peripherals, and
speed. They combine high CPU performance (up to 40 million instructions per second)
with high peripheral functionality and enhanced IO-capabilities. They also provide clock
generation via PLL and various on-chip memory modules such as program Flash,
program RAM, and data RAM.
VAREF
VDDI/P
VAGND
VSSI/P
XTAL1
XTAL2
PORT0
16 bit
XTAL3
XTAL4
PORT1
16 bit
Port 2
8 bit
NMI
RSTIN
RSTOUT
EA
Port 20
6 bit
XC161
Port 3
15 bit
Port 4
8 bit
READY
ALE
RD
WR/WRL
Port 6
8 bit
Port 7
4 bit
Port 9
6 bit
Port 5
16 bit
TRST JTAG Debug
5 bit
2 bit
Figure 1
Data Sheet
Logic Symbol
4
V1.0, 2002-03
XC161
Derivatives
General Device Information
Preliminary
2.2
Pin Configuration and Definition
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
XC161
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
NC
NC
P0H.1/AD9
P0H.0/AD8
VSSP
VDDP
P0L.7/AD7
P0L.6/AD6
P0L.5/AD5
P0L.4/AD4
P0L.3/AD3
P0L.2/AD2
P0L.1/AD1
P0L.0/AD0
P20.5/EA
P20.4/ALE
P20.2/READY
P20.1/WR/WRL
P20.0/RD
VSSP
VDDP
P4.7/A23/C*)
P4.6/A22/C*)
P4.5/A21/C*)
P4.4/A20/C*)
P4.3/A19
P4.2/A18
P4.1/A17
P4.0/A16
VSSI
VDDI
P3.15/CLKOUT/FO
P3.13/SCLK0/E*)
P3.12/BHE/WRH/
TMS
/E*)
TDO
P5.8/AN8
P5.9/AN9
P5.6/AN6
P5.7/AN7
VAREF
VAGND
P5.12/AN12/T6IN
P5.13/AN13/T5IN
P5.14/AN14T4EUD
P5.15/AN15/T2EUD
VSSI
VDDI
P2.8/CC8IO/EX0IN
P2.9/CC9IO/EX1IN
P2.10/CC10IO/EX2IN
P2.11/CC11IO/EX3IN
P2.12/CC12IO/EX4IN
P2.13/CC13IO/EX5IN
P2.14/CC14IO/EX6IN
P2.15/CC15IO/EX7IN/T7IN
TRST
VDDP
P3.0/T0IN/TxD1/E*)
P3.1/T6OUT/RxD1/E*)
P3.2/CAPIN
P3.3/T3OUT
P3.4/T3EUD
P3.5/T4IN
P3.6/T3IN
P3.7/T2IN
P3.8/MRST0
P3.9/MTSR0
P3.10/TxD0/E*)
P3.11/RxD0/E*)
TCK
TDI
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
NC
NC
P20.12/RSTOUT
NMI
VSSP
VDDP
P6.0/CS0/CC0
P6.1/CS1/CC1
P6.2/CS2/CC2
P6.3/CS3/CC3
P6.4/CS4/CC4
P6.5/HOLD/CC5
P6.6/HLDA/CC6
P6.7/BREQ/CC7
P7.4/CC28IO/C*)
P7.5/CC29IO/C*)
P7.6/CC30IO/C*)
P7.7/CC31IO/C*)
VSSP
VDDP
P9.0/SDA0/CC16io/C*)
P9.1/SCL0/CC17io/C*)
P9.2/SDA1/CC18io/C*)
P9.3/SCL1/CC19io/C*)
P9.4/SDA2/CC20IO
P9.5/SCL2/CC21IO
VSSP
VDDP
P5.0/AN0
P5.1/AN1
P5.2/AN2
P5.3/AN3
P5.4/AN4
P5.5/AN5
P5.10/AN10/T6EUD
P5.11/AN11/T5EUD
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
BRKIN
BRKOUT
RSTIN
XTAL4
XTAL3
VSSI
XTAL1
XTAL2
VSSI
VDDI
P1H.7/A15/CC27IO
P1H.6/A14/CC26IO
P1H.5/A13/CC25IO
P1H.4/A12/CC24IO
P1H.3/A11/SCLK1/E*)
P1H.2/A10/MTSR1
P1H.1/A9/MRST1
P1H.0/A8/CC23IO/E*)
VSSP
VDDP
P1L.7/A7/CC22IO
P1L.6/A6
P1L.5/A5
P1L.4/A4
P1L.3/A3
P1L.2/A2
P1L.1/A1
P1L.0/A0
P0H.7/AD15
P0H.6/AD14
P0H.5/AD13
P0H.4/AD12
P0H.3/AD11
P0H.2/AD10
NC
NC
The pins of the XC161 are described in detail in Table 2, including all their alternate
functions. Figure 2 summarizes all pins in a condensed way, showing their location on
the 4 sides of the package. E*) and C*) mark pins to be used as alternate external
interrupt inputs, C*) marks pins that can have CAN/SDLM interface lines assigned to
them.
Figure 2
Data Sheet
Pin Configuration (top view)
5
V1.0, 2002-03
XC161
Derivatives
General Device Information
Preliminary
Table 2
Pin Definitions and Functions
Symbol Pin
Num.
Input
Outp.
Function
P20.12 3
IO
For details, please refer to the description of P20.
NMI
I
Non-Maskable Interrupt Input. A high to low transition at this
pin causes the CPU to vector to the NMI trap routine. When
the PWRDN (power down) instruction is executed, the NMI
pin must be low in order to force the XC161 into power down
mode. If NMI is high, when PWRDN is executed, the part will
continue to run in normal mode.
If not used, pin NMI should be pulled high externally.
IO
Port 6 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into highimpedance state. Port 6 outputs can be configured as push/
pull or open drain drivers.
The Port 6 pins also serve for alternate functions:
CS0
Chip Select 0 Output,
CC0IO
CAPCOM1: CC0 Capture Inp./Compare Output
Chip Select 1 Output,
CS1
CC1IO
CAPCOM1: CC1 Capture Inp./Compare Output
CS2
Chip Select 2 Output,
CC2IO
CAPCOM1: CC2 Capture Inp./Compare Output
CS3
Chip Select 3 Output,
CC3IO
CAPCOM1: CC3 Capture Inp./Compare Output
Chip Select 4 Output,
CS4
CC4IO
CAPCOM1: CC4 Capture Inp./Compare Output
HOLD
External Master Hold Request Input,
CC5IO
CAPCOM1: CC5 Capture Inp./Compare Output
HLDA
Hold Acknowledge Output (master mode)
or Input (slave mode),
CC6IO
CAPCOM1: CC6 Capture Inp./Compare Output
BREQ
Bus Request Output,
CC7IO
CAPCOM1: CC7 Capture Inp./Compare Output
4
P6
P6.0
7
P6.1
8
P6.2
9
P6.3
10
P6.4
11
P6.5
12
P6.6
13
P6.7
14
Data Sheet
O
IO
O
IO
O
IO
O
IO
O
IO
I
IO
I/O
IO
O
IO
6
V1.0, 2002-03
XC161
Derivatives
General Device Information
Preliminary
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin
Num.
Input
Outp.
Function
P7
IO
Port 7 is a 4-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into highimpedance state. Port 7 outputs can be configured as push/
pull or open drain drivers. The input threshold of Port 7 is
selectable (standard or special). Port 7 pins provide inputs/
outputs for CAPCOM2 and serial interface lines.1)
CC28IO
CAPCOM2: CC28 Capture Inp./Compare Outp.,
CAN2_RxD CAN Node 2 Receive Data Input,
EX7IN
Fast External Interrupt 7 Input (alternate pin B)
CC29IO
CAPCOM2: CC29 Capture Inp./Compare Outp.,
CAN2_TxD CAN Node 2 Transmit Data Output,
EX6IN
Fast External Interrupt 6 Input (alternate pin B)
CC30IO
CAPCOM2: CC30 Capture Inp./Compare Outp.,
CAN1_RxD CAN Node 1 Receive Data Input,
SDL_TxD SDLM Transmit Data Output,
EX7IN
Fast External Interrupt 7 Input (alternate pin A)
CC31IO
CAPCOM2: CC31 Capture Inp./Compare Outp.,
CAN1_TxD CAN Node 1 Transmit Data Output,
SDL_RxD SDLM Receive Data Input,
EX6IN
Fast External Interrupt 6 Input (alternate pin A)
P7.4
15
P7.5
16
P7.6
17
P7.7
18
Data Sheet
I/O
I
I
I/O
O
I
I/O
I
O
I
I/O
O
I
I
7
V1.0, 2002-03
XC161
Derivatives
General Device Information
Preliminary
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin
Num.
Input
Outp.
Function
P9
IO
Port 9 is a 6-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into highimpedance state. Port 9 outputs can be configured as push/
pull or open drain drivers.
The following Port 9 pins also serve for alternate functions:1)
CC16IO
CAPCOM2: CC16 Capture Inp./Compare Outp.,
CAN2_RxD CAN Node 2 Receive Data Input,
SDA0
IIC Bus Data Line 0
CC17IO
CAPCOM2: CC17 Capture Inp./Compare Outp.,
CAN2_TxD CAN Node 2 Transmit Data Output,
SCL0
IIC Bus Clock Line 0
CC18IO
CAPCOM2: CC18 Capture Inp./Compare Outp.,
CAN1_RxD CAN Node 1 Receive Data Input,
SDL_TxD SDLM Transmit Data Output,
SDA1
IIC Bus Data Line 1
CC19IO
CAPCOM2: CC19 Capture Inp./Compare Outp.,
CAN1_TxD CAN Node 1 Transmit Data Output,
SDL_RxD SDLM Receive Data Input,
SCL1
IIC Bus Clock Line 1
CC20IO
CAPCOM2: CC20 Capture Inp./Compare Outp.,
SDA2
IIC Bus Data Line 2
CC21IO
CAPCOM2: CC21 Capture Inp./Compare Outp.,
SCL2
IIC Bus Clock Line 2
P9.0
21
P9.1
22
P9.2
23
P9.3
24
P9.4
25
P9.5
26
Data Sheet
I/O
I
I/O
I/O
O
I/O
I/O
I
O
I/O
I/O
O
I
I/O
I/O
I/O
I/O
I/O
8
V1.0, 2002-03
XC161
Derivatives
General Device Information
Preliminary
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin
Num.
Input
Outp.
Function
P5
I
Port 5 is a 12-bit (or 16-bit, see note) input-only port.
The pins of Port 5 also serve as analog input channels for the
A/D converter, or they serve as timer inputs:
AN0
AN1
AN2
AN3
AN4
AN5
AN10,
T6EUD GPT2 Timer T6 Ext. Up/Down Ctrl. Inp.
AN11,
T5EUD GPT2 Timer T5 Ext. Up/Down Ctrl. Inp.
AN8
AN9
AN6
AN7
AN12,
T6IN
GPT2 Timer T6 Count/Gate Input
AN13,
T5IN
GPT2 Timer T5 Count/Gate Input
AN14,
T4EUD GPT1 Timer T4 Ext. Up/Down Ctrl. Inp.
AN15,
T2EUD GPT1 Timer T2 Ext. Up/Down Ctrl. Inp.
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.10
P5.11
P5.8
P5.9
P5.6
P5.7
P5.12
P5.13
P5.14
P5.15
29
30
31
32
33
34
35
36
37
38
39
40
43
44
45
46
Data Sheet
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Note: Inputs P5.8-11 are not available in all derivatives.
For reasons of compatibility and EMI the respective
pins should then be connected to VSSP.
9
V1.0, 2002-03
XC161
Derivatives
General Device Information
Preliminary
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin
Num.
Input
Outp.
Function
P2
IO
Port 2 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into highimpedance state. Port 2 outputs can be configured as push/
pull or open drain drivers. The input threshold of Port 2 is
selectable (standard or special).
The following Port 2 pins also serve for alternate functions:
CC8IO
CAPCOM1: CC8 Capture Inp./Compare Output,
EX0IN
Fast External Interrupt 0 Input (default pin)
CC9IO
CAPCOM1: CC9 Capture Inp./Compare Output,
EX1IN
Fast External Interrupt 1 Input (default pin)
CC10IO
CAPCOM1: CC10 Capture Inp./Compare Outp.,
EX2IN
Fast External Interrupt 2 Input (default pin)
CC11IO
CAPCOM1: CC11 Capture Inp./Compare Outp.,
EX3IN
Fast External Interrupt 3 Input (default pin)
CC12IO
CAPCOM1: CC12 Capture Inp./Compare Outp.,
EX4IN
Fast External Interrupt 4 Input (default pin)
CC13IO
CAPCOM1: CC13 Capture Inp./Compare Outp.,
EX5IN
Fast External Interrupt 5 Input (default pin)
CC14IO
CAPCOM1: CC14 Capture Inp./Compare Outp.,
EX6IN
Fast External Interrupt 6 Input (default pin)
CC15IO
CAPCOM1: CC15 Capture Inp./Compare Outp.,
EX7IN
Fast External Interrupt 7 Input (default pin),
T7IN
CAPCOM2: Timer T7 Count Input
P2.8
49
P2.9
50
P2.10
51
P2.11
52
P2.12
53
P2.13
54
P2.14
55
P2.15
56
TRST
57
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I
I
Test-System Reset Input. A high level at this pin activates
the XC161’s debug system.
Note: For normal system operation, pin TRST should be
held low.
Data Sheet
10
V1.0, 2002-03
XC161
Derivatives
General Device Information
Preliminary
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin
Num.
Input
Outp.
Function
P3
IO
I
O
I
O
I/O
I
I
O
I
I
I
I
I/O
I/O
O
I
I/O
I
O
O
I
I/O
I
O
O
Port 3 is a 15-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into highimpedance state. Port 3 outputs can be configured as push/
pull or open drain drivers. The input threshold of Port 3 is
selectable (standard or special).
The following Port 3 pins also serve for alternate functions:
T0IN
CAPCOM1 Timer T0 Count Input,
TxD1
ASC1 Clock/Data Output (Async./Sync),
EX1IN
Fast External Interrupt 1 Input (alternate pin B)
T6OUT
GPT2 Timer T6 Toggle Latch Output,
RxD1
ASC1 Data Input (Async.) or Inp./Outp. (Sync.),
EX1IN
Fast External Interrupt 1 Input (alternate pin A)
CAPIN
GPT2 Register CAPREL Capture Input
T3OUT
GPT1 Timer T3 Toggle Latch Output
T3EUD
GPT1 Timer T3 External Up/Down Control Input
T4IN
GPT1 Timer T4 Count/Gate/Reload/Capture Inp
T3IN
GPT1 Timer T3 Count/Gate Input
T2IN
GPT1 Timer T2 Count/Gate/Reload/Capture Inp
MRST0
SSC0 Master-Receive/Slave-Transmit In/Out.
MTSR0
SSC0 Master-Transmit/Slave-Receive Out/In.
TxD0
ASC0 Clock/Data Output (Async./Sync.),
EX2IN
Fast External Interrupt 2 Input (alternate pin B)
RxD0
ASC0 Data Input (Async.) or Inp./Outp. (Sync.),
EX2IN
Fast External Interrupt 2 Input (alternate pin A)
External Memory High Byte Enable Signal,
BHE
WRH
External Memory High Byte Write Strobe,
EX3IN
Fast External Interrupt 3 Input (alternate pin B)
SCLK0
SSC0 Master Clock Output / Slave Clock Input.,
EX3IN
Fast External Interrupt 3 Input (alternate pin A)
CLKOUT Master Clock Output,
FOUT
Programmable Frequency Output
P3.0
59
P3.1
60
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3.8
P3.9
P3.10
61
62
63
64
65
66
67
68
69
P3.11
70
P3.12
75
P3.13
76
P3.15
77
TCK
71
I
Debug System: JTAG Clock Input
TDI
72
I
Debug System: JTAG Data In
TDO
73
O
Debug System: JTAG Data Out
TMS
74
I
Debug System: JTAG Test Mode Selection
Data Sheet
11
V1.0, 2002-03
XC161
Derivatives
General Device Information
Preliminary
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin
Num.
Input
Outp.
Function
P4
IO
Port 4 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into highimpedance state. The Port 4 outputs can be configured as
push/pull or open drain drivers. The input threshold of Port 4
is selectable (standard or special).
Port 4 can be used to output the segment address lines, the
optional chip select lines, and for serial interface lines:1)
A16
Least Significant Segment Address Line
A17
Segment Address Line
A18
Segment Address Line
A19
Segment Address Line
A20
Segment Address Line,
CAN2_RxD CAN Node 2 Receive Data Input,
SDL_RxD SDLM Receive Data Input,
EX5IN
Fast External Interrupt 5 Input (alternate pin B)
A21
Segment Address Line,
CAN1_RxD CAN Node 1 Receive Data Input,
EX4IN
Fast External Interrupt 4 Input (alternate pin B)
A22
Segment Address Line,
CAN1_TxD CAN Node 1 Transmit Data Output,
SDL_RxD SDLM Receive Data Input,
EX5IN
Fast External Interrupt 5 Input (alternate pin A)
A23
Most Significant Segment Address Line,
CAN1_RxD CAN Node 1 Receive Data Input,
CAN2_TxD CAN Node 2 Transmit Data Output,
SDL_TxD SDLM Transmit Data Output,
EX4IN
Fast External Interrupt 4 Input (alternate pin A)
P4.0
P4.1
P4.2
P4.3
P4.4
80
81
82
83
84
P4.5
85
P4.6
86
P4.7
87
Data Sheet
O
O
O
O
O
I
I
I
O
I
I
O
O
I
I
O
I
O
I
I
12
V1.0, 2002-03
XC161
Derivatives
General Device Information
Preliminary
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin
Num.
Input
Outp.
Function
P20
IO
Port 20 is a 6-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into highimpedance state.
The following Port 20 pins also serve for alternate functions:
RD
External Memory Read Strobe, activated for
every external instruction or data read access.
WR/WRL External Memory Write Strobe.
In WR-mode this pin is activated for every
external data write access.
In WRL-mode this pin is activated for low byte
data write accesses on a 16-bit bus, and for
every data write access on an 8-bit bus.
READY
READY Input. When the READY function is
enabled, memory cycle time waitstates can be
forced via this pin during an external access.
ALE
Address Latch Enable Output.
Can be used for latching the address into
external memory or an address latch in the
multiplexed bus modes.
External Access Enable pin.
EA
A low level at this pin during and after Reset
forces the XC161 to latch the configuration from
PORT0 and pin RD, and to begin instruction
execution out of external memory.
A high level forces the XC161 to latch the
configuration from pins RD, ALE, and WR, and
to begin instruction execution out of the internal
program memory. "ROMless" versions must
have this pin tied to ‘0’.
RSTOUT Internal Reset Indication Output.
Is activated asynchronously with an external
hardware reset. It may also be activated
(selectable) synchronously with an internal
software or watchdog reset.
Is deactivated upon the execution of the EINIT
instruction, optionally at the end of reset, or at
any time (before EINIT) via user software.
P20.0
90
O
P20.1
91
O
P20.2
92
I
P20.4
93
O
P20.5
94
I
P20.12 3
O
Note: Port 20 pins may input configuration values (see EA).
Data Sheet
13
V1.0, 2002-03
XC161
Derivatives
General Device Information
Preliminary
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin
Num.
Input
Outp.
Function
PORT0
IO
PORT0 consists of the two 8-bit bidirectional I/O ports P0L
and P0H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state.
In case of an external bus configuration, PORT0 serves as
the address (A) and address/data (AD) bus in multiplexed
bus modes and as the data (D) bus in demultiplexed bus
modes.
Demultiplexed bus modes:
Data Path Width:
8-bit
16-bit
P0L.0 – P0L.7:
D0 – D7
D0 - D7
P0H.0 – P0H.7:
I/O
D8 - D15
Multiplexed bus modes:
Data Path Width:
8-bit
16-bit
P0L.0 – P0L.7:
AD0 – AD7 AD0 - AD7
P0H.0 – P0H.7:
A8 - A15
AD8 - AD15
P0L.0-7 95 102
P0H.0-1 105 106
P0H.2-7 111 116
Note: At the end of an external reset (EA = ’0’) PORT0 also
may input configuration values.
PORT1
IO
P1L.0-6 117 123
P1L.7
124
P1H.0 127
O
PORT1 consists of the two 8-bit bidirectional I/O ports P1L
and P1H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state. PORT1 is used as the 16bit address bus (A) in demultiplexed bus modes (also after
switching from a demultiplexed to a multiplexed bus mode).
The following PORT1 pins also serve for alt. functions:
(A0-6)
Address output only
I/O
I/O
O
O
I/O
I/O
I
I/O
I/O
I/O
I/O
CC22IO
CC23IO
EX0IN
MRST1
MTSR1
SCLK1
EX0IN
CC24IO
CC25IO
CC26IO
CC27IO
P1H.1
P1H.2
P1H.3
128
129
130
P1H.4
P1H.5
P1H.6
P1H.7
131
132
133
134
Data Sheet
CAPCOM2: CC22 Capture Inp./Compare Outp.
CAPCOM2: CC23 Capture Inp./Compare Outp.,
Fast External Interrupt 0 Input (alternate pin B)
SSC1 Master-Receive/Slave-Transmit In/Outp.
SSC1 Master-Transmit/Slave-Receive Out/Inp.
SSC1 Master Clock Output / Slave Clock Input,
Fast External Interrupt 0 Input (alternate pin A)
CAPCOM2: CC24 Capture Inp./Compare Outp.
CAPCOM2: CC25 Capture Inp./Compare Outp.
CAPCOM2: CC26 Capture Inp./Compare Outp.
CAPCOM2: CC27 Capture Inp./Compare Outp.
14
V1.0, 2002-03
XC161
Derivatives
General Device Information
Preliminary
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin
Num.
Input
Outp.
Function
XTAL2
XTAL1
137
138
O
I
XTAL2:
XTAL1:
XTAL3
XTAL4
140
141
I
O
XTAL3:
XTAL4:
RSTIN
142
I
Reset Input with Schmitt-Trigger characteristics. A low level
at this pin while the oscillator is running resets the XC161. An
internal pullup resistor permits power-on reset using only a
capacitor connected to VSS.
A spike filter suppresses input pulses <10 ns. Input pulses
>100 ns safely pass the filter. The minimum duration for a
safe recognition should be 100 ns + 2 CPU clock cycles.
Output of the main oscillator amplifier circuit
Input to the main oscillator amplifier and input
to the internal clock generator
To clock the device from an external source, drive XTAL1,
while leaving XTAL2 unconnected. Minimum and maximum
high/low and rise/fall times specified in the AC
Characteristics must be observed.
Input to the auxiliary (32-kHz) oscillator amplifier
Output of the auxiliary (32-kHz) oscillator
amplifier circuit
To clock the device from an external source, drive XTAL3,
while leaving XTAL4 unconnected. Minimum and maximum
high/low and rise/fall times specified in the AC
Characteristics must be observed.
Note: To let the reset configuration of PORT0 settle and to
let the PLL lock a reset duration of ca. 1 ms is
recommended.
BRK
OUT
143
O
Debug System: Break Out
BRKIN
144
I
Debug System: Break In
NC
1, 2,
107 110
-
No connection.
It is recommended not to connect these pins to the PCB.
VAREF
VAGND
VDDI
41
-
Reference voltage for the A/D converter.
42
-
Reference ground for the A/D converter.
48, 78, 135
Data Sheet
Digital Core Supply Voltage (On-Chip Modules):
+2.5 V during normal operation and idle mode.
Please refer to the Operating Conditions
15
V1.0, 2002-03
XC161
Derivatives
General Device Information
Preliminary
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin
Num.
Input
Outp.
Function
VDDP
6, 20, 28, 58,
88,
103,
125
Digital Pad Supply Voltage (Pin Output Drivers):
+5 V during normal operation and idle mode.
Please refer to the Operating Conditions
VSSI
47, 79, 136,
139
VSSP
5, 19, 27, 89,
104,
126
Digital Ground.
Connect decoupling capacitors to adjacent VDD/VSS pin
pairs as close as possible to the pins.
All VSS pins must be connected to the ground-line or groundplane.
1)
The CAN/SDLM interface lines are assigned to ports P4, P7, and P9 under software control.
Data Sheet
16
V1.0, 2002-03
XC161
Derivatives
Functional Description
Preliminary
3
Functional Description
The architecture of the XC161 combines advantages of RISC, CISC, and DSP
processors with an advanced peripheral subsystem in a very well-balanced way. In
addition, the on-chip memory blocks allow the design of compact systems-on-silicon with
maximum performance (computing, control, communication).
The on-chip memory blocks (program code-memory and SRAM, dual-port RAM, data
SRAM) and the set of generic peripherals are connected to the CPU via separate buses.
Another bus, the LXBus, connects additional on-chip resoures as well as external
resources (see Figure 3).
This bus structure enhances the overall system performance by enabling the concurrent
operation of several subsystems of the XC161.
The following block diagram gives an overview of the different on-chip components and
of the advanced, high bandwidth internal bus structure of the XC161.
PSRAM
DPRAM
DSRAM
ProgMem
Flash
128 KBytes
DMU
PMU
EBC
CPU
XBUS Control
External Bus
Control
C166SV2-Core
OCDS
Debug Support
XTAL
Osc / PLL
RTC
WDT
Interrupt & PEC
Clock Generation
Interrupt Bus
Peripheral Data Bus
ADC
GPT ASC0 ASC1 SSC0 SSC1 CC1
8/10-Bit
12/16
Channels
(USART) (USART)
T2
(SPI)
(SPI)
T3
CC2
T0
T7
T1
T8
IIC
SDLM
Twin
CAN
T4
A B
T5
T6
BRGen
P 20 Port 9 P 7
6
6
4
Port 6
BRGen
Port 5
8
16
BRGen
BRGen
BRGen
Port 4
Port 3
Port 2
PORT1
PORT0
8
15
8
16
16
MCB04323_x1.vsd
Figure 3
Data Sheet
Block Diagram
17
V1.0, 2002-03
XC161
Derivatives
Functional Description
Preliminary
3.1
Memory Subsystem and Organization
The memory space of the XC161 is configured in a Von Neumann architecture, which
means that all internal and external resources, such as code memory, data memory,
registers and I/O ports, are organized within the same linear address space. This
common memory space includes 16 MBytes and is arranged as 256 segments of
64 KBytes each, where each segment consists of four data pages of 16 KBytes each.
The entire memory space can be accessed bytewise or wordwise. Portions of the onchip DPRAM and the register spaces (E/SFR) have additionally been made directly
bitaddressable.
The internal data memory areas and the Special Function Register areas (SFR and
ESFR) are mapped into segment 0, the system segment.
The Program Management Unit (PMU) handles all code fetches and, therefore, controls
accesses to the program memories, such as Flash memory and PSRAM.
The Data Management Unit (DMU) handles all data transfers and, therefore, controls
accesses to the DSRAM and the on-chip peripherals.
Both units (PMU and DMU) are connected via the high-speed system bus to exchange
data. This is required if operands are read from program memory, code or data is written
to the PSRAM, code is fetched from external memory, or data is read from or written to
external resources, including peripherals on the LXbus (such as TwinCAN). The system
bus allows concurrent two-way communication for maximum transfer performance.
128 KBytes of on-chip Flash memory store code or constant data. The on-chip Flash
memory is organized as four 8-KByte sectors, one 32-KByte sector, and one 64-KByte
sector. Each sector can be separately write protected1), erased and programmed (in
blocks of 128 Bytes). The complete Flash area can be read-protected. A password
sequence temporarily unlocks protected areas. The Flash module combines very fast
64-bit one-cycle read accesses with protected and efficient writing algorithms for
programming and erasing. Thus, program execution out of the internal Flash results in
maximum performance. Dynamic error correction provides extremely high read data
security for all read accesses.
Programming typically takes 2 ms per 128-byte block (5 ms max.), erasing a sector
typically takes 200 ms (500 ms max.).
2 KBytes of on-chip Program SRAM (PSRAM) are provided to store user code or data.
The PSRAM is accessed via the PMU and is therefore optimized for code fetches.
4 KBytes of on-chip Data SRAM (DSRAM) are provided as a storage for general user
data.The DSRAM is accessed via the DMU and is therefore optimized for data accesses.
2 KBytes of on-chip Dual-Port RAM (DPRAM) are provided as a storage for user
defined variables, for the system stack, general purpose register banks. A register bank
can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, …, RL7, RH7)
1)
Each two 8-KByte sectors are combined for write-protection purposes.
Data Sheet
18
V1.0, 2002-03
XC161
Derivatives
Functional Description
Preliminary
so-called General Purpose Registers (GPRs).
The upper 256 bytes of the DPRAM are directly bitaddressable. When used by a GPR,
any location in the DPRAM is bitaddressable.
1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function
Register areas (SFR space and ESFR space). SFRs are wordwide registers which are
used for controlling and monitoring functions of the different on-chip units. Unused SFR
addresses are reserved for future members of the XC166 Family. Therefore, they should
either not be accessed, or written with zeros, to ensure upward compatibility.
In order to meet the needs of designs where more memory is required than is provided
on chip, up to 12 MBytes (approximately, see Table 3) of external RAM and/or ROM can
be connected to the microcontroller. The External Bus Interface also provides access to
external peripherals.
Table 3
XC161 Memory Map1)
Address Area
Start Loc.
End Loc.
Area Size2)
Flash register space
FF’F000H
FF’FFFFH
4 KBytes
Reserved (Acc. trap)
F8’0000H
FF’EFFFH
< 1 MByte
Minus Flash regs
Reserved for PSRAM
E0’0800H
F7’FFFFH
<1.5 MBytes
Minus PSRAM
Program SRAM
E0’0000H
E0’07FFH
2 KBytes
Reserved for pr. mem.
C2’0000H
DF’FFFFH
< 2 MBytes
Program Flash
C0’0000H
C1’FFFFH
128 KBytes
Reserved
BF’0000H
BF’FFFFH
64 KBytes
40’0000H
BE’FFFFH
< 8 MBytes
Minus res. seg.
20’0800H
3F’FFFFH
< 2 MBytes
Minus TwinCAN
TwinCAN registers
20’0000H
20’07FFH
2 KBytes
External memory area
01’0000H
1F’FFFFH
< 2 MBytes
Data RAMs and SFRs
00’8000H
00’FFFFH
32 KBytes
External memory area
00’0000H
00’7FFFH
32 KBytes
External memory area
External IO area
4)
Notes
3)
Maximum
Minus Flash
Minus segment 0
Partly used
1)
Accesses to the shaded areas generate external bus accesses.
2)
The areas marked with “<“ are slightly smaller than indicated, see column “Notes”.
3)
Not defined register locations return a trap code.
4)
Several pipeline optimizations are not active within the external IO area. This is necessary to control external
peripherals properly.
Data Sheet
19
V1.0, 2002-03
XC161
Derivatives
Functional Description
Preliminary
3.2
External Bus Controller
All of the external memory accesses are performed by a particular on-chip External Bus
Controller (EBC). It can be programmed either to Single Chip Mode when no external
memory is required, or to one of four different external memory access modes1), which
are as follows:
–
–
–
–
16 … 24-bit Addresses, 16-bit Data, Demultiplexed
16 … 24-bit Addresses, 16-bit Data, Multiplexed
16 … 24-bit Addresses, 8-bit Data, Multiplexed
16 … 24-bit Addresses, 8-bit Data, Demultiplexed
In the demultiplexed bus modes, addresses are output on PORT1 and data is input/
output on PORT0 or P0L, respectively. In the multiplexed bus modes both addresses
and data use PORT0 for input/output. The high order address (segment) lines use
Port 4. The number of active segment address lines is selectable, restricting the external
address space to 8 MBytes … 64 KBytes. This is required when interface lines are
assigned to Port 4.
Up to 5 external CS signals (4 windows plus default) can be generated in order to save
external glue logic. External modules can directly be connected to the common address/
data bus and their individual select lines.
Access to very slow memories or modules with varying access times is supported via a
particular ‘Ready’ function. The active level of the control input signal is selectable.
A HOLD/HLDA protocol is available for bus arbitration and allows the sharing of external
resources with other bus masters. The bus arbitration is enabled by software. After
enabling, pins P6.7 … P6.5 (BREQ, HLDA, HOLD) are automatically controlled by the
EBC. In Master Mode (default after reset) the HLDA pin is an output. In Slave Mode pin
HLDA is switched to input. This allows the direct connection of the slave controller to
another master controller without glue logic.
Important timing characteristics of the external bus interface have been made
programmable (via registers TCONCSx/FCONCSx) to allow the user the adaption of a
wide range of different types of memories and external peripherals.
In addition, up to 4 independent address windows may be defined (via registers
ADDRSELx) which control the access to different resources with different bus
characteristics. These address windows are arranged hierarchically where window 4
overrides window 3, and window 2 overrides window 1. All accesses to locations not
covered by these 4 address windows are controlled by TCONCS0/FCONCS0. The
currently active window can generate a chip select signal.
The external bus timing is related to the rising edge of the reference clock output
CLKOUT. The external bus protocol is compatible with that of the standard C166 Family.
1)
Bus modes are switched dynamically if several address windows with different mode settings are used.
Data Sheet
20
V1.0, 2002-03
XC161
Derivatives
Functional Description
Preliminary
The EBC also controls accesses to resources connected to the on-chip LXBus. The
LXBus is an internal representation of the external bus and allows accessing integrated
peripherals and modules in the same way as external components.
The TwinCAN module is connected and accessed via the LXBus.
3.3
Central Processing Unit (CPU)
The main core of the CPU consists of a 5-stage execution pipeline with a 2-stage
instruction-fetch pipeline, a 16-bit arithmetic and logic unit (ALU), a 32-bit/40-bit multiply
and accumulate unit (MAC), a register-file providing three register banks, and dedicated
SFRs. The ALU features a multiply and divide unit, a bit-mask generator, and a barrel
shifter.
System-Bus
data in
Internal Program Memory
data out
address
PMU
CPU
Prefetch Unit
Branch Unit
DPRAM
CSP
IP
FIFO
Return Stack
IDX0
IDX1
QX0
QX1
QR0
QR1
+/-
+/-
Multiply Unit
VECSEG
CPUCON1
CPUCON2
CPUID
MRW
+/-
MCW
MSW
MAH
MAL
5-Stage
Pipeline
Injection/Exception
Handler
IFU
DPP0
DPP1
DPP2
DPP3
CP
address
R15
R15
R14 R15
R14
R14
GPRs
GPRs
GPRs
ADU
Division Unit
Bit-Mask-Gen.
Multiply Unit
Barrel-Shifter
PSW
+/-
MDH
Zeros
MDL
Ones
R15
R14
GPRs
R1
R1
R0 R1
R0
R0
MDC
R1
R0
RF
data in
Buffer
ALU
WB
data out
data in
address
data out
address
data out
data in
DMU
Peripheral-Bus
Figure 4
IPIP
SPSEG
SP
STKOV
STKUN
MAC
SRAM
2-Stage
Prefetch
Pipeline
TFR
System-Bus
CPU Block Diagram
Based on these hardware provisions, most of the XC161’s instructions can be executed
in just one machine cycle which requires 25 ns at 40 MHz CPU clock. For example, shift
and rotate instructions are always processed during one machine cycle independent of
Data Sheet
21
V1.0, 2002-03
XC161
Derivatives
Functional Description
Preliminary
the number of bits to be shifted. Also multiplication and most MAC instructions execute
in one single cycle. All multiple-cycle instructions have been optimized so that they can
be executed very fast as well: for example, a 32-/16-bit division is started within 4 cycles,
while the remaining 15 cycles are executed in the background. Another pipeline
optimization, the branch target prediction, allows eliminating the execution time of
branch instructions if the prediction was correct.
The CPU has a register context consisting of up to three register banks with 16 wordwide
GPRs each at its disposal. One of these register banks is physically allocated within the
on-chip DPRAM area. A Context Pointer (CP) register determines the base address of
the active register bank to be accessed by the CPU at any time. The number of register
banks is only restricted by the available internal RAM space. For easy parameter
passing, a register bank may overlap others.
A system stack of up to 32 Kwords is provided as a storage for temporary data. The
system stack can be allocated to any location within the address space (preferably in the
on-chip RAM area), and it is accessed by the CPU via the stack pointer (SP) register.
Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack
pointer value upon each stack access for the detection of a stack overflow or underflow.
The high performance offered by the hardware implementation of the CPU can efficiently
be utilized by a programmer via the highly efficient XC161 instruction set which includes
the following instruction classes:
–
–
–
–
–
–
–
–
–
–
–
–
–
Standard Arithmetic Instructions
DSP-Oriented Arithmetic Instructions
Logical Instructions
Boolean Bit Manipulation Instructions
Compare and Loop Control Instructions
Shift and Rotate Instructions
Prioritize Instruction
Data Movement Instructions
System Stack Instructions
Jump and Call Instructions
Return Instructions
System Control Instructions
Miscellaneous Instructions
The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes
and words. A variety of direct, indirect or immediate addressing modes are provided to
specify the required operands.
Data Sheet
22
V1.0, 2002-03
XC161
Derivatives
Functional Description
Preliminary
3.4
Interrupt System
With an interrupt response time of typically 8 CPU clocks (in case of internal program
execution), the XC161 is capable of reacting very fast to the occurrence of nondeterministic events.
The architecture of the XC161 supports several mechanisms for fast and flexible
response to service requests that can be generated from various sources internal or
external to the microcontroller. Any of these interrupt requests can be programmed to
being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).
In contrast to a standard interrupt service where the current program execution is
suspended and a branch to the interrupt vector table is performed, just one cycle is
‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies a
single byte or word data transfer between any two memory locations with an additional
increment of either the PEC source, or the destination pointer, or both. An individual PEC
transfer counter is implicitly decremented for each PEC service except when performing
in the continuous transfer mode. When this counter reaches zero, a standard interrupt is
performed to the corresponding source related vector location. PEC services are very
well suited, for example, for supporting the transmission or reception of blocks of data.
The XC161 has 8 PEC channels each of which offers such fast interrupt-driven data
transfer capabilities.
A separate control register which contains an interrupt request flag, an interrupt enable
flag and an interrupt priority bitfield exists for each of the possible interrupt nodes. Via its
related register, each node can be programmed to one of sixteen interrupt priority levels.
Once having been accepted by the CPU, an interrupt service can only be interrupted by
a higher prioritized service request. For the standard interrupt processing, each of the
possible interrupt nodes has a dedicated vector location.
Fast external interrupt inputs are provided to service external interrupts with high
precision requirements. These fast interrupt inputs feature programmable edge
detection (rising edge, falling edge, or both edges).
Software interrupts are supported by means of the ‘TRAP’ instruction in combination with
an individual trap (interrupt) number.
Table 4 shows all of the possible XC161 interrupt sources and the corresponding
hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers.
Note: Interrupt nodes which are not assigned to peripherals (unassigned nodes), may
be used to generate software controlled interrupt requests by setting the
respective interrupt request bit (xIR).
Data Sheet
23
V1.0, 2002-03
XC161
Derivatives
Functional Description
Preliminary
Table 4
XC161 Interrupt Nodes
Source of Interrupt or PEC
Service Request
Control
Register
Vector
Location1)
Trap
Number
CAPCOM Register 0
CC1_CC0IC
xx’0040H
10H / 16D
CAPCOM Register 1
CC1_CC1IC
xx’0044H
11H / 17D
CAPCOM Register 2
CC1_CC2IC
xx’0048H
12H / 18D
CAPCOM Register 3
CC1_CC3IC
xx’004CH
13H / 19D
CAPCOM Register 4
CC1_CC4IC
xx’0050H
14H / 20D
CAPCOM Register 5
CC1_CC5IC
xx’0054H
15H / 21D
CAPCOM Register 6
CC1_CC6IC
xx’0058H
16H / 22D
CAPCOM Register 7
CC1_CC7IC
xx’005CH
17H / 23D
CAPCOM Register 8
CC1_CC8IC
xx’0060H
18H / 24D
CAPCOM Register 9
CC1_CC9IC
xx’0064H
19H / 25D
CAPCOM Register 10
CC1_CC10IC
xx’0068H
1AH / 26D
CAPCOM Register 11
CC1_CC11IC
xx’006CH
1BH / 27D
CAPCOM Register 12
CC1_CC12IC
xx’0070H
1CH / 28D
CAPCOM Register 13
CC1_CC13IC
xx’0074H
1DH / 29D
CAPCOM Register 14
CC1_CC14IC
xx’0078H
1EH / 30D
CAPCOM Register 15
CC1_CC15IC
xx’007CH
1FH / 31D
CAPCOM Register 16
CC2_CC16IC
xx’00C0H
30H / 48D
CAPCOM Register 17
CC2_CC17IC
xx’00C4H
31H / 49D
CAPCOM Register 18
CC2_CC18IC
xx’00C8H
32H / 50D
CAPCOM Register 19
CC2_CC19IC
xx’00CCH
33H / 51D
CAPCOM Register 20
CC2_CC20IC
xx’00D0H
34H / 52D
CAPCOM Register 21
CC2_CC21IC
xx’00D4H
35H / 53D
CAPCOM Register 22
CC2_CC22IC
xx’00D8H
36H / 54D
CAPCOM Register 23
CC2_CC23IC
xx’00DCH
37H / 55D
CAPCOM Register 24
CC2_CC24IC
xx’00E0H
38H / 56D
CAPCOM Register 25
CC2_CC25IC
xx’00E4H
39H / 57D
CAPCOM Register 26
CC2_CC26IC
xx’00E8H
3AH / 58D
CAPCOM Register 27
CC2_CC27IC
xx’00ECH
3BH / 59D
CAPCOM Register 28
CC2_CC28IC
xx’00E0H
3CH / 60D
CAPCOM Register 29
CC2_CC29IC
xx’0110H
44H / 68D
Data Sheet
24
V1.0, 2002-03
XC161
Derivatives
Functional Description
Preliminary
Table 4
XC161 Interrupt Nodes (cont’d)
Source of Interrupt or PEC
Service Request
Control
Register
Vector
Location1)
Trap
Number
CAPCOM Register 30
CC2_CC30IC
xx’0114H
45H / 69D
CAPCOM Register 31
CC2_CC31IC
xx’0118H
46H / 70D
CAPCOM Timer 0
CC1_T0IC
xx’0080H
20H / 32D
CAPCOM Timer 1
CC1_T1IC
xx’0084H
21H / 33D
CAPCOM Timer 7
CC2_T7IC
xx’00F4H
3DH / 61D
CAPCOM Timer 8
CC2_T8IC
xx’00F8H
3EH / 62D
GPT1 Timer 2
GPT12E_T2IC
xx’0088H
22H / 34D
GPT1 Timer 3
GPT12E_T3IC
xx’008CH
23H / 35D
GPT1 Timer 4
GPT12E_T4IC
xx’0090H
24H / 36D
GPT2 Timer 5
GPT12E_T5IC
xx’0094H
25H / 37D
GPT2 Timer 6
GPT12E_T6IC
xx’0098H
26H / 38D
GPT2 CAPREL Reg.
GPT12E_CRIC
xx’009CH
27H / 39D
A/D Conversion Compl.
ADC_CIC
xx’00A0H
28H / 40D
A/D Overrun Error
ADC_EIC
xx’00A4H
29H / 41D
ASC0 Transmit
ASC0_TIC
xx’00A8H
2AH / 42D
ASC0 Transmit Buffer
ASC0_TBIC
xx’011CH
47H / 71D
ASC0 Receive
ASC0_RIC
xx’00ACH
2BH / 43D
ASC0 Error
ASC0_EIC
xx’00B0H
2CH / 44D
ASC0 Autobaud
ASC0_ABIC
xx’017CH
5FH / 95D
SSC0 Transmit
SSC0_TIC
xx’00B4H
2DH / 45D
SSC0 Receive
SSC0_RIC
xx’00B8H
2EH / 46D
SSC0 Error
SSC0_EIC
xx’00BCH
2FH / 47D
IIC Data Transfer Event
IIC_DTIC
xx’0100H
40H / 64D
IIC Protocol Event
IIC_PEIC
xx’0104H
41H / 65D
PLL/OWD
PLLIC
xx’010CH
43H / 67D
ASC1 Transmit
ASC1_TIC
xx’0120H
48H / 72D
ASC1 Transmit Buffer
ASC1_TBIC
xx’0178H
5EH / 94D
ASC1 Receive
ASC1_RIC
xx’0124H
49H / 73D
ASC1 Error
ASC1_EIC
xx’0128H
4AH / 74D
ASC1 Autobaud
ASC1_ABIC
xx’0108H
42H / 66D
Data Sheet
25
V1.0, 2002-03
XC161
Derivatives
Functional Description
Preliminary
Table 4
XC161 Interrupt Nodes (cont’d)
Source of Interrupt or PEC
Service Request
Control
Register
Vector
Location1)
Trap
Number
SDLM
SDLM_IC
xx’012CH
4BH / 75D
End of PEC Subch.
EOPIC
xx’0130H
4CH / 76D
SSC1 Transmit
SSC1_TIC
xx’0144H
51H / 81D
SSC1 Receive
SSC1_RIC
xx’0148H
52H / 82D
SSC1 Error
SSC1_EIC
xx’014CH
53H / 83D
CAN0
CAN_0IC
xx’0150H
54H / 84D
CAN1
CAN_1IC
xx’0154H
55H / 85D
CAN2
CAN_2IC
xx’0158H
56H / 86D
CAN3
CAN_3IC
xx’015CH
57H / 87D
CAN4
CAN_4IC
xx’0164H
59H / 89D
CAN5
CAN_5IC
xx’0168H
5AH / 90D
CAN6
CAN_6IC
xx’016CH
5BH / 91D
CAN7
CAN_7IC
xx’0170H
5CH / 92D
RTC
RTC_IC
xx’0174H
5DH / 93D
Unassigned node
---
xx’0134H
4DH / 77D
Unassigned node
---
xx’0138H
4EH / 78D
Unassigned node
---
xx’013CH
4FH / 79D
Unassigned node
---
xx’0140H
50H / 80D
Unassigned node
---
xx’00FCH
3FH / 63D
Unassigned node
---
xx’0160H
58H / 88D
1)
Register VECSEG defines the segment where the vector table is located to.
Bitfield VECSC in register CPUCON1 defines the distance between two adjacent vectors. This table
represents the default setting, with a distance of 4 (two words) between two vectors.
Data Sheet
26
V1.0, 2002-03
XC161
Derivatives
Functional Description
Preliminary
The XC161 also provides an excellent mechanism to identify and to process exceptions
or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware
traps cause immediate non-maskable system reaction which is similar to a standard
interrupt service (branching to a dedicated vector table location). The occurence of a
hardware trap is additionally signified by an individual bit in the trap flag register (TFR).
Except when another higher prioritized trap service is in progress, a hardware trap will
interrupt any actual program execution. In turn, hardware trap services can normally not
be interrupted by standard or PEC interrupts.
Table 5 shows all of the possible exceptions or error conditions that can arise during runtime:
Table 5
Hardware Trap Summary
Trap
Vector
Vector
Location1)
Trap
Trap
Number Priority
RESET
RESET
RESET
xx’0000H
xx’0000H
xx’0000H
00H
00H
00H
III
III
III
NMI
STKOF
STKUF
SOFTBRK
NMITRAP
STOTRAP
STUTRAP
SBRKTRAP
xx’0008H
xx’0010H
xx’0018H
xx’0020H
02H
04H
06H
08H
II
II
II
II
UNDOPC
PACER
PRTFLT
BTRAP
BTRAP
BTRAP
xx’0028H
xx’0028H
xx’0028H
0AH
0AH
0AH
I
I
I
ILLOPA
BTRAP
xx’0028H
0AH
I
Reserved
–
–
[2CH –
3CH]
[0BH –
0FH]
–
Software Traps
– TRAP Instruction
–
–
Any
Any
[xx’0000H – [00H –
xx’01FCH] 7FH]
in steps
of 4H
Exception Condition
Trap
Flag
Reset Functions:
– Hardware Reset
– Software Reset
– W-dog Timer Overflow
–
Class A Hardware Traps:
– Non-Maskable Interrupt
– Stack Overflow
– Stack Underflow
– Software Break
Class B Hardware Traps:
– Undefined Opcode
– PMI Access Error
– Protected Instruction
Fault
– Illegal Word Operand
Access
1)
Current
CPU
Priority
Register VECSEG defines the segment where the vector table is located to.
Data Sheet
27
V1.0, 2002-03
XC161
Derivatives
Functional Description
Preliminary
3.5
On-Chip Debug Support (OCDS)
The On-Chip Debug Support system provides a broad range of debug and emulation
features built into the XC161. The user software running on the XC161 can thus be
debugged within the target system environment.
The OCDS is controlled by an external debugging device via the debug interface,
consisting of the IEEE-1149-conforming JTAG port and a break interface. The debugger
controls the OCDS via a set of dedicated registers accessible via the JTAG interface.
Additionally, the OCDS system can be controlled by the CPU, e.g. by a monitor program.
An injection interface allows the execution of OCDS-generated instructions by the CPU.
Multiple breakpoints can be triggered by on-chip hardware, by software, or by an
external trigger input. Single stepping is supported as well as the injection of arbitrary
instructions and read/write access to the complete internal address space. A breakpoint
trigger can be answered with a CPU-halt, a monitor call, a data transfer, or/and the
activation of an external signal.
Tracing data can be obtained via the JTAG interface or via the external bus interface for
increased performance.
The debug interface uses a set of 6 interface signals (4 JTAG lines, 2 break lines) to
communicate with external circuitry. These interface signals use dedicated pins.
Complete system emulation is supported by the New Emulation Technology (NET)
interface. Via this full-featured emulation interface (including internal buses, control,
status, and pad signals) the XC161 chip can be connected to a NET carrier chip.
The use of the XC161 production chip together with the carrier chip provides superior
emulation behavior, because the emulation system shows exactly the same functionality
as the production chip (use of the identical silicon).
Data Sheet
28
V1.0, 2002-03
XC161
Derivatives
Functional Description
Preliminary
3.6
Capture/Compare Units (CAPCOM1/2)
The CAPCOM units support generation and control of timing sequences on up to
32 channels with a maximum resolution of 1 system clock cycle (8 cycles in staggered
mode). The CAPCOM units are typically used to handle high speed I/O tasks such as
pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A)
conversion, software timing, or time recording relative to external events.
Four 16-bit timers (T0/T1, T7/T8) with reload registers provide two independent time
bases for each capture/compare register array.
The input clock for the timers is programmable to several prescaled values of the internal
system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2.
This provides a wide range of variation for the timer period and resolution and allows
precise adjustments to the application specific requirements. In addition, external count
inputs for CAPCOM timers T0 and T7 allow event scheduling for the capture/compare
registers relative to external events.
Both of the two capture/compare register arrays contain 16 dual purpose capture/
compare registers, each of which may be individually allocated to either CAPCOM timer
T0 or T1 (T7 or T8, respectively), and programmed for capture or compare function.
All registers of each module have each one port pin associated with it which serves as
an input pin for triggering the capture function, or as an output pin to indicate the
occurrence of a compare event.
Table 6
Compare Modes (CAPCOM1/2)
Compare Modes
Function
Mode 0
Interrupt-only compare mode;
several compare interrupts per timer period are possible
Mode 1
Pin toggles on each compare match;
several compare events per timer period are possible
Mode 2
Interrupt-only compare mode;
only one compare interrupt per timer period is generated
Mode 3
Pin set ‘1’ on match; pin reset ‘0’ on compare timer overflow;
only one compare event per timer period is generated
Double Register
Mode
Two registers operate on one pin;
pin toggles on each compare match;
several compare events per timer period are possible
Single Event Mode
Generates single edges or pulses;
can be used with any compare mode
Data Sheet
29
V1.0, 2002-03
XC161
Derivatives
Functional Description
Preliminary
When a capture/compare register has been selected for capture mode, the current
contents of the allocated timer will be latched (‘captured’) into the capture/compare
register in response to an external event at the port pin which is associated with this
register. In addition, a specific interrupt request for this capture/compare register is
generated. Either a positive, a negative, or both a positive and a negative external signal
transition at the pin can be selected as the triggering event.
The contents of all registers which have been selected for one of the five compare modes
are continuously compared with the contents of the allocated timers.
When a match occurs between the timer value and the value in a capture/compare
register, specific actions will be taken based on the selected compare mode.
Reload Reg. TxREL
fSYS
2n : 1
TxIN
Tx
Input
Control
CAPCOM Timer Tx
Mode
Control
(Capture
or
Compare)
16-Bit
Capture/
Compare
Registers
Ty
Input
Control
CAPCOM Timer Ty
Interrupt
Request
(TxIR)
GPT2 Timer T6
Over/Underflow
CCzIO
Capture Inputs
Compare Outputs
Capture/Compare
Interrupt Requests
(CCzIR)
CCzIO
fSYS
GPT2 Timer T6
Over/Underflow
x
y
n
z
=
=
=
=
2n : 1
0, 7
1, 8
0/3 … 10
0 … 31
Figure 5
Data Sheet
Interrupt
Request
(TyIR)
Reload Reg. TyREL
MCB02143_X1.VSD
CAPCOM1/2 Unit Block Diagram
30
V1.0, 2002-03
XC161
Derivatives
Functional Description
Preliminary
3.7
General Purpose Timer (GPT12E) Unit
The GPT12E unit represents a very flexible multifunctional timer/counter structure which
may be used for many different time related tasks such as event timing and counting,
pulse width and duty cycle measurements, pulse generation, or pulse multiplication.
The GPT12E unit incorporates five 16-bit timers which are organized in two separate
modules, GPT1 and GPT2. Each timer in each module may operate independently in a
number of different modes, or may be concatenated with another timer of the same
module.
Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for
one of four basic modes of operation, which are Timer, Gated Timer, Counter, and
Incremental Interface Mode. In Timer Mode, the input clock for a timer is derived from
the system clock, divided by a programmable prescaler, while Counter Mode allows a
timer to be clocked in reference to external events.
Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the
operation of a timer is controlled by the ‘gate’ level on an external input pin. For these
purposes, each timer has one associated port pin (TxIN) which serves as gate or clock
input. The maximum resolution of the timers in module GPT1 is 4 system clock cycles.
The count direction (up/down) for each timer is programmable by software or may
additionally be altered dynamically by an external signal on a port pin (TxEUD) to
facilitate e.g. position tracking.
In Incremental Interface Mode the GPT1 timers (T2, T3, T4) can be directly connected
to the incremental position sensor signals A and B via their respective inputs TxIN and
TxEUD. Direction and count signals are internally derived from these two input signals,
so the contents of the respective timer Tx corresponds to the sensor position. The third
position sensor signal TOP0 can be connected to an interrupt input.
Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer overflow/underflow. The state of this latch may be output on pin T3OUT e.g. for time out
monitoring of external hardware components. It may also be used internally to clock
timers T2 and T4 for measuring long time periods with high resolution.
In addition to their basic operating modes, timers T2 and T4 may be configured as reload
or capture registers for timer T3. When used as capture or reload registers, timers T2
and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a
signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2
or T4 triggered either by an external signal or by a selectable state transition of its toggle
latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite
state transitions of T3OTL with the low and high times of a PWM signal, this signal can
be constantly generated without software intervention.
Data Sheet
31
V1.0, 2002-03
XC161
Derivatives
Functional Description
Preliminary
fSYS
2n : 1
Interrupt
Request
(T2IR)
GPT1 Timer T2
T2IN
T2
Mode
Control
T2EUD
fSYS
U/D
Reload
Capture
Interrupt
Request
(T3IR)
2n : 1
Toggle FF
T3
Mode
Control
T3IN
GPT1 Timer T3
T3OTL
T6OUT
U/D
T3EUD
fSYS
T4IN
T4EUD
Capture
2n : 1
Reload
T4
Mode
Control
GPT1 Timer T4
Interrupt
Request
(T4IR)
U/D
Mct04825_xc.vsd
n = 2 … 12
Figure 6
Block Diagram of GPT1
With its maximum resolution of 2 system clock cycles, the GPT2 module provides
precise event control and time measurement. It includes two timers (T5, T6) and a
capture/reload register (CAPREL). Both timers can be clocked with an input clock which
is derived from the CPU clock via a programmable prescaler or with external signals. The
count direction (up/down) for each timer is programmable by software or may
additionally be altered dynamically by an external signal on a port pin (TxEUD)1).
Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6,
which changes its state on each timer overflow/underflow.
The state of this latch may be used to clock timer T5, and/or it may be output on pin
T6OUT. The overflows/underflows of timer T6 can additionally be used to clock the
CAPCOM1/2 timers, and to cause a reload from the CAPREL register.
1)
If the respective derivative provides these pins.
Data Sheet
32
V1.0, 2002-03
XC161
Derivatives
Functional Description
Preliminary
The CAPREL register may capture the contents of timer T5 based on an external signal
transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared
after the capture procedure. This allows the XC161 to measure absolute time differences
or to perform pulse multiplication without software overhead.
The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of
GPT1 timer T3’s inputs T3IN and/or T3EUD. This is especially advantageous when T3
operates in Incremental Interface Mode.
fSYS
2n : 1
T5IN
T5
Mode
Control
T5EUD
Interrupt
Request
(T5IR)
GPT2 Timer T5
U/D
Clear
Capture
GPT2 CAPREL
T3IN/
T3EUD
Interrupt
Request
(CRIR)
MUX
CAPIN
Interrupt
Request
(T6IR)
CT3
Clear
fSYS
T6IN
2n : 1
GPT2 Timer T6
T6
Mode
Control
U/D
Toggle FF
T6OTL
T6OUT
Other
Modules
T6EUD
Mcb03999_xc.vsd
n = 1 … 11
Figure 7
1)
Block Diagram of GPT21)
The availability of pins TxEUD depends on the respective derivative.
Data Sheet
33
V1.0, 2002-03
XC161
Derivatives
Functional Description
Preliminary
3.8
Real Time Clock
The Real Time Clock (RTC) module of the XC161 is directly clocked via a separate clock
driver with the on-chip auxiliary oscillator frequency (fRTC = fOSCa). It is therefore
independent from the selected clock generation mode of the XC161.
The RTC basically consists of a chain of divider blocks:
• a selectable 8:1 divider (on - off)
• the reloadable 16-bit timer T14
• the 32-bit RTC timer block (accessible via registers RTCH and RTCL), made of:
– a reloadable 10-bit timer
– a reloadable 6-bit timer
– a reloadable 6-bit timer
– a reloadable 10-bit timer
All timers count up. Each timer can generate an interrupt request. All requests are
combined to a common node request. Additionally, T14 can generate a separate node
request.
RUN
fRTC
PRE
T14INT
1
MUX
0
8
RTCINT
Interrupt Sub Node
CNT
INT0
CNT
INT1
CNT
INT2
CNT
INT3
REL-Register
T14REL
10 Bits
6 Bits
6 Bits
10 Bits
T14
10 Bits
6 Bits
6 Bits
10 Bits
T14-Register
CNT-Register
mcb04805_xc.vsd
Figure 8
RTC Block Diagram
Note: The registers associated with the RTC are not affected by a reset in order to
maintain the correct system time even when intermediate resets are executed.
Data Sheet
34
V1.0, 2002-03
XC161
Derivatives
Functional Description
Preliminary
The RTC module can be used for different purposes:
• System clock to determine the current time and date,
optionally during idle mode, sleep mode, and power down mode
• Cyclic time based interrupt, to provide a system time tick independent of CPU
frequency and other resources, e.g. to wake up regularly from idle mode.
• 48-bit timer for long term measurements (maximum timespan is >100 years).
• Alarm interrupt for wake-up on a defined time
Data Sheet
35
V1.0, 2002-03
XC161
Derivatives
Functional Description
Preliminary
3.9
A/D Converter
For analog signal measurement, a 10-bit A/D converter with up to 16 multiplexed input
channels and a sample and hold circuit has been integrated on-chip. It uses the method
of successive approximation. The sample time (for loading the capacitors) and the
conversion time is programmable (in two modes) and can thus be adjusted to the
external circuitry. The A/D converter can also operate in 8-bit conversion mode, where
the conversion time is further reduced.
Overrun error detection/protection is provided for the conversion result register
(ADDAT): either an interrupt request will be generated when the result of a previous
conversion has not been read from the result register at the time the next conversion is
complete, or the next conversion is suspended in such a case until the previous result
has been read.
For applications which require less analog input channels, the remaining channel inputs
can be used as digital input port pins.
The A/D converter of the XC161 supports four different conversion modes. In the
standard Single Channel conversion mode, the analog level on a specified channel is
sampled once and converted to a digital result. In the Single Channel Continuous mode,
the analog level on a specified channel is repeatedly sampled and converted without
software intervention. In the Auto Scan mode, the analog levels on a prespecified
number of channels are sequentially sampled and converted. In the Auto Scan
Continuous mode, the prespecified channels are repeatedly sampled and converted. In
addition, the conversion of a specific channel can be inserted (injected) into a running
sequence without disturbing this sequence. This is called Channel Injection Mode.
The Peripheral Event Controller (PEC) may be used to automatically store the
conversion results into a table in memory for later evaluation, without requiring the
overhead of entering and exiting interrupt routines for each data transfer.
After each reset and also during normal operation the ADC automatically performs
calibration cycles. This automatic self-calibration constantly adjusts the converter to
changing operating conditions (e.g. temperature) and compensates process variations.
These calibration cycles are part of the conversion cycle, so they do not affect the normal
operation of the A/D converter.
In order to decouple analog inputs from digital noise and to avoid input trigger noise
those pins used for analog input can be disconnected from the digital IO or input stages
under software control. This can be selected for each pin separately via register P5DIDIS
(Port 5 Digital Input Disable).
The Auto-Power-Down feature of the A/D converter minimizes the power consumption
when no conversion is in progress.
Data Sheet
36
V1.0, 2002-03
XC161
Derivatives
Functional Description
Preliminary
3.10
Asynchronous/Synchronous Serial Interfaces (ASC0/ASC1)
The Asynchronous/Synchronous Serial Interfaces ASC0/ASC1 (USARTs) provide serial
communication with other microcontrollers, processors, terminals or external peripheral
components. They are upward compatible with the serial ports of the Infineon 8-bit
microcontroller families and support full-duplex asynchronous communication and halfduplex synchronous communication. A dedicated baud rate generator with a fractional
divider precisely generates all standard baud rates without oscillator tuning. For
transmission, reception and error handling 4 separate interrupt vectors are provided.
In asynchronous mode, 8- or 9-bit data frames (with optional parity bit) are transmitted
or received, preceded by a start bit and terminated by one or two stop bits. For
multiprocessor communication, a mechanism to distinguish address from data bytes has
been included (8-bit data plus wake-up bit mode). IrDA data transmissions up to
115.2 kbit/s with fixed or programmable IrDA pulse width are supported.
In synchronous mode, bytes (8 bits) are transmitted or received synchronously to a shift
clock which is generated by the ASC0/1. The LSB is always shifted first.
In both modes, transmission and reception of data is FIFO-buffered. An autobaud
detection unit allows to detect asynchronous data frames with its baudrate and mode
with automatic initialization of the baudrate generator and the mode control bits.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. A parity bit can automatically be generated on
transmission or be checked on reception. Framing error detection allows to recognize
data frames with missing stop bits. An overrun error will be generated, if the last
character received has not been read out of the receive buffer register at the time the
reception of a new character is complete.
Summary of Features
• Full-duplex asynchronous operating modes
– 8- or 9-bit data frames, LSB first, one or two stop bits, parity generation/checking
– Baudrate from 2.5 Mbit/s to 0.6 bit/s (@ 40 MHz)
– Multiprocessor mode for automatic address/data byte detection
– Support for IrDA data transmission/reception up to max. 115.2 kbit/s (@ 40 MHz)
– Loop-back capability
– Auto baudrate detection
• Half-duplex 8-bit synchronous operating mode at 5 Mbit/s to 406.9 bit/s (@ 40 MHz)
• Buffered transmitter/receiver with FIFO support (8 entries per direction)
• Loop-back option available for testing purposes
• Interrupt generation on transmitter buffer empty condition, last bit transmitted
condition, receive buffer full condition, error condition (frame, parity, overrun error),
start and end of an autobaud detection
Data Sheet
37
V1.0, 2002-03
XC161
Derivatives
Functional Description
Preliminary
3.11
High Speed Synchronous Serial Channels (SSC0/SSC1)
The High Speed Synchronous Serial Channels SSC0/SSC1 support full-duplex and halfduplex synchronous communication. It may be configured so it interfaces with serially
linked peripheral components, full SPI functionality is supported.
A dedicated baud rate generator allows to set up all standard baud rates without
oscillator tuning. For transmission, reception and error handling three separate interrupt
vectors are provided.
The SSC transmits or receives characters of 2 … 16 bits length synchronously to a shift
clock which can be generated by the SSC (master mode) or by an external master (slave
mode). The SSC can start shifting with the LSB or with the MSB and allows the selection
of shifting and latching clock edges as well as the clock polarity.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. Transmit error and receive error supervise the correct
handling of the data buffer. Phase error and baudrate error detect incorrect serial data.
Summary of Features
•
•
•
•
Master or Slave mode operation
Full-duplex or Half-duplex transfers
Baudrate generation from 20 Mbit/s to 305.18 bit/s (@ 40 MHz)
Flexible data format
– Programmable number of data bits: 2 to 16 bits
– Programmable shift direction: LSB-first or MSB-first
– Programmable clock polarity: idle low or idle high
– Programmable clock/data phase: data shift with leading or trailing clock edge
• Loop back option available for testing purposes
• Interrupt generation on transmitter buffer empty condition, receive buffer full condition,
error condition (receive, phase, baudrate, transmit error)
• Three pin interface with flexible SSC pin configuration
Data Sheet
38
V1.0, 2002-03
XC161
Derivatives
Functional Description
Preliminary
3.12
Serial Data Link Module (SDLM)
The Serial Data Link Module (SDLM) provides serial communication on a J1850 type
multiplexed serial bus via an external J1850 bus transceiver. The module conforms to
the SAE Class B J1850 specification for variable pulse width modulation (VPW).
General SDLM Features:
•
•
•
•
•
•
•
•
•
•
•
Compliant to the SAE Class B J1850 specification (VPW)
Class 2 protocol fully supported
Variable Pulse Width (VPW) operation at 10.4 kbit/s
High Speed 4X operation at 41.6 kbit/s
Programmable Normalization Bit
Programmable Delay for transceiver interface
Digital Noise Filter
Power Down mode with automatic wake-up support upon bus activity
Single Byte Header and Consolidated Header supported
CRC generation and checking
Receive and transmit Block Mode
Data Link Operation Features:
•
•
•
•
•
11-Byte Transmit Buffer
Double buffered 11-Byte receive buffer (optional overwrite enable)
Support for In Frame Response (IFR) types 1, 2 and 3
Transmit and Receiver Message Buffers configurable for either FIFO or Byte mode
Advanced Interrupt Handling with 8 separately enabled sources:
Error, format or bus shorted
CRC error
Lost Arbitration
Break received
In-Frame-Response request
Header received
Complete message received
Transmit successful
• Automatic IFR transmission (Types 1 and 2) for 3-Byte consolidated headers
• User configurable clock divider
• Bus status flags (IDLE, EOF, EOD, SOF, Tx and Rx in progress)
Note: When the SDLM is used with the interface lines assigned to Port 4, the segment
address output on Port 4 must be limited. CS lines can be used to increase the
total amount of addressable external memory.
Data Sheet
39
V1.0, 2002-03
XC161
Derivatives
Functional Description
Preliminary
3.13
TwinCAN Module
The integrated TwinCAN module handles the completely autonomous transmission and
reception of CAN frames in accordance with the CAN specification V2.0 part B (active),
i.e. the on-chip TwinCAN module can receive and transmit standard frames with 11-bit
identifiers as well as extended frames with 29-bit identifiers.
Two Full-CAN nodes share the TwinCAN module’s resources to optimize the CAN bus
traffic handling and to minimize the CPU load. The module provides up to 32 message
objects, which can be assigned to one of the CAN nodes and can be combined to FIFOstructures. Each object provides separate masks for acceptance filtering.
The flexible combination of Full-CAN functionality and FIFO architecture reduces the
efforts to fulfill the real-time requirements of complex embedded control applications.
Improved CAN bus monitoring functionality as well as the number of message objects
permit precise and comfortable CAN bus traffic handling.
Gateway functionality allows automatic data exchange between two separate CAN bus
systems, which reduces CPU load and improves the real time behavior of the entire
system.
The bit timing for both CAN nodes is derived from the master clock and is programmable
up to a data rate of 1 Mbit/s. Each CAN node uses two pins of Port 4, Port 7, or Port 9 to
interface to an external bus transceiver. The interface pins are assigned via software.
TwinCAN module kernel
clock fCAN
control
CAN
node A
CAN
node B
TXDCA
RXDCA
address
decoder
CAN
message object buffer
TXDCB
port
control
RXDCB
interrupt
control
Figure 9
Data Sheet
TwinCAN control
TwinCAN Module Block Diagram
40
V1.0, 2002-03
XC161
Derivatives
Functional Description
Preliminary
Summary of Features
•
•
•
•
•
CAN functionality according to CAN specification V2.0 B active.
Data transfer rate up to 1 Mbit/s
Flexible and powerful message transfer control and error handling capabilities
Full-CAN functionality and Basic CAN functionality for each message object
32 flexible message objects
– Assignment to one of the two CAN nodes
– Configuration as transmit object or receive object
– Concatenation to a 2-, 4-, 8-, 16-, or 32-message buffer with FIFO algorithm
– Handling of frames with 11-bit or 29-bit identifiers
– Individual programmable acceptance mask register for filtering for each object
– Monitoring via a frame counter
– Configuration for Remote Monitoring Mode
• Up to eight individually programmable interrupt nodes can be used
• CAN Analyzer Mode for bus monitoring is implemented
Note: When a CAN node has the interface lines assigned to Port 4, the segment address
output on Port 4 must be limited. CS lines can be used to increase the total amount
of addressable external memory.
3.14
IIC Bus Module
The integrated IIC Bus Module handles the transmission and reception of frames over
the two-line IIC bus in accordance with the IIC Bus specification. The IIC Module can
operate in slave mode, in master mode or in multi-master mode. It can receive and
transmit data using 7-bit or 10-bit addressing. Up to 4 send/receive data bytes can be
stored in the extended buffers.
Several physical interfaces (port pins) can be established under software control. Data
can be transferred at speeds up to 400 kbit/sec.
Two interrupt nodes dedicated to the IIC module allow efficient interrupt service and also
support operation via PEC transfers.
Note: The port pins associated with the IIC interfaces must be switched to open drain
mode, as required by the IIC specification.
Data Sheet
41
V1.0, 2002-03
XC161
Derivatives
Functional Description
Preliminary
3.15
Watchdog Timer
The Watchdog Timer represents one of the fail-safe mechanisms which have been
implemented to prevent the controller from malfunctioning for longer periods of time.
The Watchdog Timer is always enabled after a reset of the chip, and can be disabled
until the EINIT instruction has been executed (compatible mode), or it can be disabled
and enabled at any time by executing instructions DISWDT and ENWDT (enhanced
mode). Thus, the chip’s start-up procedure is always monitored. The software has to be
designed to restart the Watchdog Timer before it overflows. If, due to hardware or
software related failures, the software fails to do so, the Watchdog Timer overflows and
generates an internal hardware reset and pulls the RSTOUT pin low in order to allow
external hardware components to be reset.
The Watchdog Timer is a 16-bit timer, clocked with the system clock divided by 2/4/128/
256. The high byte of the Watchdog Timer register can be set to a prespecified reload
value (stored in WDTREL) in order to allow further variation of the monitored time
interval. Each time it is serviced by the application software, the high byte of the
Watchdog Timer is reloaded and the low byte is cleared. Thus, time intervals between
13 µs and 419 ms can be monitored (@ 40 MHz).
The default Watchdog Timer interval after reset is 3.28 ms (@ 40 MHz).
Data Sheet
42
V1.0, 2002-03
XC161
Derivatives
Functional Description
Preliminary
3.16
Clock Generation
The Clock Generation Unit uses a programmable on-chip PLL with multiple prescalers
to generate the clock signals for the XC161 with high flexibility. The master clock fMC is
the reference clock signal, and is used for TwinCAN and is output to the external system.
The CPU clock fCPU and the system clock fSYS are derived from the master clock either
directly (1:1) or via a 2:1 prescaler (fSYS = fCPU = fMC / 2). See also Section 5.1.
The on-chip oscillator can drive an external crystal or accepts an external clock signal.
The oscillator clock frequency can be multiplied by the on-chip PLL (by a programmable
factor) or can be divided by a programmable prescaler factor.
If the bypass mode is used (direct drive or prescaler) the PLL can deliver an independent
clock to monitor the clock signal generated by the on-chip oscillator. This PLL clock is
independent from the XTAL1 clock. When the expected oscillator clock transitions are
missing the Oscillator Watchdog (OWD) activates the PLL Unlock / OWD interrupt node
and supplies the CPU with an emergency clock, the PLL clock signal. Under these
circumstances the PLL will oscillate with its basic frequency.
The oscillator watchdog can be disabled by switching the PLL off. This reduces power
consumption, but also no interrupt request will be generated in case of a missing
oscillator clock.
Note: At the end of an external reset (EA = ‘0’) the oscillator watchdog may be disabled
via hardware by (externally) pulling the RD line low upon a reset, similar to the
standard reset configuration.
3.17
Parallel Ports
The XC161 provides up to 103 I/O lines which are organized into nine input/output ports
and one input port. All port lines are bit-addressable, and all input/output lines are
individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O
ports are true bidirectional ports which are switched to high impedance state when
configured as inputs. The output drivers of some I/O ports can be configured (pin by pin)
for push/pull operation or open-drain operation via control registers. During the internal
reset, all port pins are configured as inputs (except for pin RSTOUT).
The edge characteristics (shape) and driver characteristics (output current) of the port
drivers can be selected via registers POCONx.
The input threshold of some ports is selectable (TTL or CMOS like), where the special
CMOS like input threshold reduces noise sensitivity due to the input hysteresis. The
input threshold may be selected individually for each byte of the respective ports.
All port lines have programmable alternate input or output functions associated with
them. All port lines that are not used for these alternate functions may be used as general
purpose IO lines.
Data Sheet
43
V1.0, 2002-03
XC161
Derivatives
Functional Description
Preliminary
Table 7
Summary of the XC161’s Parallel Ports
Port
Control
Alternate Functions
PORT0
Pad drivers
Address/Data lines or data lines1)
PORT1
Pad drivers
Address lines2)
Capture inputs or compare outputs,
Serial interface lines
Port 2
Pad drivers,
Open drain,
Input threshold
Capture inputs or compare outputs,
Timer control signal,
Fast external interrupt inputs
Port 3
Pad drivers,
Open drain,
Input threshold
Timer control signals, serial interface lines,
Optional bus control signal BHE/WRH,
System clock output CLKOUT (or FOUT)
Port 4
Pad drivers,
Open drain,
Input threshold
Segment address lines3)
Port 5
---
Analog input channels to the A/D converter,
Timer control signals
Port 6
Open drain,
Input threshold
Capture inputs or compare outputs,
Bus arbitration signals BREQ, HLDA, HOLD,
Optional chip select signals
Port 7
Open drain,
Input threshold
Capture inputs or compare outputs,
CAN/SDLM interface lines4)
Port 9
Pad drivers,
Open drain,
Input threshold
Capture inputs or compare outputs
Pad drivers,
Open drain
Bus control signals RD, WR/WRL, READY, ALE,
External access enable pin EA,
Reset indication output RSTOUT
Port 20
CAN/SDLM interface lines4)
CAN/SDLM interface lines4),
IIC bus interface lines4)
1)
For multiplexed bus cycles.
2)
For demultiplexed bus cycles.
3)
For more than 64 Kbytes of external resources.
4)
Can be assigned by software.
Data Sheet
44
V1.0, 2002-03
XC161
Derivatives
Functional Description
Preliminary
3.18
Power Management
The XC161 provides several means to control the power it consumes either at a given
time or averaged over a certain timespan. Three mechanisms can be used (partly in
parallel):
• Power Saving Modes switch the XC161 into a special operating mode (control via
instructions).
Idle Mode stops the CPU while the peripherals can continue to operate.
Sleep Mode and Power Down Mode stop all clock signals and all operation (RTC may
optionally continue running). Sleep Mode can be terminated by external interrupt
signals.
• Clock Generation Management controls the distribution and the frequency of
internal and external clock signals. While the clock signals for currently inactive parts
of logic are disabled automatically, the user can reduce the XC161’s CPU clock
frequency which drastically reduces the consumed power.
External circuitry can be controlled via the programmable frequency output FOUT.
• Peripheral Management permits temporary disabling of peripheral modules (control
via register SYSCON3). Each peripheral can separately be disabled/enabled.
The on-chip RTC supports intermittend operation of the XC161 by generating cyclic
-up signals. This offers full performance to quickly react on action requests while the
intermittend sleep phases greatly reduce the average power consumption of the system.
Data Sheet
45
V1.0, 2002-03
XC161
Derivatives
Functional Description
Preliminary
3.19
Instruction Set Summary
Table 8 lists the instructions of the XC161 in a condensed way.
The various addressing modes that can be used with a specific instruction, the operation
of the instructions, parameters for conditional execution of instructions, and the opcodes
for each instruction can be found in the “Instruction Set Manual”.
This document also provides a detailled description of each instruction.
Table 8
Instruction Set Summary
Mnemonic
ADD(B)
ADDC(B)
SUB(B)
SUBC(B)
MUL(U)
DIV(U)
DIVL(U)
CPL(B)
NEG(B)
AND(B)
(X)OR(B)
BCLR / BSET
BMOV(N)
BAND / BOR /
BXOR
BCMP
BFLDH / BFLDL
CMP(B)
CMPD1/2
CMPI1/2
PRIOR
SHL / SHR
ROL / ROR
ASHR
MOV(B)
MOVBS/Z
Data Sheet
Description
Add word (byte) operands
Add word (byte) operands with Carry
Subtract word (byte) operands
Subtract word (byte) operands with Carry
(Un)Signed multiply direct GPR by direct GPR (16-16-bit)
(Un)Signed divide register MDL by direct GPR (16-/16-bit)
(Un)Signed long divide reg. MD by direct GPR (32-/16-bit)
Complement direct word (byte) GPR
Negate direct word (byte) GPR
Bitwise AND, (word/byte operands)
Bitwise (exclusive)OR, (word/byte operands)
Clear/Set direct bit
Move (negated) direct bit to direct bit
AND/OR/XOR direct bit with direct bit
Bytes
2/4
2/4
2/4
2/4
2
2
2
2
2
2/4
2/4
2
4
4
Compare direct bit to direct bit
Bitwise modify masked high/low byte of bit-addressable
direct word memory with immediate data
Compare word (byte) operands
Compare word data to GPR and decrement GPR by 1/2
Compare word data to GPR and increment GPR by 1/2
Determine number of shift cycles to normalize direct
word GPR and store result in direct word GPR
Shift left/right direct word GPR
Rotate left/right direct word GPR
Arithmetic (sign bit) shift right direct word GPR
Move word (byte) data
Move byte operand to word op. with sign/zero extension
4
4
46
2/4
2/4
2/4
2
2
2
2
2/4
2/4
V1.0, 2002-03
XC161
Derivatives
Functional Description
Preliminary
Table 8
Instruction Set Summary (cont’d)
Mnemonic
JMPA/I/R
JMPS
JB(C)
JNB(S)
CALLA/I/R
CALLS
PCALL
TRAP
PUSH / POP
SCXT
RET(P)
RETS
RETI
SBRK
SRST
IDLE
PWRDN
SRVWDT
DISWDT/ENWDT
EINIT
ATOMIC
EXTR
EXTP(R)
EXTS(R)
NOP
CoMUL / CoMAC
CoADD / CoSUB
Co(A)SHR/CoSHL
CoLOAD/STORE
CoCMP/MAX/MIN
CoABS / CoRND
CoMOV/NEG/NOP
Data Sheet
Description
Jump absolute/indirect/relative if condition is met
Jump absolute to a code segment
Jump relative if direct bit is set (and clear bit)
Jump relative if direct bit is not set (and set bit)
Call absolute/indirect/relative subroutine if condition is met
Call absolute subroutine in any code segment
Push direct word register onto system stack and call
absolute subroutine
Call interrupt service routine via immediate trap number
Push/pop direct word register onto/from system stack
Push direct word register onto system stack and update
register with word operand
Return from intra-segment subroutine
(and pop direct word register from system stack)
Return from inter-segment subroutine
Return from interrupt service subroutine
Software Break
Software Reset
Enter Idle Mode
Enter Power Down Mode (supposes NMI-pin being low)
Service Watchdog Timer
Disable/Enable Watchdog Timer
Signify End-of-Initialization on RSTOUT-pin
Begin ATOMIC sequence
Begin EXTended Register sequence
Begin EXTended Page (and Register) sequence
Begin EXTended Segment (and Register) sequence
Null operation
Multiply (and accumulate)
Add / Subtract
(Arithmetic) Shift right / Shift left
Load accumulator / Store MAC register
Compare (maximum/minimum)
Absolute value / Round accumulator
Data move / Negate accumulator / Null operation
47
Bytes
4
4
4
4
4
4
4
2
2
4
2
2
2
2
4
4
4
4
4
4
2
2
2/4
2/4
2
4
4
4
4
4
4
4
V1.0, 2002-03
XC161
Derivatives
Electrical Parameters
Preliminary
4
Electrical Parameters
4.1
Absolute Maximum Ratings
Table 9
Absolute Maximum Rating Parameters
Parameter
Symbol
Limit Values
min.
Storage temperature
Junction temperature
Voltage on VDDI pins with
respect to ground (VSS)
TST
TJ
VDDI
Voltage on VDDP pins with VDDP
respect to ground (VSS)
Unit
Notes
max.
-65
150
°C
–
-40
150
°C
under bias
-0.5
3.25
V
–
-0.5
6.2
V
–
-0.5
VDDP
V
–
Voltage on any pin with
respect to ground (VSS)
VIN
Input current on any pin
during overload condition
–
-10
10
mA
–
Absolute sum of all input
currents during overload
condition
–
–
|100|
mA
–
+ 0.5
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
During absolute maximum rating overload conditions (VIN > VDDP or VIN < VSS)
the voltage on VDDP pins with respect to ground (VSS) must not exceed the values
defined by the absolute maximum ratings.
4.2
Table 10
Package Properties
Package Parameters (P-TQFP-144-19)
Parameter
Symbol
Limit Values
min.
Power dissipation
Thermal Resistance
Data Sheet
PDISS
RTHA
Unit
Notes
max.
–
0.8
W
–
–
32
K/W
Chip-Ambient
48
V1.0, 2002-03
XC161
Derivatives
Electrical Parameters
Preliminary
4.3
Operating Conditions
The following operating conditions must not be exceeded to ensure correct operation of
the XC161. All parameters specified in the following sections refer to these operating
conditions, unless otherwise noticed.
Table 11
Operating Condition Parameters
Parameter
Symbol
Limit Values
min.
Unit Notes
max.
Digital supply voltage for
the core
VDDI
2.45
2.75
V
Active mode,
fCPUmax = 40 MHz
Digital supply voltage for
IO pads
VDDP
4.75
5.25
V
Active mode
Supply Voltage Difference ∆VDD
-0.5
–
V
VDDP - VDDI1)
V
Reference voltage
Digital ground voltage
VSS
IOV
0
-5
5
mA
Per IO pin2)3)
-2
5
mA
Per analog input
pin2)3)
Overload current coupling KOVA
factor for analog inputs4)
–
1.0 × 10-4 –
–
1.5 × 10-3 –
Overload current coupling KOVD
factor for digital I/O pins4)
–
5.0 × 10-3 –
–
1.0 × 10-2 –
Absolute sum of overload
currents
Σ|IOV|
–
50
mA
3)
External Load
Capacitance
CL
–
50
pF
Pin drivers in
default mode5)
Ambient temperature
TA
0
70
°C
SAB-XC161…
-40
85
°C
SAF-XC161…
-40
125
°C
SAK-XC161…
Overload current
IOV > 0
IOV < 0
IOV > 0
IOV < 0
1)
This limitation must be fulfilled under all operating conditions including power-ramp-up, power-ramp-down, and
power-save modes.
2)
Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin
exceeds the specified range: VOV > VDDP + 0.5 V (IOV > 0) or VOV < VSS - 0.5 V (IOV < 0). The absolute sum
of input overload currents on all pins may not exceed 50 mA. The supply voltages must remain within the
specified limits.
Proper operation is not guaranteed if overload conditions occur on functional pins such as XTAL1, RD, WR,
etc.
3)
Not 100% tested, guaranteed by design and characterization.
Data Sheet
49
V1.0, 2002-03
XC161
Derivatives
Electrical Parameters
Preliminary
4)
An overload current (IOV) through a pin injects a certain error current (IINJ) into the adjacent pins. This error
current adds to the respective pin’s leakage current (IOZ). The amount of error current depends on the overload
current and is defined by the overload coupling factor KOV. The polarity of the injected error current is inverse
compared to the polarity of the overload current that produces it.
The total current through a pin is |ITOT| = |IOZ| + (|IOV| × KOV). The additional error current may distort the input
voltage on analog inputs.
5)
The timing is valid for pin drivers operating in default current mode (selected after reset). Reducing the output
current may lead to increased delays or reduced driving capability (CL).
4.4
Parameter Interpretation
The parameters listed in the following partly represent the characteristics of the XC161
and partly its demands on the system. To aid in interpreting the parameters right, when
evaluating them for a design, they are marked in column “Symbol”:
CC (Controller Characteristics):
The logic of the XC161 will provide signals with the respective characteristics.
SR (System Requirement):
The external system must provide signals with the respective characteristics to the
XC161.
Data Sheet
50
V1.0, 2002-03
XC161
Derivatives
Electrical Parameters
Preliminary
4.5
DC Parameters
DC Characteristics
(Operating Conditions apply)1)
Parameter
Symbol
Limit Values
min.
Unit Test Condition
max.
Input low voltage (TTL,
all except XTAL1, XTAL3)
VIL
SR -0.5
0.2×VDDP V
- 0.1
–
Input low voltage XTAL1,
XTAL3
VILC SR -0.5
0.3 ×VDDI V
–
Input low voltage
(Special Threshold)
VILS SR -0.5
0.45
× VDDP
V
–
Input high voltage (TTL,
all except XTAL1, XTAL3)
VIH
SR 0.2×VDDP VDDP
+ 0.5
+ 0.9
V
–
Input high voltage XTAL1,
XTAL3
VIHC SR 0.7
VDDI
× VDDI
+ 0.5
VIHS SR 0.8×VDDP VDDP
V
–
V
–
mV
VDDP in [V],
Input high voltage
(Special Threshold)
- 0.2
+ 0.5
65×VDDP –
Input Hysteresis
(Special Threshold)
HYS
Output low voltage
VOL CC –
Series
resistance = 0 Ω
1.0
V
0.45
V
–
V
IOL ≤ IOLmax2)
IOL ≤ IOLnom2) 3)
IOH ≥ IOHmax2)
–
V
IOH ≥ IOHnom2) 3)
Input leakage current (Port 5)5) IOZ1 CC –
±200
nA
0 V < VIN < VDDP
IOZ2 CC –
±500
nA
0.45 V < VIN <
–
Output high voltage4)
VOH CC VDDP
- 1.0
VDDP
- 0.45
Input leakage current (all
other)5)
6)
Configuration pull-up current
Configuration pull-down
current9)
Data Sheet
7)
ICPUH
ICPUL8)
ICPDL7)
ICPDH8)
–
-10
µA
-100
–
µA
–
10
µA
120
–
µA
51
VDDP
VIN = VIHmin
VIN = VILmax
VIN = VILmax
VIN = VIHmin
V1.0, 2002-03
XC161
Derivatives
Electrical Parameters
Preliminary
DC Characteristics (cont’d)
(Operating Conditions apply)1)
Parameter
Symbol
Limit Values
min.
max.
–
-10
µA
–
µA
±20
µA
10
pF
Level inactive hold current10)
ILHI7)
Level active hold current10)
ILHA8)
-100
IIL CC –
CIO CC –
XTAL1, XTAL3 input current
Pin capacitance11)
(digital inputs/outputs)
Unit Test Condition
VOUT =
0.5 × VDDP
VOUT = 0.45 V
0 V < VIN < VDDI
1)
Keeping signal levels within the limits specified in this table, ensures operation without overload conditions.
For signal levels outside these specifications, also refer to the specification of the overload current IOV.
2)
The maximum deliverable output current of a port driver depends on the selected output driver mode, see
Table 12, Current Limits for Port Output Drivers. The limit for pin groups must be respected.
3)
As a rule, with decreasing output current the output levels approach the respective supply level (VOL→VSS,
VOH→VDDP). However, only the levels for nominal output currents are guaranteed.
4)
This specification is not valid for outputs which are switched to open drain mode. In this case the respective
output will float and the voltage results from the external circuitry.
5)
An additional error current (IINJ) will flow if an overload current flows through an adjacent pin. Please refer to
the definition of the overload coupling factor KOV.
6)
This specification is valid during Reset for configuration on RD, WR, EA, PORT0.
The pull-ups on RD and WR (WRL/WRH) are also active during bus hold.
7)
The maximum current may be drawn while the respective signal line remains inactive.
8)
The minimum current must be drawn to drive the respective signal line active.
9)
This specification is valid during Reset for configuration on ALE.
The pull-down on ALE is also active during bus hold.
10)
This specification is valid during Reset for pins P6.4-0, which can act as CS outputs.
The pull-ups on CS outputs are also active during bus hold.
11)
Not 100% tested, guaranteed by design and characterization.
Data Sheet
52
V1.0, 2002-03
XC161
Derivatives
Electrical Parameters
Preliminary
Table 12
Current Limits for Port Output Drivers
Port Output Driver
Mode
Maximum Output Current
(IOLmax, -IOHmax)1)
Nominal Output Current
(IOLnom, -IOHnom)
Strong driver
10 mA
2.5 mA
Medium driver
4.0 mA
1.0 mA
Weak driver
0.5 mA
0.1 mA
1)
An output current above |IOXnom| may be drawn from up to three pins at the same time.
For any group of 16 neighboring port output pins the total output current in each direction (ΣIOL and Σ-IOH)
must remain below 50 mA.
Power Consumption XC161
(Operating Conditions apply)
Parameter
Symbol
Limit Values
Unit Test Condition
min.
max.
30 +
mA
3.0 × fCPU
Power supply current (active)
with all peripherals active
IDDI
–
Idle mode supply current
with all peripherals active
IIDX
–
Sleep and Power-down mode
supply current with RTC
disabled3)
IPDO4)
–
25 +
mA
1.2 × fCPU
20
µA
1)
fCPU in [MHz]2)
fCPU in [MHz]2)
VDDI=VDDImax5)
TJ ≤ 25 °C
1)
During Flash programming or erase operations the supply current is increased by max. 5 mA.
2)
The supply current is a function of the operating frequency. This dependency is illustrated in Figure 10.
These parameters are tested at VDDImax and maximum CPU clock frequency with all outputs disconnected and
all inputs at VIL or VIH.
The VDDP pins only draw leakage currents if no output is toggling. Otherwise, the respective charging current
must be delivered.
3)
If the RTC remains active in Sleep or Power-down mode the supply current is increased by max. 100 µA.
4)
This parameter is determined mainly by the transistor leakage currents. This current heavily depends on the
junction temperature (see Figure 11). The junction temperature TJ is the same as the ambient temperature TA
if no current flows through the port output drivers. Otherwise, the resulting temperature difference must be
taken into account.
5)
This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to
0.1 V or at VDDP - 0.1 V to VDDP, all outputs (including pins configured as outputs) disconnected.
Data Sheet
53
V1.0, 2002-03
XC161
Derivatives
Electrical Parameters
Preliminary
I [mA]
IDDImax
140
120
IDDItyp
100
IIDXmax
80
IIDXtyp
60
40
20
10
Figure 10
Data Sheet
20
30
40
fCPU [MHz]
Supply/Idle Current as a Function of Operating Frequency
54
V1.0, 2002-03
XC161
Derivatives
Electrical Parameters
Preliminary
IPDO
[µA]
1500
1000
500
-50
Figure 11
Data Sheet
0
50
100
150
TJ [°C]
Sleep and Power Down Supply Current as a Function of Temperature
55
V1.0, 2002-03
XC161
Derivatives
Electrical Parameters
Preliminary
4.6
Table 13
A/D Converter Characteristics
A/D Converter Characteristics
(Operating Conditions apply)
Parameter
Analog reference supply
Symbol
VAREF
Limit Values
min.
max.
Unit Test
Condition
4.5
VDDP
V
SR
Analog reference ground
VAGND
1)
+ 0.1
VSS - 0.1
VSS + 0.1 V
SR
Analog input voltage range
Basic clock frequency
Conversion time4)
VAIN SR VAGND
fBC
0.5
–
tC10
CC
tC8
–
CC
VAREF
V
2)
20
MHz
3)
48×tBC + –
tS+2×tSYS
10-bit conv.
tSYS = 1 / fCPU
40×tBC + –
tS+2×tSYS
11,696
tBC
tSYS = 1 / fCPU
8-bit conv.
5)
Calibration time after reset
tCAL
Total unadjusted error
TUE CC –
±2
LSB
1)
Total capacitance
of an analog input
CAINT
–
15
pF
6)
Switched capacitance
of an analog input
CAINS
–
10
pF
6)
Resistance of
the analog input path
RAIN
–
2
kΩ
6)
Total capacitance
of the reference input
CAREFT
–
20
pF
6)
Switched capacitance
of the reference input
CAREFS
–
15
pF
6)
Resistance of
the reference input path
RAREF
–
1
kΩ
6)
1)
CC 484
CC
CC
CC
CC
CC
CC
TUE is tested at VAREF = VDDP + 0.1 V, VAGND = 0 V. It is guaranteed by design for all other voltages within
the defined voltage range.
If the analog reference supply voltage drops below 4.5 V (i.e. VAREF ≥ 4.0 V) or exceeds the power supply
voltage by up to 0.2 V (i.e. VAREF = VDDP + 0.2 V) the maximum TUE is increased to ±3 LSB. This range is not
100% tested.
The specified TUE is guaranteed only if the absolute sum of input overload currents on Port 5 pins (see IOV
specification) does not exceed 10 mA.
During the reset calibration sequence the maximum TUE may be ±4 LSB.
Data Sheet
56
V1.0, 2002-03
XC161
Derivatives
Electrical Parameters
Preliminary
2)
VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in
these cases will be X000H or X3FFH, respectively.
3)
The limit values for fBC must not be exceeded when selecting the peripheral frequency and the ADCTC setting.
4)
This parameter includes the sample time tS, the time for determining the digital result and the time to load the
result register with the conversion result.
Values for the basic clock tBC depend on programming and can be taken from Table 14.
5)
The actual duration of the reset calibration depends on the noise on the reference signal. Conversions
executed during the reset calibration increase the calibration time. The TUE for those conversions may be
increased.
6)
Not 100% tested, guaranteed by design and characterization.
The given parameter values cover the complete operating range. Under relaxed operating conditions
(temperature, supply voltage) reduced values can be used for calculations. At room temperature and nominal
supply voltage the following typical values can be used:
CAINTtyp = 12 pF, CAINStyp = 7 pF, RAINtyp = 1.5 kΩ, CAREFTtyp = 15 pF, CAREFStyp = 13 pF, RAREFtyp = 0.7 kΩ.
RSource
VAIN =
RAIN, On
CExt
CAINT - CAINS
A/D Converter
CAINS
mcs04879_p.vsd
Figure 12
Data Sheet
Equivalent Circuitry for Analog Inputs
57
V1.0, 2002-03
XC161
Derivatives
Electrical Parameters
Preliminary
Sample time and conversion time of the XC161’s A/D Converter are programmable. In
compatibility mode, the above timing can be calculated using Table 14.
The limit values for fBC must not be exceeded when selecting ADCTC.
Table 14
A/D Converter Computation Table1)
ADCON.15|14
(ADCTC)
A/D Converter
Basic Clock fBC
ADCON.13|12 Sample time
(ADSTC)
tS
00
fSYS / 4
fSYS / 2
fSYS / 16
fSYS / 8
00
01
10
11
1)
01
10
11
tBC × 8
tBC × 16
tBC × 32
tBC × 64
These selections are available in compatibility mode. An improved mechanism to control the ADC input clock
can be selected.
Converter Timing Example:
fSYS
Basic clock
fBC
Sample time
tS
Conversion 8-bit tC8
Conversion 10-bit tC10
Assumptions:
Data Sheet
= 40 MHz (i.e. tSYS = 25 ns), ADCTC = ‘01’, ADSTC = ‘00’.
= fSYS / 2 = 20 MHz, i.e. tBC = 50 ns.
= tBC × 8 = 400 ns.
= tS + 40 × tBC + 2 × tSYS = (400 + 2000 + 50) ns = 2.45 µs.
= tS + 48 × tBC + 2 × tSYS = (400 + 2400 + 50) ns = 2.85 µs.
58
V1.0, 2002-03
XC161
Derivatives
Timing Parameters
Preliminary
5
Timing Parameters
5.1
Definition of Internal Timing
The internal operation of the XC161 is controlled by the internal master clock fMC.
The master clock signal fMC can be generated from the oscillator clock signal fOSC via
different mechanisms. The duration of master clock periods (TCMs) and their variation
(and also the derived external timing) depend on the used mechanism to generate fMC.
This influence must be regarded when calculating the timings for the XC161.
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Figure 13
Generation Mechanisms for the Master Clock
Note: The example for PLL operation shown in Figure 13 refers to a PLL factor of 1:4,
the example for prescaler operation refers to a divider factor of 2:1.
The used mechanism to generate the master clock is selected by register PLLCON.
CPU and EBC are clocked with the CPU clock signal fCPU. The CPU clock can have the
same frequency as the master clock (fCPU = fMC) or can be the master clock divided by
two: fCPU = fMC / 2. This factor is selected by bit CPSYS in register SYSCON1.
The specification of the external timing (AC Characteristics) depends on the period of the
CPU clock, called “TCP”.
The other peripherals are supplied with the system clock signal fSYS which has the same
frequency as the CPU clock signal fCPU.
Data Sheet
59
V1.0, 2002-03
XC161
Derivatives
Timing Parameters
Preliminary
Bypass Operation
When bypass operation is configured (PLLCTRL = 0xB) the master clock is derived from
the internal oscillator (input clock signal XTAL1) through the input- and outputprescalers:
fMC = fOSC / ((PLLIDIV+1)×(PLLODIV+1)).
If both divider factors are selected as ’1’ (PLLIDIV = PLLODIV = ’0’) the frequency of fMC
directly follows the frequency of fOSC so the high and low time of fMC is defined by the
duty cycle of the input clock fOSC.
The lowest master clock frequency is achieved by selecting the maximum values for both
divider factors:
fMC = fOSC / ((3+1)×(14+1)) = fOSC / 60.
Phase Locked Loop (PLL)
When PLL operation is configured (PLLCTRL = 11B) the on-chip phase locked loop is
enabled and provides the master clock. The PLL multiplies the input frequency by the
factor F (fMC = fOSC × F) which results from the input divider, the multiplication factor,
and the output divider (F = PLLMUL+1 / (PLLIDIV+1 × PLLODIV+1)). The PLL circuit
synchronizes the master clock to the input clock. This synchronization is done smoothly,
i.e. the master clock frequency does not change abruptly.
Due to this adaptation to the input clock the frequency of fMC is constantly adjusted so it
is locked to fOSC. The slight variation causes a jitter of fMC which also affects the duration
of individual TCMs.
The timing listed in the AC Characteristics refers to TCPs. Because fCPU is derived from
fMC, the timing must be calculated using the minimum TCP possible under the respective
circumstances.
The actual minimum value for TCP depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency so it corresponds to the applied input frequency
(crystal or oscillator) the relative deviation for periods of more than one TCP is lower than
for one single TCP.
This is especially important for bus cycles using waitstates and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
Data Sheet
60
V1.0, 2002-03
XC161
Derivatives
Timing Parameters
Preliminary
5.2
Table 15
External Clock Drive XTAL1
External Clock Drive Characteristics
(Operating Conditions apply)
Parameter
Symbol
tOSC
t1
t2
t3
t4
Oscillator period
High time2)
Low time2)
Rise time2)
Fall time2)
Limit Values
Unit
min.
max.
SR
20
2501)
ns
SR
6
–
ns
SR
6
–
ns
SR
–
8
ns
SR
–
8
ns
1)
The maximum limit is only relevant for PLL operation to ensure the minimum input frequency for the PLL.
2)
The clock input signal must reach the defined levels VILC and VIHC.
t1
t3
t4
VIHC
0.5 VDDI
VILC
t2
t OSC
MCT05138
Figure 14
External Clock Drive XTAL1
Note: If the on-chip oscillator is used together with a crystal or a ceramic resonator, the
oscillator frequency is limited to a range of 4 MHz to 16 MHz.
It is strongly recommended to measure the oscillation allowance (negative
resistance) in the final target system (layout) to determine the optimum
parameters for the oscillator operation. Please refer to the limits specified by the
crystal supplier.
When driven by an external clock signal it will accept the specified frequency
range. Operation at lower input frequencies is possible but is guaranteed by
design only (not 100% tested).
Data Sheet
61
V1.0, 2002-03
XC161
Derivatives
Timing Parameters
Preliminary
5.3
Testing Waveforms
Input signal
(driven by tester)
Output signal
(measured)
2.0 V
0.8 V
0.45 V
Figure 15
Input Output Waveforms
VLoad + 0.1 V
VOH - 0.1 V
Timing
Reference
Points
VLoad - 0.1 V
VOL + 0.1 V
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs,
but begins to float when a 100 mV change from the loaded VOH / VOL level occurs (I OH / I OL = 20 mA).
MCA00763
Figure 16
Data Sheet
Float Waveforms
62
V1.0, 2002-03
XC161
Derivatives
Timing Parameters
Preliminary
5.4
AC Characteristics
Note: The timing parameters given in this section are based on measurements
done with early silicon.
The next version of this datasheet will provide updated parameters based on
statistical data and characterization done with final production silicon.
Table 16
CLKOUT Reference Signal
Parameter
Symbol
Limits
min.
tc5
tc6
tc7
tc8
tc9
CLKOUT cycle time
CLKOUT high time
CLKOUT low time
CLKOUT rise time
CLKOUT fall time
1)
CC
Unit
max.
40/30/251)
ns
CC 8
–
ns
CC 6
–
ns
CC –
4
ns
CC –
4
ns
The CLKOUT cycle time is influenced by the PLL jitter (given values apply to fCPU = 25/33/40 MHz).
For longer periods the relative deviation decreases.
tc7
tc5
tc6
tc9
tc8
CLKOUT
MCT04415
Figure 17
Data Sheet
CLKOUT Signal Timing
63
V1.0, 2002-03
XC161
Derivatives
Timing Parameters
Preliminary
Variable Memory Cycles
External bus cycles of the XC161 are executed in five subsequent cycle phases (AB, C,
D, E, F). The duration of each cycle phase is programmable (via the TCONCSx
registers) to adapt the external bus cycles to the respective external module (memory,
peripheral, etc.).
The duration of the access phase can optionally be controlled by the external module via
the READY handshake input.
This table provides a summary of the phases and the respective choices for their
duration.
Table 17
Programmable Bus Cycle Phases (see timing diagrams)
Bus Cycle Phase
Parameter
Address setup phase, the standard duration of this tpAB
phase (1 … 2 TCP) can be extended by 0 … 3 TCP
if the address window is changed
tpC
tpD
tpE
tpF
Command delay phase
Write Data setup / MUX Tristate phase
Access phase
Address / Write Data hold phase
Valid Values Unit
1 … 2 (5)
TCP
0…3
TCP
0…1
TCP
1 … 32
TCP
0…3
TCP
Note: The bandwidth of a parameter (minimum and maximum value) covers the whole
operating range (temperature, voltage) as well as process variations. Within a
given device, however, this bandwidth is smaller than the specified range. This is
also due to interdependencies between certain parameters. Some of these
interdependencies are described in additional notes (see standard timing).
Data Sheet
64
V1.0, 2002-03
XC161
Derivatives
Timing Parameters
Preliminary
Table 18
External Bus Cycle Timing (Operating Conditions apply)
Parameter
Symbol
Limits
min.
Unit
max.
Output delay rising edge
Valid for: address, CS, BHE
tc10 CC -1
6
ns
Output delay rising edge
Valid for: RD, WR, ALE
tc11 CC -1
6
ns
Output delay rising edge
Valid for: write data
tc12 CC -1
6
ns
Output delay falling edge
Valid for: address, CS, BHE
tc13 CC -1
10
ns
Output delay falling edge
Valid for: RD, WR, ALE
tc14 CC -1
10
ns
Output delay falling edge
Valid for: write data
tc15 CC -1
10
ns
Output hold time
Valid for: address, CS, BHE
tc16 CC –
2
ns
Output hold time
Valid for: RD, WR, ALE
tc17 CC –
2
ns
Output hold time
Valid for: write data
tc18 CC –
2
ns
Input setup time
Valid for: read data, READY
tc19 SR 15
–
ns
Input hold time
Valid for: read data1), READY
tc20 SR 5
–
ns
Turn off delay
tc21 CC 0
5
ns
1)
Read data are latched with the same (internal) clock edge that triggers the address change and the rising edge
of RD. Therefore address changes before the end of RD have no impact on (demultiplexed) read cycles. Read
data can be removed after the rising edge of RD.
Data Sheet
65
V1.0, 2002-03
XC161
Derivatives
Timing Parameters
Preliminary
tpAB
tpC
tpD
tpE
tpF
CLKOUT
tc11
tc14
ALE
tc10|tc13
A23-A16,
BHE, CSx
High Address
tc14
tc11
tc19
tc20
RD, WR
tc10|tc13
AD15-AD0
(read)
Low Address
tc10|tc13
AD15-AD0
(write)
Figure 18
Data Sheet
tc21
Data In
tc18
tc12|tc15
Low Address
Data Out
Multiplexed Bus Cycle
66
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XC161
Derivatives
Timing Parameters
Preliminary
tpAB
tpC
tpD
tpE
tpF
CLKOUT
tc11
tc14
ALE
tc10|tc13
A23-A0,
BHE, CSx
Address
tc14
tc11
tc19
tc20
RD, WR
D15-D0
(read)
Data In
tc12|tc15
D15-D0
(write)
Figure 19
Data Sheet
tc21
Data Out
Demultiplexed Bus Cycle
67
V1.0, 2002-03
XC161
Derivatives
Timing Parameters
Preliminary
Bus Cycle Control via READY Input
The duration of an external bus cycle can be controlled by the external circuitry via the
READY input signal. The polarity of this input signal can be selected.
Synchronous READY permits the shortest possible bus cycle but requires the input
signal to be synchronous to the reference signal CLKOUT.
Asynchronous READY puts no timing constraints on the input signal but incurs one
waitstate minimum due to the additional synchronization stage. The minimum duration
of an asynchronous READY signal to be safely synchronized must be one CLKOUT
period plus the input setup time.
An active READY signal can be deactivated in response to the trailing (rising) edge of
the corresponding command (RD or WR).
If the next following bus cycle is READY-controlled, an active READY signal must be
disabled before the first valid sample point for the next bus cycle. This sample point
depends on the programmed phases of the next following cycle.
Data Sheet
68
V1.0, 2002-03
XC161
Derivatives
Timing Parameters
Preliminary
tpD
tpE
tpRDY
tpF
CLKOUT
tc14
tc11
RD, WR
tc19
D15-D0
(read)
tc20
Data In
tc21
D15-D0
(write)
Data Out
tc19 tc20 tc19 tc20
READY
Synchronous
Not Rdy
Ready
tc19 tc20 tc19 tc20
READY
Asynchron.
Figure 20
Not Rdy
Ready
READY Timing
Note: If the READY input is sampled inactive at the indicated sampling point (“Not Rdy”)
a READY-controlled waitstate is inserted (tpRDY),
sampling the READY input active at the indicated sampling point (“Ready”)
terminates the currently running bus cycle.
Note the different sampling points for synchronous and asynchronous READY.
This example uses one mandatory waitstate (see tpE) before the READY input is
evaluated.
Data Sheet
69
V1.0, 2002-03
XC161
Derivatives
Timing Parameters
Preliminary
External Bus Arbitration
Table 19
Bus Arbitration Timing (Operating Conditions apply)
Parameter
Symbol
Limits
min.
max.
Unit
Input setup time
Valid for: HOLD input
tc28 SR
15
–
ns
Output delay rising edge
Valid for: HLDA, BREQ
tc29 CC
1
6
ns
Output delay falling edge
Valid for: HLDA
tc30 CC
1
10
ns
Data Sheet
70
V1.0, 2002-03
XC161
Derivatives
Timing Parameters
Preliminary
CLKOUT
tc28
HOLD
tc30
HLDA
BREQ
2)
tc10|tc11
CSx, RD,
WR(L/H)
3)
tc21
Addr, Data,
BHE
1)
Figure 21
External Bus Arbitration, Releasing the Bus
Notes
1)
The XC161 will complete the currently running bus cycle before granting bus access.
2)
This is the first possibility for BREQ to get active.
3)
The CS outputs will be resistive high (pullup) after being driven inactive.
Data Sheet
71
V1.0, 2002-03
XC161
Derivatives
Timing Parameters
Preliminary
3)
CLKOUT
tc28
HOLD
tc29
HLDA
tc29
BREQ
1)
tc10|tc11
CSx, RD,
WR(L/H)
2)
tc10|tc12|tc13|tc15
Addr, Data,
BHE
Figure 22
External Bus Arbitration, (Regaining the Bus)
Notes
1)
This is the last chance for BREQ to trigger the indicated regain-sequence.
Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high.
Please note that HOLD may also be deactivated without the XC161 requesting the bus.
3)
The CS outputs will be resistive high (pullup) before being driven inactive.
5)
The next XC161 driven bus cycle may start here.
Data Sheet
72
V1.0, 2002-03
XC161
Derivatives
Packaging
Preliminary
6
Packaging
0.5
0.22
±0.05 2)
17.5
7˚ MAX.
H
0.6 ±0.15
C
0.08
0.08 M A-B D C 144x
22
+0.08
0.12 -0.03
0.1 ±0.05
1.4 ±0.05
1.6 MAX.
P-TQFP-144-19
(Plastic Metric Quad Flat Package)
0.2 A-B D 144x
0.2 A-B D H 4x
20 1)
D
22
B
20 1)
A
144
1
Index Marking
1)
2)
Figure 23
Does not include plastic or metal protrusion of 0.25 max. per side
Does not include dambar protrusion of 0.08 max. per side
Package Outlines P-TQFP-144-19
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
Dimensions in mm
SMD = Surface Mounted Device
Data Sheet
73
V1.0, 2002-03
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