AP0101AT2L00XPGAH-GEVB_SCHEMATIC.rev2.pdf - 458 KB

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AP0101_81BGA_Adapter_Rev2
D
D
Page
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C
Description
Title Page
Block Diagram
AP0101
Power
Clock and Reset
External Interfaces
BEAGLE/FPGA EXT I/F
FPGA Interface
Configuration Setting
Rev
Who
Date
Description
Rev 0.0
W.B.Foo
06/20/11
Initial.
Rev 0.1
W.B.Foo
08/18/11
Add P5, P51 and P19
Rev 0.2
W.B.Foo
08/19/11
Add U20, R63, Q1 and change P29 to polarized type type connector
Rev 0.3
W.B.Foo
08/23/11
Add P30, P31, P52, P53, R63, Q2, Q3, P8 and R55
Rev 1.0
W.B.Foo
10/10/11
Change Level Translator U11/U12 from PCA9517 to TXB0102
C
& R24/R25 to 2.2K resistor on Pg 5
Rev 1.1
W.B.Foo
10/28/11
Rev 1.2
W.B.Foo
12/19/11
Change test point TP6/TP7/TP8/TP11/TP10 to through hole type
1) Change U16/U24 to single part of U24(SN74AVCH4T245) combine M_TRIG/MCLK_OUT/RST_N_OUT
2) Add power supply for FPGA +1V2_VCCINT/+2V5_VCCA/+VCCIO/+3V3_HVCCIO
3) Add FPGA U32 & Flash Memory U47
4) Change P29 to smallest dimension type connector
B
B
5) Change U21 to TXB0102DCUR and add AND gate logic U27 SN74LVC1G08 FOR Auto-Config Circuit
Rev 1.3
W.B.Foo
01/30/12
1) Add external signal access for FRAME_SYNC
2) Change U31 AP0101 Symbol to non socket type
Rev 1.4
W.B.Foo
02/06/12
Add feedback resistor (R86) for XTAL (Y3)
Rev 1.5
W.B.Foo
02/22/12
Change U11 & U12 from TXB0102DCUR to TXS0102DCUR
Rev 2.0
W.B.Foo
04/25/12
Initial.
1) Change net name of U7 pin 5 VDDREG_ADJ to VCCINT_ADJ
2) Change U47 from N25Q128A13ESF40F to M25P64
Rev 2.1
W.B.Foo
05/03/12
Change SMPTE from J5 pin 15 to J6 pin 10 to support full PIXCLK of 20bit mode
Rev 2.2
W.B.Foo
05/08/12
Add Serial EEPROM (U16) on Host serial
A
A
Title
<Title>
5
4
3
2
Size
C
Document Name
Date:
Monday, May 07, 2012
Rev
2.2
AP0101_81BGA_Adapter
Sheet
1
1
of
9
5
4
3
2
1
Block Diagram
Ext +5V
SUPPLY
To Demo2
To Headboard
D
D
USB +5V SUPPLY
Power Supplies
1.2V
Peripheral
2.5V
3.3V
1.8V/
2.8V
Sensor
1.8V/
2.8V
Peripheral Sensor
3.3V/
2.8V
3.3V/
2.8V
1.2V/
1.8V
EEPROM 64kbit
0xAA (default)
3.3V/
2.8V/2.5V
H_Serial
FPGA
+1V2
+VCCINT +VCCA
+HVCCIO
+HVDDIO_LS
+3.3V +SVDDIO_LS
+VCCIO
DEMO_DOUT[15:0]
+3.3V
S_FV
+OTPM
+VDD_PLL
+DVDD
H_PIXCLK
FB_SENSE
FPGA
DEMO_PIXCLK
C
LDO_O/P
H_LV
+SVDDIO_LS
+VDD_REG
DEMO_LV
+HVDDIO
H_FV
+SVDDIO
+1V8
DEMO_FV
S_LV
Data
Level
Shifter
C
S_PIXCLK
H_DOUT[15:0]
GPIO[2:5]_D[16:19]
DEMO_RST
XMCLK
+SVDDIO_LS
3.3V
+3.3V
RESET_N_OUT
+HVDDIO_LS
S_RST_OUT
Level
Shifter
MCLK_OUT
HCLK_IN
Selector
Header
SCLK_OUT
AP0101 CHIP
M_TRIG
XTAL1
S_TRIG
XTAL
(27MHz)
OSC
(27MHz)
XTAL2
Direct to Sensor
+SVDDIO_LS
+3.3V
B
MR
+3.3V
+HVDDIO_LS
M_Serial
H_RST_N
RESET
(240ms)
3.3V
FRAME_SYNC
+3.3V
+HVDDIO_LS
STANDBY
STANDBY
Header
SADDR
SADDR
Header
TRST_N
TRST_N
Header
HF_SYNC
Selector
Header
S_Serial
B
Beagle_Serial
DEMO_RST
2 wire
Serial
Level
Shifter
13-Pin Headboard Connector
FPGA[2:5]_D[16:19]
26-Pin Headboard Connector
26-Pin Demo2 Connector
13-Pin Demo2 Connector
S_DOUT[11:0]
+HVDDIO_LS
GPIO_1
DEMO_Serial
2 wire
Serial
Level
Shifter
LED
H_Serial
+3.3V
A
Beagle
Connector
Beagle_SPI
+HVDDIO_LS
Level
Shifter
TMS/TCK
TDI/TDO
H_SPI
A
TRST_N
GPIO2~5
Beagle_Serial
SPI_SDI Control
I/O
Expander
SPI EEPROM/Flash
1Mbit
JTAG/GPIO
Title
Block Diagram
DEMO_Serial
5
4
3
2
Size
C
Document Name
Date:
Tuesday, May 08, 2012
Rev
2.2
AP0101_81BGA_Adapter
Sheet
1
2
of
9
5
4
3
2
1
AP0101 IC
P26
HDR3-1x3-P
+VDD_REG
+1V2_VDD
+SVDDIO
+VDD_REG
C22
C21
C20
100nF
100nF
10uF
VDD
C6
C5
C4
C3
C2
C1
100nF
100nF
100nF
100nF
100nF
100nF
HDR2-1x2-P
P19
1
C12
10uF
D
2
D
3
2
1
P19:
Short 1-2 (Default)
+OTPM_VCC
P19:
Close -> Default
+HVDDIO
C108
1uF
+HVDDIO
R61
390
C7
10uF
+HVDDIO
P4 (SADDR):
Pins 2-3(GND) I2C Addr --> 0x90 (default)
Pins 1-2(+HVDDIO) I2C Addr --> 0xBA
R2
10K
C14
C11
10uF
100nF 100nF
C15
P4
1
2
3
HDR2-1x2-P
C
5,8
6
+HVDDIO
P6 (STANDBY) Tri-stage:
Pins 2-3(GND) --> Standby mode
Pins 1-2(+3V3) --> Active mode (default)
Open -> Auto Control by serial
+3V3
R62
10K
R3
10K
5
HCLK_IN
5
5
H_SCL
H_SDA
HCLK_IN
A1
H_SCL
H_SDA
A3
B3
C3
G7
H_RST_N
H_RST_N
SENIN_D[11:0]
SENIN_D[11:0]
STANDBY
3
P6
STDY_BAR1
Q1
BCR108E6327
2
+HVDDIO
HDR3-1x3-P
3,7
R1
10K
P3
1
2
3
P3:
Short 2-3 (Default)
TRST_BAR
HDR3-1x3-P
6
H2
G2
F2
E1
G3
J1
G1
E2
H3
J2
H1
F1
SENIN_D0
SENIN_D1
SENIN_D2
SENIN_D3
SENIN_D4
SENIN_D5
SENIN_D6
SENIN_D7
SENIN_D8
SENIN_D9
SENIN_D10
SENIN_D11
SPI_SDI
SPI_SDI
B4
J9
H8
H9
G8
G9
8
8
8
8
GPIO2_D16
GPIO3_D17
GPIO4_D18
GPIO5_D19
GPIO2_D16
GPIO3_D17
GPIO4_D18
GPIO5_D19
6
HF_SYNC
HF_SYNC
H7
J7
D6
TRST_BAR
5
5
M_SCL
M_SDA
GPIO1_LED
G4
B2
H6
F9
E7
F7
F8
DOUT0
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5
DOUT6
DOUT7
DOUT8
DOUT9
DOUT10
DOUT11
DOUT12
DOUT13
DOUT14
DOUT15
SCLK
SDATA
SADDR
RESET_BAR
DIN0
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
DIN8
DIN9
DIN10
DIN11
DIGITAL IMAGE
SENSOR
SPI_SCLK
SPI_SDO
SPI_CS_BAR
SPI_SDI
XTAL
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
FRAME_VALID_IN
LINE_VALID_IN
PIXCLK_IN
FRAME_VALID_OUT
LINE_VALID_OUT
PIXCLK_OUT
FRAME_SYNC
STNDBY
TRST_BAR
EXT_CLK_OUT
TRIGGER_OUT
M_SCLK
M_SDATA
3,5
C5
D3
D5
E3
E5
E6
F5
F6
R63
10K
RESET_BAR_OUT
EXTCLK
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
+HVDDIO
J5
H5
M_SCL
M_SDA
VDD_REG
GPIO1_LED
GND_REG
2
U31
AP0101-DEMO
LDO_OP
FB_SENSE
D1
RST_N_OUT
E9
E8
D9
D8
C9
C8
B9
B8
A9
A8
A7
B7
B6
A6
B5
A5
H_DATA0
H_DATA1
H_DATA2
H_DATA3
H_DATA4
H_DATA5
H_DATA6
H_DATA7
H_DATA8
H_DATA9
H_DATA10
H_DATA11
H_DATA12
H_DATA13
H_DATA14
H_DATA15
D4
A4
C4
SPI_SCLK
SPI_SDO
SPI_CS_N
A2
XTAL2
H4
J4
J3
SENIN_FV
SENIN_LV
SENIN_PIXCLK
C7
D7
C6
H_FV
H_LV
H_PIXCLK
C1
J8
MCLK_OUT
M_TRIG
H_DATA[15:0]
F3
E4
3
1
C
3,7
3,7
3,7
XTAL2
5
SENIN_FV
SENIN_LV
SENIN_PIXCLK
6
6
6
H_FV
H_LV
H_PIXCLK
8
8
8
MCLK_OUT
M_TRIG
6
6
C17
1uF
B
1
2
3
Q2
BCR108E6327
2
+HVDDIO_LS
HDR3-1x3-P
3
GPIO_BAR
6
8
+1V2_VDD
P8
B
RST_N_OUT
H_DATA[15:0]
SPI_SCLK
SPI_SDO
SPI_CS_N
F4
1
VDD_PLL1
VDD_PLL2
VDD_PLL3
GPIO1_LED
VDDIO_S1
VDDIO_S2
3,5
P17
VDDIO_H1
VDDIO_H2
VCC_OTP
HDR3-1x3-P
C2
G5
SADDR
B1
D2
G6
J6
GRN
VDD1
VDD2
VDD3
VDD4
D3
1
2
3
C8
100nF
Q3
BCR108E6327
2
1
P8 (GPIO1_LED):
Pins 2-3 --> Set to GPO
Pins 1-2 --> Set to GPI
+HVDDIO_LS
+HVDDIO_LS
+HVDDIO_LS
C83
100nF
SPI_CS_N
SPI_CS_N
1
3
7
P7 (SPI Memory Selection):
Jumper 2-3 -> FLASH disable
Jumper 1-2 -> EEPROM disable
VCC
Q
S
W
HOLD VSS
2
10K
R60
10K
4
P7
A
1
2
3
EEPROM_DISABLE
FLASH_DISABLE
U20
M25P05-A
6
5
HDR3-1x3-P
1
3
7
C
D
VCC
Q
S
W
HOLD VSS
SPI_SDI_SEL
8
R67
10K
A
VCC
B
GND
U27
SN74LVC1G08
Y
4
SPI_SDI_BAR
7
8
1
2
VCCB
VCCA
B1
B2
A1
A2
GND
OE
2
0 (DNL)
0 SPI_RST
P25
HDR8-2x4-P
1
3
5
7
SPI_CS_N
SPI_SCLK
SPI_SDO
SPI_SDI_SEL
SPI_CS_N
SPI_SCLK
SPI_SDO
3,7
3,7
3,7
(DNL)
SPI PROGRAMMING CONNECTOR
3
+3V3
5
4
SPI_SDI
6
SPI_EN
SPI_SDI
3,7
P45
10K
R68
2
1
U28
PCA9536
HDR2-1x2-P
GPIO_BAR
STDY_BAR
1.0K
1.0K
1
2
3
5
R69
R70
P5
IO0
IO1
IO2
IO3
VDD
SCL
SDA
VSS
HOST Mode (Default)
P5 = Short 1-2/P45 = Open => SPI_SDI = GND
C98
100nF
8
6
7
DEMO_SCL
DEMO_SDA
5,6,7
5,6,7
4
A
Device Address:0x82
FLASH Mode
P5 = Open/P45 = Open => SPI_SDI = Flash/EEPROM Data
4
AUTO Config Mode
P5 = Short 1-2/P45 = Short 1-2 => SPI_SDI = High Impedance
Serial Control
P5 = Open/P45 = Open => SPI_SDI = Serial control mode type
4
SPI_SDI
R43
EXT_RST R45
EXT_RST
2
4
6
8
R84
10K
U21
TXB0102DCUR
SPI_EN
FLASH_EN
SPI FLASH
(512Kbit)
5
1
2
SPI EEPROM
(1Mbit)
R59
5
3,7
C
D
3
SPI_SCLK
SPI_SDO
8
HDR2-1x2-P
2
1
3,7
3,7
6
5
C82
100nF
+HVDDIO_LS
5,6
C95
100nF
C94
100nF
C110
100nF
U17
M95M01-R
SPI_SCLK
SPI_SDO
+HVDDIO_LS
3
4,6,7
4
4
4
4,5,6,7
4,5,6
4,5,6,7
4
4,8
4,7,8
4,8
4,8
+5V0
+VDD_REG
+SVDDIO
+HVDDIO
+3V3
+SVDDIO_LS
+HVDDIO_LS
+OTPM_VCC
+VCCIO
+3V3_HVCCIO
+1V2_VCCINT
+2V5_VCCA
2
+5V0
+VDD_REG
+SVDDIO
+HVDDIO
+3V3
+SVDDIO_LS
+HVDDIO_LS
+OTPM_VCC
+VCCIO
+3V3_HVCCIO
+1V2_VCCINT
+2V5_VCCA
Title
AP0101 IC
Size
C
Document Name
Date:
Monday, May 07, 2012
Rev
2.2
AP0101_81BGA_Adapter
Sheet
1
3
of
9
5
4
3
2
1
Power
PERIPHERAL SVDDIO_LS SUPPLY
VDD_REG 1.8V SUPPLY
D
+5V0
+5V0
U2
ADP1712AUJZ
+SVDDIO
+VDD_REG
D
+SVDDIO_LS
U3
ADP1714AUJZ-3.3
P9
4
ADJ
GND
EN
3
1
R28
50K
R27
15K
(300mA)
2
C65
10uF
1
2
3
VDDREG_ADJ
1
C35
10uF
HDR3-1x3-P
C66
10uF
IN
3
EN
C36
100nF
AP0101 VDD_REG
5
OUT
GND
3
5
OUT
2
IN
2
1
1
4
TRK
TP2
TESTPAD-SMT40RD
+SVDDIO_LS
C37
10uF
C38
100nF
(300mA)
Adjust to 1.8V (default) & Jumper 1-2
PERIPHERAL HVDDIO_LS SUPPLY
SVDDIO 1.8V or 2.8V SUPPLY
U4
TPS79301
+SVDDIO
+5V0
+HVDDIO
VIN
1
1
3
C67
22pF
5
FB
R29
50K
R30
24K
(200mA)
2
C70
10nF
GND
NR
1
2
3
SVDDIO_ADJ
3
EN
4
C69
10uF
6
VOUT
C40
10uF
HDR3-1x3-P
C68
10uF
C45
100nF
AP0101 Sensor VDDIO
IN
OUT
EN
TRK
2
3
2
1
+HVDDIO_LS
U6
ADP1714AUJZ-3.3
P10
GND
+5V0
5
1
4
TP9
TESTPAD-SMT40RD
+HVDDIO_LS
C39
10uF
C46
100nF
(300mA)
C
C
Adjust to 1.8V (default) or 2.8V & Jumper 1-2
VCCINT 1.2V SUPPLY
+5V0
U7
ADP1712AUJZ
P12
ADJ
2
HVDDIO_ADJ
HDR3-1x3-P
4
3
EN
ADJ
C84
10uF
AP0101 Host VDDIO
1
+VCCIO
R9
50K
R10
15K
(300mA)
C43
10uF
2
C41
10uF
5
5
4
3
1
50K
R40
15K
(300mA)
+5V0
1
2
3
VCCINT_ADJ
R46
2
EN
GND
3
OUT
OUT
HDR3-1x3-P
C88
10uF
FPGA VCC_INT
P20
1
2
3
Adjust to 1.2V (default) & Jumper 1-2
HDR3-1x3-P
FPGA VCCIO
Adjust to 3.3V (default) or 2.8V & Jumper 1-2
VCCA 2.5V SUPPLY
+5V0
B
U10
ADP1712AUJZ
VDD_OTPM 3.3V, 2.8V or 2.5V SUPPLY
P24
U15
TPS79301
C89
10uF
6
3
EN
NR
2
C57
10nF
FB
1
2
3
OTPM_ADJ
1
C48
22pF
5
R12
50K
(200mA)
R14
24K
ADJ
1
2
3
VCCA_ADJ
4
3
1
HDR3-1x3-P
R65
50K
(300mA)
R56
15K
HDR3-1x3-P
C55
10uF
2
4
VOUT
GND
3
C56
10uF
VIN
OUT
EN
2
P14
1
IN
5
C90
10uF
2
3
GND
1
+OTPM_VCC
+5V0
+2V5_VCCA
FPGA VCCA
R4
560
2
3
IN
IN
( Mount LED on bottom side of PCB )
1
2
U5
ADP1712AUJZ
1
5V LED
+1V2_VCCINT
P21
GND
+5V0
1
2
3
HDR2-1x2-P
P11
1
VCCIO & HVDDIO 3.3V or 2.8V SUPPLY
+HVDDIO
B
D1
GRN
Adjust to 2.5V (default) & Jumper 1-2
AP0101 OTPM_VCC
+5V0
External +5V
Adjust to 3.3V (default) or 2.5V/2.8V & Jumper 1-2
+5V0_EXT
P13
+5V0_EXT
1
+5V0_BUS
+5V0_EXT
FD1
C80
22uF
FD2
1
FD3
1
FD4
1
1
3
PERIPHERAL 3.3V SUPPLY
C79
100nF
3
2
1
2
JACK-3-PWR-24V-P
+5V0
FIDUCIAL
FIDUCIAL
FIDUCIAL
FD5
FD6
FD7
1
1
SKIP BLOCK
FD8
1
1
+3V3
U1
LT1763-3.3V
C27
10uF
IN
OUT
SENSE
5
(500mA)
SHDN
BYP
GND1
GND2
GND3
FIDUCIAL
1
1
2
C31
10nF
C29
10uF
+3V3_HVCCIO
Ground Testpoints
P32
3
2
1
TP3
TSTPT-5016
1
HDR3-1x3-P
FPGA_HVCCIO
5
FIDUCIAL
SKIP BLOCK
A
+3V3
4
3
6
7
FIDUCIAL
P15
HDR3-1x3-P
TP1
TESTPAD-SMT40RD
4
3
TP4
TSTPT-5016
1
8
A
6,7
3
3
3
3,5,6,7
5,6
3,5,6,7
3
8
7,8
8
8
+5V0
+VDD_REG
+SVDDIO
+HVDDIO
+3V3
+SVDDIO_LS
+HVDDIO_LS
+OTPM_VCC
+VCCIO
+3V3_HVCCIO
+1V2_VCCINT
+2V5_VCCA
2
+5V0
+VDD_REG
+SVDDIO
+HVDDIO
+3V3
+SVDDIO_LS
+HVDDIO_LS
+OTPM_VCC
+VCCIO
+3V3_HVCCIO
+1V2_VCCINT
+2V5_VCCA
Title
Power
Size
C
Document Name
Date:
Monday, May 07, 2012
Rev
2.2
AP0101_81BGA_Adapter
Sheet
1
4
of
9
5
4
3
2
1
Clock/Reset/I2C Interface
D
D
User Note: P16
Host I2C BUFFER
1
2
3
1
TP7
C73
100nF
Y2
4
1
C74
100nF
VCC
OUT
EN/DIS
GND
3
U13
SN74LVC1G17
CLKGEN
2
5
2
MCLK_IN
27MHz
1
3,6,7
3,6,7
VCC
A
4
Y
NC
R13
HCLK_OUT
33
3
GND
3
+HVDDIO_LS
C61
100nF
R20
10K
R21
10K
7
8
1
DEMO_SCL
DEMO_SDA
DEMO_SCL
DEMO_SDA
2
P22
3
2
1
HCLK_IN
HCLK_IN
TP8
1
+HVDDIO_LS
TSTPT-5000-RED
+3V3
P16
HDR3-1x3-P
+3V3
CLOCK CIRCUIT
: OSC CLK
: DEMO2X CLK
TSTPT-5000-RED
Jumper (1-2)
Jumper (2-3)
C62
100nF
U11
TXS0102DCUR
VCCB
VCCA
B1
B2
A1
A2
GND
OE
R71 R22
10K 10K
R23
10K
3
5
4
H_SCL
H_SDA
H_SCL
H_SDA
3,5
3,5
6
XTAL1
HDR3-1x3-P
6
XMCLK
XMCLK
C71
P22 = Jumper 2-3 & P23 = OPEN;
-> OSCILLATOR/DEMO2X CLK IN
Y3
27MHz
Sensor I2C BUFFER
+3V3
+SVDDIO_LS
P22 = Jumper 1-2 & P23 =
CLOSE;
-> CRYSTAL IN
TP11
C63
C72
R31
10K
R26
10K
R64
10K
C64
100nF
100nF
3
18pF
P23
2
1
XTAL2
XTAL2
3
3
3
HDR2-1x2-P
5
4
M_SCL
M_SDA
M_SCL
M_SDA
6
U12
TXS0102DCUR
VCCA
VCCB
A1
A2
B1
B2
OE
GND
R24
2.2K
R25
2.2K
7
TSTPT-5000-RED
1
4
C
R86
1M
3
Jumper (2-3) : DEMO2X CLK for 20Bit SMPTE
XMCLK: 17.4MHz
TSTPT-5000-RED
1
GND1 GND2
User Note: P16
1
2
18pF
TP10
8
1
C
S_SCL
S_SDA
S_SCL
S_SDA
6
6
2
RESET CIRCUIT
R11
C33
10K
100nF
U25
CAT811
SW7
4
100nF
1
3
VCC
MR
RESET
GND
2
2
PWRST
A
4
Y
B
BOARD_RST
H_SCL
H_SDA
3,5
3,5
GND
1
+3V3
PB-SPST
1
240msec
R42
10K
3,6
TP18TP17
+HVDDIO_LS
C101
100nF
VCC
5
B
2
1
3
C49
U8
SN74LVC1G08
5
+3V3
+HVDDIO_LS
1
R41
10K
TESTPAD-SMT40RD
+3V3
1
+3V3
DEMO_RST
DEMO_RST
TESTPAD-SMT40RD
+3V3
6
EXT_RST
EXT_RST
B
GND
U26
SN74LVC1G08
Y
4
R99
10K
H_RST_N
1
H_RST_N
3,8
TP6
TSTPT-5000-RED
3
2
A
VCC
H_RST_N
R78
10K
R100
10K
U16
24FC64-I/SN
8
C127
10uF
VCC
C130
100nF
4
VSS
SCL
SDA
A0
A1
A2
WP
B
P59
6
5
1
2
3
7
1
2
HDR2-1x2-P
P47
1
2
EP_A0
EP_A1
EP_A2
A0
A1
HDR2-1x2-P
P48
1
2
A2
HDR2-1x2-P
Primary EPPROM Address Switch Settings:
+HVDDIO_LS
+HVDDIO_LS
A2=HIGH,
A2=LOW,
A2=LOW,
A2=HIGH,
+3V3
P29
R36
HDR2-1x2-P
P28
2
P28:
Open -> Default
1
UART_RX
L7
C85
7
5
220nF
9
8
10K
GPIO1_LED
UART_RX R47
0
1
R48
0
11
6
13
CAP
SW
VCC
RXD
TXD
GND
VDD
VL
RIN
ROUT
TIN
TOUT
3
Address
Address
Address
Address
=>
=>
=>
=>
0xAA (default)
0xA2
0xA6
0xAE
MTG
HDR4-1x4-P
4
10
A
12
R49
0
2
R50
0
GPIO2_D16_FPGA
6,8
UART_TX
4,6,7
3,4
3,4
3,4
3,4,6,7
4,6
3,4,6,7
3,4
4,8
4,7,8
4,8
4,8
GND
VEE/EPAD
C87
C86
1uF
5
A0=HIGH;
A0=HIGH;
A0=HIGH;
A0=HIGH;
1uF
VCC
MODE
PS
1
2
3
4
5
6
C75
U18
LTC2801
A
3
UART_TX
10uH
A1=LOW,
A1=LOW,
A1=HIGH,
A1=HIGH,
1uF
4
3
+5V0
+VDD_REG
+SVDDIO
+HVDDIO
+3V3
+SVDDIO_LS
+HVDDIO_LS
+OTPM_VCC
+VCCIO
+3V3_HVCCIO
+1V2_VCCINT
+2V5_VCCA
2
+5V0
+VDD_REG
+SVDDIO
+HVDDIO
+3V3
+SVDDIO_LS
+HVDDIO_LS
+OTPM_VCC
+VCCIO
+3V3_HVCCIO
+1V2_VCCINT
+2V5_VCCA
Title
Clock/Reset/I2C Interface
Size
C
Document Name
Date:
Tuesday, May 08, 2012
Rev
2.2
AP0101_81BGA_Adapter
Sheet
1
5
of
9
5
4
3
2
1
External Interface
+HVDDIO_LS
D
Demo2X I/F
C81
100nF
J6
P18
+5V0_BUS
3
8
5,8
8
TRST_BAR
GPIO4_D18_FPGA
GPIO2_D16_FPGA
GPIO3_D17_FPGA
8
3,5
GPIO5_D19_FPGA
EXT_RST
TRST_BAR
R53
R52
R51
JTDI
JTMS
JTCK
0 JTAG_RTCK
JTDO
J_RST
0
0
0
0
R39
R54
0
R44
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
C60
100nF
HDR20-2x10-P (TSW)
(Internal Use ONLY)
D
Demo2X I/F
8
8
8
8
8
8
DEMO_D4
DEMO_D5
DEMO_D2
DEMO_D3
DEMO_D0
DEMO_D1
8
SMPTE
1
2
3
4
5
6
7
8
9
10
11
12
13
DEMO_D4
DEMO_D5
DEMO_D2
DEMO_D3
DEMO_D0
DEMO_D1
SMPTE
J5
8
8
8
8
8
DEMO_D8
DEMO_D10
DEMO_D12
DEMO_D14
DEMO_D6
8
DEMO_LV
8
3,5,6,7
8
1
3
5
7
9
11
13
15
17
19
21
23
25
DEMO_D8
DEMO_D10
DEMO_D12
DEMO_D14
DEMO_D6
DEMO_LV
DEMO_FV
DEMO_SCL R57
DEMO_FV
DEMO_SCL
0
DEMO_PIXCLK
DEMO_PIXCLK
2
4
6
8
10
12
14
16
18
20
22
24
26
DEMO_D9
DEMO_D11
DEMO_D13
DEMO_D15
DEMO_D7
R58
0
HDR13-1x13-650-P (MTLW)
DEMO_D9
DEMO_D11
DEMO_D13
DEMO_D15
DEMO_D7
8
8
8
8
8
FRAME_SYNC
DEMO_RST
DEMO_SDA
DEMO_RST
DEMO_SDA
5,6
3,5,6,7
XMCLK
XMCLK
5
+HVDDIO_LS
C47
100nF
U14
SN74LVC1G17
HDR26-2x13-540-P
5
P33
1
Parallel Data Level Shifter
(HeadBoard -> AP0101 board )
+3V3
C53
100nF
S_PIXCLK
S_FV
S_LV
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
VCCB1
VCCB2
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
S_DOUT3
S_DOUT7
S_DOUT11
S_DOUT2
S_DOUT6
S_DOUT1
S_DOUT10
S_DOUT4
S_DOUT5
S_DOUT0
S_DOUT9
S_DOUT8
DEMO2X access to SYNC signal (Default):
Close P33 --> Pin 1-2
Open P54
SENIN_D3
SENIN_D7
SENIN_D11
SENIN_D2
SENIN_D6
SENIN_D1
SENIN_D10
SENIN_D4
SENIN_D5
SENIN_D0
SENIN_D9
SENIN_D8
SENIN_PIXCLK
SENIN_FV
SENIN_LV
SENIN_D3
SENIN_D7
SENIN_D11
SENIN_D2
SENIN_D6
SENIN_D1
SENIN_D10
SENIN_D4
SENIN_D5
SENIN_D0
SENIN_D9
SENIN_D8
3
3
3
3
3
3
3
3
3
3
3
3
SENIN_PIXCLK
SENIN_FV
SENIN_LV
3
3
3
4
10
15
21
28
34
39
45
S_TRIG
Operation
B --> A
A --> B
Isolation
+3V3
R34
10K
(DNL)
12
13
10
11
1B2
1B1
2B2
2B1
1A2
1A1
2A2
2A1
1DIR
2DIR
GND1 1OE
GND2 2OE
R35
10K
(DNL)
1
TP12
TSTPT-5000-RED
C77
100nF
1
VCCA
VCCB
1
3
5
7
9
11
13
15
17
19
21
23
25
S_DOUT4
S_DOUT6
S_DOUT8
S_DOUT10
S_DOUT2
S_LV
S_FV
SEN_SCLK
S_PIXCLK
HDR2-1x2-P
DEMO_RST
DEMO_RST
SEN_RST_OUT
S_RST_OUT
3
2
1
S_DOUT5
S_DOUT7
S_DOUT9
S_DOUT11
S_DOUT3
B
SEN_RST_OUT
SEN_SDATA
SCLK_OUT
P50
3,5,6,7
7
5
DEMO_SDA
SEN_SDATA
S_SDA
1
2
3
DEMO_SDA
SEN_SDATA
S_SDA
HDR3-1x3-P
P51
Pins 2 - 3 --- DEMO2X Reset
Pins 1 - 2 --- AP0101 Reset (default)
2
4
6
8
10
12
14
16
18
20
22
24
26
CON26-2x13-J
P51
TSTPT-5000-RED
C111
10nF
U24
SN74AVCH4T245
8
9
5
C
J7
1
2
3
4
5
6
7
8
9
10
11
12
13
CON26-1x13-J
TP13
M_TRIG
MCLK_OUT
RST_N_OUT
3
C76
100nF
J8
S_DOUT0
S_DOUT1
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
DIR
L
H
X
C78
100nF
C109
10nF
3
3
3
HF_SYNC
3
GND
P54
R85
47K
Headboard I/F
5,6
A
NC
4
Y
+5V0
U9
SN74AVC16T245
+SVDDIO_LS
R33
10K
(DNL)
A
Input signal Voltage => 2.8V ~3.3V
1
24
48
25
nOE
L
L
H
R32
10K
(DNL)
VCC
2
1
EXT access to SYNC signal:
Open P33
Input Signal P54 --> Pin 2
10nF
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
1DIR
2DIR
1OE
2OE
B
1
HDR2-1x2-P
C54
100nF
7
18
10nF
C52
2
31
42
C51
FRAME_SYNC_BAR
+SVDDIO_LS
VCCA1
VCCA2
C
2
P49
3,5,6,7
7
5
DEMO_SCL
SEN_SCLK
S_SCL
DEMO_SCL
SEN_SCLK
S_SCL
HDR3-1x3-P
1
2
3
HDR3-1x3-P
P50
Pins 1 - 2 --- DEMO2X serial control
Pins 2 - 3 --- AP0101 serial control (default)
P49
Pins 1 - 2 --- DEMO2X serial control
Pins 2 - 3 --- AP0101 serial control (default)
1
16
5
4
7
6
S_TRIG
SCLK_OUT
S_RST_OUT
A
2
3
15
14
4,7
3,4
3,4
3,4
3,4,5,7
4,5
3,4,5,7
3,4
4,8
4,7,8
4,8
4,8
4
3
+5V0
+VDD_REG
+SVDDIO
+HVDDIO
+3V3
+SVDDIO_LS
+HVDDIO_LS
+OTPM_VCC
+VCCIO
+3V3_HVCCIO
+1V2_VCCINT
+2V5_VCCA
2
+5V0
+VDD_REG
+SVDDIO
+HVDDIO
+3V3
+SVDDIO_LS
+HVDDIO_LS
+OTPM_VCC
+VCCIO
+3V3_HVCCIO
+1V2_VCCINT
+2V5_VCCA
Title
External Interface
Size
C
Document Name
Date:
Monday, May 07, 2012
Rev
2.2
AP0101_81BGA_Adapter
Sheet
1
6
of
9
5
4
3
2
1
BEAGLE/FPGA EXT I/F
D
D
BEAGLE I/F
+5V0
R55
0
+HVDDIO_LS
+3V3
FPGA Memory I/F
P27
1
3
5
7
9
BEAGLE_SCL
BEAGLE_SDA
BEAGLE_SDO
BEAGLE_SCLK
BEAGLE_CS_N
2
4
6
8
10
C106
100nF
C107
100nF
U30
TXB0102DCUR
BEAGLE_SDI
7
HDR10-2x5-P (TSW)
8
1
BEAGLE_SDO
BEAGLE_SDI
2
VCCB
R38
10K
VCCA
B1
B2
A1
A2
GND
OE
+3V3
3
5
4
SPI_SDO
SPI_SDI
SPI_SDO
SPI_SDI
6
1
R79
100
3
3
7,8
6,7
SEN_SCLK
2
SEN_SCLK
C129
R80
100
+3V3
U47
M25P64
16
15
DCLK
HDR2-1x2-P
DEMO_SCL
6,7
SEN_SCLK
R75
4.7K
P52
DEMO_SCL
BEAGLE_SCL
SEN_SCLK
10nF
(DNL)
1
3,5,6
C128
100nF
P43
HDR2-1x2-P
P30
C
DCLK
2
P30
Open --- DEMO2X & Sensor NO accessed (Default)
Closed --- DEMO2X & Sensor accessed
+3V3
(DNL)
1
2
3
Beagle access to SPI Bus:
Open P44
Open P43
HDR3-1x3-P
7,8
ASDO
7,8
nCSO
7
9
1
3
4
5
6
Beagle no access to SPI Bus (Default):
Close P44 --> Pin 1-2
Close P43 --> Pin 1-2
P52
Pins 1 - 2 --- DEMO2X accessed (default)
Pins 2 - 3 --- Sensor accessed Only
C
D
C
VCC
Q
S
W/VPP
HOLD DU_5
DU_6
DU_1 DU_7
DU_2 DU_8
DU_3
DU_4
VSS
2
8
R77
0
DATA0
7,8
11
12
13
14
10
place the Thevenin close to U47
+HVDDIO_LS
+3V3
P31
Open --- DEMO2X & Sensor NO accessed (Default)
Closed --- DEMO2X & Sensor accessed
+3V3_HVCCIO
C105
100nF
P31
6,7
SEN_SDATA
SEN_SDATA
2
C104
100nF
U29
TXB0102DCUR
1
7
HDR2-1x2-P
3,5,6
6,7
DEMO_SDA
SEN_SDATA
P53
DEMO_SDA
BEAGLE_SDA
SEN_SDATA
B
BEAGLE_CS_N
BEAGLE_SCLK
1
2
3
8
1
2
VCCB
VCCA
B1
B2
A1
A2
GND
OE
+3V3
R37
10K
R19
10K
3
5
4
SPI_CS_N
SPI_SCLK
SPI_CS_N
SPI_SCLK
3
3
P36
7,8
8
8
7,8
7,8
6
HDR3-1x3-P
1
P53
Pins 1 - 2 --- DEMO2X accessed (default)
Pins 2 - 3 --- Sensor accessed Only
R74
10K
2
1
3
5
7
9
DCLK
CONF_DONE
nCONFIG
DATA0
ASDO
2
4
6
8
10
nCE
nCSO
B
7,8
R73
10K
HDR10-2x5-P (TSW)
P44
HDR2-1x2-P
8
(DNL)
A
A
4,6
3,4
3,4
3,4
3,4,5,6
4,5,6
3,4,5,6
3,4
4,8
4,8
4,8
4,8
5
4
3
+5V0
+VDD_REG
+SVDDIO
+HVDDIO
+3V3
+SVDDIO_LS
+HVDDIO_LS
+OTPM_VCC
+VCCIO
+3V3_HVCCIO
+1V2_VCCINT
+2V5_VCCA
2
+5V0
+VDD_REG
+SVDDIO
+HVDDIO
+3V3
+SVDDIO_LS
+HVDDIO_LS
+OTPM_VCC
+VCCIO
+3V3_HVCCIO
+1V2_VCCINT
+2V5_VCCA
Title
BEAGLE/FPGA EXT I/F
Size
C
Document Name
Date:
Monday, May 07, 2012
Rev
2.2
AP0101_81BGA_Adapter
Sheet
1
7
of
9
5
4
3
2
1
FPGA Interface
+VCCIO
+VCCIO
+2V5_VCCA
D
D
C122
10uF
C120
C119
100nF
100nF 100nF
U32-2
EP4CE6F17
C121
P4
P7
T1
3
3
H_DATA9
H_DATA7
3
H_DATA11
3
3
3
3
H_DATA10
H_DATA8
H_FV
H_LV
3
H_DATA12
3
3
3
H_DATA6
H_DATA5
H_DATA4
RES_PU90
P6
H_DATA9
H_DATA7
RES_PU52
RES_PU63
RES_PU64
RES_PU72
RES_PU73
RES_PU74
RES_PU79
RES_PU80
RES_PU81
RES_PU82
H_DATA11
RES_PU91
H_DATA10
H_DATA8
H_FV
H_LV
RES_PU98
H_DATA12
RES_PU101
H_DATA6
H_DATA5
H_DATA4
RES_PU102
R4
T4
K8
L7
L8
M6
M7
M8
N3
N5
N6
N8
P3
P8
R3
R5
R6
R7
R8
T2
T3
T5
T6
T7
T8
C126
VCCIO3_1
VCCIO3_2
VCCIO3_3
VCCIO4_1
VCCIO4_2
VCCIO4_3
VREFB3N0
VREFB4N0
IO_B3/ PLL1_CLKOUTp
IO_B3/ PLL1_CLKOUTn
IO_B3/ DIFFIO_B5n
IO_B3/ DQ3B_1
IO_B3/ DIFFIO_B9p/ DQ3B
IO_B3/ DQ3B_2
IO_B3/ DIFFIO_B5p/ DQS3B/CQ3B#
IO_B3/ DIFFIO_B9n/ DM5B/BWS#5B
IO_B3/ DIFFIO_B1p
IO_B3/ DIFFIO_B4p/ DQ3B
IO_B3/ DIFFIO_B4n/ DQ3B
IO_B3/ DIFFIO_B10p/ DQ5B
IO_B3/ DIFFIO_B1n/ DM3B/BWS#3B
IO_B3/ DIFFIO_B10n/ DQ5B
IO_B3/ DIFFIO_B2p/ DQ3B
IO_B3/ DIFFIO_B6p/ DQ3B
IO_B3/ DIFFIO_B7p/ DQ3B
IO_B3/ DIFFIO_B8p/ DQ3B
IO_B3/ DIFFIO_B11p
IO_B3/ DQS1B/CQ1B#,DPCLK2
IO_B3/ DIFFIO_B2n
IO_B3/ DIFFIO_B6n
IO_B3/ DIFFIO_B7n
IO_B3/ DIFFIO_B8n/ DQS5B/CQ5B#
IO_B3/ DIFFIO_B11n
IO_B4/ RUP2
IO_B4/ RDN2
IO_B4/ DIFFIO_B18p
IO_B4/ DIFFIO_B13p
IO_B4/ DIFFIO_B18n
IO_B4/ DIFFIO_B21n
IO_B4/ DIFFIO_B13n
IO_B4/ DIFFIO_B22p
IO_B4/ DIFFIO_B14p
IO_B4/ DIFFIO_B22n
IO_B4/ DIFFIO_B14n/DQ5B
IO_B4/ DIFFIO_B21p
IO_B4/ DQS2B/CQ3B
IO_B4/ DIFFIO_B15p/DQ5B
IO_B4/ DIFFIO_B16p/DQ5B
IO_B4/ DIFFIO_B17p/DQ5B
IO_B4/ DIFFIO_B19p
IO_B4_1
IO_B4/ DIFFIO_B12p
IO_B4/ DIFFIO_B15n/DQS4B/CQ5B
IO_B4/ DIFFIO_B16n
IO_B4/ DIFFIO_B17n/DQ5B
IO_B4/ DIFFIO_B19n/DQ5B
IO_B4/ DIFFIO_B20p/DQ5B
IO_B4/ DIFFIO_B20n/DQS0B/CQ1B,DPCLK3
IO_B4/ DIFFIO_B12n
C124 C123
C125
100nF 100nF 100nF
10uF
U32-6
EP4CE6F17
+1V2_VCCINT
P10
P13
T16
C9
C16
P11
RES_PU93
M10
N11
K10
K9
L10
L11
L9
M11
M9
N12
N9
P14
P9
R10
R11
R12
R13
R14
R9
T10
T11
T12
T13
T14
T15
T9
RES_PU76
RES_PU84
RES_PU54
RES_PU53
RES_PU66
RES_PU67
RES_PU65
RES_PU77
RES_PU75
RES_PU85
RES_PU83
RES_PU94
RES_PU92
H_DATA0
GPIO2_D16_FPGA
GPIO3_D17
GPIO4_D18_FPGA
GPIO4_D18
H_DATA3
H_DATA1
RES_PU103
GPIO5_D19
GPIO3_D17_FPGA
GPIO2_D16
GPIO5_D19_FPGA
H_DATA2
10uF
H_DATA0
GPIO2_D16_FPGA
GPIO3_D17
GPIO4_D18_FPGA
GPIO4_D18
H_DATA3
H_DATA1
3
5,6
3
6
3
3
3
GPIO5_D19
GPIO3_D17_FPGA
GPIO2_D16
GPIO5_D19_FPGA
H_DATA2
3
6
3
6
3
100nF
C10
C13
C18
C19
C23
C24
C25
100nF
100nF
100nF
100nF
100nF
100nF
100nF
H7
H8
H9
H10
J7
J8
J9
J10
B2
B15
C5
C12
D7
D10
E4
E13
+3V3_HVCCIO
C115
10uF
C114
100nF
C102
C99
10uF
100nF
K14
M14
C97
100nF
M15
M16
3,5
H_RST_N
6
SMPTE
RES_PU70
L14
RES_PU87
RES_PU95
RES_PU43
RES_PU44
RES_PU45
RES_PU46
RES_PU55
RES_PU56
RES_PU57
RES_PU99
RES_PU68
RES_PU69
RES_PU71
RES_PU100
RES_PU78
RES_PU86
RES_PU88
H_RST_N
RES_PU96
SMPTE
N14
P15
J11
J12
J13
J14
K11
K12
K15
K16
L12
L13
L15
L16
M12
N13
N15
N16
P16
R16
VCCIO6_1
VCCIO6_2
CLK6/ DIFFCLK_3p
CLK7/ DIFFCLK_3n
CLK4/ DIFFCLK_2p
CLK5/ DIFFCLK_2n
VREFB5N0
VREFB6N0
IO_B5/ RUP3/DM1R/BWS#1R
IO_B6/ DQS0R/CQ1R,DPCLK5
IO_B5/ RDN3/DQ1R
IO_B6/ DIFFIO_R1p
IO_B5_1
IO_B6/ DIFFIO_R1n/DQS2R/CQ3R
IO_B5/ DIFFIO_R6p
IO_B6/ DIFFIO_R2p
IO_B5/ DQ1R_1
IO_B6/ DIFFIO_R2n
IO_B5/ DIFFIO_R6n/DQ1R
IO_B6_1
IO_B5_2
IO_B6_2
IO_B5_3
IO_B5/ DIFFIO_R8p/ DQS1R/CQ1R#,DPCLK4
IO_B5/ DIFFIO_R8n/ DQ1R
IO_B5_4
IO_B5/ DQ1R_2
IO_B5/ DIFFIO_R9p
IO_B5/ DIFFIO_R9n/DQ1R
IO_B5_5
IO_B5_6
IO_B5/ DIFFIO_R10p/DQ1R
IO_B5/ DIFFIO_R10n/DQ1R
IO_B5/ DIFFIO_R11n/DQS3R/CQ3R#
IO_B5/ DIFFIO_R11p/DQ1R
E14
G14
C112
100nF
C103
C113
100nF
10uF
E15
E16
F14
RES_PU41
B16
C15
C16
D15
D16
F13
G11
LOCKED
RES_PU11
RES_PU12
RES_PU23
PIXCLK_X1
RES_PU40
RES_PU105
1
TP15
TESTPAD-SMT40RD
1
TP14
TESTPAD-SMT40RD
RES_PU33
F3
RES_PU4
RES_PU5
RES_PU13
RES_PU15
RES_PU24
RES_PU31
RES_PU32
RES_PU34
RES_PU109
RES_PU110
RES_PU111
B1
C2
D1
D4
E5
F1
F2
F5
G1
G2
G5
C59
10uF
R76
10K
U32-5
EP4CE6F17
+3V3_HVCCIO
R7
10K
R6
10K
(DNL)
R5
10K
6
DEMO_PIXCLK
7
DCLK
RES_PU107
DCLK
(DNL)
7
nCE
nCE
6
DEMO_D14
MSEL0
MSEL1
MSEL2
7
R15
10K
R8
10K
(DNL)
R16
10K
8
8
8
nCONFIG
JTAG_TDI
JTAG_TCK
JTAG_TMS
H2
C1
E8
F8
B7
E7
E6
A5
G15
H1
J3
H13
H12
G12
nCONFIG
H5
JTAG_TDI
JTAG_TCK
JTAG_TMS
H4
H3
J5
IO_B1/ DATA0
IO_B1/ DIFFIO_L1n/DATA1,ASDO
IO_B8/ DIFFIO_T10n/DATA2/DQ3T
IO_B8/ DIFFIO_T10p/DATA3
IO_B8/ DIFFIO_T9p/DATA4/DQ3T
IO_B8/ DATA5/DQ3T
IO_B8/ DATA6/DQ3T
IO_B8/ DIFFIO_T6n/DATA7/DQ3T
CONF_DONE
nSTATUS
IO_B6/ DIFFIO_R4n/INIT_DONE
IO_B5/ DIFFIO_R7n/DEV_OE
IO_B5/ DIFFIO_R7p/DEV_CLRn
IO_B6/ DIFFIO_R3n/nCEO
IO_B6/ DIFFIO_R3p/CLKUSR
IO_B6/ DIFFIO_R4p/CRC_ERROR
DCLK
IO_B1/ DIFFIO_L2p/FLASH_nCE,nCSO
H14
CONF_DONE
F4
G16
nSTATUS
RES_PU108
J16
J15
PIXCLK_X2
RES_PU47
F16
F15
RES_PU42
D2
nCSO
CONF_DONE
1
7
TP5
TESTPAD-SMT40RD
nCSO
7
nCE
MSEL0
MSEL1
MSEL2
nCONFIG
TDI
TCK
TMS
TDO
+3V3_HVCCIO
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
+1V2_VCCINT
N4
D13
+1V2_PLL
M5
E12
C34
C32
C42
100nF
100nF
10uF
FL1
1uF
G4
G13
K4
K13
M4
M13
N7
N10
P5
P12
R2
R15
E2
H16
H15
+VCCIO
VCCIO2_1
VCCIO2_2
CLK1/ DIFFCLK_0n
CLK2/ DIFFCLK_1p
CLK3/ DIFFCLK_1n
VREFB1N0
VREFB2N0
IO_B1/ DQS2L/CQ3L
IO_B1/ DIFFIO_L1p
IO_B1/ DIFFIO_L2n
IO_B1_1
IO_B1_ 2
IO_B1/ DIFFIO_L3n
IO_B1/ DIFFIO_L3p
IO_B1_3
IO_B1/ DIFFIO_L4n
IO_B1/ DIFFIO_L4p/ DQS0L/CQ1L,DPCLK0
IO_B1_ 4
C44
100nF
C50
C117
C116
C118
100nF
100nF
10uF
IO_B2/ RUP1/ DQ1L
IO_B2/ RDN1/ DQ1L
IO_B2/ DIFFIO_L5n/ DQ1L
IO_B2/ DIFFIO_L5p/ DQ1L
IO_B2_1
IO_B2/ DIFFIO_L7n/ DQ1L
IO_B2/ DIFFIO_L7p
IO_B2/ DIFFIO_L6p
IO_B2/ DIFFIO_L8n/ DQ1L
IO_B2/ DIFFIO_L8p/ DQS1L/CQ1L#,DPCLK1
IO_B2/ DIFFIO_L6n
IO_B2/ DIFFIO_L9n/ DQ1L
IO_B2/ DIFFIO_L9p/ DQ1L
IO_B2/ DIFFIO_L10n/ DM1L/BWS#1L
IO_B2/ DIFFIO_L10p/ DQ1L
IO_B2/ DQS3L/CQ3L#
K3
M3
C
M2
M1
H_PIXCLK
L3
RES_PU60
K5
L4
RES_PU50
RES_PU61
J1
J2
J6
K1
K2
K6
L1
L2
L6
N1
N2
P1
P2
R1
RES_PU112
RES_PU113
RES_PU114
RES_PU48
RES_PU49
RES_PU51
RES_PU58
RES_PU59
RES_PU62
H_DATA15
H_DATA14
H_DATA13
RES_PU89
RES_PU97
100nF
U32-4
EP4CE6F17
C58
H_PIXCLK
3
H_DATA15
H_DATA14
H_DATA13
3
3
3
J4
JTAG_TDO
JTAG_TDO
8
6
6
DEMO_D11
DEMO_D8
6
6
6
6
DEMO_D5
DEMO_D10
DEMO_D4
DEMO_D9
6
DEMO_D13
C93
C92
C91
C96
100nF
100nF
100nF
10uF
100nF
A16
C10
C13
DATA0
ASDO
RES_PU27
RES_PU37
DEMO_D14
RES_PU26
RES_PU25
DEMO_PIXCLK
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
10uF
+3V3_HVCCIO
+3V3_HVCCIO
DATA0
ASDO
GNDA1
GNDA2
100nF
+3V3_HVCCIO
B
7
7
VCCD_PLL1
VCCD_PLL2
100nF
L5
F12
VCCIO1_1
VCCIO1_2
E1
+3V3_HVCCIO
VCCIO5_1
VCCIO5_2
VCCA1
VCCA2
C30
U32-1
EP4CE6F17
100nF
E3
G3
U32-3
EP4CE6F17
VCCINT_1
VCCINT_2
VCCINT_3
VCCINT_4
VCCINT_5
VCCINT_6
VCCINT_7
VCCINT_8
C26
C100
C
+3V3_HVCCIO
G6
G7
G8
G9
G10
H6
H11
K7
C28
RES_PU9
C11
RES_PU30
RES_PU29
RES_PU116
RES_PU104
DEMO_D11
DEMO_D8
RES_PU115
RES_PU2
RES_PU3
DEMO_D5
DEMO_D10
DEMO_D4
DEMO_D9
RES_PU105
DEMO_D13
RES_PU10
RES_PU8
RES_PU20
RES_PU21
RES_PU22
RES_PU19
RES_PU28
RES_PU39
RES_PU40
RES_PU38
E11
E10
A14
B14
A10
A11
A12
A13
A15
A9
B10
B11
B12
B13
B9
C14
C9
D11
D12
D14
D9
E9
F10
F11
F9
VCCIO7_1
VCCIO7_2
VCCIO7_3
VCCIO8_1
VCCIO8_2
VCCIO8_3
VREFB7N0
VREFB8N0
IO_B7/ RUP4
IO_B8/ DIFFIO_T5n
IO_B7/ RDN4
IO_B8/ DIFFIO_T2n
IO_B7/ PLL2_CLKOUTn
IO_B8/ DIFFIO_T4n/DM3T/BWS#3T
IO_B7/ PLL2_CLKOUTp
IO_B8/ DIFFIO_T7n/DQS3T/CQ3T#
IO_B7/ DIFFIO_T14n/DQ5T
IO_B8/ DIFFIO_T9n/DQ3T
IO_B7/ DIFFIO_T17n/DQ5T
IO_B8/ DIFFIO_T11n
IO_B7/ DIFFIO_T18n/DQ5T
IO_B8/ DIFFIO_T2p/DQS1T/CQ1T#,DPCLK7
IO_B7/ DIFFIO_T19n
IO_B8/ DIFFIO_T4p
IO_B7/ DIFFIO_T15p
IO_B8/ DIFFIO_T5p/DQ3T
IO_B7/ DIFFIO_T12n
IO_B8/ DIFFIO_T7p/DQ3T
IO_B7/ DIFFIO_T14p/DQ5T
IO_B8/ DIFFIO_T11p
IO_B7/ DIFFIO_T17p/DQ5T
IO_B8/ DIFFIO_T1n
IO_B7/ DIFFIO_T18p/DQ5T
IO_B8/ DQS5T/CQ5T#
IO_B7/ DIFFIO_T19p/DQ5T
IO_B8/ DIFFIO_T1p
IO_B7/ DIFFIO_T12p
IO_B8/ DIFFIO_T3n
IO_B7/ DIFFIO_T21n
IO_B8/ DIFFIO_T3p
IO_B7/ DIFFIO_T13n/DQ5T
IO_B8/ DQ3T
IO_B7/ DIFFIO_T20n
IO_B8/ DIFFIO_T8n
IO_B7/ DIFFIO_T20p/DQS0T/CQ1T,DPCLK6
IO_B8/ DIFFIO_T8p
IO_B7/ DIFFIO_T21p/DQ5T
IO_B7/ DIFFIO_T13p/DM5T/BWS#5T
IO_B7/ DQS4T/CQ5T
IO_B7/ DIFFIO_T16n
IO_B7/ DIFFIO_T15n
IO_B7/ DIFFIO_T16p/DQS2T/CQ3T
A1
C4
C7
B
C6
RES_PU7
A2
A3
A4
A6
A7
A8
B3
B4
B5
B6
B8
C3
C8
D3
D5
D6
D8
F6
F7
RES_PU1
DEMO_LV
DEMO_D0
DEMO_D3
DEMO_D15
DEMO_D12
DEMO_FV
DEMO_D1
DEMO_D6
DEMO_D7
DEMO_D2
RES_PU6
RES_PU7
RES_PU14
RES_PU16
RES_PU17
RES_PU18
RES_PU35
RES_PU36
DEMO_LV
DEMO_D0
DEMO_D3
DEMO_D15
DEMO_D12
DEMO_FV
DEMO_D1
DEMO_D6
DEMO_D7
DEMO_D2
6
6
6
6
6
6
6
6
6
6
+3V3_HVCCIO
+3V3_HVCCIO
A
R18
10K
R72
10K
R66
A
10K
4,6,7
3,4
3,4
3,4
3,4,5,6,7
4,5,6
3,4,5,6,7
3,4
4
4,7
4
4
P2
8
8
8
JTAG_TCK
JTAG_TDO
JTAG_TMS
JTAG_TCK
JTAG_TDO
JTAG_TMS
8
JTAG_TDI
JTAG_TDI
1
3
5
7
9
2
4
6
8
10
HDR10-2x5-P (TSW)
5
4
3
+5V0
+VDD_REG
+SVDDIO
+HVDDIO
+3V3
+SVDDIO_LS
+HVDDIO_LS
+OTPM_VCC
+VCCIO
+3V3_HVCCIO
+1V2_VCCINT
+2V5_VCCA
2
+5V0
+VDD_REG
+SVDDIO
+HVDDIO
+3V3
+SVDDIO_LS
+HVDDIO_LS
+OTPM_VCC
+VCCIO
+3V3_HVCCIO
+1V2_VCCINT
+2V5_VCCA
Title
FPGA Interface
Size
C
Document Name
Date:
Monday, May 07, 2012
Rev
2.2
AP0101_81BGA_Adapter
Sheet
1
8
of
9
5
4
3
2
1
Configuration Setting
D
D
C
C
B
B
A
A
4,6,7
3,4
3,4
3,4
3,4,5,6,7
4,5,6
3,4,5,6,7
3,4
4,8
4,7,8
4,8
4,8
5
4
3
+5V0
+VDD_REG
+SVDDIO
+HVDDIO
+3V3
+SVDDIO_LS
+HVDDIO_LS
+OTPM_VCC
+VCCIO
+3V3_HVCCIO
+1V2_VCCINT
+2V5_VCCA
+5V0
+VDD_REG
+SVDDIO
+HVDDIO
+3V3
+SVDDIO_LS
+HVDDIO_LS
+OTPM_VCC
+VCCIO
+3V3_HVCCIO
+1V2_VCCINT
+2V5_VCCA
2
Title
Configuration Setting
Size
C
Document Name
Date:
Monday, May 07, 2012
Rev
2.2
AP0101_81BGA_Adapter
Sheet
1
9
of
9
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