Low Power, 8-/16-Channel, 31.25 kSPS, 24-Bit, Highly Integrated Sigma-Delta ADC AD7173-8 Data Sheet FEATURES APPLICATIONS Low power, 8-/16-channel, highly integrated multiplexed analog-to-digital converter (ADC) Integration Precision analog input buffers and reference input buffers 2.5 V precision reference (3.5 ppm/°C) Cross point multiplexer (enable system diagnostic) 8 full differential or 16 single-ended channels Clock oscillator GPIO and GPO pins with automatic external mux control Fast and flexible output rate: 1.25 SPS to 31.25 kSPS Channel scan data rate: 6.21 kSPS/channel (161 µs settling) Performance specifications 17.5 noise free bits at 31.25 kSPS 24 noise free bits at 1.25 SPS INL: ±3 ppm/FSR 85 dB rejection of 50 Hz and 60 Hz with 50 ms settling Operates with either 3.3 V or5 V supply Single supply 3.3 V or 5 V AVDD1, 2 V to 5 V AVDD2, and 2 V to 5 V IOVDD Optional split supply AVDD1 and AVSS ± 2.5 V or AVDD1 and AVSS ± 1.65 V Current: 1.4 mA 3-/4-wire serial digital interface (Schmitt trigger on SCLK) CRC error checking SPI, QSPI, MICROWIRE, and DSP compatible Package: 40-lead 6 mm × 6 mm LFCSP Temperature range: −40°C to +105°C Process control: PLC/DCS modules Voltage, current, temperature, and pressure measurement Flow meters Medical and scientific multichannel instrumentation Seismic instrumentation Chemical analysis instrumentation: chromatography GENERAL DESCRIPTION Fast settling, highly accurate, low power, 8-/16-channel, multiplexed ADC for low bandwidth input signals with integrated input buffers. Integrated precision, 2.5 V, low drift (3.5 ppm/°C), band gap reference and integrated oscillator. Eight flexible setups with configurability for output data rate, digital filter mode, offset/gain error correction, reference selection, buffer enables and more. This per channel configurability extends to the output data rate used for each channel when using sinc5 + sinc1 filter. Sinc5 + sinc1 filter maximizes channel scan rate, and sinc3 filter maximizes resolution and enhanced 50 Hz/60 Hz rejection, with four selectable options to maximize rejection. Integrated diagnostic features, including CRC, register checksum, temperature sensor, crosspoint multiplexer, burnout currents, and GPIOs/GPOs. FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD2 REGCAPA BUFFERED PRECISION REFERENCE 1.8V LDO 1.8V LDO REFERENCE INPUT BUFFERS CROSSPOINT MULTIPLEXER AIN0/REF2– IOVDD REGCAPD REF– REF+ REFOUT AVDD AIN1/REF2+ INT REF ANALOG INPUT BUFFERS CS SCLK DIGITAL FILTER Σ-Δ ADC SERIAL INTERFACE AND CONTROL DIN DOUT/RDY SYNC AIN15 AVSS AIN16 I/O AND EXTERNAL MUX CONTROL ERROR XTAL AND INTERNAL CLOCK OSCILLATOR CIRCUITRY AD7173-8 AVSS PDSW GPIO0 GPIO1 GPO2 GPO3 XTAL1 XTAL2/CLKIO DGND 11773-001 TEMPERATURE SENSOR Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013–2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD7173-8 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 General-Purpose I/O ................................................................. 43 Applications ....................................................................................... 1 External Multiplexer Control ................................................... 43 General Description ......................................................................... 1 Delay ............................................................................................ 43 Functional Block Diagram .............................................................. 1 16-Bit/24-Bit Conversions......................................................... 43 Revision History ............................................................................... 3 Serial Interface Reset (DOUT_RESET) .................................. 43 Specifications..................................................................................... 4 Synchronization .......................................................................... 43 Timing Characteristics ................................................................ 8 Error Flags ................................................................................... 44 Absolute Maximum Ratings............................................................ 9 DATA_STAT ............................................................................... 44 Thermal Resistance ...................................................................... 9 IOSTRENGTH Bit ..................................................................... 44 ESD Caution .................................................................................. 9 Grounding and Layout .................................................................. 45 Pin Configuration and Function Descriptions ........................... 10 Register Summary .......................................................................... 46 Typical Performance Characteristics ........................................... 12 Register Details ............................................................................... 48 Noise Performance and Resolution .............................................. 18 Communications Register ......................................................... 48 Getting Started ................................................................................ 19 Status Register ............................................................................. 50 Power Supplies ............................................................................ 20 ADC Mode Register ................................................................... 51 Digital Communication............................................................. 20 Interface Mode Register ............................................................ 52 Configuration Overview ........................................................... 22 Register Check ............................................................................ 53 Circuit Description ......................................................................... 27 Data Register ............................................................................... 53 Analog Input ............................................................................... 27 GPIO Configuration Register ................................................... 54 Reference Options ...................................................................... 29 ID Register................................................................................... 55 Clock Source ............................................................................... 29 Channel Register 0 ..................................................................... 55 Digital Filters ................................................................................... 31 Channel Register 1 to Channel Register 15 ............................ 57 Sinc5 + Sinc1 Filter..................................................................... 31 Setup Configuration Register 0 ................................................ 58 Sinc3 Filter ................................................................................... 32 Single Cycle Settling ................................................................... 33 Setup Configuration Register 1 to Setup Configuration Register 7 ..................................................................................... 59 Enhanced 50 Hz and 60 Hz Rejection Filters ......................... 33 Filter Configuration Register 0 ................................................. 60 Operating Modes ............................................................................ 36 Filter Configuration Register 1 to Filter Configuration Register 7 ..................................................................................... 61 Continuous Conversion Mode ................................................. 36 Continuous Read Mode ............................................................. 37 Single Conversion Mode ........................................................... 38 Standby and Power-Down Modes ............................................ 39 Calibration Modes ...................................................................... 39 Digital Interface .............................................................................. 40 Checksum Protection................................................................. 40 Offset Register 0 ......................................................................... 62 Offset Register 1 to Offset Register 7 ....................................... 62 Gain Register 0............................................................................ 62 Gain Register 1 to Gain Register 7 ........................................... 62 Outline Dimensions ....................................................................... 63 Ordering Guide .......................................................................... 63 CRC Calculation ......................................................................... 41 Integrated Functions ...................................................................... 43 Rev. A | Page 2 of 64 Data Sheet AD7173-8 REVISION HISTORY 4/14—Rev. 0 to Rev. A Changes to General Description and Functional Block Diagram .............................................................................................. 1 Moved Revision History ................................................................... 3 Changes to Figure 18 ......................................................................14 Changes to Getting Started Section ..............................................19 Change to Table 11 ..........................................................................23 Change to Table 17 ..........................................................................29 Changes to Digital Filters Section .................................................31 Replaced Diagnostics Section with Integrated Function Section ..............................................................................................43 Changes to Address 0x02, Table 22 ...............................................46 Changes to Bit 10, Table 26 ............................................................52 Changes to Bits[6:5], Table 35 .......................................................60 10/13—Revision 0: Initial Version Rev. A | Page 3 of 64 AD7173-8 Data Sheet SPECIFICATIONS AVDD1 = 3.0 V to 5.5 V, AVDD2 = 2 V to 5.5 V, IOVDD = 2 V to 5.5 V, AVSS = DGND = 0 V, REF+ = 2.5 V, REF− = AVSS, internal master clock = 2 MHz, TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter ADC SPEED AND PERFORMANCE Output Data Rate (ODR) No Missing Codes 1 Resolution Noise Noise Free Resolution ACCURACY Integral Nonlinearity (INL) Offset Error 2 Offset Drift Offset Drift vs. Time 3 Gain Error2 Gain Drift vs. Temperature1 Gain Drift vs. Time3 REJECTION Power Supply Rejection Common-Mode Rejection At DC At 50 Hz and 60 Hz1 Normal Mode Rejection1 ANALOG INPUTS Differential Input Voltage Range Absolute AIN Voltage Limits1 Buffers Disabled Buffers Enabled Analog Input Current Buffers Enabled Input Current Input Current Drift Buffers Disabled Input Current Input Current Drift Crosstalk INTERNAL REFERENCE Output Voltage Initial Accuracy1 Temperature Coefficient 0°C to +105°C −40°C to +105°C Reference Load Current, ILOAD Test Conditions/Comments Excluding sinc3 filter at 31.25 kSPS See Table 6 See Table 6 Sinc5 + sinc1 filter (default) 31.25 kSPS, REF+ = 5 V 2.6 kSPS, REF+ = 5 V 1.25 SPS, REF+ = 5 V Min Typ 1.25 24 Unit 31250 SPS Bits 17.5 18.4 24 2.5 V reference 5 V reference Internal short Internal short ±3 ±5 ±40 ±350 ±450 ±10 ±0.5 ±3 25°C, AVDD1 = 5 V AVDD1 and AVDD2, VIN = 1 V VIN = 0.1 V 20 SPS ODR (post filter); 50 Hz ± 1 Hz and 60 Hz ± 1 Hz 50 Hz ± 1 Hz and 60 Hz ± 1 Hz Internal clock, 20 SPS ODR (post filter) External clock, 20 SPS ODR (post filter) Max Bits Bits Bits ±7.5 ±50 ±1 90 dB 95 120 71 85 ppm/FSR ppm/FSR µV nV/°C nV/1000 hrs ppm/FSR ppm/FSR/°C ppm/FSR/ 1000 hrs dB dB 90 90 dB dB ±VREF V AVSS − 0.05 AVSS AVDD1 + 0.05 AVDD1 − 1.1 V V Single cycle settling enabled (default) External clock Internal clock (±2.5% clock) 1 kHz input 100 nF external capacitor on REFOUT to AVSS REFOUT with respect to AVSS TA = 25°C 4 ±2 ±25 nA pA/°C ±6 ±0.1 ±0.5 −120 µA/V nA/V/°C nA/V/°C dB 2.5 −0.1 3.5 3.5 IL −10 Rev. A | Page 4 of 64 +0.1 V % of V 8 10 +10 ppm/°C ppm/°C mA Data Sheet Parameter Power Supply Rejection (Line Regulation) Load Regulation Voltage Noise Voltage Noise Density Turn-On Settling Time Long-Term Stability3 Short Circuit EXTERNAL REFERENCE Reference Input Voltage Absolute Reference Input Voltage Limits1 Buffers Disabled Buffers Enabled Average Reference Input Current Buffers Disabled Buffers Enabled Average Reference Input Current Drift External clock Internal clock Normal Mode Rejection1 Common-Mode Rejection TEMPERATURE SENSOR Accuracy Sensitivity BURNOUT CURRENTS Source/Sink Current BRIDGE POWER-DOWN SWITCH RON Allowable Currents GENERAL-PURPOSE I/O (GPIO0, GPIO1, GPO2, GPO3) Input Mode Leakage Current1 Floating State Output Capacitance AVDD1 − AVSS = 5 V Output High Voltage, VOH1 Output Low Voltage, VOL1 Input High Voltage, VIH1 Input Low Voltage, VIL1 AVDD1 − AVSS = 3.3 V Output High Voltage, VOH1 Output Low Voltage, VOL1 Input High Voltage, VIH1 Input Low Voltage, VIL1 CLOCK Internal Clock Frequency Accuracy Duty Cycle Output Low Voltage, VOL Output High Voltage, VOH Crystal Frequency Start-Up Time External Clock (CLKIO) Duty Cycle1 AD7173-8 Test Conditions/Comments AVDD1 and AVDD2 Min ∆VOUT/∆IL eN, 0.1 Hz to 10 Hz eN, 1 kHz 100 nF capacitor 1000 hours ISC Typ 90 Max 140 6.5 215 60 460 25 Reference input = (REF+) − (REF−) 1 2.5 AVSS − 0.05 AVSS Unit dB ppm/mA µV rms nV/√Hz µs ppm mA AVDD1 V AVDD1 + 0.05 AVDD1 V V ±9 ±50 µA/V nA ±5 ±6 nA/V/°C nA/V/°C 83 dB After user calibration at 25°C ±2 477 °C µV/°C Analog input buffers must be enabled ±10 µA Buffers disabled See the Rejection parameter 24 16 Ω mA With respect to AVSS −10 +10 5 ISOURCE = 200 µA ISINK = 800 µA AVSS + 4 AVSS + 0.4 AVSS + 3 AVSS + 0.7 ISOURCE = 200 µA ISINK = 800 µA AVSS + 2.7 V V V V AVSS + 0.45 V V V V +2.5 MHz % AVSS + 0.27 AVSS + 2 2 −2.5 µA pF 50:50 0.4 V V 16.384 MHz µs MHz 0.8 × IOVDD 14 Typical duty cycle 50:50 (maximum:minimum) Rev. A | Page 5 of 64 30:70 16 10 2 50:50 2.048 70:30 AD7173-8 Parameter LOGIC INPUTS Input High Voltage, VINH1 Input Low Voltage, VINL1 Hysteresis1 Leakage Currents LOGIC OUTPUT (DOUT/RDY) Output High Voltage, VOH1 Output Low Voltage, VOL1 Leakage Current Output Capacitance SYSTEM CALIBRATION1 Full-Scale Calibration Limit Zero-Scale Calibration Limit Input Span POWER REQUIREMENTS Power Supply Voltage AVDD1 − AVSS AVDD2 − AVSS AVSS − DGND IOVDD − DGND IOVDD − AVSS POWER SUPPLY CURRENTS Full Operating Mode AVDD1 Current AVDD1 = 5 V Typical, 5.5 V Maximum AVDD1 = 3.3 V Typical, 3.6 V Maximum1 AVDD2 Current IOVDD Current Standby Mode Standby (LDO on) Power-Down Mode Data Sheet Test Conditions/Comments Min 2 V ≤ IOVDD ≤ 2.3 V 2.3 V ≤ IOVDD ≤ 5.5 V 2 V ≤ IOVDD ≤ 2.3 V 2.3 V ≤ IOVDD ≤ 5.5 V IOVDD > 2.7 V IOVDD < 2.7 V 0.65 × IOVDD 0.7 × IOVDD Typ 0.08 0.04 −10 IOVDD ≥ 4.5 V, ISOURCE = 1 mA 2.7 V ≤ IOVDD < 4.5 V, ISOURCE = 500 μA IOVDD < 2.7 V, ISOURCE = 200 μA IOVDD ≥ 4.5 V, ISINK = 2 mA 2.7 V ≤ IOVDD < 4.5 V, ISINK = 1 mA IOVDD < 2.7 V, ISINK = 400 μA Floating state Floating state Max Unit 0.35 × IOVDD 0.7 0.25 0.2 +10 V V V V V V µA 0.8 × IOVDD 0.8 × IOVDD 0.8 × IOVDD 0.4 0.4 0.4 +10 −10 10 1.05 × FS V V V V V V µA pF 2.1 × FS V V V 5.5 5.5 0 5.5 6.35 V V V V V 0.23 0.27 mA 0.42 0.49 mA 2.12 2.71 mA 0.945 1.22 mA 0.16 0.19 mA 0.34 0.4 mA 1.9 2.45 mA −1.05 × FS 0.8 × FS 3.0 2 −2.75 2 For AVSS < DGND All outputs unloaded AIN± and REF± buffers disabled; external reference AIN± and REF± buffers disabled; internal reference AIN± and REF± buffers enabled; external reference Each enabled buffered pair: AIN+, AIN− and REF+, REF− AIN± and REF± buffers disabled; external reference AIN± and REF± buffers disabled; internal reference AIN± and REF± buffers enabled; external reference Each enabled buffered pair: AIN+, AIN− and REF+, REF− External reference Internal reference External clock Internal clock External crystal 0.87 1.13 mA 1 1.25 0.24 0.52 0.9 1.15 1.4 0.39 0.76 mA mA mA mA mA Reference off, total current consumption Reference on, total current consumption Full power-down, LDO, REF± 25 400 2 Rev. A | Page 6 of 64 10 µA µA µA Data Sheet Parameter POWER DISSIPATION Full Operating Mode Standby Mode Power-Down Mode AD7173-8 Test Conditions/Comments Unbuffered, external clock and reference; AVDD1 = 3.3 V, AVDD2 = 2 V, IOVDD = 2 V Unbuffered, external clock and reference; all supplies = 5 V Unbuffered, external clock and reference; all supplies = 5.5 V Fully buffered, internal clock and reference (note that REFOUT has no load); AVDD1 = 3.3 V, AVDD2 = 2 V, IOVDD = 2 V Fully buffered, internal clock and reference (note that REFOUT has no load); all supplies = 5V Fully buffered, internal clock and reference (note that REFOUT has no load); all supplies = 5.5 V Reference off, all supplies = 5 V Reference on, all supplies = 5 V Full power-down, all supplies = 5 V Full power-down, all supplies = 5.5 V Min Typ Max Unit 3 mW 7.35 mW 9.96 mW 10.4 mW 20.4 mW 28 mW 55 µW mW µW µW 125 2 10 Specification is not production tested but is supported by characterization data at the initial product release. Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed output data rate selected. A system full-scale calibration reduces the gain error to the order of the noise for the programmed output data rate. 3 This specification is noncumulative and includes MSL preconditioning effects. 4 This specification includes MSL preconditioning effects. 1 2 Rev. A | Page 7 of 64 AD7173-8 Data Sheet TIMING CHARACTERISTICS IOVDD = 2 V to 5.5 V, DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = IOVDD, CLOAD = 20 pF, unless otherwise noted. Table 2. Parameter SCLK PULSE WIDTH t3 t4 READ OPERATION t1 t2 3 t5 5 t6 t7 WRITE OPERATION t8 t9 t10 t11 Limit at TMIN, TMAX Unit Test Conditions/Comments 1, 2 25 25 ns min ns min SCLK high pulse width SCLK low pulse width 0 15 40 0 12 25 2.5 20 0 10 ns min ns max ns max ns min ns max ns max ns min ns max ns min ns min CS falling edge to DOUT/RDY active time IOVDD = 4.5 V to 5.5 V IOVDD = 2 V to 3.6 V SCLK active edge to data valid delay 4 IOVDD = 4.5 V to 5.5 V IOVDD = 2 V to 3.6 V Bus relinquish time after CS inactive edge 0 8 8 5 ns min ns min ns min ns min CS falling edge to SCLK active edge setup time4 Data valid to SCLK edge setup time Data valid to SCLK edge hold time CS rising edge to SCLK edge hold time SCLK inactive edge to CS inactive edge SCLK inactive edge to DOUT/RDY high/low Sample tested during initial release to ensure compliance. See Figure 2 and Figure 3. The time required for the output to cross the VOL or VOH limits. 4 The SCLK active edge is the falling edge of SCLK. 5 RDY returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high. It is important to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the digital word can be read only once. 1 2 3 Timing Diagrams CS (I) t6 t1 t5 MSB DOUT/RDY (O) LSB t7 t2 t3 11773-002 SCLK (I) t4 I = INPUT, O = OUTPUT Figure 2. Read Cycle Timing Diagram CS (I) t11 t8 SCLK (I) t9 t10 MSB LSB I = INPUT, O = OUTPUT Figure 3. Write Cycle Timing Diagram Rev. A | Page 8 of 64 11773-003 DIN (I) Data Sheet AD7173-8 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. THERMAL RESISTANCE Table 3. θJA is specified for a device soldered on a JEDEC test board for surface-mount packages. The values listed in Table 4 are based on simulated data. Parameter AVDD1, AVDD2 to AVSS AVDD1 to DGND IOVDD to DGND IOVDD to AVSS AVSS to DGND Analog Input Voltage to AVSS Reference Input Voltage to AVSS Digital Input Voltage to DGND Digital Output Voltage to DGND AIN[16:0] or Digital Input Current Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Lead Soldering, Reflow Temperature ESD Rating (HBM) Rating −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to +7.5 V −3.25 V to +0.3 V −0.3 V to AVDD1 + 0.3 V −0.3 V to AVDD1 + 0.3 V −0.3 V to IOVDD + 0.3 V −0.3 V to IOVDD + 0.3 V 10 mA −40°C to +105°C −65°C to +150°C 150°C 260°C 4 kV Table 4. Thermal Resistance Package Type 40-Lead, 6 mm × 6 mm LFCSP 1-Layer JEDEC Board 4-Layer JEDEC Board 4-Layer JEDEC Board with 16 Thermal Vias ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. A | Page 9 of 64 θJA Unit 114 54 34 °C/W °C/W °C/W AD7173-8 Data Sheet 40 39 38 37 36 35 34 33 32 31 REF+ REF– GPO3 AIN15 AIN14 AIN13 AIN12 AIN11 AIN10 AIN9 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 AD7173-8 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 AIN8 AIN7 AIN6 AIN5 AIN4 GPO2 GPIO1 GPIO0 REGCAPD DGND NOTES 1. THE EXPOSED PAD SHOULD BE SOLDERED TO A SIMILAR PAD ON THE PCB UNDER THE EXPOSED PAD TO CONFER MECHANICAL STRENGTH AND FOR HEAT DISSIPATION. THE EXPOSED PAD MUST BE CONNECTED TO AVSS THROUGH THIS PAD ON THE PCB. 11773-004 PDSW XTAL1 XTAL2/CLKIO DOUT/RDY DIN SCLK CS ERROR SYNC IOVDD 11 12 13 14 15 16 17 18 19 20 AIN16 AIN0/REF2– AIN1/REF2+ AIN2 AIN3 REFOUT REGCAPA AVSS AVDD1 AVDD2 Figure 4. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 Mnemonic AIN16 AIN0/REF2− Type 1 AI AI 3 AIN1/REF2+ AI 4 5 6 7 8 9 10 11 12 13 AIN2 AIN3 REFOUT REGCAPA AVSS AVDD1 AVDD2 PDSW XTAL1 XTAL2/CLKIO AI AI AO AO P P P AO AI AI/DI 14 DOUT/RDY DO Description Analog Input 16. Selectable through cross point mux. Analog Input 0 (AIN0)/Reference 2, Negative Input (REF2−). An external reference can be applied between REF2+ and REF2−. REF2− can span from AVSS to AVDD1 − 1 V. Analog Input 0 is selectable through cross point mux. Reference 2 can be selected through the REFSEL bits in the setup configuration register. Analog Input 1 (AIN0)/Reference 2, Positive Input (REF2+). An external reference can be applied between REF2+ and REF2−. REF2+ can span from AVDD1 to AVSS + 1 V. Analog Input 1 is selectable through cross point mux. Reference 2 can be selected through the REFSEL bits in the setup configuration register. Analog Input 2. Selectable through cross point mux. Analog Input 3. Selectable through cross point mux. Buffered Output of Internal Reference. The output is 2.5 V with respect to AVSS. Analog LDO Regulator Output. Decouple this pin to AVSS using a 1 µF capacitor. Negative Analog Supply. This supply ranges from 0 V to −2.75 V and is nominally set to 0 V. Analog Supply Voltage 1. This voltage ranges from 3.0 V minimum to 5.5 V maximum with respect to AVSS. Analog Supply Voltage 2. This voltage ranges from 2 V to AVDD1 with respect to AVSS. Power-Down Switch Connected to AVSS. This pin is controlled by the PDSW bit in the GPIOCON register. Input 1 for Crystal. Input 2 for Crystal (XTAL2)/Clock Input or Output (CLKIO). See the CLOCKSEL bit settings in the ADCMODE register (Table 25) for more information. Serial Data Output (DOUT)/Data Ready Output (RDY). This pin serves a dual purpose. It functions as a serial data output pin to access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data or control registers. The data-word/control word information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. When CS is high, the DOUT/RDY output is tristated. When CS is low, and a register is not being read, DOUT/RDY operates as a data ready pin, going low to indicate the completion of a conversion. If the data is not read after the conversion, the pin goes high before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available. Rev. A | Page 10 of 64 Data Sheet AD7173-8 Pin No. 15 Mnemonic DIN Type 1 DI 16 SCLK DI 17 CS DI 18 ERROR DI/O 19 SYNC DI 20 IOVDD P 21 22 DGND REGCAPD P AO 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 GPIO0 GPIO1 GPO2 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 AIN12 AIN13 AIN14 AIN15 GPO3 REF− DI/O DI/O DO AI AI AI AI AI AI AI AI AI AI AI AI DO AI 40 REF+ AI EP P 1 Description Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control registers in the ADC, with the register address (RA) bits of the communications register identifying the appropriate register. Data is clocked in on the rising edge of SCLK. Serial Clock Input. This serial clock input is for data transfers to and from the ADC. SCLK has a Schmitt trigger input, making the interface suitable for opto-isolated applications. Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in systems with more than one device on the serial bus. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and DOUT used to interface with the device. When CS is high, the DOUT/RDY output is tristated. This pin can be used in one of the following three modes: Active low error input mode. This mode sets the ADC_ERROR bit in the STATUS register. Active low, open-drain error output mode. The STATUS register error bits are mapped to the ERROR pin. The ERROR pins of multiple devices can be wired together to a common pull-up resistor so that an error on any device can be observed. General-purpose output mode. The status of the pin is controlled by the ERR_DAT bit in the GPIOCON register. The pin is referenced between IOVDD and DGND, as opposed to the AVDD1 and AVSS levels used by the GPIO1 and GPIO2 pins. The ERROR pin has an active pull-up in this case. Synchronization Input. Allows synchronization of the digital filters and analog modulators when using multiple AD7173-8 devices. Digital I/O Supply Voltage. IOVDD voltage ranges from 2 V to 5 V. IOVDD is independent of AVDD1 and AVDD2. For example, IOVDD can be operated at 3.3 V when AVDD1 or AVDD2 equals 5 V, or vice versa. If AVSS is set to −2.5 V, the voltage on IOVDD must not exceed 3.6 V. Digital Ground. Digital LDO Regulator Output. This pin is for decoupling purposes only. Decouple this pin to DGND using a 1 µF capacitor. General-Purpose Input/Output. Logic input/output on this this pin is referred to the AVDD1 and AVSS supplies. General-Purpose Input/Output. Logic input/output on this this pin is referred to the AVDD1 and AVSS supplies. General-Purpose Output. Logic output on this this pin is referred to the AVDD1 and AVSS supplies. Analog Input 4. Selectable through cross point mux. Analog Input 5. Selectable through cross point mux. Analog Input 6. Selectable through cross point mux. Analog Input 7. Selectable through cross point mux. Analog Input 8. Selectable through cross point mux. Analog Input 9. Selectable through cross point mux. Analog Input 10. Selectable through cross point mux. Analog Input 11. Selectable through cross point mux. Analog Input 12. Selectable through cross point mux. Analog Input 13. Selectable through cross point mux. Analog Input 14. Selectable through cross point mux. Analog Input 15. Selectable through cross point mux. General-Purpose Output. Logic output on this this pin is referred to the AVDD1 and AVSS supplies. Reference 1 Input Negative Terminal. REF− can span from AVSS to AVDD1 − 1 V. Reference 1 can be selected through the REFSEL bits in the SETUP CONFIGURATION register. Reference 1 Input Positive Terminal. An external reference can be applied between REF+ and REF−. REF+ can span from AVDD1 to AVSS + 1 V. Reference 1 can be selected through the REFSEL bits in the SETUP CONFIGURATION register. Exposed Pad. The exposed pad should be soldered to a similar pad on the PCB under the exposed paddle to confer mechanical strength to the package and for heat dissipation. The exposed pad must be connected to AVSS through this pad on the PCB. AI = analog input, AO = analog output, DI/O = bidirectional digital input/output, DO = digital output, DI = digital input, P = power supply. Rev. A | Page 11 of 64 AD7173-8 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS AVDD1 = 5 V, AVDD2 = 5 V, IOVDD = 3.3 V, unless otherwise noted. 8388539 700 600 500 ADC CODE OCCURRENCE 8388538 400 300 8388537 200 0 100 200 300 400 500 600 700 800 900 1000 SAMPLE 0 11773-005 8388536 8388536 8388537 8388538 ADC CODE 8388539 11773-008 100 Figure 8. Noise Distribution Histogram (Output Data Rate = 1.25 SPS, Analog Input Buffers Disabled)) Figure 5. Noise (Output Data Rate = 1.25 SPS, Analog Input Buffers Disabled) 8388551 600 500 ADC CODE OCCURRENCE 8388550 400 300 200 8388549 0 100 200 300 400 500 600 700 800 900 1000 SAMPLE 0 11773-006 8388548 8388548 8388549 8388550 8388551 ADC CODE Figure 6. Noise (Output Data Rate = 1.25 SPS, Analog Input Buffers Enabled) 11773-009 100 Figure 9. Noise Distribution Histogram (Output Data Rate = 1.25 SPS, Analog Input Buffers Enabled) 8388580 60 8388570 50 8388560 OCCURRENCE 40 8388540 8388530 8388520 30 20 8388510 10 8388500 100 200 300 400 500 600 700 800 900 1000 SAMPLE 0 ADC CODE Figure 7. Noise (Output Data Rate = 10 kSPS, Analog Input Buffers Disabled) Figure 10. Noise Distribution Histogram (Output Data Rate = 10 kSPS, Analog Input Buffers Disabled)) Rev. A | Page 12 of 64 11773-010 0 8388499 8388502 8388505 8388508 8388511 8388514 8388517 8388520 8388523 8388526 8388529 8388532 8388535 8388538 8388541 8388544 8388547 8388550 8388553 8388556 8388559 8388562 8388565 8388568 8388571 8388574 8388490 11773-007 ADC CODE 8388550 Data Sheet AD7173-8 8388610 50 8388600 45 8388590 40 8388580 35 OCCURRENCE ADC CODE 8388570 8388560 8388550 8388540 30 25 20 15 8388530 10 8388520 5 8388510 300 400 500 600 700 800 900 1000 SAMPLE NUMBER 0 ADC CODE Figure 14. Noise Distribution Histogram (Output Data Rate = 10 kSPS, Analog Input Buffers Enabled)) 8388580 45 8388570 40 8388560 35 8388550 30 OCCURRENCE 8388540 8388530 8388520 25 20 15 8388510 10 8388500 5 100 200 300 400 500 600 700 800 900 1000 SAMPLE NUMBER 0 11773-012 8388490 8388497 8388500 8388503 8388506 8388509 8388512 8388515 8388518 8388521 8388524 8388527 8388530 8388533 8388536 8388539 8388542 8388545 8388548 8388551 8388554 8388557 8388560 8388563 8388566 8388569 8388572 8388575 ADC CODE Figure 11. Noise (Output Data Rate = 10 kSPS, Analog Input Buffers Enabled) 0 11773-014 200 ADC CODE 11773-015 100 8388506 8388510 8388514 8388518 8388522 8388526 8388530 8388534 8388538 8388542 8388546 8388550 8388554 8388558 8388562 8388566 8388570 8388574 8388578 8388582 8388586 8388590 8388594 8388598 0 11773-011 8388500 Figure 15. Noise Distribution Histogram (Output Data Rate = 31.25 kSPS, Analog Input Buffers Disabled) Figure 12. Noise (Output Data Rate = 31.25 kSPS, Analog Input Buffers Disabled) 40 8388620 35 8388600 30 OCCURRENCE 8388560 8388540 8388520 25 20 15 10 8388500 5 100 200 300 400 500 600 700 800 900 1000 SAMPLE NUMBER 0 ADC CODE Figure 13. Noise (Output Data Rate = 31.25 kSPS, Analog Input Buffers Enabled) Figure 16. Noise Distribution Histogram (Output Data Rate = 31.25 kSPS, Analog Input Buffers Enabled) Rev. A | Page 13 of 64 11773-016 0 8388494 8388499 8388504 8388509 8388514 8388519 8388524 8388529 8388534 8388539 8388544 8388549 8388554 8388559 8388564 8388569 8388574 8388579 8388584 8388589 8388594 8388599 8388604 8388609 8388480 11773-013 ADC CODE 8388580 AD7173-8 Data Sheet 14 0 –20 12 –40 AMPLITUDE (dB) –60 8 6 BUFFER ON, DEVICE 1 BUFFER OFF, DEVICE 1 BUFFER ON, DEVICE 2 BUFFER OFF, DEVICE 2 BUFFER ON, DEVICE 3 BUFFER OFF, DEVICE 3 1 2 3 4 –160 –180 5 VCM (V) –200 0 –20 16 –40 14 –60 AMPLITUDE (dB) 0 18 12 10 8 1.5 2.0 2.5 3.0 3.5 FREQUENCY (kHz) 4.0 4.5 5.0 –80 –120 –140 4 –160 2 –180 0 1 1.0 –100 6 2 FREQUENCY (MHz) –200 11773-018 0 2 4 6 8 10 12 14 FREQUENCY (kHz) Figure 21. ADC Output FFT; 1 kHz Input Tone, −0.5 dBFS Input FFT (Output Data Rate = 31.25 kSPS, External Reference, External Clock, Buffers Enabled) Figure 18. RMS Noise vs. Master Clock Frequency (Output Data Rate = 31.25 kSPS, Analog Input Buffers Enabled) 0 0 –20 –20 –40 –40 –60 AMPLITUDE (dB) –60 –80 –100 –120 –80 –100 –120 –140 –140 –160 –160 –180 –180 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 FREQUENCY (kHz) 4.0 4.5 5.0 11773-019 –200 –200 0 2 4 6 8 10 12 14 FREQUENCY (kHz) Figure 22. ADC Output FFT; 1 kHz Input Tone, −6 dBFS Input FFT (Output Data Rate = 31.25 kSPS, External Reference, External Clock, Buffers Enabled) Figure 19. ADC Output FFT; 1 kHz Input Tone, −0.5 dBFS Input FFT (Output Data Rate = 10 kSPS, External Reference, External Clock, Buffers Enabled) Rev. A | Page 14 of 64 11773-022 RMS NOISE (µV) 20 0 0.5 Figure 20. ADC Output FFT; 1 kHz Input Tone, −6 dBFS Input FFT (Output Data Rate = 10 kSPS, External Reference, External Clock, Buffers Enabled) Figure 17. RMS Noise vs. Common-Mode Input Voltage AMPLITUDE (dB) –120 –140 0 0 –100 11773-020 2 –80 11773-021 4 11773-017 RMS NOISE (µV) 10 Data Sheet AD7173-8 1.0 0 UNIT 1 BUFFERS OFF UNIT 1 BUFFERS ON UNIT 2 BUFFERS OFF UNIT 2 BUFFERS ON UNIT 3 BUFFERS OFF UNIT 3 BUFFERS ON –20 0.5 –40 REJECTION (dB) ERROR (%) FROM POWER-DOWN 0 FROM STANDBY – REFERENCE OFF –60 –80 –100 –0.5 0.0001 0.001 0.01 0.1 TIME (Seconds) –140 11773-023 –1.0 0.00001 0 50k 100k 150k 200k FREQUENCY (Hz) Figure 23. Internal Reference Settling Time 11773-026 –120 Figure 26. Common-Mode Rejection Ratio vs. Frequency (Output Data Rate = 31.25 kSPS) 0.10 0 –20 UNIT UNIT UNIT UNIT 0.05 REJECTION (dB) ERROR (%) –40 0 1 BUFFERS OFF 1 BUFFERS ON 2 BUFFERS OFF 2 BUFFERS ON –60 –80 –100 –0.05 0 10 20 30 40 50 TIME (Seconds) –100 –105 UNIT 1 BUFFERS OFF UNIT 1 BUFFERS ON UNIT 2 BUFFERS ON UNIT 3 BUFFERS ON REJECTION (dB) –115 –120 –125 –130 –140 20 30 40 FREQUENCY (Hz) 50 60 70 11773-025 –135 10 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 27. Power Supply Rejection Ratio vs. Frequency Figure 24. Internal Reference Settling Time (Extended) –110 –140 Figure 25. Common-Mode Rejection Ratio (10 Hz to 70 Hz) vs. Frequency (20 SPS Enhanced Filter) Rev. A | Page 15 of 64 10M 11773-027 –0.10 11773-024 –120 AD7173-8 Data Sheet 10 6 9 INL ERROR (ppm) 8 4 3 2 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 6 5 4 2 1 5.0 0 –40 –30 –20 –10 REFERENCE VOLTAGE (V) 0 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (°C) Figure 28. Integral Nonlinearity (INL) Error vs. Reference Voltage (Differential Input, External Reference) 11773-031 1 7 3 BUFFER ON, DEVICE 1 BUFFER OFF, DEVICE 1 BUFFER ON, DEVICE 2 BUFFER OFF, DEVICE 2 BUFFER ON, DEVICE 3 BUFFER OFF, DEVICE 3 11773-028 INL ERROR (ppm) 5 Figure 31. Integral Nonlinearity (INL) Error vs. Temperature (Differential Input, VREF = 2.5 V) 30 16.02 16.00 15.98 20 FREQUENCY (Hz) OCCURRENCE 25 15 10 15.96 15.94 15.92 15.90 DEVICE 1 DEVICE 2 DEVICE 3 15.88 15.86 5 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 INL ERROR (ppm) 15.82 –40 11773-029 0 –20 0 20 40 60 80 100 TEMPERATURE (°C) 11773-032 15.84 Figure 32. Internal Oscillator Frequency vs. Temperature Figure 29. Integral Nonlinearity (INL) Distribution Histogram (Differential Input, VREF = 2.5 V External) 2.5010 25 2.5008 2.5006 REFERENCE VOLTAGE (V) 15 10 2.5004 2.5002 2.5000 2.4998 DEVICE 1 DEVICE 2 DEVICE 3 2.4996 2.4994 5 0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 INL ERROR (ppm) 2.4990 –40 –20 0 20 40 60 80 TEMPERATURE (°C) Figure 30. Integral Nonlinearity (INL) Distribution Histogram (Differential Input, VREF = 5 V External) Figure 33. Internal Reference Voltage vs. Temperature Rev. A | Page 16 of 64 100 11773-033 2.4992 11773-030 OCCURRENCE 20 Data Sheet AD7173-8 16 9 14 8 7 OCCURRENCE OCCURRENCE 12 10 8 6 6 5 4 3 4 0 –48 –46 –44 –42 –40 –38 –36 –34 –32 –30 –28 –26 –24 –22 –20 –18 VOLTAGE (µV) 0 –0.08 –0.06 –0.04 –0.02 0 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 0.22 0.24 0.26 0.28 0.30 0.32 0.34 0.36 0.38 0.40 11773-034 1 GAIN ERROR DRIFT (ppm/°C) Figure 34. Offset Error Distribution Histogram (Internal Short) 11773-037 2 2 Figure 37. Gain Error Drift Distribution Histogram 6 7 6 5 CURRENT (mA) 4 3 4 3 DEVICE 1 DEVICE 2 DEVICE 3 2 2 1 1 300 350 400 450 OFFSET DRIFT (nV/°C) 0 –40 –30 –20 –10 11773-035 0 250 0 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (°C) Figure 35. Offset Error Drift Distribution Histogram (Internal Short) 11773-038 OCCURRENCE 5 Figure 38. Current Consumption vs. Temperature (Continuous Conversion Mode, Buffers Enabled, Internal Reference, Internal Clock) 35 5.0 4.5 30 4.0 CURRENT (µA) 3.5 20 15 3.0 2.5 2.0 DEVICE 1 DEVICE 2 DEVICE 3 1.5 10 1.0 5 3.0 11773-036 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 –0.2 –0.6 –1.0 –1.4 GAIN ERROR (ppm) 0 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (°C) Figure 39. Current Consumption vs. Temperature (Power-Down Mode) Figure 36. Gain Error Distribution Histogram Rev. A | Page 17 of 64 11773-039 0.5 0 –1.8 OCCURRENCE 25 AD7173-8 Data Sheet NOISE PERFORMANCE AND RESOLUTION Table 6 shows the rms noise, peak-to-peak noise, effective resolution, and the noise free (peak-to-peak) resolution of the AD7173-8 for various output data rates and filters. The values listed are for the bipolar input range with an external 5 V reference. These values are typical and are generated with a differential input voltage of 0 V when the ADC is continuously converting on a single channel. It is important to note that the peak-topeak resolution is calculated based on the peak-to-peak noise. The peak-to-peak resolution represents the resolution for which there is no code flicker. Using the sinc3 filter at the fastest rate results in the noise being quantization limited. This limitation degrades the noise specification at this rate and does not give a result of 24 bits, no missing codes. Table 6. RMS Noise and Peak-to-Peak Resolution vs. Output Data Rate using Sinc5 + Sinc1 Filter (Default) 1 Output Data Rate (SPS) 31,250 5208 1007 381 100.5 20.01 5 1.25 1 RMS Noise (µV rms) 8.0 4.5 2.2 1.3 0.71 0.32 0.15 0.07 Sinc5 + Sinc1 Filter (Default) Peak-to-Peak Effective Resolution (Bits) Noise (µV rms) 20.2 67 21.1 30 22.2 15 22.9 8.9 23.8 5.1 24 1.7 24 0.75 24 0.32 Peak-to-Peak Resolution (Bits) 17.5 18.3 19.3 20.1 21 22.2 23.4 24 Selected rates only; 1000 samples. Table 7. RMS Noise and Peak-to-Peak Resolution vs. Output Data Rate using Sinc3 Filter 1 Output Data Rate (SPS) 31,250 5208 1008 400.6 100.5 20.01 5 1.25 1 RMS Noise (µV rms) 210 3.6 1.5 1 0.55 0.25 0.11 0.07 Sinc3 Filter Peak-to-Peak Effective Resolution (Bits) Noise (µV rms) 15.5 1665 21.4 28 22.7 12 23.3 6.6 24 3.5 24 1.2 24 0.56 24 0.27 Selected rates only; 1000 samples. Rev. A | Page 18 of 65 Peak-to-Peak Resolution (Bits) 12.8 18.7 19.9 20.5 21.4 22.4 23.4 24 Data Sheet AD7173-8 GETTING STARTED The AD7173-8 offers the user a fast settling, high resolution, multiplexed ADC with high levels of configurability. • • Eight fully differential or 16 single-ended analog inputs. Cross point mux. Selects any analog input combination as a pairing to be converted. The signals are routed to the input buffers and onto the modulator positive or negative input. ADC input. Selectable as a fully differential input or as a single-ended input. Per setup configurability. Up to eight different setups can be defined. A separate setup can be mapped to each of the channels. Each setup allows the user to configure the following: • Output data rate when using sinc5 + sinc1 filter • Digital filter mode • Offset/gain error correction • Reference source selection (internal/external) • Analog and reference input buffer enables • Digital output coding The AD7173-8 includes two separate linear regulator blocks for both the analog and digital circuitry. The analog LDO regulates the AVDD2 supply to 1.8 V, supplying the ADC core. The user can tie the AVDD1 and AVDD2 supplies together for easiest connection. If a clean analog supply rail is in the system in the range of 2 V to 5.5 V (minimum to maximum), the user can also choose to connect this supply rail to the AVDD2 input, allowing for lower power dissipation. 16MHz CX2 CX1 SEE ANALOG INPUT SECTION FOR FURTHER DETAILS OPTIONAL EXTERNAL CRYSTAL CIRCUITRY CAPACITORS XTAL1 12 2 AIN0/REF2– XTAL2/CLKIO 13 DOUT/RDY 14 3 DOUT/RDY AIN1/REF2+ DIN DIN 15 36 SCLK SCLK 16 AIN14 CS CS 17 37 AIN15 1 AIN16 CLKIN OPTIONAL EXTERNAL CLOCK INPUT AD7173-8 IOVDD IOVDD 20 0.1µF DGND 21 VIN 1 2 4.7µF VIN 3 REGCAPD 22 NC 7 0.1µF 1µF 0.1µF ADR44xBRZ 4 GND 5 AVDD1 9 VOUT 6 8 AVDD1 40 0.1µF 4.7µF 0.1µF REF+ AVDD2 0.1µF AVDD2 10 39 REF– 0.1µF REGCAPA 7 AVSS 8 Figure 40. Typical Connection Diagram Rev. A | Page 19 of 64 0.1µF 1µF 11773-040 • • The AD7173-8 includes a precision 2.5 V low drift (3.5 ppm/°C) band gap internal reference. This reference can be selected to be used for the ADC conversions, reducing the external component count. When enabled, the internal reference is output to the REFOUT pin and can be used as a low noise biasing voltage for the external circuitry. An example of this is using the REFOUT signal to set the input common mode for an external single-ended to differential amplifier. AD7173-8 Data Sheet The linear regulator for the digital IOVDD supply performs a similar function, regulating the input voltage applied at the IOVDD pin to 1.8 V for the internal digital filtering. The serial interface signals always operate from the IOVDD supply seen at the pin. This means that if 3.3 V is applied to the IOVDD pin, the interface logic inputs and outputs operate at this level. The AD7173-8 can be used across a wide variety of applications, providing high resolution and accuracy. A sample of these scenarios follows: • • • Fast scanning of analog input channels using the internal mux Fast scanning of analog input channels using an external mux High resolution at lower speeds in either multichannel or ADC per channel applications Single ADC per channel; the fast low latency output allows further application specific filtering in an external microcontroller, DSP, or FPGA POWER SUPPLIES The AD7173-8 device has the ability to operate with AVSS set to a negative voltage, allowing true bipolar inputs to be applied. This allows for a fully differential input signal centered around 0 V and eliminates the need for an external level shifting circuit. For example, with a 5 V split supply, AVDD1 = 2.5 V and AVSS = −2.5 V. In this use case, the AD7173-8 internally level shifts the signals, allowing the digital output to function between DGND (nominally 0 V) and IOVDD. When using a split supply for AVDD1 and AVSS, the absolute maximum ratings must be considered (refer to the Absolute Maximum Ratings section). Ensure that IOVDD is set below 3.6 V to stay within the absolute maximum rating for the device. DIGITAL COMMUNICATION The AD7173-8 can run from either a 3.3 V or 5 V supply voltage. The device has three independent power supply pins: AVDD1, AVDD2, and IOVDD. • • • • Split Supply Operation (AVSS ≠ DGND) AVDD1 and AVDD2 are referred to AVSS. AVDD2 powers the internal regulator supplying the ADC. AVDD1 and AVDD2 can be tied together for convenience. IOVDD is referred to DGND. The supply sets the interface logic levels on the SPI interface and powers an internal regulator for operation of the digital processing. The AD7173-8 has a 3-wire or 4-wire SPI interface that is compatible with QSPI™, MICROWIRE®, and DSPs. The interface operates in SPI Mode 3 and can be operated with CS tied low. In SPI Mode 3, SCLK idles high, the falling edge of SCLK is the drive edge, and the rising edge of SCLK is the sample edge. This means that data is clocked out on the falling/drive edge and data is clocked in on the rising/sample edge. Single Supply Operation (AVSS = DGND) When the AD7173-8 is powered from a single supply that is connected to AVDD1, the supply can be either 3.3 V or 5 V. In this configuration, AVSS and DGND can be shorted together on one single ground plane. With this setup, an external level shifting circuit is required to use fully differential inputs to shift the common-mode voltage. Rev. A | Page 20 of 64 DRIVE EDGE SAMPLE EDGE 11773-041 • AVDD2 is the input to the internal voltage regulator. Connect AVDD2 to AVDD1 for convenience. Otherwise, if a separate supply is available in the system, a voltage from 2 V to 5.5 V can be applied. IOVDD can range from 2 V to 5.5 V in this unipolar input configuration. Figure 41. SPI Mode 3 SCLK Edges Data Sheet AD7173-8 Accessing the ADC Register Map The communications register controls access to the full register map of the ADC. This register is an 8-bit write only register. On power-up or after a reset, the digital interface defaults to a state where it is expecting a write to the communications register; therefore, all communication begins by writing to the communications register. 8-BIT COMMAND 8 BITS, 16 BITS, OR 24 BITS OF DATA CMD DATA CS DIN The data written to the communications register determines which register is being accessed and if the next operation is a read or write. The register address bits (RA[5:0]) determine the specific register to which the read or write operation applies. 11773-042 SCLK Figure 42. Writing to a Register (8-Bit Command with Register Address Followed by Data of 8, 16, or 24 Bits; Data Length Is Dependent on the Register Selected) When the read or write operation to the selected register is complete, the interface returns to its default state, where it expects a write operation to the communications register. In situations where interface synchronization is lost, a write operation of at least 64 serial clock cycles with DIN high returns the ADC to its default state by resetting the entire part, including the register contents. Alternatively, if CS is being used with the digital interface, returning CS high resets the digital interface to its default state and aborts any current operation. 8-BIT COMMAND 8 BITS, 16 BITS, 24 BITS, OR 32 BITS OUTPUT CS CMD DIN Figure 42 and Figure 43 illustrate writing to and reading from a register by first writing the 8-bit command to the communications register followed by the data for the addressed register. DOUT/RDY Reading the ID register is the recommended method for verifying correct communication with the part. The ID register is a read only register and contains the value 0x30DX for the AD7173-8. The communication register and ID register details are described in Table 8 and Table 9. DATA 11773-043 SCLK Figure 43. Reading from a Register (8-Bit Command with Register Address Followed by Data of 8, 16, or 24 Bits; Data Length on DOUT Is Dependent on the Register Selected) Table 8. Communications Register Bit Map Reg 0x00 Name COMMS Bits [7:0] Bit 7 WEN Bit 6 R/W Bit 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset 0x00 RW W Bit 2 Bit 1 Bit 0 Reset 0x30DX 1 RW R RA Table 9. ID Register Bit Map Reg 0x07 1 Name ID Bits [15:8] [7:0] Bit 4 Bit 3 ID[15:8] ID[7:0] X = don’t care. Rev. A | Page 21 of 65 AD7173-8 Data Sheet CONFIGURATION OVERVIEW Channel Configuration After power on-or reset, the AD7173-8 default configuration is as follows: The AD7173-8 has 16 independent channels and eight independent setups. The user can select any of the analog input pairs on any channel, as well as any of the eight setups for any channel, giving the user full flexibility in the channel configuration. This also allows per channel configuration when using eight differential inputs because each channel can have its own dedicated setup. Channel configuration. CH0 is enabled, AIN0 is selected as the positive input, and AIN1 is selected as the negative input. Setup 0 is selected. Setup configuration. The input buffers are disabled, and the external reference is selected. ADC mode. Continuous conversion mode, the internal oscillator, and single cycle settling are enabled. Interface mode. CRC is disabled, and data + status output is disabled. Note that only a few of the register setting options are shown; this list is just an example. For full register information, see the Register Details section. Figure 44 shows an overview of the suggested flow for changing the ADC configuration, divided into the following three blocks: Channel configuration (see Box A in Figure 44) Setup configuration (see Box B in Figure 44) ADC mode and interface mode configuration (see Box C in Figure 44) Channel Registers The channel registers are used to select which of the 17 analog input pins (AIN0 to AIN16) are used as either the positive analog input or the negative analog input for that channel. This register also contains a channel enable/disable bit and the setup selection bits, which are used to pick which of the eight available setups are used for this channel. When the AD7173-8 is operating with more than one channel enabled, the channel sequencer cycles through the enabled channels in sequential order, from Channel 0 to Channel 15. If a channel is disabled, it is skipped by the sequencer. Details of the channel register for Channel 0 are shown in Table 10. A CHANNEL CONFIGURATION SELECT POSITIVE AND NEGATIVE INPUT FOR EACH ADC CHANNEL SELECT ONE OF 8 SETUPS FOR ADC CHANNEL B SETUP CONFIGURATION 8 POSSIBLE ADC SETUPS SELECT FILTER ORDER, OUTPUT DATA RATE, AND MORE C ADC MODE AND INTERFACE MODE CONFIGURATION SELECT ADC OPERATING MODE, CLOCK SOURCE, ENABLE CRC, DATA + STATUS, AND MORE 11773-044 Figure 44. Suggested ADC Configuration Flow Table 10. Channel 0 Register Bit Map Reg Name 0x10 CH0 Bits Bit 7 [15:8] CH_EN0 [7:0] Bit 6 Bit 5 Bit 4 SETUP_SEL[2:0] AINPOS0[2:0] Bit 3 Rev. A | Page 22 of 64 Bit 2 Bit 1 Bit 0 RESERVED AINPOS0[4:3] AINNEG0 Reset RW 0x8001 RW Data Sheet AD7173-8 ADC Setups Setup Configuration Registers The AD7173-8 has eight independent setups. Each setup consists of the following four registers: The setup configuration registers allow the user to select the output coding of the ADC by selecting between bipolar and unipolar. In bipolar mode, the ADC accepts negative differential input voltages, and the output coding is offset binary. In unipolar mode, the ADC accepts only positive differential voltages, and the coding is straight binary. In either case, the input voltage must be within the AVDD1/ AVSS supply voltages. The user can also select the reference source using this register. Four options are available: an internal 2.5 V reference, an external reference connected between the REF+ and REF− pins, an external reference connected between AIN0/REF2− and AIN1/REF2+, or AVDD1 − AVSS. The analog input buffers and reference input buffers for the setup can also be enabled using this register. • • • • Setup configuration register Filter configuration register Offset register Gain register For example, Setup 0 consists of Setup Configuration Register 0, Filter Configuration Register 0, Offset Register 0, and Gain Register 0. Figure 45 shows the grouping of these registers The setup is selectable from the channel registers detailed in the Channel Configuration section. This allows each channel to be assigned to one of 8 separate setups. Table 11 through Table 14 show the four registers that are associated with Setup 0. This structure is repeated for Setup 1 to Setup 7. Filter Configuration Registers The filter configuration register selects which digital filter is used at the output of the ADC modulator. The order of the filter and the output data rate is selected by setting the bits in this register. For more information, see the Digital Filters section. FILTER CONFIG REGISTERS SETUP CONFIG REGISTERS GAIN REGISTERS* OFFSET REGISTERS SETUPCON0 0x20 FILTCON0 0x28 GAIN0 0x38 OFFSET0 0x30 SETUPCON1 0x21 FILTCON1 0x29 GAIN1 0x39 OFFSET1 0x31 SETUPCON2 0x22 FILTCON2 0x2A GAIN2 0x3A OFFSET2 0x32 SETUPCON3 0x23 FILTCON3 0x2B GAIN3 0x3B OFFSET3 0x33 SETUPCON4 0x24 FILTCON4 0x2C GAIN4 0x3C OFFSET4 0x34 SETUPCON5 0x25 FILTCON5 0x2D GAIN5 0x3D OFFSET5 0x35 SETUPCON6 0x26 FILTCON6 0x2E GAIN6 0x3E OFFSET6 0x36 SETUPCON7 0x27 FILTCON7 0x2F GAIN7 0x3F OFFSET7 0x37 AIN BUFFERS REF BUFFERS BURNOUT REFERENCE SOURCE SELECT DIGITAL FILTER TYPE AND OUTPUT DATA RATE SINC5 + SINC1 SINC3 SINC3 MAP ENHANCED 50/60 GAIN CORRECTION OPTIONALLY PROGRAMMED PER SETUP AS REQUIRED (*FACTORY CALIBRATED) OFFSET CORRECTION OPTIONALLY PROGRAMMED PER SETUP AS REQUIRED 11773-045 SELECT PERIPHERAL FUNCTIONS FOR ADC CHANNEL Figure 45. ADC Setup Register Grouping Table 11. Setup Configuration 0 Register Bit Map Reg 0x20 Name Bits Bit 7 Bit 6 Bit 5 SETUPCON0 [15:8] RESERVED [7:0] BURNOUT_EN0 BUFCHOPMAX0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BI_UNIPOLAR0 REF_BUF 0[1:0] AIN_BUF 0[1:0] REF_SEL0 RESERVED Reset 0x1000 RW RW Reset 0x0000 RW RW Table 12. Filter Configuration 0 Register Bit Map Reg 0x28 Name FILTCON0 Bits Bit 7 SINC3_MAP0 Bit 6 Bit 5 Bit 4 RESERVED ORDER0 Bit 3 Bit 2 ENHFILTEN0 ODR0 Bit 1 Bit 0 ENHFILT0 Table 13. Offset Configuration 0 Register Bit Map Reg 0x30 Name OFFSET0 Bits [23:0] Bit[23:0] OFFSET0[23:0] Reset RW 0x800000 RW Bit[23:0] GAIN0[23:0] Reset RW 0x5XXXX0 RW Table 14. Gain Configuration 0 Register Bit Map Reg 0x38 Name GAIN0 Bits [23:0] Rev. A | Page 23 of 64 AD7173-8 Data Sheet Offset Registers ADC Mode and Interface Mode Configuration The offset register holds the offset calibration coefficient for the ADC. The power-on reset value of the offset register is 0x800000. The offset register is a 24-bit read/write register. The power-on reset value is automatically overwritten if an internal or system zero-scale calibration is initiated by the user or if the offset register is written to by the user. The ADC mode register and the interface mode register configure the core peripherals for use by the AD7173-8 and the mode for the digital interface. ADC Mode Register The ADC mode register is used primarily to set the conversion mode of the ADC to either continuous or single conversion. The user can also select the standby and power-down modes, as well as any of the calibration modes. In addition, this register contains the clock source select bits and the internal reference enable bits. The reference select bits are contained in the setup configuration registers (see the ADC Setups section for more information). Gain Registers The gain register is a 24-bit register that holds the gain calibration coefficient for the ADC. The gain registers are read/write registers. These registers are configured at power-on with factory calibrated coefficients. Therefore, every device has different default coefficients. The default value is automatically overwritten if a system full-scale calibration is initiated by the user or if the gain register is written to by the user. For more information on calibration, see the Operating Modes section. Interface Mode Register The interface mode register configures the digital interface operation. This register allows the user to control data-word length, CRC enable, data + status read and continuous read mode. The details of both registers are shown in Table 15 and Table 16. For more information, see the Digital Interface section. Table 15. ADC Mode Register Bit Map Reg 0x01 Name ADCMODE Bits [15:8] [7:0] Bit 7 REF_EN RESERVED Bit 6 RESERVED Bit 5 SING_CYC MODE Bit 4 Bit 3 RESERVED Bit 2 CLOCKSEL Bit 1 Bit 0 DELAY RESERVED Reset 0x2000 RW RW Reset 0x0000 RW RW Table 16. Interface Mode Register Bit Map Reg 0x02 Name IFMODE Bits [15:8] Bit 7 [7:0] CONTREAD Bit 6 RESERVED DATA_ STAT Bit 5 Bit 4 ALT_SYNC REG_ CHECK RESERVED Bit 3 IOSTRENGTH Rev. A | Page 24 of 64 Bit 2 HIDE_DELAY CRC_EN Bit 1 RESERVED Bit 0 DOUT_RESET RESERVED WL16 Data Sheet AD7173-8 Understanding Configuration Flexibility The most straightforward implementation of the AD7173-8 is to use eight differential inputs with adjacent analog inputs and run all of them with the same setup, gain correction, and offset correction register. In this case, the user selects the following differential inputs: AIN0/AIN1, AIN2/AIN3, AIN4/AIN5, AIN6/AIN7, AIN8/AIN9. AIN10/AIN11, AIN12/AIN13, AIN14/AIN15. In Figure 46, the registers shown in black font must be programmed for such a configuration. The registers that are shown in gray font are redundant in this configuration. Programming the gain and offset registers is optional for any use case, as indicated by the dashed lines between the register blocks. An alternative way to implement these eight fully differential inputs is by taking advantage of the eight available setups. Motivation for doing this includes having is a different speed/noise requirement on some of the eight differential inputs vs. other inputs, or there may be a specific offset or gain correction for particular channels. Figure 47 shows how each of the differential inputs may use a separate setup, allowing full flexibility in the configuration of each channel. CHANNEL REGISTERS AIN0 CH0 0x10 AIN1 CH1 0x11 AIN2 CH2 0x12 AIN3 CH3 0x13 AIN4 CH4 0x14 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 AIN12 CH5 CH6 CH7 CH8 CH9 GAIN REGISTERS* OFFSET REGISTERS SETUPCON0 0x20 FILTCON0 0x28 GAIN0 0x38 OFFSET0 0x30 SETUPCON1 0x21 FILTCON1 0x29 GAIN1 0x39 OFFSET1 0x31 SETUPCON2 0x22 FILTCON2 0x2A GAIN2 0x3A OFFSET2 0x32 SETUPCON3 0x23 FILTCON3 0x2B GAIN3 0x3B OFFSET3 0x33 SETUPCON4 0x24 FILTCON4 0x2C GAIN4 0x3C OFFSET4 0x34 SETUPCON5 0x25 FILTCON5 0x2D GAIN5 0x3D OFFSET5 0x35 SETUPCON6 0x26 FILTCON6 0x2E GAIN6 0x3E OFFSET6 0x36 SETUPCON7 0x27 FILTCON7 0x2F GAIN7 0x3F OFFSET7 0x37 0x15 0x16 0x17 0x18 0x19 CH10 0x1A CH11 0x1B CH12 0x1C AIN13 CH13 0x1D AIN14 CH14 0x1E AIN15 CH15 0x1F AIN16 FILTER CONFIG REGISTERS SELECT ANALOG INPUT PARTS ENABLE THE CHANNEL SELECT SETUP 0 SELECT PERIPHERAL FUNCTIONS FOR ADC CHANNEL SELECT DIGITAL FILTER TYPE AND OUTPUT DATA RATE AIN BUFFERS REF BUFFERS BURNOUT REFERENCE SOURCE 31.25kSPS TO 1.25SPS SINC5 + SINC1 SINC3 GAIN CORRECTION OFFSET CORRECTION OPTIONALLY OPTIONALLY PROGRAMMED PROGRAMMED PER SETUP AS REQUIRED PER SETUP AS REQUIRED (*FACTORY CALIBRATED) 11773-046 AIN5 SETUP CONFIG REGISTERS SINC3 MAP ENHANCED 50/60 Figure 46. Eight Fully Differential Inputs, All Using a Single Setup (SETUPCON0; FILTCON0; GAIN0; OFFSET0) CHANNEL REGISTERS AIN0 CH0 AIN1 CH1 0x11 AIN2 CH2 0x12 AIN3 CH3 0x13 AIN4 CH4 0x14 AIN6 AIN7 AIN8 CH5 CH6 CH7 FILTER CONFIG REGISTERS GAIN REGISTERS* OFFSET REGISTERS SETUPCON0 0x20 FILTCON0 0x28 GAIN0 0x38 OFFSET0 0x30 SETUPCON1 0x21 FILTCON1 0x29 GAIN1 0x39 OFFSET1 0x31 SETUPCON2 0x22 FILTCON2 0x2A GAIN2 0x3A OFFSET2 0x32 SETUPCON3 0x23 FILTCON3 0x2B GAIN3 0x3B OFFSET3 0x33 SETUPCON4 0x24 FILTCON4 0x2C GAIN4 0x3C OFFSET4 0x34 SETUPCON5 0x25 FILTCON5 0x2D GAIN5 0x3D OFFSET5 0x35 SETUPCON6 0x26 FILTCON6 0x2E GAIN6 0x3E OFFSET6 0x36 SETUPCON7 0x27 FILTCON7 0x2F GAIN7 0x3F OFFSET7 0x37 0x15 0x16 0x17 CH8 0x18 AIN9 CH9 0x19 AIN10 CH10 0x1A AIN11 CH11 0x1B AIN12 CH12 0x1C AIN13 CH13 0x1D AIN14 CH14 0x1E AIN15 CH15 0x1F AIN16 SETUP CONFIG REGISTERS SELECT ANALOG INPUT PARTS ENABLE THE CHANNEL SELECT SETUP SELECT PERIPHERAL FUNCTIONS FOR ADC CHANNEL SELECT DIGITAL FILTER TYPE AND OUTPUT DATA RATE AIN BUFFERS REF BUFFERS BURNOUT REFERENCE SOURCE 31.25kSPS TO 1.25SPS SINC5 + SINC1 SINC3 GAIN CORRECTION OFFSET CORRECTION OPTIONALLY OPTIONALLY PROGRAMMED PROGRAMMED PER SETUP AS REQUIRED PER SETUP AS REQUIRED (*FACTORY CALIBRATED) SINC3 MAP ENHANCED 50/60 Figure 47. Eight Fully Differential Inputs with a Setup per Channel Rev. A | Page 25 of 64 11773-047 AIN5 0x10 AD7173-8 Data Sheet Figure 48 shows an example of how the channel registers span between the analog input pins and the setup configurations downstream. In this random example, seven differential inputs and two single-ended inputs are required. The single-ended inputs are the AIN8/AIN16 and AIN15/AIN16 combinations. The first five differential input pairs (AIN0/AIN1, AIN2/AIN3, AIN4/AIN5, AIN6/AIN7, AIN9/AIN10) use the same setup: SETUPCON0. The two single-ended input pairs (AIN8/AIN16 and AIN15/ AIN16) are set up as a diagnostics; therefore, use a separate setup: SETUPCON1. The final two differential inputs (AIN11/AIN12 and AIN13/AIN14) also use a separate setup: SETUPCON2. Given that three setups are selected for use, the SETUPCON0, SETUPCON1, and SETUPCON2 registers are programmed as required, and the FILTCON0, FILTCON1, and FILTCON2 registers are also programmed as desired. Optional gain and offset correction can be employed on a per setup basis by programming the GAIN0, GAIN1, and GAIN2 registers and the OFFSET0, OFFSET1, and OFFSET2 registers. In the example shown in Figure 48, the CH0 to CH8 registers are used. Setting the MSB in each of these registers, the CH_EN0 to CH_EN8 bits enable the nine combinations via the cross point mux. When the AD7173-8 converts, the sequencer transitions in ascending sequential order from CH0 to CH1 to CH2, and then on to CH8 before looping back to CH0 to repeat the sequence. CHANNEL REGISTERS AIN0 CH0 0x10 AIN1 CH1 0x11 AIN2 CH2 0x12 AIN3 CH3 0x13 AIN4 CH4 0x14 AIN6 AIN7 AIN8 CH5 CH6 CH7 GAIN REGISTERS* OFFSET REGISTERS SETUPCON0 0x20 FILTCON0 0x28 GAIN0 0x38 OFFSET0 0x30 SETUPCON1 0x21 FILTCON1 0x29 GAIN1 0x39 OFFSET1 0x31 SETUPCON2 0x22 FILTCON2 0x2A GAIN2 0x3A OFFSET2 0x32 SETUPCON3 0x23 FILTCON3 0x2B GAIN3 0x3B OFFSET3 0x33 SETUPCON4 0x24 FILTCON4 0x2C GAIN4 0x3C OFFSET4 0x34 SETUPCON5 0x25 FILTCON5 0x2D GAIN5 0x3D OFFSET5 0x35 SETUPCON6 0x26 FILTCON6 0x2E GAIN6 0x3E OFFSET6 0x36 SETUPCON7 0x27 FILTCON7 0x2F GAIN7 0x3F OFFSET7 0x37 0x15 0x16 0x17 CH8 0x18 AIN9 CH9 0x19 AIN10 CH10 0x1A AIN11 CH11 0x1B AIN12 CH12 0x1C AIN13 CH13 0x1D AIN14 CH14 0x1E AIN15 CH15 0x1F AIN16 FILTER CONFIG REGISTERS SELECT ANALOG INPUT PARTS ENABLE THE CHANNEL SELECT SETUP SELECT PERIPHERAL FUNCTIONS FOR ADC CHANNEL SELECT DIGITAL FILTER TYPE AND OUTPUT DATA RATE AIN BUFFERS REF BUFFERS BURNOUT REFERENCE SOURCE 31.25kSPS TO 1.25SPS SINC5 + SINC1 SINC3 GAIN CORRECTION OFFSET CORRECTION OPTIONALLY OPTIONALLY PROGRAMMED PROGRAMMED PER SETUP AS REQUIRED PER SETUP AS REQUIRED (*FACTORY CALIBRATED) SINC3 MAP ENHANCED 50/60 Figure 48. Mixed Differential and Single-Ended Configuration Using Multiple Shared Setups Rev. A | Page 26 of 64 11773-048 AIN5 SETUP CONFIG REGISTERS Data Sheet AD7173-8 CIRCUIT DESCRIPTION this is by using adjacent input pins as the differential pair. All analog inputs decoupling capacitors connect to AVSS. ANALOG INPUT Buffered Analog Input The AD7173-8 integrates precision unity gain buffers on the ADC inputs. The output of the integrated cross point mux is connected to the ADC via these precision buffers. The buffers provide the benefit of giving the user high input impedance and fully drive the internal ADC switch capacitor sampling network. There is a buffer on both the positive and negative analog inputs to the ADC. The input signals of the AIN pair that is selected via control of the cross point mux (BUF+, BUF−) pass to the buffer inputs, which drive the ADC sampling capacitor circuitry. Each analog input buffer has an input voltage range as shown in Figure 49. Each buffer can operate with an input signal down to AVSS (analog ground) or up to an input voltage of 1.1 V from the AVDD1 supply. Fully Differential Inputs The AIN0 to AIN16 analog inputs are connected to a cross point mux. Any combination of signals can be used to create an analog input pair. This allows the user to select eight fully differential inputs or 16 single-ended inputs. If all signals to the AD7173-8 are fully differential, it is recommended that the traces of the inputs be of the same length. The most reliable and efficient way to do Single-Ended Inputs The user can also choose to measure 16 different single-ended analog inputs. In this case, each of the analog inputs is converted as being the difference between the single-ended input to be measured and a set analog input common pin. Because there is a cross point mux, the user can set any of the analog inputs as the common pin. An example of such a scenario is to connect the AIN16 pin to AVSS or to the REFOUT voltage (that is, AVSS + 2.5 V) and select this input when configuring the cross point mux. When using the AD7173-8 with single-ended inputs, the INL specification is degraded. When the user requires a buffered input in either the fully differential or single-ended case, the user is required to turn on the analog input buffers as a pair. This means that, even where an input pin is connected to AVSS, the input buffer of this channel is turned on if the other pin making up the differential input is going to be buffered. AVDD1 1.1V CROSSPOINT MULTIPLEXER USABLE INPUT VOLTAGE RANGE: BUFFERS ON (AVDD1 – 1.1V) – (AVSS) REF– REF+ REFOUT AVDD1 AIN X REFERENCE INPUT BUFFERS INT REF ANALOG INPUT BUFFERS BUF+ AIN Y CS ON Σ-Δ ADC BUF– DIGITAL FILTER ON SERIAL INTERFACE AND CONTROL SCLK DIN DOUT/RDY AVSS AVSS Figure 49. Analog Input Voltage Range with Analog Input Buffers Enabled Rev. A | Page 27 of 64 11773-049 TEMPERATURE SENSOR AD7173-8 Data Sheet Buffer Chopping, Noise, and Input Current Each analog input buffer amplifier is fully chopped, meaning that it minimizes the offset error drift and 1/f noise of the signal chain. The 1/f noise profile is shown in Figure 51. The noise performance of the buffer at certain output data rates can be improved by increasing the chopping rate of the buffer, giving a corresponding increase in input current. This is done by setting the BUFCHOPMAXx bit in the setup configuration register of the selected setup. The average input current to the AD7173-8 changes linearly with the differential input voltage at a rate of 6 µA/V. Each analog input must be buffered externally, not only to provide the varying input current with differential input amplitude, but also to settle the switched capacitor input to allow accurate sampling. The simplified analog input circuit for this situation is shown in Figure 50. 0 Running with Single Cycle = 0 AIN0 –250 0.1 1 10 100 1k 10k FREQUENCY (Hz) Figure 51. Shorted Input FFT 12 10 RMS NOISE (µV) AVDD1 –150 –200 Using External Buffers The analog input buffers can be disabled. When they are disabled, the input voltage range on the analog inputs is AVDD1 – AVSS. The analog input switched capacitor input is then exposed to the user. A suitable external amplifier is required to sufficiently drive and settle the analog input in such cases. The CS1 and CS2 capacitors each have a magnitude in the order of a number of picofarads (pF). This capacitance is the combination of both the sampling capacitance and the parasitic capacitance. –100 11773-051 The output data rate can be maximized when using only a single channel by setting the SING_CYC bit to 0. However, the analog input current changes in magnitude, depending on the output data rate selected. In this condition, the input current increases by approximately 32× for output data rates selected at >2.6 kSPS. Set the SING_CYC bit to 0 only in this specific use case. Figure 52 and Figure 53 show rms noise and input current vs. output data rate for various conditions. AMPLITUDE (dB) –50 8 6 BUFCHOP MAX = 0 BUFCHOP MAX = 1 4 AVSS AVDD1 2 Ø1 CS1 0 1 AVSS 10 100 1k 10k ODR (SPS) Ø2 Figure 52. RMS Noise vs. Output Data Rate (Sinc5 + Sinc1 Filter) Ø2 AVDD1 11773-052 +IN AIN1 CS2 14 AIN14 12 –IN AIN15 AVSS AVDD1 11773-050 AVSS 10 8 SINGLE CHANNEL AND SING_CYC = 0 BUFCHOPMAX = 1 SING_CYC = 1 6 4 2 0 –2 –4 Figure 50. Simplfied Analog Input Circuit –6 1 10 100 1k 10k ODR (SPS) Figure 53. Typical Analog Input Current vs. Output Data Rate (2.5 V Common Mode) Rev. A | Page 28 of 64 11773-053 AIN16 AVERAGE AIN CURRENT (nA) AVSS AVDD1 Ø1 Data Sheet AD7173-8 REFERENCE OPTIONS Internal Reference The AD7173-8 offers the user the option of either supplying an external reference to the REF+ and REF− pins of the device or allowing the use of the internal 2.5 V, low noise, low drift reference. Select the reference source to be used by the analog input by setting the REF_SELx bits (Bits[5:4]) in the setup configuration registers appropriately. The structure of the Setup Configuration 0 register is shown in Table 17. The AD7173-8 defaults on power-up to use of an external reference. The AD7173-8 includes its own low noise, low drift voltage reference. On power-up, the internal reference is disabled by default and a register write is required to select it as the reference source for the ADC. Write to the REF_EN bit (Bit 15) in the ADC mode register to enable it (see Table 18). The internal reference has a 2.5 V output and is output on the REFOUT pin after the REF_EN bit is set in the ADC mode register. Decouple the internal reference to AVSS with a 0.1 μF capacitor. External Reference The REFOUT signal is buffered prior to being output to the pin. The signal can be used externally in the circuit as a common-mode source for external amplifier configurations. The AD7173-8 has a fully differential reference input applied through the REF+ and REF− pins. Standard low noise, low drift voltage references, such as the ADR445, ADR444, and ADR441, are recommended for use. Apply the external reference to the AD7173-8 reference pins as shown in Figure 54. Decouple the output of any external reference is to AVSS. As shown in Figure 54, the ADR441 output is decoupled with a 0.1 μF capacitor at its output for stability purposes. The output is then connected to a 4.7 μF capacitor, which acts as a reservoir for any dynamic charge required by the ADC, and followed by a 0.1 μF decoupling capacitor at the REF+ input. This capacitor is placed as close as possible to the REF+ and REF− pins. The REF− pin is connected directly to the AVSS potential. CLOCK SOURCE The AD7173-8 requires a master clock of 2 MHz. The AD7173-8 can use one of the following sources as its sampling clock: Internal oscillator External crystal (use a 16 MHz crystal, automatically divided internally to set the 2 MHz clock) External clock source All output data rates listed in the data sheet relate to a master clock rate of 2 MHz. Using a lower clock frequency from, for example, an external source proportionally scales any listed data rate. To achieve the specified data rates, particularly rates for rejection of 50 Hz and 60 Hz, a use a 2 MHz clock. The source of the master clock is selected by setting the CLOCKSEL bits in the ADCMODE register, as shown in Table 25. The default, on power-up and reset, is to operate with the internal oscillator. AD7173-8 3V TO 18V 40 REF+ ADR441** 0.1µF 0.1µF * 2.5V VREF 0.1µF * * 4.7µF * 39 REF– * 11773-054 *ALL DECOUPLING IS TO AVSS. **ANY OF THE ADR44x FAMILY REFERENCES CAN BE USED. ADR441 ENABLES REUSE OF THE 3.3V ANALOG SUPPLY NEEDED FOR AVDD1 TO POWER THE REFERENCE VIN. Figure 54. External Reference ADR441 Connected to AD7173-8 Reference Pins Table 17. Setup Configuration 0 Register Reg Name Bits Bit 7 Bit 6 Bit 5 Bit 4 0x20 SETUPCON0 [15:8] RESERVED RESERVED BI_UNIPOLAR [7:0] BURNOUT_EN BUFCHOPMAX0 REF_SEL0 Bit 3 Bit 2 Bit 1 Bit 0 REF_BUF 0[1:0] AIN_BUF 0[1:0] RESERVED Reset RW 0x1000 RW 0 Reset 0x2000 RW RW Table 18. ADC Mode Register Reg Name 0x01 ADCMODE Bits Bit 7 Bit 6 [15:8] INT_REF_EN RESERVED [7:0] RESERVED Bit 5 SING_CYC MODE Bit 4 Bit 3 RESERVED Rev. A | Page 29 of 64 Bit 2 CLOCKSEL Bit 1 Bit 0 DELAY RESERVED AD7173-8 Data Sheet The internal oscillator is used as the ADC master clock by default. The clock used for the ADC sampling is 2 MHz (this is divided down from a higher frequency in the case of the internal oscillator use). It is the default clock source for the AD7173-8 and is specified with an accuracy of ±2.5%. There is an option to allow the internal clock oscillator to be output on the XTAL2/CLKIO pin. The clock output is driven to the IOVDD logic level. Use of this option may affect the dc performance of the AD7173-8 due to a disturbance that may be introduced by the output driver. The extent to which the performance is affected depends on the IOVDD voltage supply. Higher IOVDD voltages create a wider logic output swing from the driver and may affect performance to a greater extent. This effect may be further exaggerated if the IOSTRENGTH bit (Register 0x02, Bit 11) is set at higher IOVDD levels (see Table 26 for more information). External Crystal If higher precision, lower jitter clock sources are required, the AD7173-8 has the ability to use an external crystal to generate the master clock. For the AD7173-8 the required crystal frequency is 16 MHz. Internally this is automatically divided to create the 2 MHz needed for sampling the ADC input. The crystal is connected to the XTAL1 and XTAL2/CLKIO pins. A recommended crystal for use is the FA-20H: a 16 MHz, 10 ppm, 9 pF crystal from Epson-Toyocom, which is available in a surface-mounted package. As shown in Figure 55, allow two capacitors to be inserted from the traces connecting the crystal to the XTAL1 and XTAL2/CLKIO pins. These capacitors enable circuit tuning. Connect these capacitors to the DGND pin. The value for these capacitors depends on the length and capacitance of the trace connections between the crystal and the XTAL1 and XTAL2/CLKIO pins. Therefore, the values of these capacitors differ depending on the PCB layout and the crystal employed. As a result, empirical testing of the circuit is required. AD7173-8 * CX1 XTAL1 12 CLKIO/XTAL2 13 CX2 * *DECOUPLE TO GND 11773-055 Internal Oscillator Figure 55. External Crystal Connections External Clock The AD7173-8 can also use an externally supplied clock. In systems where this is desirable, the external clock is routed to the XTAL2/CLKIO pin. In this configuration, the XTAL2/ CLKIO pin accepts the externally sourced clock and routes it to the modulator. The logic level of this clock input is defined by the voltage applied to the IOVDD pin. Rev. A | Page 30 of 64 Data Sheet AD7173-8 DIGITAL FILTERS of 2.6 kSPS and lower. The sinc5 block output is fixed at the maximum rate of 31.25 kSPS, and the sinc1 block output data rate can be varied to control the final ADC output data rate. Figure 57 shows the frequency domain response of the sinc5 + sinc1 filter at a 50 SPS output data rate. The sinc5 + sinc1 filter has a slow roll-off over frequency and narrow notches. The AD7173-8 provides the following three flexible filter options to allow optimization of settling time, noise, and rejection: Sinc5 + sinc1 filter Sinc3 filter Enhanced 50 Hz and 60 Hz rejection filters 50Hz AND 60Hz REJECTION FILTERS 11773-056 –20 SINC3 Figure 56. Digital Filter Block Diagram The filter and output data rate are configured by setting the appropriate bits in the filter configuration register for the selected setup. When using the sinc5 + sinc1 filter, it is possible to select different output data rates per channel. When using the sinc3 filter, the user must select the sinc3 filter and use the same output data rate for all enabled channels. See the Register Details section for more information. SINC5 + SINC1 FILTER The sinc5 + sinc1 filter is targeted at fast switching multiplexed applications and achieves single cycle settling at output data rates –40 –60 –80 –100 –120 0 50 100 150 FREQUENCY (Hz) Figure 57. Sinc5 + Sinc1 Filter Response at 50 SPS ODR The output data rates with the accompanying settling time and rms noise for the sinc5 + sinc1 filter are listed in Table 19. Table 19. Output Data Rate (ODR), Settling Time (tSETTLE), and Noise Using the Sinc5 + Sinc1 Filter Default Output Data Rate (SPS/Channel);1 SING_CYC = 1 or with Multiple Channels Enabled 6211 5181 4444 3115 2597 1007 503.8 381 200.3 100.5 59.52 49.68 20.01 16.63 10 5 2.5 1.25 1 2 Output Data Rate (SPS);1 SING_CYC = 0 and Single Channel Enabled 31,250 15,625 10,417 5208 2597 1007 503.8 381 200.3 100.5 59.52 49.68 20.01 16.63 10 5 2.5 1.25 Settling Time 1 161 µs 193 µs 225 µs 321 µs 385 µs 993 µs 1.99 ms 2.63 ms 4.99 ms 9.95 ms 16.8 ms 20.13 ms 49.98 ms 60.13 ms 100 ms 200 ms 400 ms 800 ms Notch Frequency (Hz) 31250 15625 10417 5208 3890 1156 539 401 206 102 60 50 20 16.67 10 5 2.5 1.25 11773-057 SINC1 SINC5 0 FILTER GAIN (dB) • • • Noise (µV rms) 8.0 6.9 6.0 4.5 3.9 2.2 1.5 1.3 0.99 0.71 0.57 0.52 0.32 0.3 0.22 0.15 0.08 0.07 Noise (µV p-p) 2 67 52 40 30 27 15 11 8.9 6.6 5.1 3.3 3 1.7 1.6 1.1 0.75 0.32 0.32 Effective Resolution with 5 V Reference (Bits) 20.2 20.4 20.7 21.1 21.3 22.2 22.7 22.9 23.3 23.8 24 24 24 24 24 24 24 24 Peak-to-Peak Resolution with 5 V Reference (Bits) 17.5 17.7 17.9 18.3 18.5 19.3 19.9 20.1 20.5 21 21.4 21.4 22.2 22.4 22.7 23.4 24 24 The settling time (tSETTLE) is rounded to the nearest microsecond (µs). This is reflected in the output data rate and switching rate. Switching rate = 1 ÷ tSETTLE. 1000 samples. Rev. A | Page 31 of 64 AD7173-8 Data Sheet SINC3 FILTER The sinc3 filter achieves the best single-channel noise performance at lower rates and is, therefore, most suitable for single-channel applications. When using the sinc3 filter, the user must select the sinc3 filter and use the same output data rate for all enabled channels. The sinc3 filter always has a settling time equal to tSETTLE = 3/Output Data Rate Figure 58 shows the frequency domain filter response for the sinc3 filter. The sinc3 filter has good roll-off over frequency and has wide notches for good notch frequency rejection. It is possible to fine-tune the output data rate for the sinc3 filter by setting the SINC3_MAPx bit in the Filter Configuration x register. If this bit is set, the mapping of the filter register changes to directly program the decimation rate of the sinc3 filter. All other options are eliminated. The data rate, when on a single channel, can be calculated using the following equation: Output Data Rate = f MOD 32 × FILTCONx[14:0] where: fMOD is the modulator rate and is equal to 1 MHz. FILTCONx[14:0] is the contents of the filter configuration register, excluding the MSB. 0 –10 –20 –30 FILTER GAIN (dB) The output data rates with the accompanying settling time and rms noise for the sinc3 filter are shown in Table 20. –40 For example, an output data rate of 50 SPS can be achieved with SINC3_MAPx enabled by setting the FILTCONx[14:0] bits to a value of 625. –50 –60 –70 –80 –90 –100 0 50 100 150 FREQUENCY (Hz) 11773-058 –110 –120 Figure 58. Sinc3 Filter Response Table 20. Output Data Rate (ODR), Settling Time (tSETTLE), and Noise Using the Sinc3 Filter Default Output Data Rate (SPS/Channel);1 SING_CYC = 1 or with Multiple Channels Enabled 10417 5208 3472 1736 868 336 168 133.53 67.76 33.5 19.99 16.67 6.67 5.56 3.33 1.67 0.83 0.42 1 Output Data Rate (SPS);1 SING_CYC = 0 and Single Channel Enabled 31,250 15,625 10,417 5208 2,604 1,008 504 400.6 200.3 100.5 59.98 50 20.01 16.67 10 5 2.5 1.25 Settling Time 1 96 µs 192 µs 288 µs 576 µs 1.15 ms 2.98 ms 5.95 ms 7.49 ms 14.99 ms 29.85 ms 50.02 ms 60 ms 149.93 ms 179.96 ms 300 ms 600 ms 1.2 sec 2.4 sec Notch Frequency (Hz) 31,250 15,625 10,417 5208 2,604 1,008 504 400.6 200.3 100.5 59.98 50 20.01 16.67 10 5 2.5 1.25 Noise (µV rms) 210 27 7.8 3.6 2.4 1.5 1.1 1 0.73 0.55 0.44 0.42 0.25 0.21 0.16 0.11 0.08 0.07 Noise (µV p-p) 1665 206 63 28 20 12 8 7.6 5.1 3.5 2.5 2.3 1.2 1.1 0.83 0.56 0.41 0.27 Effective Resolution with 5 V Reference (Bits) 15.5 18.5 20.3 21.4 22 22.7 23.1 23.3 23.8 24 24 24 24 24 24 24 24 24 Peak-to-Peak Resolution with 5 V Reference (Bits) 12.8 15.7 17.5 18.7 19.2 19.9 20.4 20.5 21.2 21.4 21.6 21.7 22.4 22.6 22.9 23.4 24 24 The settling time (tSETTLE) is rounded to the nearest microsecond (µs). This settling time is reflected in the output data rate and switching rate. Switching rate = 1 ÷ tSETTLE. Rev. A | Page 32 of 64 Data Sheet AD7173-8 By default, the AD7173-8 is configured with the SING_CYC bit in the ADC Mode Register. This means that only fully settled data is output, thus putting the ADC into a single cycle settling mode. This mode achieves single cycle settling by reducing the output data rate to be equal to the settling time of the ADC for the selected output data rate. This bit has no effect with the sinc5 + sinc1 at output data rates of 2.6 kSPS and lower or when multiple channels are enabled. Figure 59 shows the same step on the analog input but with single cycle settling enabled. At least a single cycle is required for the output to be fully settled. The output data rate is equal to the settling time of the filter at the selected output data rate. ANALOG INPUT FULLY SETTLED ADC OUTPUT 1/ODR Figure 60. Step Input Without Single Cycle Settling ENHANCED 50 Hz AND 60 Hz REJECTION FILTERS The enhanced filters are designed to provide rejection of 50 Hz and 60 Hz simultaneously and to allow the user to trade off settling time and rejection. These filters can operate up to 27.27 SPS or can reject up to 90 dB of 50 Hz ± 1 Hz and 60 Hz ± 1 Hz interference. These filters are realized by post filtering the output of the sinc5 + sinc1 filter. For this reason, the sinc5 + sinc1 filter must be selected when using the enhanced filters. Table 21 shows the output data rates with the accompanying settling time, rejection, and rms noise. Figure 61 to Figure 68 show the frequency domain plots of the responses from the enhanced filters. ANALOG INPUT FULLY SETTLED 11773-059 ADC OUTPUT tSETTLE Figure 60 shows a step on the analog input with this mode disabled, one channel enabled and the Sinc3 filter selected. At least three cycles are required after the step change for the output to reach the final settled value. However, the ADC can then output a new conversion result at the higher rate of 1/ODR. 11773-060 SINGLE CYCLE SETTLING Figure 59. Step Input with Single Cycle Settling Table 21. Enhanced Filter Output Data Rate (ODR), Noise, Settling Time (tSETTLE), and Rejection Using the Enhanced Filters Output Data Rate (SPS) 27.27 25 20 16.67 1 Settling Time (ms) Simultaneous Rejection of 50 Hz ± 1 Hz and 60 Hz ± 1 Hz (dB) 1 Noise (µV rms) Noise (µV p-p) Effective Resolution (Bits) Peak-to-Peak Resolution (Bits) Reference 36.67 40.0 50.0 60.0 47 62 85 90 0.45 0.44 0.41 0.41 3.6 3.6 3.0 3.0 24.4 24.4 24.5 24.5 21.4 21.4 21.7 21.7 See Figure 61 and Figure 64 See Figure 62 and Figure 65 See Figure 63 and Figure 66 See Figure 67 and Figure 68 Master clock = 2 MHz. Rev. A | Page 33 of 64 AD7173-8 Data Sheet 0 –10 –20 –20 –30 –30 –40 –50 –60 –40 –50 –60 –70 –70 –80 –80 –90 –90 –100 200 300 400 500 600 FREQUENCY (Hz) –100 40 –20 –20 –30 –30 FILTER GAIN (dB) 0 –10 –40 –50 –60 –80 –90 –90 –100 –100 40 500 600 FREQUENCY (Hz) –10 –20 –20 –30 –30 FILTER GAIN (dB) –10 –40 –50 –60 –80 –90 –90 –100 500 FREQUENCY (Hz) 65 70 –60 –80 400 60 –50 –70 300 55 –40 –70 600 11773-063 FILTER GAIN (dB) 0 200 50 Figure 65. 25 SPS ODR, 40 ms Settling Time 0 100 45 FREQUENCY (Hz) Figure 62. 25 SPS ODR, 40 ms Settling Time 0 70 –60 –70 400 65 –50 –80 300 60 –40 –70 11773-062 FILTER GAIN (dB) 0 200 55 Figure 64. 27.27 SPS ODR, 36.67 ms Settling Time –10 100 50 FREQUENCY (Hz) Figure 61. 27.27 SPS ODR, 36.67 ms Settling Time 0 45 11773-065 100 Figure 63. 20 SPS ODR, 50 ms Settling Time –100 40 45 50 55 60 65 FREQUENCY (Hz) Figure 66. 20 SPS ODR, 50 ms Settling Time Rev. A | Page 34 of 64 70 11773-066 0 11773-064 FILTER GAIN (dB) 0 –10 11773-061 FILTER GAIN (dB) 50 Hz and 60 Hz Rejection Filter Frequency Domain Plots AD7173-8 0 –10 –10 –20 –20 –30 –30 –40 –50 –60 –40 –50 –60 –70 –70 –80 –80 –90 –90 –100 –100 40 0 100 200 300 400 500 FREQUENCY (Hz) 600 Figure 67. 16.667 SPS ODR, 60 ms Settling Time 45 50 55 60 65 FREQUENCY (Hz) Figure 68. 16.667 SPS ODR, 60 ms Settling Time Rev. A | Page 35 of 64 70 11773-068 FILTER GAIN (dB) 0 11773-067 FILTER GAIN (dB) Data Sheet AD7173-8 Data Sheet OPERATING MODES CONTINUOUS CONVERSION MODE Continuous conversion (see Figure 69) is the default power-up mode. The AD7173-8 converts continuously, and the RDY bit in the status register goes low each time a conversion is complete. If CS is low, the DOUT/RDY line also goes low when a conversion is complete. To read a conversion, the user writes to the communications register, indicating that the next operation is a read of the data register. When the data-word has been read from the data register, DOUT/RDY goes high. The user can read this register additional times, if required. However, the user must ensure that the data register is not being accessed at the completion of the next conversion. When several channels are enabled, the ADC automatically sequences through the enabled channels, performing one conversion on each channel. When all channels are converted, the sequence starts again with the first channel. The channels are converted, in order, from lowest enabled channel to highest enabled channel. The data register is updated as soon as each conversion is available. The DOUT/RDY pin pulses low each time a conversion is available. The user must then read the conversion result while the ADC converts the next enabled channel; otherwise, the new conversion result is lost. If the DATA_STAT bit in the interface mode register is set to 1, the contents of the status register, along with the conversion data, are output each time the data register is read. The status register indicates the channel to which the conversion corresponds. CS 0x44 0x44 DIN DATA DATA 11773-069 DOUT/RDY SCLK Figure 69. Continuous Conversion Mode Rev. A | Page 36 of 64 Data Sheet AD7173-8 To enable continuous read mode, set the CONTREAD bit in the interface mode register. When this bit is set, the only serial interface operations possible are reads from the data register. To exit continuous read mode, issue a dummy read of the ADC data register command (0x44) while RDY is low. Alternatively, apply a software reset, that is, 64 SCLKs with CS = 0 and DIN = 1. This resets the ADC and all register contents. These are the only commands that the interface recognizes after it is placed in continuous read mode. Hold DIN low in continuous read mode until an instruction is to be written to the device. CONTINUOUS READ MODE In continuous read mode (see Figure 70), it is not required that the communications register be written to before the ADC data is read. Instead, apply the required number of SCLKs after DOUT/RDY goes low to indicate the end of a conversion. When the conversion is read, DOUT/RDY returns high until the next conversion is available. In this mode, the data can be read only once. The user must also ensure that the data-word is read before the next conversion is complete. If the user has not read the conversion before the completion of the next conversion or if insufficient serial clocks are applied to the AD7173-8 to read the word, the serial output register is reset shortly before the next conversion is complete, and the new conversion is placed in the output serial register. To use continuous read mode, the ADC must be configured for continuous conversion mode. If multiple ADC channels are enabled, each channel is output in turn, with the status bits being appended to the data if the DATA_STAT bit is set in the interface mode register. The status register indicates the channel to which the conversion corresponds. CS 0x02 0x0080 DIN DATA DATA DATA 11773-070 DOUT/RDY SCLK Figure 70. Continuous Read Mode Rev. A | Page 37 of 64 AD7173-8 Data Sheet SINGLE CONVERSION MODE In single conversion mode (see Figure 71), the AD7173-8 performs a single conversion and is placed in standby mode after the conversion is complete. DOUT/RDY goes low to indicate the completion of a conversion. After the data-word is read from the data register, DOUT/RDY goes high. The data register can be read several times, if required, even when DOUT/RDY is high. If several channels are enabled, the ADC automatically sequences through the enabled channels and performs a conversion on each channel. When a conversion is started, DOUT/RDY goes high and remains high until a valid conversion is available and CS is low. As soon as the conversion is available, DOUT/RDY goes low. The ADC then selects the next channel and begins a conversion. The user must read the present conversion while the next conversion is being performed. As soon as the next conversion is complete, the data register is updated; therefore, the period in which to read the conversion is limited. After the ADC performs a single conversion on each of the selected channels, it returns to standby mode. If the DATA_STAT bit in the interface mode register is set to 1, the contents of the status register, along with the conversion, are output each time the data register is read. The four LSBs of the status register indicate the channel to which the conversion corresponds. CS 0x01 0x2010 0x44 DIN DATA 11773-071 DOUT/RDY SCLK Figure 71. Single Conversion Mode Rev. A | Page 38 of 64 Data Sheet AD7173-8 STANDBY AND POWER-DOWN MODES In standby mode, most blocks are powered down. The LDOs remain active such that the registers maintain their contents. The internal reference remains active, if enabled; and the crystal oscillator remains active, if selected. To power down the reference in standby mode, set the REF_EN bit in the ADC mode register to 0. To power down the clock in standby mode, set the CLOCKSEL bits in the ADC mode register to 00 (internal oscillator). In power-down mode, all blocks are powered down, including the LDOs. All registers lose their contents, and the GPIO outputs are placed in tristate. To prevent accidental entry to power-down mode, the ADC must first be placed into standby mode. Exiting power-down mode requires 64 SCLKs with CS = 0 and DIN = 1, that is, a serial interface reset. A delay of 500 µs is recommended before issuing a subsequent serial interface command to allow the LDO to power up. CALIBRATION MODES The AD7173-8 provides three calibration modes that can be used to eliminate the offset and gain errors on a per setup basis: • • • Internal zero-scale calibration mode System zero-scale calibration mode System full-scale calibration mode Only one channel can be active during calibration. After each conversion, the ADC conversion result is scaled using the ADC calibration registers before being written to the data register. The default value of the offset register is 0x800000, and the nominal value of the gain register is 0x555555. The calibration range of the ADC gain is from 0.4 × VREF to 1.05 × VREF. The following equations show the calculations that are used. In unipolar mode, the ideal relationship—that is, not taking into account the ADC gain error and offset error—is as follows: 0.75 × VIN Gain Data = × 2 23 − (Offset − 0x800000) × ×2 VREF 0x400000 In bipolar mode, the ideal relationship—that is, not taking into account the ADC gain error and offset error—is as follows: 0.75 × VIN Gain Data = × 223 − (Offset − 0x800000) × + 0x800000 VREF 0x400000 To start a calibration, write the relevant value to the MODE bits in the ADC mode register. The DOUT/RDY pin and the RDY bit in the status register go high when the calibration initiates. When the calibration is complete, the contents of the corresponding offset or gain register are updated, the RDY bit in the status register is set, the DOUT/RDY pin returns low (if CS is low), and the AD7173-8 reverts to standby mode. During an internal offset calibration, the selected positive analog input pin is disconnected, and both modulator inputs are connected internally to the selected negative analog input pin. For this reason, it is necessary to ensure that the voltage on the selected negative analog input pin does not exceed the allowed limits and is free from excessive noise and interference. System calibrations, however, expect the system zero-scale (offset) and system full-scale (gain) voltages to be applied to the ADC pins before initiating the calibration modes. As a result, errors external to the ADC are removed. From an operational point of view, treat a calibration like another ADC conversion. An offset calibration, if required, must always be performed before a full-scale calibration. Set the system software to monitor the RDY bit in the status register or the DOUT/RDY pin to determine the end of a calibration via a polling sequence or an interrupt-driven routine. All calibrations require a time that is equal to the settling time of the selected filter and the output data rate to be completed. An internal offset calibration, system zero-scale calibration, and system full-scale calibration can be performed at any output data rate. Using lower output data rates results in better calibration accuracy and is accurate for all output data rates. A new calibration is required for a given channel if the reference source for that channel is changed. The offset error is typically ±40 µV, and an offset calibration reduces the offset error to the order of the noise. The gain error is factory calibrated at ambient temperature. Following this calibration, the gain error is typically ±0.001%. The AD7173-8 provides the user with access to the on-chip calibration registers, allowing the microprocessor to read the calibration coefficients of the device and to write its own calibration coefficients. A read or write of the offset and gain registers can be performed at any time except during an internal or self calibration. Rev. A | Page 39 of 64 AD7173-8 Data Sheet DIGITAL INTERFACE Figure 2 and Figure 3 show timing diagrams for interfacing to the AD7173-8 using CS to decode the part. Figure 2 shows the timing for a read operation from the AD7173-8, and Figure 3 shows the timing for a write operation to the AD7173-8. It is possible to read from the data register several times, even though the DOUT/RDY line returns high after the first read operation. However, take care to ensure that the read operations are completed before the next output update occurs. In continuous read mode, the data register can be read only once. The serial interface can operate in 3-wire mode by tying CS low. In this case, the SCLK, DIN, and DOUT/RDY lines are used to communicate with the AD7173-8. The end of the conversion can also be monitored using the RDY bit in the status register. The serial interface can be reset by writing 64 SCLKs with CS = 0 and DIN = 1. A reset returns the interface to the state in which it expects a write to the communications register. This operation resets the contents of all registers to their power-on values. Following a reset, allow a period of 500 µs before addressing the serial interface. CHECKSUM PROTECTION The AD7173-8 has a checksum mode that can be used to improve interface robustness. Using the checksum ensures that only valid data is written to a register and allows data read from a register to be validated. If an error occurs during a register write, the CRC_ERROR bit is set in the status register. However, For CRC checksum calculations during a write operation, the following polynomial is always used: x8 + x2 + x + 1 During read operations, the user can select between this polynomial and a similar XOR function. The XOR function requires less time to process on the host microcontroller than the polynomial-based checksum. The CRC_EN bits in the interface mode register enable and disable the checksum and allow the user to select between the polynomial check and the simple XOR check. The checksum is appended to the end of each read and write transaction. The checksum calculation for the write transaction is calculated using the 8-bit command word and the 8- to 24-bit data. For a read transaction, the checksum is calculated using the command word and the 8- to 32-bit data output. Figure 72 and Figure 73 show SPI write and read transactions, respectively. 8-BIT COMMAND UP TO 24-BIT INPUT 8-BIT CRC CMD DATA CRC CS DIN 11773-072 The DOUT/RDY pin also functions as a data-ready signal, with the line going low if CS is low when a new data-word is available in the data register. The pin is reset high when a read operation from the data register is complete. The DOUT/RDY pin also goes high before updating the data register to indicate when not to read from the device to ensure that a data read is not attempted while the register is being updated. Take care to avoid reading from the data register when DOUT/RDY is about to go low. The best method to ensure that no data read occurs is to always monitor the DOUT/RDY line; start reading the data register as soon as DOUT/RDY goes low; and ensure a sufficient SCLK rate, such that the read is completed before the next conversion result. CS is used to select a device. It can be used to decode the AD7173-8 in systems where several components are connected to the serial bus. to ensure that the register write was successful, it is important to read back the register and verify the checksum. SCLK Figure 72. SPI Write Transaction with CRC 8-BIT COMMAND UP TO 32-BIT OUTPUT 8-BIT CRC CS DIN DOUT/ RDY CMD DATA CRC SCLK 11337-073 The programmable functions of the AD7173-8 are via the SPI serial interface. The serial interface of the AD7173-8 consists of four signals: CS, DIN, SCLK, and DOUT/RDY. The DIN line is used to transfer data into the on-chip registers, and DOUT/RDY is used to access data from the on-chip registers. SCLK is the serial clock input for the device, and all data transfers (either on DIN or on DOUT/RDY) occur with respect to the SCLK signal. Figure 73. SPI Read Transaction with CRC If checksum protection is enabled when continuous read mode is active, there is an implied read data command of 0x44 before every data transmission that must be accounted for when calculating the checksum value. This ensures a nonzero checksum value even if the ADC data equals 0x000000. Rev. A | Page 40 of 64 Data Sheet AD7173-8 CRC CALCULATION Polynomial The checksum, which is eight bits wide, is generated using the following polynomial: x 8 + x2 + x + 1 To generate the checksum, the data is left shifted by eight bits to create a number ending in eight Logic 0s. The polynomial is aligned such that its MSB is adjacent to the leftmost Logic 1 of the data. An exclusive OR (XOR) function is applied to the data to produce a new, shorter number. The polynomial is again aligned so that its MSB is adjacent to the leftmost Logic 1 of the new result, and the procedure is repeated. This process is repeated until the original data is reduced to a value less than the polynomial. This is the 8-bit checksum. Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) An example of generating the 8-bit checksum using the polynomial based checksum is as follows: Initial value 011001010100001100100001 x +x +x+1 8 2 01100101010000110010000100000000 left shifted eight bits = polynomial 100000111 100100100000110010000100000000 100000111 XOR result polynomial 100011000110010000100000000 100000111 XOR result polynomial 11111110010000100000000 100000111 XOR result polynomial value 1111101110000100000000 100000111 XOR result polynomial value 111100000000100000000 100000111 XOR result polynomial value 11100111000100000000 100000111 XOR result polynomial value 1100100100100000000 100000111 XOR result polynomial value 100101010100000000 100000111 XOR result polynomial value 101101100000000 100000111 1101011000000 100000111 101010110000 100000111 1010001000 100000111 10000110 XOR result polynomial value XOR result polynomial value XOR result polynomial value XOR result polynomial value checksum = 0x86. Rev. A | Page 41 of 64 AD7173-8 Data Sheet XOR Calculation The checksum, which is 8-bits wide, is generated by splitting the data into bytes and then performing an XOR of the bytes. Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) Using the previous example, Divide into three bytes: 0x65, 0x43, and 0x21 01100101 0x65 01000011 0x43 00100110 XOR result 00100001 0x21 00000111 CRC Rev. A | Page 42 of 64 Data Sheet AD7173-8 INTEGRATED FUNCTIONS The AD7173-8 has a number of integrated functions that can be used to improve usefulness in a number of applications, as well as for diagnostic purposes in safety conscious applications. GENERAL-PURPOSE I/O The AD7173-8 has two general-purpose digital input/output pins (GPIO0, GPIO1) and two general-purpose digital output pins (GPO2, GPO3). As the naming convention suggests, the GPIO0 and GPIO1 pins can be configured as inputs or outputs, but GPO2 and GPO3 are outputs only. The GPIO and GPO pins are enabled using the following bits in the GPIOCON register: IP_EN0, IP_EN1 (or OP_EN0, OP_EN1) for GPIO0 and GPIO1, and OP_EN2_3 for GPO2 and GPO3. When the GPIO0 or GPIO1 pin is enabled as an input, the logic level at the pin is contained in the GP_DATA0 or GP_DATA1 bit, respectively. When the GPIO0, GPIO1, GPO2, or GPO3 pin is enabled as an output, the GP_DATA0, GP_DATA1, GP_DATA2, or GP_DATA3 bit, respectively, determines the logic level output at the pin. The logic levels for these pins are referenced to AVDD1 and AVSS; therefore, outputs have an amplitude of either 5 V or 3.3 V depending on the AVDD1 − AVSS voltage. The ERROR pin can also be used as a general-purpose output if the ERR_EN bits in the GPIOCON register are set to 11. In this configuration, the ERR_DAT bit in the GPIOCON register determines the logic level output at the ERROR pin. The logic level for the pin is referenced to IOVDD and DGND, and the ERROR pin has an active pull-up. EXTERNAL MULTIPLEXER CONTROL conversion time the same but may affect the noise performance, depending on the length of the delay compared to the conversion time. It is only possible to absorb the delay for output data rates less than 2.6 kSPS, with the exception of four rates which cannot absorb any delay: 381 SPS, 59.52 SPS, 49.68 SPS and 16.63 SPS. 16-BIT/24-BIT CONVERSIONS By default, the AD7173-8 generates 24-bit conversions. However, the width of the conversions can be reduced to 16 bits. Setting Bit WL16 in the interface mode register to 1 rounds all data conversions to 16 bits. Clearing this bit sets the width of the data conversions to 24 bits. SERIAL INTERFACE RESET (DOUT_RESET) The serial interface is reset when each read operation is complete. The instant at which the serial interface is reset is programmable. By default, the serial interface is reset after a short period of time following the last SCLK rising edge, the SCLK edge on which the LSB is read by the processor. By setting the DOUT_RESET bit to 1 in the interface mode register, the instant at which the interface is reset is controlled by the CS rising edge. In this case, the DOUT/RDY pin continues to output the LSB of the register being read until CS is taken high. Only on the CS rising edge is the interface reset. This configuration is useful if the CS signal is used to frame all read operations. If CS is not used to frame all read operations, DOUT_RESET must be set to 0 so that the interface is reset following the last SCLK edge in the read operation. SYNCHRONIZATION Normal Synchronization If an external multiplexer is used to increase the channel count, the multiplexer logic pins can be controlled using the AD7173-8 GPIO and GPO pins. When the MUX_IO bit is set in the GPIOCON register (Address 0x06, Bit 12), the timing of the GPIO pins is controlled by the ADC; therefore, the channel change is synchronized with the ADC, eliminating any need for external synchronization. DELAY It is possible to insert a programmable delay before the AD7173-8 begins taking samples when using the sinc5 + sinc1 filter. This allows for an external amplifier or multiplexer to settle and can also relax the specification requirements for the external amplifier or multiplexer. There are 8 programmable settings ranging from 0 μs to 8 ms which can be set using the DELAY bits in the ADC Mode Register (Address 0x01, Bits[10:8]). If a delay greater than 0 μs is selected and HIDE_DELAY in the Interface Mode Register (Address 0x02, Bit 10) is set to 1, then this delay is added to the conversion time for each sample regardless of selected output data rate. If HIDE_DELAY is set to 0 and the selected delay is less than half of the conversion time, then the delay can be absorbed by reducing the number of averages performed. This keeps the When the SYNC_EN bit in the GPIOCON register is set to 1, the SYNC pin functions as a synchronization pin. The SYNC input allows the user to reset the modulator and the digital filter without affecting any of the setup conditions on the part. This allows the user to start gathering samples of the analog input from a known point in time, that is, the rising edge of SYNC. This pin must be low for at least one master clock cycle to ensure that synchronization occurs. If multiple channels are enabled, the sequencer is reset to the first enabled channel. If multiple AD7173-8 devices are operated from a common master clock, they can be synchronized so that their data registers are updated simultaneously. This is normally done after each AD7173-8 has performed its own calibration or has calibration coefficients loaded into its calibration registers. A falling edge on the SYNC pin resets the digital filter and the analog modulator and places the AD7173-8 into a consistent known state. While the SYNC pin is low, the AD7173-8 is maintained in this state. On the SYNC rising edge, the modulator and filter are taken out of this reset state, and on the next master clock edge, the part starts to gather input samples again. The part is taken out of reset on the master clock falling edge following the SYNC low-to-high transition. Therefore, when Rev. A | Page 43 of 64 AD7173-8 Data Sheet multiple devices are being synchronized, take the SYNC pin high on the master clock rising edge to ensure that all devices begin sampling on the master clock falling edge. If the SYNC pin is not taken high in sufficient time, it is possible to have a difference of one master clock cycle between the devices; that is, the instant at which conversions are available differs from part to part by a maximum of one master clock cycle. The SYNC pin can also be used as a start conversion command. In this mode, the rising edge of SYNC starts a conversion, and the falling edge of RDY indicates when the conversion is complete. The settling time of the filter must be allowed for each data register update. Alternate Synchronization Setting Bit ALT_SYNC in the interface mode register to 1 enables an alternate synchronization scheme. The SYNC_EN bit in the GPIOCON register must be set to 1 to enable this alternate scheme. In this mode, the SYNC pin operates as a start conversion command when several channels of the AD7173-8 are enabled. When SYNC is taken low, the ADC completes the conversion on the current channel, selects the next channel in the sequence, and then waits until SYNC is taken high to commence the conversion. The RDY pin goes low when the conversion is complete on the current channel, and the data register is updated with the corresponding conversion. Therefore, the SYNC command does not interfere with the sampling on the currently selected channel but allows the user to control the instant at which the conversion begins on the next channel in the sequence. This mode can be used only when several channels are enabled. It is not recommended to use this mode when a single channel is enabled. ERROR FLAGS The status register contains three error bits—ADC_ERROR, CRC_ERROR, and REG_ERROR—that flag errors with the ADC conversion, errors with the CRC check, and errors due to changes in the registers, respectively. In addition, the ERROR pin can indicate that an error has occurred. ADC_ERROR The ADC_ERROR bit in the status register flags any errors that occur during the conversion process. The flag is set when an overrange or underrange occurs at the output of the ADC. When an underrange or overrange occurs, the ADC also outputs all 0s or all 1s, respectively. This flag is reset only when the underrange or overrange is removed. It is not reset by a read of the data register. CRC_ERROR If the CRC value that accompanies a write operation does not correspond with the information sent, the CRC_ERROR flag is set. The flag is reset as soon as the status register is explicitly read. REG_ERROR the AD7173-8 monitors the values in the on-chip registers. If a bit changes, the REG_ERROR bit is set. Therefore, for writes to the on-chip registers, ensure that REG_CHECK is set to 0. When the registers have been updated, the REF_CHK bit can be set to 1. The AD7173-8 calculates a checksum of the on-chip registers. If one of the register values has changed, the REG_ERROR bit is set. If an error is flagged, the REG_CHECK bit must be set to 0 to clear the REG_ERROR bit in the status register. The register check function does not monitor the data register, status register, or interface mode register. ERROR Pin The ERROR pin functions as an error input/output pin or a general-purpose output pin. The ERR_EN bits in the GPIOCON register determine the function of the pin. When the ERR_EN bits are set to 10, the pin functions as an open-drain error output pin. The three error bits in the status register (ADC_ERROR, CRC_ERROR, and REG_ERROR) are OR’ed, inverted, and mapped to the ERROR pin. Therefore, the ERROR pin indicates that an error has occurred. To identify the error source, read the status register. When ERR_EN bits are set to 01, the ERROR pin functions as an error input pin. The error pin of another component can be connected to the AD7173-8 ERROR pin so that the AD7173-8 indicates when an error occurs on either itself or the external component. The value on the ERROR pin is inverted and OR’ed with the errors from the ADC conversion, and the result is indicated via the ADC_ERROR bit in the status register. The value of the ERROR pin is reflected in the ERR_DAT bit in the status register. The ERROR pin is disabled when the ERR_EN bits are set to 00. When the ERR_EN1 bits are set to 11, the ERROR pin operates as a general-purpose output. DATA_STAT The contents of the status register can be appended to each conversion on the AD7173-8. This is a useful function if several channels are enabled. Each time a conversion is output, the contents of the status register are appended. The four LSBs of the status register indicate to which channel the conversion corresponds. In addition, the user can determine if any errors are being flagged by the error bits. IOSTRENGTH BIT The serial interface can operate with a power supply as low as 2 V. At higher speeds (from 10 MHz to 15 MHz upward), the DOUT/RDY pin may not have sufficient drive strength if there is moderate parasitic capacitance on the board. The IOSTRENGTH bit in the interface mode register increases the drive strength of the DOUT/RDY pin. It is recommended that this bit be kept to its default value unless a high frequency SPI SCLK (that is, ~15 MHz upward) is being used. This flag is used in conjunction with the REG_CHECK bit in the interface mode register. When the REG_CHECK bit is set, Rev. A | Page 44 of 64 Data Sheet AD7173-8 GROUNDING AND LAYOUT The analog inputs and reference inputs are differential and, therefore, most of the voltages in the analog modulator are common-mode voltages. The high common-mode rejection of the part removes common-mode noise on these inputs. The analog and digital supplies to the AD7173-8 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. The digital filter provides rejection of broadband noise on the power supplies, except at integer multiples of the master clock frequency. with digital ground to prevent radiating noise to other sections of the board and never run clock signals near the analog inputs. Avoid crossover of digital and analog signals. Run traces on opposite sides of the board at right angles to each other. This reduces the effects of feedthrough on the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, whereas signals are placed on the solder side. The digital filter also removes noise from the analog and reference inputs, provided that these noise sources do not saturate the analog modulator. As a result, the AD7173-8 is more immune to noise interference than a conventional high resolution converter. However, because the resolution of the AD7173-8 is high and the noise levels from the converter are so low, take care with regard to grounding and layout. Good decoupling is important when using high resolution ADCs. The AD7173-8 has three power supply pins: AVDD1, AVDD2, and IOVDD. The AVDD1 and AVDD2 pins are referenced to AVSS, and the IOVDD pin is referenced to DGND. Decouple AVDD1 and AVDD2 with a 10 μF tantalum capacitor in parallel with a 0.1 μF capacitor to AVSS on each pin. Place the 0.1 μF capacitor as near as possible to the device on each supply, ideally right up against the device. Decouple IOVDD with a 10 μF tantalum capacitor, in parallel with a 0.1 μF capacitor to DGND. Decouple all analog inputs to AVSS. If an external reference is used, decouple the REF+ and REF− pins to AVSS. The printed circuit board (PCB) that houses the ADC must be designed so that the analog and digital sections are separated and confined to certain areas of the board. A minimum etch technique is generally best for ground planes because it results in the best shielding. In any layout, the user must keep in mind the flow of currents in the system, ensuring that the paths for all return currents are as close as possible to the paths the currents took to reach their destinations. If using the AD7173-8 for split supply operation, a separate plane must be used for AVSS. As an example, the EVAL-AD7173-8SDZ customer evaluation board uses a 4-layer PCB, with the largest central section of Layer 3 used as the AVSS plane. Figure 74 shows the PCB layout of this layer. 11773-074 Avoid running digital lines under the device because this couples noise onto the die and allows the analog ground plane to run under the AD7173-8 to prevent noise coupling. The power supply lines to the AD7173-8 must use as wide a trace as possible to provide low impedance paths and reduce glitches on the power supply line. Shield fast switching signals like clocks The AD7173-8 also has two on-board LDO regulators—one that regulates the AVDD2 supply and one that regulates the IOVDD supply. For the REGCAPA pin, it is recommended that 1 μF and 0.1 μF capacitors to AVSS be used. Similarly, for the REGCAPD pin, it is recommended that 1 μF and 0.1 μF capacitors to DGND be used. Figure 74. EVAL-AD7173-8SDZ, PCB Layer 3 Rev. A | Page 45 of 64 AD7173-8 Data Sheet REGISTER SUMMARY Table 22. Register Summary Reg 0x00 Name COMMS Bits [7:0] Bit 7 WEN 0x00 STATUS [7:0] RDY 0x01 ADCMODE REF_EN RESERVED RESERVED 0x02 IFMODE [15:8] [7:0] [15:8] CONTREAD DATA_STAT 0x03 0x04 0x06 0x07 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 [7:0] REGCHECK [23:16] [15:8] [7:0] DATA [23:0] GPIOCON [15:8] [7:0] ID [15:8] [7:0] CH0 [15:8] [7:0] CH1 [15:8] [7:0] CH2 [15:8] [7:0] CH3 [15:8] [7:0] CH4 [15:8] [7:0] CH5 [15:8] [7:0] CH6 [15:8] [7:0] CH7 [15:8] [7:0] CH8 [15:8] [7:0] CH9 [15:8] [7:0] CH10 [15:8] [7:0] CH11 [15:8] [7:0] CH12 [15:8] [7:0] CH13 [15:8] [7:0] CH14 [15:8] [7:0] CH15 [15:8] [7:0] SETUPCON0 [15:8] [7:0] 0x21 0x22 SETUPCON1 [15:8] [7:0] SETUPCON2 [15:8] [7:0] Bit 6 R/W ADC_ERROR Bit 5 Bit 4 CRC_ERROR REG_ERROR SING_CYC MODE PDSW GP_DATA2 CH_EN0 AINPOS0[2:0] CH_EN1 AINPOS1[2:0] CH_EN2 AINPOS2[2:0] CH_EN3 AINPOS3[2:0] CH_EN4 AINPOS4[2:0] CH_EN5 AINPOS5[2:0] CH_EN6 AINPOS6[2:0] CH_EN7 AINPOS7[2:0] CH_EN8 AINPOS8[2:0] CH_EN9 AINPOS9[2:0] CH_EN10 AINPOS10[2:0] CH_EN11 AINPOS11[2:0] CH_EN12 AINPOS12[2:0] CH_EN13 AINPOS13[2:0] CH_EN14 AINPOS14[2:0] CH_EN15 AINPOS15[2:0] RESERVED BURNOUT_ EN0 BURNOUT_ EN1 BURNOUT_ EN2 BUFCHOPMAX 0 RESERVED BUFCHOPMAX 1 RESERVED BUFCHOPMAX 2 Bit 2 RA Bit 1 Bit 0 CHANNEL ALT_SYNC Reset 0x00 RW W 0x80 R 0x2000 RW 0x0000 RW 0x000000 R 0x000000 0x0800 R RW 0x30DX1 R 0x8001 RW 0x0001 RW 0x0001 RW 0x0001 RW 0x0001 RW 0x0001 RW 0x0001 RW 0x0001 RW 0x0001 RW 0x0001 RW 0x0001 RW 0x0001 RW 0x0001 RW 0x0001 RW 0x0001 RW 0x0001 RW 0x1000 RW AIN_BUF 1[1:0] 0x1000 RW AIN_BUF 2[1:0] 0x1000 RW RESERVED RESERVED RESERVED GP_DATA3 Bit 3 DELAY CLOCKSEL RESERVED IOSTRENGTH HIDE_DELAY RESERVED DOUT_RESET REG_CHECK RESERVED CRC_EN RESERVED WL16 REGISTER_CHECK[23:16] REGISTER_CHECK[15:8] REGISTER_CHECK[7:0] DATA[23:0] OP_EN2_3 MUX_IO SYNC_EN ERR_EN ERR_DAT IP_EN1 IP_EN0 OP_EN1 OP_EN0 GP_DATA1 GP_DATA0 ID[15:8] ID[7:0] SETUP_SEL0 RESERVED AINPOS0[4:3] AINNEG0 SETUP_SEL1 RESERVED AINPOS1[4:3] AINNEG1 SETUP_SEL2 RESERVED AINPOS2[4:3] AINNEG2 SETUP_SEL3 RESERVED AINPOS3[4:3] AINNEG3 SETUP_SEL4 RESERVED AINPOS4[4:3] AINNEG4 SETUP_SEL5 RESERVED AINPOS5[4:3] AINNEG5 SETUP_SEL6 RESERVED AINPOS6[4:3] AINNEG6 SETUP_SEL7 RESERVED AINPOS7[4:3] AINNEG7 SETUP_SEL8 RESERVED AINPOS8[4:3] AINNEG8 SETUP_SEL9 RESERVED AINPOS9[4:3] AINNEG9 SETUP_SEL10 RESERVED AINPOS10[4:3] AINNEG10 SETUP_SEL11 RESERVED AINPOS11[4:3] AINNEG11 SETUP_SEL12 RESERVED AINPOS12[4:3] AINNEG12 SETUP_SEL13 RESERVED AINPOS13[4:3] AINNEG13 SETUP_SEL14 RESERVED AINPOS14[4:3] AINNEG14 SETUP_SEL15 RESERVED AINPOS15[4:3] AINNEG15 REF_BUF 0[1:0] AIN_BUF 0[1:0] BI_ UNIPOLAR0 REF_SEL0 RESERVED BI_UNIPOLAR1 REFSEL1 REF_BUF 1[1:0] BI_UNIPOLAR2 REFSEL2 REF_BUF 2[1:0] Rev. A | Page 46 of 64 RESERVED RESERVED Data Sheet Reg 0x23 0x24 0x25 0x26 0x27 Name Bits SETUPCON3 [15:8] [7:0] SETUPCON4 [15:8] [7:0] SETUPCON5 [15:8] [7:0] SETUPCON6 [15:8] [7:0] SETUPCON7 [15:8] [7:0] AD7173-8 Bit 7 BURNOUT_ EN3 BURNOUT_ EN4 BURNOUT_ EN5 BURNOUT_ EN6 BURNOUT_ EN7 SINC3_MAP0 RESERVED SINC3_MAP1 RESERVED SINC3_MAP2 RESERVED SINC3_MAP3 RESERVED SINC3_MAP4 RESERVED SINC3_MAP5 RESERVED SINC3_MAP6 RESERVED SINC3_MAP7 RESERVED Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESERVED BI_UNIPOLAR3 REF_BUF 3[1:0] AIN_BUF 3[1:0] REFSEL3 RESERVED BUFCHOPMAX 3 RESERVED BI_UNIPOLAR4 REF_BUF 4[1:0] AIN_BUF 4[1:0] REFSEL4 RESERVED BUFCHOPMAX 4 RESERVED BI_UNIPOLAR5 REF_BUF 5[1:0] AIN_BUF 5[1:0] REFSEL5 RESERVED BUFCHOPMAX 5 RESERVED BI_UNIPOLAR6 REF_BUF 6[1:0] AIN_BUF 6[1:0] REFSEL6 RESERVED BUFCHOPMAX 6 RESERVED BI_UNIPOLAR7 REF_BUF 7[1:0] AIN_BUF 7[1:0] REFSEL7 RESERVED BUFCHOPMAX 7 RESERVED ENHFILTEN0 ENHFILT0 ORDER0 ODR0 RESERVED ENHFILTEN1 ENHFILT1 ORDER1 ODR1 RESERVED ENHFILTEN2 ENHFILT2 ORDER2 ODR2 RESERVED ENHFILTEN3 ENHFILT3 ORDER3 ODR3 RESERVED ENHFILTEN4 ENHFILT4 ORDER4 ODR4 RESERVED ENHFILTEN5 ENHFILT5 ORDER5 ODR5 RESERVED ENHFILTEN6 ENHFILT6 ORDER6 ODR6 RESERVED ENHFILTEN7 ENHFILT7 ORDER7 ODR7 OFFSET0[23:0] OFFSET1[23:0] OFFSET2[23:0] OFFSET3[23:0] OFFSET4[23:0] OFFSET5[23:0] OFFSET6[23:0] OFFSET7[23:0] GAIN0[23:0] GAIN1[23:0] Reset 0x1000 RW RW 0x1000 RW 0x1000 RW 0x1000 RW 0x1000 RW 0x0000 RW 0x0000 RW 0x0000 RW 0x0000 RW 0x0000 RW 0x0000 RW 0x0000 RW 0x0000 RW 0x800000 0x800000 0x800000 0x800000 0x800000 0x800000 0x800000 0x800000 0x5XXXX02 0x5XXXX02 RW RW RW RW RW RW RW RW RW RW 0x28 FILTCON0 0x29 FILTCON1 0x2A FILTCON2 0x2B FILTCON3 0x2C FILTCON4 0x2D FILTCON5 0x2E FILTCON6 0x2F FILTCON7 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 OFFSET0 OFFSET1 OFFSET2 OFFSET3 OFFSET4 OFFSET5 OFFSET6 OFFSET7 GAIN0 GAIN1 [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] 0x3A GAIN2 [23:0] GAIN2[23:0] 0x5XXXX02 RW 0x3B GAIN3 [23:0] GAIN3[23:0] 0x5XXXX02 RW 0x3C GAIN4 [23:0] GAIN4[23:0] 2 RW 0x3D GAIN5 [23:0] GAIN5[23:0] 2 RW 2 0x5XXXX0 0x5XXXX0 0x3E GAIN6 [23:0] GAIN6[23:0] 0x5XXXX0 RW 0x3F GAIN7 [23:0] GAIN7[23:0] 0x5XXXX02 RW 1 2 X = don’t care. The value of X is specific to the ADC. The value of X varies, depending on the IC that is used. Rev. A | Page 47 of 64 AD7173-8 Data Sheet REGISTER DETAILS COMMUNICATIONS REGISTER Address: 0x00, Reset: 0x00, Name: COMMS Table 23. Bit Descriptions for COMMS Bits 7 Bit Name WEN 6 R/W Settings 0 1 [5:0] RA 000000 000001 000010 000011 000100 000110 000111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 Description This bit must be low to begin communications with the ADC. Reset 0x0 Access W This bit determines if the command is a read or write operation. Write command Read command The register address bits determine which register is to be read from or written to as part of the current communication. Status register ADC mode register Interface mode register Register checksum register Data register GPIO configuration register ID register Channel 0 register Channel 1 register Channel 2 register Channel 3 register Channel 4 register Channel 5 register Channel 6 register Channel 7 register Channel 8 register Channel 9 register Channel 10 register Channel 11 register Channel 12 register Channel 13 register Channel 14 register Channel 15 register Setup Configuration 0 register Setup Configuration 1 register Setup Configuration 2 register Setup Configuration 3 register Setup Configuration 4 register Setup Configuration 5 register Setup Configuration 6 register Setup Configuration 7 register Filter Configuration 0 register Filter Configuration 1 register Filter Configuration 2 register Filter Configuration 3 register Filter Configuration 4 register Filter Configuration 5 register Filter Configuration 6 register Filter Configuration 7 register Offset 0 register Offset 1 register 0x0 W 0x00 W Rev. A | Page 48 of 64 Data Sheet Bits Bit Name AD7173-8 Settings 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 Description Offset 2 register Offset 3 register Offset 4 register Offset 5 register Offset 6 register Offset 7 register Gain 0 register Gain 1 register Gain 2 register Gain 3 register Gain 4 register Gain 5 register Gain 6 register Gain 7 register Reset Rev. A | Page 49 of 64 Access AD7173-8 Data Sheet STATUS REGISTER Address: 0x00, Reset: 0x80, Name: STATUS The status register is an 8-bit register that contains ADC and serial interface status information. It can optionally be appended to the data register by setting the DATA_STAT bit in the interface mode register (Bit 6, Register 0x02). Table 24. Bit Descriptions for STATUS Bits 7 Bit Name RDY Settings 0 1 6 ADC_ERROR 0 1 5 CRC_ERROR 0 1 4 REG_ERROR 0 1 [3:0] CHANNEL 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description The status of RDY is output to the DOUT/RDYpin whenever CS is low and a register is not being read. This bit goes low when the ADC has written a new result to the data register. In ADC calibration modes, this bit goes low when the ADC has written the calibration result. RDY is brought high automatically by a read of the data register. New data result available Awaiting new data result This bit, by default, indicates if an ADC overrange or underrange has occurred. The ADC result is clamped to ± full scale if an overrange or underrange occurs. This bit is updated when the ADC result is written and is cleared by removing the overrange or underrange condition on the analog inputs. No error Error This bit indicates if a CRC error has occurred during a register write. For register reads, the host microcontroller determines if a CRC error has occurred. This bit is cleared by a read of this register. No error CRC error This bit indicates if the content of one of the internal registers has changed from the value calculated when the register integrity check was activated. The check is activated by setting the REG_CHECK bit in the interface mode register. This bit is cleared by clearing the REG_CHECK bit. No error Error These bits indicate which channel was active for the ADC conversion whose result is currently in the data register. This may be different from the channel currently being converted. The bits are a direct mapping from the Channel x registers; therefore, Channel 0 results in 0x0 and Channel 15 results in 0x1F. Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Channel 8 Channel 9 Channel 10 Channel 11 Channel 12 Channel 13 Channel 14 Channel 15 Rev. A | Page 50 of 64 Reset 0x1 Access R 0x0 R 0x0 R 0x0 R 0x0 R Data Sheet AD7173-8 ADC MODE REGISTER Address: 0x01, Reset: 0x2000, Name: ADCMODE The ADC mode register controls the operating mode of the ADC and the master clock selection. A write to the ADC mode register resets the filter and the RDY bits and starts a new conversion or calibration. Table 25. Bit Descriptions for ADCMODE Bits 15 Bit Name REF_EN Settings 0 1 14 13 RESERVED SING_CYC 0 1 [12:11] [10:8] RESERVED DELAY 000 001 010 011 100 101 110 111 7 [6:4] RESERVED MODE 000 001 010 011 100 110 111 [3:2] CLOCKSEL 00 01 10 11 [1:0] RESERVED Description Enables internal reference and outputs a buffered 2.5 V to the REFOUT pin. Disabled Enabled This bit is reserved. Set to 0. This bit can be used when only a single channel is active to set the ADC to output only at the settled filter data rate. Disabled Enabled These bits are reserved. Set to 0. These bits allow a programmable delay to be added after a channel switch to allow settling of external circuitry before the ADC starts processing its input. 0 μs 32 μs 128 μs 320 μs 800 μs 1.6 ms 4 ms 8 ms This bit is reserved. Set to 0. These bits control the operating mode of the ADC. Details can be found in the Operating Modes section. Continuous conversion mode Single conversion mode Standby mode Power-down mode Internal offset calibration System offset calibration System gain calibration This bit is used to select the ADC clock source. Selecting the internal oscillator also enables the internal oscillator. Internal oscillator Internal oscillator output on XTAL2/CLKIO pin External clock input on XTAL2/CLKIO pin External crystal on XTAL1 and XTAL2/CLKIO pins These bits are reserved. Set to 0. Rev. A | Page 51 of 64 Reset 0x0 Access RW 0x0 0x1 R RW 0x0 0x0 R RW 0x0 0x0 R RW 0x0 RW 0x0 R AD7173-8 Data Sheet INTERFACE MODE REGISTER Address: 0x02, Reset: 0x0000, Name: IFMODE The interface mode register configures various serial interface options. Table 26. Bit Descriptions for IFMODE Bits [15:13] 12 Bit Name RESERVED ALT_SYNC Settings 0 1 11 IOSTRENGTH 0 1 10 HIDE_DELAY 0 1 9 8 RESERVED DOUT_RESET 0 1 7 CONTREAD 0 1 6 DATA_STAT 0 1 5 REG_CHECK 0 1 4 RESERVED Description These bits are reserved. Set to 0. This bit enables a different behavior of the SYNC pin to allow the use of SYNC as a control for conversions when cycling channels. (For details, see the description of the SYNC_EN bit in the GPIO Configuration Register.) Disabled Enabled This bit controls the drive strength of the DOUT (DOUT/RDY) pin and the XTAL2/CLKIO pin. Set this bit to 1 when reading from the serial interface at high speed with low IOVDD supply and moderate capacitance. Disabled (default) Enabled If a programmable delay is set using the DELAY bits in the ADC mode register, then this bit allows for the delay to be hidden by absorbing the delay into the conversion time for selected data rates. See the Delay section for more details. Enabled Disabled These bits are reserved. Set to 0. This bit prevents the DOUT/RDY pin from switching from outputting DOUT to outputting RDY soon after the last rising edge of SCLK during a read operation. Instead, the DOUT/RDY pin continues to output the LSB of the data until CS goes high, providing longer hold times for the SPI master to sample the LSB of the data. When this bit is set, CS must not be tied low. Disabled Enabled This bit enables continuous read of the ADC data register. To use continuous read, configure the ADC in continuous conversion mode. For more details, see the Operating Modes section. Disabled Enabled This bit enables the status register to be appended to the data register when read so that channel and status information is transmitted with the data. This is the only way to ensure that the channel bits read from the status register correspond to the data in the data register. Disabled Enabled This bit enables a register integrity checker that can be used to monitor any change in the value of the user registers. To use this feature, configure all other registers as desired, with this bit cleared. Then write to this register to set the REG_CHECK bit to 1. If the contents of any of the registers change, the REG_ERROR bit is set in the status register. To clear the error, set the REG_CHECK bit to 0. Neither the interface mode register nor the ADC data or status register is included in the registers that are checked. If a register must have a new value written, clear this bit first; otherwise, an error is flagged when the new register contents are written. Disabled Enabled This bit is reserved. Set to 0. Rev. A | Page 52 of 64 Reset 0x0 0x0 Access R RW 0x0 RW 0x0 RW 0x0 0x0 R RW 0x0 RW 0x0 RW 0x0 RW 0x0 R Data Sheet Bits [3:2] Bit Name CRC_EN AD7173-8 Settings 00 01 10 1 0 RESERVED WL16 0 1 Description Enables CRC protection of register reads/writes. CRC increases the number of bytes in a serial interface transfer by one. See the CRC Calculation section for more details. Disabled. XOR checksum enabled for register read transactions. Register writes still use CRC with these bits set. CRC checksum enabled for read and write transactions. This bit is reserved. Set to 0. Changes the ADC data register to 16 bits. The ADC is not reset by a write to the interface mode register; therefore, the ADC result is not rounded to the correct word length immediately after writing to these bits. The first new ADC result is correct. 24-bit data 16-bit data Reset 0x00 Access RW 0x0 0x0 R RW REGISTER CHECK Address: 0x03, Reset: 0x000000, Name: REGCHECK The register check register is a 24-bit checksum calculated by XOR'ing the contents of the user registers and some nonaccessible registers. The REG_CHECK bit in the interface mode register must be set for this to operate; otherwise, the register reads 0. Table 27. Bit Descriptions for REGCHECK Bits [23:0] Bit Name REGISTER_CHECK Settings Description This register contains the 24-bit checksum of user registers when the REG_CHECK bit is set in the interface mode register. Reset 0x000000 Access R DATA REGISTER Address: 0x04, Reset: 0x000000, Name: DATA The data register contains the ADC conversion result. The encoding is offset binary; however, it can be changed to unipolar by the BI_UNIPOLAR bit in the setup configuration register. Reading the data register brings the RDY bit and pin high if they are low. The ADC result can be read multiple times; however, because RDY has been brought high, it is not possible to know if another ADC result is imminent. The ADC does not write a new result into the data register if the register is currently being read. Table 28. Bit Descriptions for DATA Bits [23:0] Bit Name DATA Settings Description This register contains the ADC conversion result. If the DATA_STAT bit is set in the interface mode register, the status register is appended to this register when read, making this a 32-bit register. If WL16 is set in the interface mode register, this register is set to a length of 16 bits. Rev. A | Page 53 of 64 Reset 0x000000 Access R AD7173-8 Data Sheet GPIO CONFIGURATION REGISTER Address: 0x06, Reset: 0x0800, Name: GPIOCON The GPIO configuration register controls the general-purpose I/O pins of the ADC. Table 29. Bit Descriptions for GPIOCON Bits 15 14 Bit Name RESERVED PDSW 13 OP_EN2_3 12 MUX_IO 11 SYNC_EN Settings 0 1 [10:9] ERR_EN 00 01 10 11 8 ERR_DAT 7 6 5 GP_DATA3 GP_DATA2 IP_EN1 0 1 Description This bit is reserved. Set to 0. This bit enables/disables the power-down switch function. Setting the bit allows the pin to sink current. This function can be used for bridge sensor applications where the switch controls the power-up/power-down of the bridge. This bit enables the GPO2 and GPO3 pins. Outputs are referenced between AVDD1 and AVSS. This bit allows the ADC to control an external multiplexer, using GPIO0/GPIO1/ GPO2/GPO3 in sync with the internal channel sequencing. The analog input pins used for a channel can still be selected on a per channel basis. Therefore, it is possible to have a 16-channel multiplexer in front of each analog input pair (AIN0/AIN1 to AIN14/AIN15), giving a total of 128 differential channels. However, only 16 channels at a time can be automatically sequenced. Following the sequence of 16 channels, the user changes the analog input to the next pair of input channels, and it sequences through the next 16 channels. There is a delay function that allows extra time for the analog input to settle, in conjunction with any switching an external multiplexer (see the delay bits in the ADC Mode Register). This bit enables the SYNC pin as a sync input. When set low, the SYNC pin holds the ADC and filter in reset until SYNC goes high. An alternative operation of the SYNC pin is available when the ALT_SYNC bit in the interface mode register is set. This mode works only when multiple channels are enabled. In such cases, a low on the SYNC pin does not immediately reset the filter/ modulator. Instead, if the SYNC pin is low when the channel is due to be switched, the modulator and filter are prevented from starting a new conversion. Bringing SYNC high begins the next conversion. This alternative sync mode allows SYNC to be used while cycling through channels. Disabled Enabled These bits enable the ERROR pin as an error input/output. Disabled ERROR is an error input. The (inverted) readback state is OR'ed with other error sources and is available in the ADC_ERROR bit in the status register. The ERROR pin state can also be read from the ERR_DAT bit in this register. ERROR is an open-drain error output. The status register error bits are OR'ed, inverted, and mapped to the ERROR pin. ERROR pins of multiple devices can be wired together to a common pull-up resistor so that an error on any device can be observed. ERROR is a general-purpose output. The status of the pin is controlled by the ERR_DAT bit in this register. This is referenced between IOVDD and DGND, as opposed to the AVDD1 and AVSS levels used by the generalpurpose I/O pins. It has an active pull-up in this case. This bit determines the logic level at the ERROR pin if the pin is enabled as a general-purpose output. It reflects the readback status of the pin if the pin is enabled as an input. This bit is the write data for GPO3. This bit is the write data for GPO2. This bit turns GPIO1 into an input. Input should equal AVDD1 or AVSS. Disabled Enabled Rev. A | Page 54 of 64 Reset 0x0 0x0 Access R RW 0x0 RW 0x0 RW 0x1 RW 0x0 RW 0x0 RW 0x0 0x0 0x0 W W RW Data Sheet Bits 4 Bit Name IP_EN0 AD7173-8 Settings Description This bit turns GPIO0 into an input. Input should equal AVDD1 or AVSS. Disabled Enabled This bit turns GPIO1 into an output. Outputs are referenced between AVDD1 and AVSS. Disabled Enabled This bit turns GPIO0 into an output. Outputs are referenced between AVDD1 and AVSS. Disabled Enabled This bit is the readback or write data for GPIO1. This bit is the readback or write data for GPIO0. 0 1 3 OP_EN1 0 1 2 OP_EN0 0 1 1 0 GP_DATA1 GP_DATA0 Reset 0x0 Access RW 0x0 RW 0x0 RW 0x0 0x0 RW RW Reset 0x30DX1 Access R ID REGISTER Address: 0x07, Reset: 0x30DX, Name: ID The ID register returns a 16-bit ID. For the AD7173-8, this is 0x30DX. Table 30. Bit Descriptions for ID Bits [15:0] Bit Name ID Settings Description The ID register returns a 16-bit ID code that is specific to the ADC. AD7173-8 0x30DX 1 X = don’t care. CHANNEL REGISTER 0 Address: 0x10, Reset: 0x8001, Name: CH0 The channel registers are 16-bit registers that are used to select which channels are currently active, which inputs are selected for each channel, and which setup should be used to configure the ADC for that channel. Table 31. Bit Descriptions for CH0 Bits 15 Bit Name CH_EN0 Settings 0 1 [14:12] SETUP_SEL0 000 001 010 011 100 101 110 111 [11:10] RESERVED Description This bit enables Channel 0. If more than one channel is enabled, the ADC automatically sequences between them. Disabled Enabled (default) These bits identify which of the eight setups are used to configure the ADC for this channel. A setup comprises a set of four registers: the setup configuration register, the filter configuration register, the offset register, and the gain register. All channels can use the same setup, in which case the same 3-bit value is written to these bits on all active channels; alternatively, up to eight channels can be configured differently. Setup 0 Setup 1 Setup 2 Setup 3 Setup 4 Setup 5 Setup 6 Setup 7 These bits are reserved. Set to 0. Rev. A | Page 55 of 64 Reset 0x1 Access RW 0x0 RW 0x0 R AD7173-8 Bits [9:5] Bit Name AINPOS0 Data Sheet Settings 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10101 10110 [4:0] AINNEG0 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10101 10110 Description These bits select which of the analog inputs is connected to the positive input of the ADC for this channel. TEMP SENSOR ± is an internal temperature sensor. AIN0 (default) AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 AIN12 AIN13 AIN14 AIN15 AIN16 TEMP SENSOR + TEMP SENSOR − REF+ REF− These bits select which of the analog inputs is connected to the negative input of the ADC for this channel. AIN0 AIN1(default) AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 AIN12 AIN13 AIN14 AIN15 AIN16 TEMP SENSOR + TEMP SENSOR − REF+ REF− Rev. A | Page 56 of 64 Reset 0x0 Access RW 0x1 RW Data Sheet AD7173-8 CHANNEL REGISTER 1 TO CHANNEL REGISTER 15 Address Range: 0x11 to 0x1F, Reset: 0x0001, Name: CH1 to CH15 Subsequent channel registers, CH1 to CH15, use the same structure as the CH0 register. They are disabled by default (MSB = 0). Each channel created can be referred to one of eight setups. The sequencer progresses through each of the enabled channels in order. Table 32 shows the summary of these registers, their addresses, and their reset values. Table 32. Summary of CH1 to CH15 Reg 0x11 Name CH1 0x12 CH2 0x13 CH3 0x14 CH4 0x15 CH5 0x16 CH6 0x17 CH7 0x18 CH8 0x19 CH9 0x1A CH10 0x1B CH11 0x1C CH12 0x1D CH13 0x1E CH14 0x1F CH15 Bits [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] Bit 7 CH_EN1 CH_EN2 CH_EN3 CH_EN4 CH_EN5 CH_EN6 CH_EN7 CH_EN8 CH_EN9 CH_EN10 CH_EN11 CH_EN12 CH_EN13 CH_EN14 CH_EN15 Bit 6 Bit 5 Bit 4 SETUP_SEL1 AINPOS1[2:0] SETUP_SEL2 AINPOS2[2:0] SETUP_SEL3 AINPOS3[2:0] SETUP_SEL4 AINPOS4[2:0] SETUP_SEL5 AINPOS5[2:0] SETUP_SEL6 AINPOS6[2:0] SETUP_SEL7 AINPOS7[2:0] SETUP_SEL8 AINPOS8[2:0] SETUP_SEL9 AINPOS9[2:0] SETUP_SEL10 AINPOS10[2:0] SETUP_SEL11 AINPOS11[2:0] SETUP_SEL12 AINPOS12[2:0] SETUP_SEL13 AINPOS13[2:0] SETUP_SEL14 AINPOS14[2:0] SETUP_SEL15 AINPOS15[2:0] Bit 3 Rev. A | Page 57 of 64 Bit 2 Bit 1 RESERVED AINNEG1 RESERVED AINNEG2 RESERVED AINNEG3 RESERVED AINNEG4 RESERVED AINNEG5 RESERVED AINNEG6 RESERVED AINNEG7 RESERVED AINNEG8 RESERVED AINNEG9 RESERVED AINNEG10 RESERVED AINNEG11 RESERVED AINNEG12 RESERVED AINNEG13 RESERVED AINNEG14 RESERVED AINNEG15 Bit 0 AINPOS1[4:3] Reset 0x0001 RW RW AINPOS2[4:3] 0x0001 RW AINPOS3[4:3] 0x0001 RW AINPOS4[4:3] 0x0001 RW AINPOS5[4:3] 0x0001 RW AINPOS6[4:3] 0x0001 RW AINPOS7[4:3] 0x0001 RW AINPOS8[4:3] 0x0001 RW AINPOS9[4:3] 0x0001 RW AINPOS10[4:3] 0x0001 RW AINPOS11[4:3] 0x0001 RW AINPOS12[4:3] 0x0001 RW AINPOS13[4:3] 0x0001 RW AINPOS14[4:3] 0x0001 RW AINPOS15[4:3] 0x0001 RW AD7173-8 Data Sheet SETUP CONFIGURATION REGISTER 0 Address: 0x20, Reset: 0x1000, Name: SETUPCON0 The setup configuration registers are 16-bit registers that configure the reference selection, input buffers, burnout currents, and output coding of the ADC. Table 33. Bit Descriptions for SETUPCON0 Bits [15:13] 12 Bit Name RESERVED BI_UNIPOLAR0 Settings 0 1 [11:10] REF_BUF_0[1:0] 00 11 [9:8] AIN_BUF_0[1:0] 00 11 7 BURNOUT_EN0 6 BUFCHOPMAX0 [5:4] REF_SEL0 00 01 10 11 [3:0] RESERVED Description These bits are reserved. Set to 0. This bit sets the output coding of the ADC for Setup 0. Unipolar coded output Offset binary coded output Reference input buffer enable. These bits turn on the buffers of the positive and negative reference inputs. This offers a high impedance input for an external reference source and isolates it from the switch capacitor reference sampling input of the ADC. Use both reference buffers together. Reference input buffers disabled Reference input buffers enabled Analog input buffer enable. These bits turn on the buffers of the positive and negative analog inputs. This offers a high impedance input to the device and isolates the sensor/signal for measurement from the switch capacitor sampling input of the ADC. Use both analog input buffers together. Analog input buffers disabled Analog input buffers enabled This bit enables a 10 μA current source on the positive analog input selected and a 10 μA current sink on the negative analog input selected. The burnout currents are useful in diagnosis of an open wire, whereby the ADC result goes to full scale. Enabling the BURNOUT currents during measurement results in an offset voltage on the ADC reading of approximately 1 μV. This means the strategy for diagnosing an open wire operates best by turning on the BURNOUT currents at intervals, before or after precision measurements. This bit enables the maximum buffer chop frequency, increasing AIN input current and reducing buffer noise. These bits allow selection of the reference source for ADC conversion on Setup 0. External reference supplied to REF+ and REF− pins External Reference 2 supplied to AIN1/REF2+ and AIN0/REF2− pins Internal 2.5 V reference; this reference must also be enabled in the ADC mode register AVDD1 – AVSS; this setting can be used to as a diagnostic to validate other reference values These bits are reserved. Set to 0. Rev. A | Page 58 of 64 Reset 0x0 0x1 Access R RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 R Data Sheet AD7173-8 SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 7 Address: 0x21 to 0x27, Reset: 0x1000, Name: SETUPCON1 to SETUPCON7 The remaining seven setup configuration registers share the same 16-bit register layout as SETUPCON0. They configure the reference selection, input buffers, burnout currents, and output coding of the ADC. Table 34. Summary of SETUPCON1 to SETUPCON7 Reg 0x21 Name SETUPCON1 0x22 SETUPCON2 0x23 0x24 0x25 0x26 0x27 SETUPCON3 SETUPCON4 SETUPCON5 SETUPCON6 SETUPCON7 Bits [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] Bit 7 BURNOUT_EN1 BURNOUT_EN2 BURNOUT_EN3 BURNOUT_EN4 BURNOUT_EN5 BURNOUT_EN6 BURNOUT_EN7 Bit 6 RESERVED BUFCHOPMAX1 RESERVED BUFCHOPMAX2 RESERVED BUFCHOPMAX3 RESERVED BUFCHOPMAX4 RESERVED BUFCHOPMAX5 RESERVED BUFCHOPMAX6 RESERVED BUFCHOPMAX7 Bit 5 Bit 4 BI_UNIPOLAR1 REFSEL1 BI_UNIPOLAR2 REFSEL2 BI_UNIPOLAR3 REFSEL3 BI_UNIPOLAR4 REFSEL4 BI_UNIPOLAR5 REFSEL5 BI_UNIPOLAR6 REFSEL6 BI_UNIPOLAR7 REFSEL7 Rev. A | Page 59 of 64 Bit 3 Bit 2 Bit 1 Bit 0 REF_BUF 1[1:0] AIN_BUF 1[1:0] RESERVED REF_BUF 2[1:0] AIN_BUF 2[1:0] RESERVED REF_BUF 3[1:0] AIN_BUF 3[1:0] RESERVED REF_BUF 4[1:0] AIN_BUF 4[1:0] RESERVED REF_BUF 5[1:0] AIN_BUF 5[1:0] RESERVED REF_BUF 6[1:0] AIN_BUF 6[1:0] RESERVED REF_BUF 7[1:0] AIN_BUF 7[1:0] RESERVED Reset 0x1000 RW RW 0x1000 RW 0x1000 RW 0x1000 RW 0x1000 RW 0x1000 RW 0x1000 RW AD7173-8 Data Sheet FILTER CONFIGURATION REGISTER 0 Address: 0x28, Reset: 0x0000, Name: FILTCON0 The filter configuration registers are 16-bit registers that configure the ADC data rate and filter options. Writing to any of these registers resets any active ADC conversion and restarts converting at the first channel in the sequence. Table 35. Bit Descriptions for FILTCON0 Bits 15 Bit Name SINC3_MAP0 [14:12] 11 RESERVED ENHFILTEN0 Settings 0 1 [10:8] ENHFILT0 010 011 101 110 7 [6:5] RESERVED ORDER0 00 11 [4:0] ODR0 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 Description If this bit is set, the mapping of the filter configuration register changes to directly program the decimation rate of the sinc3 filter for Setup 0. All other options are eliminated. This allows fine tuning of the output data rate and filter notch for rejection of specific frequencies. The data rate when on a single channel, with single cycle settling disabled, equals FMOD/(32 × FILTCON0[14:0]). These bits are reserved. Set to 0. This bit enables various post filters for enhanced 50 Hz/60 Hz rejection for Setup 0. For this setting to function, the ORDERx bits must also be set to 00 to select the sinc5 + sinc1 filter. Disabled Enabled These bits select between various post filters for enhanced 50 Hz/60 Hz rejection for Setup 0. 27.27 SPS, 47 dB rejection, 36.67 ms settling 25 SPS, 62 dB rejection, 40 ms settling 20 SPS, 86 dB rejection, 50 ms settling 16.67 SPS, 92 dB rejection, 60 ms settling This bit is reserved. Set to 0. These bits control the order of the digital filter that processes the modulator data for Setup 0. Sinc5 + sinc1 (default) Sinc3. When using the sinc3 filter, the user must select the sinc3 filter and use the same output data rate for all enabled channels. These bits control the output data rate of the ADC and, therefore, the settling time and noise for Setup 0. 31,250 SPS 31,250 SPS 31,250 SPS 31,250 SPS 31,250 SPS 31,250 SPS 15,625 SPS 10,417 SPS 5208 SPS 2597 SPS (2604 SPS for sinc3) 1007 SPS (1008 SPS for sinc3) 503.8 SPS (504 SPS for sinc3) 381 SPS (400.6 SPS for sinc3) 200.3 SPS 100.5 SPS 59.52 SPS (59.98 SPS for sinc3) 49.68 SPS (50 SPS for sinc3) 20.01 SPS 16.63 SPS (16.67 SPS for sinc3) 10 SPS 5 SPS 2.5 SPS 1.25 SPS Rev. A | Page 60 of 64 Reset 0x0 Access RW 0x0 0x0 R RW 0x0 RW 0x0 0x0 R RW 0x0 RW Data Sheet AD7173-8 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 7 Address Range: 0x29 to 0x2F, Reset: 0x0000, Name: FILTCON1 to FILTCON7 The remaining seven filter configuration registers share the same 16-bit register layout as FILTCON0. They configure the ADC data rate and filter options and map as per their number. Writing to any of these registers resets any active ADC conversion and restarts converting at the first channel in the sequence. Table 36. Summary of FILTCON1 to FILTCON7 Reg 0x29 Name FILTCON1 0x2A FILTCON2 0x2B 0x2C 0x2D 0x2E 0x2F FILTCON3 FILTCON4 FILTCON5 FILTCON6 FILTCON7 Bits [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] Bit 7 SINC3_MAP1 RESERVED SINC3_MAP2 RESERVED SINC3_MAP3 RESERVED SINC3_MAP4 RESERVED SINC3_MAP5 RESERVED SINC3_MAP6 RESERVED SINC3_MAP7 RESERVED Bit 6 Bit 5 RESERVED ORDER1 RESERVED ORDER2 RESERVED ORDER3 RESERVED ORDER4 RESERVED ORDER5 RESERVED ORDER6 RESERVED ORDER7 Bit 4 Bit 3 ENHFILTEN1 Bit 2 Bit 1 Bit 0 ENHFILT1 Reset 0x0000 RW RW ENHFILT2 0x0000 RW ENHFILT3 0x0000 RW ENHFILT4 0x0000 RW ENHFILT5 0x0000 RW ENHFILT6 0x0000 RW ENHFILT7 0x0000 RW ODR1 ENHFILTEN2 ODR2 ENHFILTEN3 ODR3 ENHFILTEN4 ODR4 ENHFILTEN5 ODR5 ENHFILTEN6 ODR6 ENHFILTEN7 Rev. A | Page 61 of 64 ODR7 AD7173-8 Data Sheet OFFSET REGISTER 0 Address: 0x30, Reset: 0x800000, Name: OFFSET0 The offset (zero-scale) registers are 24-bit registers that can be used to compensate for any offset error in the ADC or in the system. Table 37. Bit Descriptions for OFFSET0 Bits [23:0] Bit Name OFFSET0 Settings Description Offset calibration coefficient for Setup 0. Reset 0x800000 Access RW OFFSET REGISTER 1 TO OFFSET REGISTER 7 Address Range: 0x31to 0x37, Reset: 0x800000, Name: OFFSET1 to OFFSET7 The offset (zero-scale) registers, OFFSET1 to OFFSET7, share the same structure (24-bit) as OFFSET0. They can be used individually to compensate for any offset error in the ADC or in the system. Table 38. Summary of OFFSET1 to OFFSET7 Reg 0x31 0x32 0x33 0x34 0x35 0x36 0x37 Name OFFSET1 OFFSET2 OFFSET3 OFFSET4 OFFSET5 OFFSET6 OFFSET7 Bits [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] Bit[23:0] OFFSET1[23:0] OFFSET2[23:0] OFFSET3[23:0] OFFSET4[23:0] OFFSET5[23:0] OFFSET6[23:0] OFFSET7[23:0] Reset 0x800000 0x800000 0x800000 0x800000 0x800000 0x800000 0x800000 RW RW RW RW RW RW RW RW GAIN REGISTER 0 Address: 0x38, Reset: 0x5XXXX0, Name: GAIN0 The gain (full-scale) registers are 24-bit registers that can be used to compensate for any gain error in the ADC or in the system. Table 39. Bit Descriptions for GAIN0 Bits [23:0] 1 Bit Name GAIN0 Settings Description Gain calibration coefficient for Setup 0. Reset1 0x5XXXX0 Access RW The value of X varies, depending on the IC that is used. GAIN REGISTER 1 TO GAIN REGISTER 7 Address Range: 0x39 to 0x3F, Reset: 0x5XXXX0, Name: GAIN1 to GAIN7 The gain (full-scale) registers for GAIN1 to GAIN7 share the same 24-bit structure as that shown by GAIN0 register. They can be used to compensate for any gain error in the ADC or in the system and are assigned as per their number to a given setup. Table 40. Summary of GAIN1 to GAIN7 Reg 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 1 Name GAIN1 GAIN2 GAIN3 GAIN4 GAIN5 GAIN6 GAIN7 Bits [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] Bit[23:0] GAIN1[23:0] GAIN2[23:0] GAIN3[[23:0] GAIN4[23:0] GAIN5[23:0] GAIN6[23:0] GAIN7[23:0] The value of X varies, depending on the IC that is used. Rev. A | Page 62 of 64 Reset1 0x5XXXX0 0x5XXXX0 0x5XXXX0 0x5XXXX0 0x5XXXX0 0x5XXXX0 0x5XXXX0 RW RW RW RW RW RW RW RW Data Sheet AD7173-8 OUTLINE DIMENSIONS 0.30 0.25 0.18 31 40 30 0.50 BSC 1 0.80 0.75 0.70 0.45 0.40 0.35 10 11 20 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 4.05 3.90 SQ 3.75 EXPOSED PAD 21 TOP VIEW PIN 1 INDICATOR BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WJJD. 05-06-2011-A PIN 1 INDICATOR 6.10 6.00 SQ 5.90 Figure 75. 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 6 mm × 6 mm Body, Very Very Thin Quad (CP-40-14) Dimensions shown in millimeters ORDERING GUIDE Models1 AD7173-8BCPZ AD7173-8BCPZ-RL EVAL-AD7173-8SDZ EVAL-SDP-CB1Z 1 Temperature Range −40°C to +105°C −40°C to +105°C Package Description 40-Lead LFCSP_WQ 40-Lead LFCSP_WQ Evaluation Board Evaluation Controller Board Z = RoHS Compliant Part. Rev. A | Page 63 of 64 Package Option CP-40-14 CP-40-14 AD7173-8 Data Sheet NOTES ©2013–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11773-0-4/14(A) Rev. A | Page 64 of 64