AD7691-EP data sheet

18-Bit, 250 kSPS PulSAR
Differential ADC in MSOP
AD7691-EP
Enhanced Product
FEATURES
APPLICATION DIAGRAM
ENHANCED PRODUCT FEATURES
Supports defense and aerospace applications (AQEC standard)
Military temperature range: −55°C to +105°C
Controlled manufacturing baseline
One assembly/test site
One fabrication site
Enhanced product change notification
Qualification data available on request
APPLICATIONS
Battery-powered equipment
Data acquisitions
Seismic data acquisition systems
Instrumentation
Medical instruments
+0.5V TO VDD
+2.5V TO +5V
IN+
REF VDD VIO
SDI
IN–
SDO
+1.8V TO VDD
3- OR 4-WIRE
INTERFACE
(SPI, DAISY CHAIN, CS)
SCK
±10V, ±5V, ...
GND
CNV
12156-001
ADA4941
AD7691-EP
Figure 1.
GENERAL DESCRIPTION
The AD7691-EP is an 18-bit, charge redistribution, successive
approximation, analog-to-digital converter (ADC) that operates
from a single power supply, VDD, between 2.3 V and 5 V. It
contains a low power, high speed, 18-bit sampling ADC with
no missing codes, an internal conversion clock, and a versatile
serial interface port. On the CNV rising edge, it samples the
voltage difference between the IN+ and IN− pins. The voltages
on these pins swing in opposite phases between 0 V and REF.
The reference voltage, REF, is applied externally and can be set
up to the supply voltage.
The power of the AD7691-EP scales linearly with throughput.
The SPI-compatible serial interface also features the ability, using
the SDI input, to daisy-chain several ADCs on a single 3-wire
bus and provides an optional busy indicator. It is compatible with
1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate VIO supply.
The AD7691-EP is housed in a 10-lead MSOP with operation
specified from −55°C to +105°C. Additional application and
technical information can be found in the AD7691 data sheet.
1.5
POSITIVE INL = 0.43LSB
NEGATIVE INL = –0.62LSB
1.0
0.5
INL (LSB)
18-bit resolution with no missing codes
Throughput: 250 kSPS
INL
±0.75 LSB typical
±1.5 LSB minimum/maximum at −40°C to +85°C
−2.7 LSB/+2 LSB minimum/maximum at −55°C to +105°C
Dynamic range: 102 dB typical
Oversampled dynamic range: 125 dB at 1 kSPS
Noise-free code resolution: 20 bits at 1 kSPS
Effective resolution: 22.7 bits at 1 kSPS
SINAD: 101 dB typical at fIN = 1 kHz, VREF = 5 V
THD: −125 dB typical at fIN = 1 kHz, VREF = 5 V
True differential analog input range: ±VREF
0 V to VREF with VREF up to VDD on both inputs
No pipeline delay
Single-supply 2.3 V to 5 V operation with 1.8 V/2.5 V/3 V/5 V
logic interface
Serial interface SPI-/QSPI™-/MICROWIRE™-/DSP-compatible
Ability to daisy-chain multiple ADCs
Optional busy indicator feature
Power dissipation
1.35 mW at VDD = 2.5 V, 100 kSPS throughput
4.24 mW at VDD = 5 V, 100 kSPS throughput
1.4 μW at VDD = 2.5 V, 100 SPS throughput
Standby current: 1 nA
10-lead MSOP
Pin-for-pin compatible with the18-bit AD7690 and 16-bit
AD7693, AD7688, and AD7687
0
–0.5
–1.5
0
65536
131072
196608
CODE
262144
12156-025
–1.0
Figure 2. Integral Nonlinearity vs. Code, 5 V
Rev. A
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Technical Support
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AD7691-EP
Enhanced Product
TABLE OF CONTENTS
Features .....................................................................................1
Absolute Maximum Ratings ...................................................... 7
Applications...............................................................................1
Thermal Resistance................................................................ 7
General Description ..................................................................1
ESD Caution.......................................................................... 7
Application Diagram .................................................................1
Pin Configurations and Function Descriptions......................... 8
Revision History ........................................................................2
Typical Performance Characteristics ......................................... 9
Specifications.............................................................................3
Outline Dimensions ................................................................ 13
Timing Specifications ............................................................5
Ordering Guide ................................................................... 13
REVISION HISTORY
8/15—Rev. 0 to Rev. A
Added Enhanced Product Features Section...............................1
9/14—Revision 0: Initial Version
Rev. A | Page 2 of 13
Enhanced Product
AD7691-EP
SPECIFICATIONS
VDD = 2.3 V to 5.25 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ANALOG INPUT
Voltage Range, VIN
Absolute Input Voltage Range
Common-Mode Input Range
Analog Input Common-Mode Rejection Ratio (CMRR)
Leakage Current at 25°C
Input Impedance 1
THROUGHPUT
Conversion Rate
Transient Response
ACCURACY
No Missing Codes
Integral Linearity Error
Differential Linearity Error
Transition Noise
Gain Error 3
Gain Error Temperature Drift
Zero Error3
Zero Temperature Drift
Power Supply Sensitivity
AC ACCURACY 4
Dynamic Range
Oversampled Dynamic Range 5
Signal-to-Noise
fIN = 1 kHz, VREF = 5 V
fIN = 1 kHz, VREF = 2.5 V
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-to-Noise-and-Distortion Ratio (SINAD)
fIN = 1 kHz, VREF = 5 V
fIN = 1 kHz, VREF = 2.5 V
Test Conditions/Comments
Min
18
IN+ − (IN−)
IN+, IN−
IN+, IN−
fIN = 250 kHz
Acquisition phase
−VREF
−0.1
VREF/2 − 0.1
VDD = 4.5 V to 5.25 V
VDD = 2.3 V to 4.5 V
Full-scale step
0
0
−55°C to +105°C
−40°C to +85°C
18
−2.7
−1.5
−1
REF = VDD = 5 V
VDD = 4.5 V to 5.25 V
VDD = 2.3 V to 4.5 V
−40
−80
VDD = 4.5 V to 5.25 V
VDD = 2.3 V to 4.5 V
−0.8
−3.5
VDD = 5 V ± 5%
Typ
VREF/2
65
1
±0.75
±0.75
±0.5
0.75
±2
±2
±0.3
±0.1
±0.7
±0.3
±0.25
Max
Unit
Bits
+VREF
VREF + 0.1
VREF/2 + 0.1
V
V
V
dB
nA
250
180
1.8
kSPS
kSPS
µs
+2
+1.5
+1.25
+40
+80
+0.8
+3.5
Bits
LSB 2
LSB2
LSB2
LSB2
LSB2
LSB2
ppm/°C
mV
mV
ppm/°C
LSB2
VREF = 5 V
fIN = 1 kSPS
101
102
125
dB
dB
−55°C to +105°C
−40°C to +85°C
−55°C to +105°C
−40°C to +85°C
fIN = 1 kHz, VREF = 5 V
fIN = 1 kHz, VREF = 5 V
98.5
100
94
95
101
101.5
96
96.5
−125
−118
dB
dB
dB
dB
dB
dB
−55°C to +105°C
−40°C to +85°C
−55°C to +105°C
−40°C to +85°C
98.5
100
94
95
101
101.5
96
96.5
115
dB
dB
dB
dB
dB
Intermodulation Distortion 6
See the Analog Inputs section of the AD7691 data sheet.
LSB means least significant bit. With the ±5 V input range, one LSB is 38.15 µV.
3 See the Terminology section of the AD7691 data sheet. These specifications include full temperature range variation but not the error contribution from the external
reference.
4 All ac accuracy specifications in dB are referred to a full-scale input FSR. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
5 Dynamic range obtained by oversampling the ADC running at a throughput f of 250 kSPS, followed by postdigital filtering with an output word rate f .
S
O
6
fIN1 = 21.4 kHz and fIN2 = 18.9 kHz, with each tone at −7 dB below full scale.
1
2
Rev. A | Page 3 of 13
AD7691-EP
Enhanced Product
VDD = 2.3 V to 5.25 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
REFERENCE
Voltage Range
Load Current
SAMPLING DYNAMICS
−3 dB Input Bandwidth
Aperture Delay
DIGITAL INPUTS
Logic Levels
VIL
VIH
IIL
IIH
DIGITAL OUTPUTS
Data Format
Pipeline Delay 1
VOL
VOH
POWER SUPPLIES
VDD Range
VIO Range
VIO Range
Standby Current 2, 3
Power Dissipation
Energy per Conversion
TEMPERATURE RANGE 4
Specified Performance
Test Conditions/Comments
Min
Typ
0.5
Max
Unit
VDD + 0.3
250 kSPS, REF = 5 V
60
V
µA
VDD = 5 V
2
2.5
MHz
ns
−0.3
0.7 × VIO
−1
−1
+0.3 × VIO
VIO + 0.3
+1
+1
V
V
µA
µA
0.4
V
V
5.25
VDD + 0.3
VDD + 0.3
50
V
V
V
nA
µW
mW
mW
mW
mW
nJ/sample
Serial 18-bit, twos complement
ISINK = +500 µA
ISOURCE = −500 µA
VIO − 0.3
Specified performance
Specified performance
Functional operation
VDD and VIO = 5 V, TA = 25°C
VDD = 2.5 V, 100 SPS throughput
VDD = 2.5 V, 100 kSPS throughput
VDD = 2.5 V, 180 kSPS throughput
VDD = 5 V, 100 kSPS throughput
VDD = 5 V, 250 kSPS throughput
2.3
2.3
1.8
TMIN to TMAX
−55
1
1.4
1.35
2.4
4.24
10.6
50
Conversion results are available immediately after completed conversion.
With all digital inputs forced to VIO or GND as required.
During acquisition phase.
4 Contact an Analog Devices, Inc., sales representative for the extended temperature range.
1
2
3
Rev. A | Page 4 of 13
5
12.5
+105
°C
Enhanced Product
AD7691-EP
TIMING SPECIFICATIONS
VDD = 4.5 V to 5.25 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted. See Figure 3 and Figure 4
for load conditions.
Table 3.
Parameter
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
CNV Pulse Width (CS Mode)
SCK Period (CS Mode)
SCK Period (Chain Mode)
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI Low to SDO D17 MSB Valid (CS Mode)
VIO Above 4.5 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with Busy Indicator)
VIO Above 4.5 V
VIO Above 2.3 V
Rev. A | Page 5 of 13
Symbol
tCONV
tACQ
tCYC
tCNVH
tSCK
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
Min
0.5
1.8
4
10
15
Typ
Max
2.2
17
18
19
20
7
7
4
Unit
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
14
15
16
17
ns
ns
ns
ns
15
18
23
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
26
ns
ns
tEN
tDIS
tSSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
15
0
5
10
3
4
AD7691-EP
Enhanced Product
VDD = 2.3 V to 4.5 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted. See Figure 3 and Figure 4
for load conditions.
Table 4.
Parameter
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
CNV Pulse Width (CS Mode)
SCK Period (CS Mode)
SCK Period (Chain Mode)
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI Low to SDO D17 MSB Valid (CS Mode)
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with Busy Indicator)
Symbol
tCONV
tACQ
tCYC
tCNVH
tSCK
tSCK
Min
0.5
1.8
5.5
10
25
tSCKL
tSCKH
tHSDO
tDSDO
Unit
μs
μs
μs
ns
ns
ns
ns
ns
ns
ns
ns
24
30
35
ns
ns
ns
18
22
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
tEN
tDIS
tSSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
30
0
5
8
8
10
36
IOL
1.4V
TO SDO
12156-002
CL
50pF
500µA
Max
3.7
29
35
40
12
12
5
Timing Diagrams
500µA
Typ
IOH
Figure 3. Load Circuit for Digital Interface Timing
70% VIO
30% VIO
tDELAY
2V OR VIO – 0.5V1
2V OR VIO – 0.5V1
0.8V OR 0.5V2
0.8V OR 0.5V2
12V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.
20.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
Figure 4. Voltage Levels for Timing
Rev. A | Page 6 of 13
12156-003
tDELAY
Enhanced Product
AD7691-EP
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 5.
Parameter
Analog Inputs (IN+, IN−)1
REF
Supply Voltages
VDD, VIO to GND
VDD to VIO
Digital Inputs to GND
Digital Outputs to GND
Storage Temperature Range
Junction Temperature
Lead Temperature Range
1
Rating
GND − 0.3 V to VDD + 0.3 V
or ±130 mA
GND − 0.3 V to VDD + 0.3 V
−0.3 V to +7 V
±7 V
−0.3 V to VIO + 0.3 V
−0.3 V to VIO + 0.3 V
−65°C to +150°C
150°C
JEDEC J-STD-20
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 6. Thermal Resistance
Package Type
10-Lead MSOP
ESD CAUTION
See the Analog Inputs section of the AD7691 data sheet.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. A | Page 7 of 13
θJA
200
θ JC
44
Unit
°C/W
AD7691-EP
Enhanced Product
REF 1
10
VIO
VDD 2
AD7691-EP
9
SDI
IN+ 3
TOP VIEW
(Not to Scale)
8
SCK
7
SDO
6
CNV
IN– 4
GND 5
12156-004
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 5. 10-Lead MSOP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
1
Mnemonic
REF
Type 1
AI
2
3
VDD
IN+
P
AI
4
IN−
AI
5
6
GND
CNV
P
DI
7
8
9
SDO
SCK
SDI
DO
DI
DI
10
VIO
P
Description
Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. Decouple this
pin closely with a 10 µF capacitor.
Power Supply.
Differential Positive Analog Input. Referenced to IN−. The input range for IN+ is between 0 V and VREF,
centered about VREF/2 and must be driven 180° out of phase with IN−.
Differential Negative Analog Input. Referenced to IN+. The input range for IN− is between 0 V and VREF,
centered about VREF/2 and must be driven 180° out of phase with IN+.
Power Supply Ground.
Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and
selects the interface mode of the device, either chain mode or CS mode. In CS mode, it enables the SDO
pin when low. In chain mode, the data should be read when CNV is high.
Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
Serial Data Clock Input. When the device is selected, the conversion result is shifted out by this clock.
Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows:
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to
daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on
SDI is output on SDO with a delay of 18 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable
the serial output signals when low, and if SDI or CNV is low when the conversion is complete, the busy
indicator feature is enabled.
Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V,
or 5 V).
AI = analog input, DI = digital input, DO = digital output, and P = power.
1
Rev. A | Page 8 of 13
Enhanced Product
AD7691-EP
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
1.5
POSITIVE DNL = 0.37LSB
NEGATIVE DNL = –0.33LSB
POSITIVE INL = 0.39LSB
NEGATIVE INL = –0.73LSB
1.0
0.5
DNL (LSB)
INL (LSB)
0.5
0
0
–0.5
–0.5
–1.0
131072
196608
262144
–1.0
CODE
65536
0
131072
Figure 9. Differential Nonlinearity (DNL) vs. Code, 5 V
80k
45k
VDD = REF = 5V
σ = 0.76LSB
69769
70k
40k
VDD = REF = 2.5V
σ = 1.42LSB
38068
35k
60k
30k
28179
COUNTS
50k
40k
28527
30k
24411
25k
20k
17460
27770
14362
15k
20k
10k
5k
0
0
26
25
26
27
28
2062
29
2A
2C
2B
14
0
0
2D
2E
2F
CODE IN HEX
0
12156-027
0
2904
4055
2997
0
12
910 78
29 501
9
0
23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31
CODE IN HEX
Figure 7. Histogram of a DC Input at the Code Center, 5 V
12156-030
10k
Figure 10. Histogram of a DC Input at the Code Center, 2.5 V
0
0
32768 POINT FFT
VDD = REF = 5V
fS = 250kSPS
fIN = 2kHz
SNR = 101.4dB
THD = –120.1dB
2ND HARMONIC = –140.7dB
3RD HARMONIC = –120.3dB
–40
–60
32768 POINT FFT
VDD = REF = 2.5V
fS = 180kSPS
fIN = 2kHz
SNR = 96.4dB
THD = –120.3dB
2ND HARMONIC = –132.5dB
3RD HARMONIC = –121.2dB
–20
AMPLITUDE (dB of Full Scale)
–20
–80
–100
–120
–140
–160
–40
–60
–80
–100
–120
–140
0
20
40
60
80
FREQUENCY (kHz)
100
120
12156-028
–160
–180
Figure 8. 2 kHz FFT Plot, 5 V
–180
0
10
20
30
40
50
60
FREQUENCY (kHz)
Figure 11. 2 kHz FFT Plot, 2.5 V
Rev. A | Page 9 of 13
70
80
90
12156-031
COUNTS
262144
CODE
Figure 6. Integral Nonlinearity (INL) vs. Code 2.5 V
AMPLITUDE (dB of Full Scale)
196608
12156-029
65536
0
12156-026
–1.5
AD7691-EP
Enhanced Product
104
–105
18
SNR
102
–110
100
17
94
THD, SFDR (dB)
16
ENOB (Bits)
ENOB
96
92
–115
THD
–120
–125
15
90
–130
88
2.9
3.2
3.5
3.8
4.4
4.1
5.0
4.7
14
5.3
–135
2.3
12156-032
2.6
REFERENCE VOLTAGE (V)
2.6
2.9
3.2
3.5
3.8
4.7
4.4
4.1
5.0
5.3
105
125
REFERENCE VOLTAGE (V)
Figure 12. SNR, SINAD, and ENOB vs. Reference Voltage
12156-038
SFDR
86
2.3
Figure 15. THD, SFDR vs. Reference Voltage
105
–90
VREF = 5V
100
–100
95
THD (dB)
SNR (dB)
VREF = 2.5V
90
–110
VREF = 5V
–120
85
–15
5
25
65
45
85
105
125
TEMPERATURE (°C)
–130
–55
12156-033
–35
–35
–15
5
25
45
65
85
TEMPERATURE (°C)
Figure 13. SNR vs. Temperature
12156-039
VREF = 2.5V
80
–55
Figure 16. THD vs. Temperature
–60
105
VREF = 5V, –10dB
VREF = 5V, –1dB
100
–70
95
–80
VREF = 5V, –1dB
VREF = 2.5V, –1dB
VREF = 2.5V, –10dB
85
–90
–100
80
–110
75
–120
70
0
25
50
75
FREQUENCY (kHz)
100
125
Figure 14. SINAD vs. Frequency
VREF = 2.5V, –10dB
VREF = 5V, –10dB
–130
0
25
50
75
FREQUENCY (kHz)
Figure 17. THD vs. Frequency
Rev. A | Page 10 of 13
100
125
12156-040
THD (dB)
VREF = 2.5V, –1dB
90
12156-037
SINAD (dB)
SNR, SINAD (dB)
SINAD
98
Enhanced Product
AD7691-EP
105
–90
SNR 5V
102
GAIN ERROR
SNR 2.5V
ZERO ERROR, GAIN ERROR (LSB)
–95
99
–100
96
–105
93
–110
THD 5V
90
–115
87
–120
THD 2.5V
84
THD (dB)
SNR (dB)
6
4
2
0
–2
–4
–125
–6
–2
–4
12156-041
–8
–6
–55
0
INPUT LEVEL (dB)
–15
25
45
65
85
105
125
Figure 21. Zero Error, Gain Error vs. Temperature
1000
1000
fS = 100kSPS
POWER-DOWN CURRENT (nA)
VDD = 5V
750
VDD = 2.5V
500
250
750
500
250
65
25
45
5
TEMPERATURE (°C)
85
105
125
Figure 19. Operating Current vs. Temperature
–35
–15
5
25
45
65
TEMPERATURE (°C)
85
105
125
12156-047
–15
12156-042
–35
0
–55
120
12156-034
VDD + VIO
VIO
0
–55
Figure 22. Power-Down Current vs. Temperature
1000
25
fS = 100kSPS
20
VDD
tDSDO DELAY (ns)
750
500
15
VDD = 5V, 85°C
10
VDD = 5V, 25°C
250
5
VIO
0
2.3
2.6
2.9
3.2
3.5
3.8
4.1
SUPPLY (V)
4.4
4.7
5.0
5.3
12156-043
OPERATING CURRENT (µA)
5
TEMPERATURE (°C)
Figure 18. SNR, THD vs. Input Level
OPERATING CURRENT (µA)
–35
12156-044
ZERO ERROR
–130
81
–10
Figure 20. Operating Current vs. Supply
0
0
20
40
60
80
SDO CAPACITIVE LOAD (pF)
100
Figure 23. tDSDO Delay vs. SDO Capacitance Load and Supply
Rev. A | Page 11 of 13
AD7691-EP
Enhanced Product
90
95
VREF = VDD = 5V
85
90
80
75
CMRR (dB)
80
75
70
65
60
55
50
70
1
10
100
1000
FREQUENCY (kHz)
10000
Figure 24. PSSR vs. Frequency
40
1
10
100
1000
FREQUENCY (kHz)
Figure 25. Analog Input CMRR vs. Frequency
Rev. A | Page 12 of 13
10000
12156-036
45
65
12156-035
PSRR (dB)
85
Enhanced Product
AD7691-EP
OUTLINE DIMENSIONS
3.10
3.00
2.90
10
3.10
3.00
2.90
5.15
4.90
4.65
6
1
5
PIN 1
IDENTIFIER
0.50 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.30
0.15
6°
0°
0.23
0.13
0.70
0.55
0.40
COMPLIANT TO JEDEC STANDARDS MO-187-BA
091709-A
0.15
0.05
COPLANARITY
0.10
Figure 26. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD7691SRMZ-EP-RL7
EVAL-AD7691SDZ
EVAL-SDP-CB1Z
1
Temperature Range
–55°C to +105°C
Package Description
10-Lead MSOP, Reel
Evaluation Board
Controller Board
Z = RoHS Compliant Part.
©2014–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12156-0-8/15(A)
Rev. A | Page 13 of 13
Package Option
RM-10
Branding
C82
Ordering Quantity
1,000
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