Dual Differential 16-Bit, 1 MSPS PulSAR ADC 12.0 mW in QSOP AD7903 Data Sheet FEATURES GENERAL DESCRIPTION 16-bit resolution with no missing codes Throughput: 1 MSPS Low power dissipation 7.0 mW at 1 MSPS (VDD1 and VDD2 only) 12.0 mW at 1 MSPS (total) 140 µW at 10 kSPS INL: ±0.5 LSB typical, ±2.0 LSB maximum SINAD: 93.5 dB at 1 kHz THD: −112 dB at 1 kHz True differential analog input range: ±VREF 0 V to VREF with VREF between 2.4 V to 5.1 V Allows use of any input range Easy to drive with the ADA4941-1 No pipeline delay Single-supply 2.5 V operation with 1.8 V/2.5 V/3 V/5 V logic interface Serial port interface (SPI)/QSPI/MICROWIRE/DSP compatible 20-lead QSOP package Wide operating temperature range: −40°C to +125°C The AD7903 is a dual 16-bit, successive approximation, analogto-digital converter (ADC) that operates from a single power supply, VDDx, per ADC. It contains two low power, high speed, 16-bit sampling ADCs and a versatile serial port interface (SPI). On the CNVx rising edge, the AD7903 samples the voltage difference between the INx+ and INx− pins. The voltages on these pins usually swing in opposite phases between 0 V and VREF. The externally applied reference voltage of the REFx pins (VREF) can be set independently from the supply voltage pins, VDDx. The power of the device scales linearly with throughput. Using the SDIx inputs, the SPI-compatible serial interface can also daisy-chain multiple ADCs on a single 3-wire bus and provide an optional busy indicator. It is compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate VIOx supplies. The AD7903 is available in a 20-lead QSOP package with operation specified from −40°C to +125°C. Table 1. MSOP 14-/16-/18-Bit PulSAR® ADCs Bits 18 APPLICATIONS Battery-powered equipment Communications Automated test equipment (ATE) Data acquisition Medical instrumentation Redundant measurement Simultaneous sampling 16 14 1 100 kSPS 250 kSPS AD76911 400 kSPS to 500 kSPS AD76901 1000 kSPS AD79821 AD7680 AD7683 AD7684 AD7940 AD76851 AD76871 AD7694 AD79421 AD76861 AD76881 AD76931 AD79461 AD79801 AD7903 AD7902 ADC Driver ADA4941-1 ADA4841-x ADA4941-1 ADA4841-x Pin-for-pin compatible. FUNCTIONAL BLOCK DIAGRAM REF = 2.5V TO 5V 2.5V REF IN1+ ADC1 ±10V, ±5V, ... IN1– ADA4941-1 REF IN2– GND VIO1 VIO1/VIO2 SDI1 SDI1/SDI2 SCK1 SCK1/SCK2 CNV1 CNV1/CNV2 SDO1 SDO1 VIO2 IN2+ 3-WIRE OR 4-WIRE INTERFACE (SPI, CS, AND CHAIN MODES) SDI2 ADC2 ±10V, ±5V, ... VDD1 VDD2 SCK2 CNV2 SDO2 SDO2 AD7903 11755-001 REF1 REF2 ADA4941-1 Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013–2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD7903 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Analog Inputs.............................................................................. 15 Applications ....................................................................................... 1 Driver Amplifier Choice ........................................................... 16 General Description ......................................................................... 1 Single-to-Differential Driver .................................................... 16 Functional Block Diagram .............................................................. 1 Voltage Reference Input ............................................................ 17 Revision History ............................................................................... 2 Power Supply............................................................................... 17 Specifications..................................................................................... 3 Digital Interface .......................................................................... 17 Timing Specifications .................................................................. 5 CS Mode ...................................................................................... 18 Absolute Maximum Ratings ............................................................ 6 Chain Mode ................................................................................ 22 ESD Caution .................................................................................. 6 Applications Information .............................................................. 24 Pin Configuration and Function Descriptions ............................. 7 Simultaneous Sampling ............................................................. 24 Typical Performance Characteristics ............................................. 8 Functional Safety Considerations ............................................ 25 Terminology .................................................................................... 13 Layout............................................................................................... 26 Theory of Operation ...................................................................... 14 Evaluating Performance of the AD7903.................................. 26 Circuit Information .................................................................... 14 Outline Dimensions ....................................................................... 27 Converter Operation .................................................................. 14 Ordering Guide .......................................................................... 27 Typical Connection Diagram.................................................... 15 REVISION HISTORY 8/14—Rev. A to Rev. B Changed Standby Current Unit from nA to µA ........................... 4 Changes to Power Supply Section ................................................ 17 1/14—Rev. 0 to Rev. A Change to Gain Error Temperature Drift Parameter .................. 3 Changes to Figure 12 ........................................................................ 9 Changes to Figure 17 and Figure 20............................................. 10 Changes to Figure 28 ...................................................................... 11 12/13—Revision 0: Initial Version Rev. B | Page 2 of 28 Data Sheet AD7903 SPECIFICATIONS VDD = 2.5 V, VIO = 2.3 V to 5.5 V, VREF = 5 V, TA = −40°C to +125°C, unless otherwise noted.1 Table 2. Parameter RESOLUTION ANALOG INPUT Voltage Range Absolute Input Voltage Common-Mode Input Range Analog Input CMRR Leakage Current at 25°C Input Impedance ACCURACY No Missing Codes Differential Nonlinearity Error Integral Nonlinearity Error Transition Noise Gain Error3 Gain Error Temperature Drift Gain Error Match3 Offset Error3 Offset Temperature Drift Offset Error Match3 Power Supply Sensitivity THROUGHPUT Conversion Rate Transient Response AC ACCURACY Dynamic Range Oversampled Dynamic Range Signal-to-Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR) Total Harmonic Distortion (THD) Signal-to-(Noise + Distortion) (SINAD) Channel-to-Channel Isolation Test Conditions/Comments Min 16 Typ INx+ − INx− INx+, INx− INx+, INx− fIN = 450 kHz Acquisition phase −VREF −0.1 VREF × 0.475 Max Unit Bits +VREF VREF + 0.1 VREF × 0.525 V V V dB nA VREF × 0.5 67 200 See the Analog Inputs section 16 −1.0 VREF = 5 V VREF = 2.5 V VREF = 5 V VREF = 2.5 V VREF = 5 V VREF = 2.5 V TMIN to TMAX −2.0 −0.04 TMIN to TMAX TMIN to TMAX −0.5 TMIN to TMAX VDD = 2.5 V ± 5% VIO ≥ 2.3 V up to 85°C, VIO ≥ 3.3 V above 85°C, up to 125°C Full-scale step VREF = 5 V VREF = 2.5 V fOUT = 10 kSPS fIN = 1 kHz, VREF = 5 V fIN = 1 kHz, VREF = 2.5 V fIN = 1 kHz fIN = 1 kHz fIN = 1 kHz, VREF = 5 V fIN = 1 kHz, VREF = 2.5 V fIN = 10 kHz ±0.4 ±0.7 ±0.5 ±0.4 0.75 1.2 ±0.006 0.19 0.0 ±0.015 0.3 0.05 ±0.1 0 92 89 91.5 88.5 95.5 92.5 113.5 94 91 −115 −112 93.5 90.5 −120 +1.0 +2.0 +0.04 0.025 +0.5 1.0 Bits LSB2 LSB2 LSB2 LSB2 LSB2 LSB2 % FS ppm/°C % FS mV ppm/°C mV LSB2 1 MSPS 290 ns dB4 dB4 dB4 dB4 dB4 dB4 dB4 dB4 dB4 dB4 In this data sheet, the voltages for the VDDx, VIOx, and REFx pins are indicated by VDD, VIO, and VREF, respectively. With the 5 V input range, 1 LSB = 152.6 µV. With the 2.5 V input range, 1 LSB = 76.3 µV. See the Terminology section. These specifications include full temperature range variation, but they do not include the error contribution from the external reference. 4 All specifications in decibels (dB) are referred to a full-scale input FSR. Although these parameters are referred to full scale, they are tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 1 2 3 Rev. B | Page 3 of 28 AD7903 Data Sheet VDD = 2.5 V, VIO = 2.3 V to 5.5 V, TA = −40°C to +125°C, unless otherwise noted.1 Table 3. Parameter REFERENCE Voltage Range Load Current SAMPLING DYNAMICS −3 dB Input Bandwidth Aperture Delay Aperture Delay Match DIGITAL INPUTS Logic Levels VIL VIH IIL IIH DIGITAL OUTPUTS Data Format Pipeline Delay VOL VOH POWER SUPPLIES VDDx VIOx VIOx Range IVDDx IVIOx Standby Current2, 3 Power Dissipation VDD Only REF Only VIO Only Energy per Conversion TEMPERATURE RANGE4 Specified Performance Test Conditions/Comments Min Typ 2.4 Max Unit 5.1 1 MSPS, VREF = 5 V, each ADC 330 V µA VDD = 2.5 V VDD = 2.5 V 10 2.0 2.0 MHz ns ns VIO > 3 V VIO ≤ 3 V VIO > 3 V VIO ≤ 3 V −0.3 −0.3 0.7 × VIO 0.9 × VIO −1 −1 +0.3 × VIO +0.1 × VVIO VIO + 0.3 VIO + 0.3 +1 +1 V V V V µA µA 0 Bits Samples Twos complement No delay; conversion results available immediately after conversion is complete ISINK = +500 µA ISOURCE = −500 µA Specified performance Full Range Each ADC Each ADC VDD and VIO = 2.5 V, 25°C 10 kSPS throughput 1 MSPS throughput TMIN to TMAX 0.4 V V 2.625 5.5 5.5 1.6 0.45 V V V mA mA µA µW mW mW mW mW nJ/sample VIO − 0.3 2.375 2.3 1.8 2.5 1.4 0.2 0.35 140 12.0 7.0 3.3 1.7 7.0 −40 In this data sheet, the voltages for the VDDx, VIOx, and REFx pins are indicated by VDD, VIO, and VREF, respectively. With all digital inputs forced to VIOx or to ground as required. 3 During the acquisition phase. 4 Contact Analog Devices, Inc., for the extended temperature range. 1 2 Rev. B | Page 4 of 28 16 +125 °C Data Sheet AD7903 TIMING SPECIFICATIONS −40°C to +125°C, VDD = 2.37 V to 2.63 V, VIO = 2.3 V to 5.5 V, unless otherwise stated. See Figure 2 and Figure 3 for load conditions. Table 4. Parameter Conversion Time (CNVx Rising Edge to Data Available) Acquisition Time Time Between Conversions VIOx Above 2.3 V CNVx Pulse Width (CS Mode) SCKx Period (CS Mode) VIOx Above 4.5 V VIOx Above 3 V VIOx Above 2.7 V VIOx Above 2.3 V SCKx Period (Chain mode) VIOx Above 4.5 V VIOx Above 3 V VIOx Above 2.7 V VIOx Above 2.3 V SCKx Low Time SCKx High Time SCKx Falling Edge to Data Remains Valid SCKx Falling Edge to Data Valid Delay VIOx Above 4.5 V VIOx Above 3 V VIOx Above 2.7 V VIOx Above 2.3 V CNVx or SDIx Low to SDOx, D15 (MSB) Valid (CS Mode) VIOx Above 3 V VIOx Above 2.3 V CNVx or SDIx High or Last SCKx Falling Edge to SDOx High Impedance (CS Mode) SDIx Valid Setup Time from CNVx Rising Edge (CS Mode) SDIx Valid Hold Time from CNVx Rising Edge (CS Mode) SCKx Valid Setup Time from CNVx Rising Edge (Chain Mode) SCKx Valid Hold Time from CNVx Rising Edge (Chain Mode) SDIx Valid Setup Time from SCKx Falling Edge (Chain Mode) SDIx Valid Hold Time from SCKx Falling Edge (Chain Mode) SDIx High to SDOx High (Chain Mode with Busy Indicator) IOL tCNVH tSCK tSCKL tSCKH tHSDO tDSDO tDIS tSSDICNV tHSDICNV tSSCKCNV tHSCKCNV tSSDISCK tHSDISCK tDSDOSDI 11755-002 IOH Unit ns ns 1000 10 ns ns 10.5 12 13 15 ns ns ns ns 11.5 13 14 16 4.5 4.5 3 ns ns ns ns ns ns ns 9.5 11 12 14 ns ns ns ns 10 15 20 ns ns ns ns ns ns ns ns ns ns 5 2 5 5 2 3 15 Y% VIOx1 tDELAY VIH2 VIL2 1.4V 500µA Max 710 tEN X% VIOx1 CL 20pF Typ tSCK tDELAY TO SDOx Min 500 290 VIH2 VIL2 1 FOR VIOx ≤ 3.0V, X = 90 AND Y = 10; FOR VIOx > 3.0V, X = 70 AND Y = 30. VIH AND MAXIMUM VIL USED. SEE SPECIFICATIONS FOR DIGITAL INPUTS PARAMETER IN TABLE 3. 2 MINIMUM Figure 2. Load Circuit for Digital Interface Timing Figure 3. Voltage Levels for Timing Rev. B | Page 5 of 28 11755-003 500µA Symbol tCONV tACQ tCYC AD7903 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Analog Inputs INx+, INx− to GND1 Supply Voltage REFx, VIOx to GND VDDx to GND VDDx to VIOx Digital Inputs to GND Digital Outputs to GND Storage Temperature Range Junction Temperature Lead Temperatures Vapor Phase (60 sec) Infrared (15 sec) 1 Rating −0.3 V to VREF + 0.3 V or ±10 mA −0.3 V to +6.0 V −0.3 V to +3.0 V +3 V to −6 V −0.3 V to VIO + 0.3 V −0.3 V to VIO + 0.3 V −65°C to +150°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 255°C 260°C See the Analog Inputs section for an explanation of INx+ and INx−. Rev. B | Page 6 of 28 Data Sheet AD7903 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS REF1 1 20 VIO1 VDD1 2 19 SDI1 IN1+ 3 GND 5 18 SCK1 AD7903 TOP VIEW (Not to Scale) 17 SDO1 16 CNV1 REF2 6 15 VIO2 VDD2 7 14 SDI2 IN2+ 8 13 SCK2 IN2– 9 12 SDO2 GND 10 11 CNV2 11755-004 IN1– 4 Figure 4. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1, 6 Mnemonic REF1, REF2 Type1 AI 2, 7 3, 8 4, 9 5, 10 11, 16 VDD1, VDD2 IN1+, IN2+ IN1−, IN2− GND CNV2, CNV1 P AI AI P DI 12, 17 SDO2, SDO1 DO 13, 18 14, 19 SCK2, SCK1 SDI2, SDI1 DI DI 15, 20 VIO2, VIO1 P 1 Description Reference Input Voltage. The REFx range is 2.4 V to 5.1 V. These pins are referred to the GND pin, and decouple each pin closely to the GND pin with a 10 μF capacitor. Power Supplies. Differential Positive Analog Inputs. Differential Negative Analog Inputs. Power Supply Ground. Conversion Inputs. These inputs have multiple functions. On the leading edge, they initiate conversions and select the interface mode of the device: chain mode or active low chip select (CS) mode. In CS mode, the SDOx pins are enabled when the CNVx pins are low. In chain mode, the data must be read when the CNVx pins are high. Serial Data Outputs. The conversion result is output on these pins. The conversion result is synchronized to SCKx. Serial Data Clock Inputs. When the device is selected, the conversion results are shifted out by these clocks. Serial Data Inputs. These inputs provide multiple functions. They select the interface mode of the ADC, as follows: CS mode is selected if the SDIx pins are high during the CNVx rising edge. In this mode, either SDIx or CNVx can enable the serial output signals when low. If SDIx or CNVx is low when the conversion is complete, the busy indicator feature is enabled. Input/Output Interface Digital Power. Nominally at the same supply as the host interface (2.5 V or 3.3 V). AI = analog input, DI = digital input, DO = digital output, and P = power. Rev. B | Page 7 of 28 AD7903 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VDD = 2.5 V, VREF = 5.0 V, VIO = 3.3 V, TA = 25°C, fSAMPLE = 1 MSPS, unless otherwise noted. 0.6 0.4 0.4 0.2 0.2 DNL (LSB) 0.6 –0.2 0 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 16384 32768 65536 49152 –1.0 11755-405 –1.0 CODE 0 1.0 POSITIVE DNL: +0.39 LSB NEGATIVE DNL: –0.39 LSB 0.8 0.6 0.4 0.4 0.2 0.2 DNL (LSB) INL (LSB) 1.0 0.6 0 –0.2 0 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 32768 65536 49152 –1.0 11755-406 –1.0 16384 CODE 49152 32768 65536 CODE Figure 9. Differential Nonlinearity vs. Code, VREF = 2.5 V 0 0 fSAMPLE = 1MSPS fIN = 10kHz –20 fSAMPLE = 1MSPS fIN = 10kHz SNR = 91.96dB THD = –110.2dB SFDR = 114.5dB SINAD = 91.91dB –20 SNR = 95.04dB THD = –117.3dB SFDR = 114.6dB SINAD = 95.02dB –40 –40 –60 SNR (dB) –60 –80 –100 –80 –100 –120 –120 –140 –140 –160 –160 0 100 200 300 FREQUENCY (kHz) 400 500 11755-407 SNR (dB) 16384 0 Figure 6. Integral Nonlinearity vs. Code, VREF = 2.5 V –180 65536 49152 Figure 8. Differential Nonlinearity vs. Code, VREF = 5 V POSITIVE INL: +0.39 LSB NEGATIVE INL: –0.44 LSB 0 32768 CODE Figure 5. Integral Nonlinearity vs. Code, VREF = 5 V 0.8 16384 11755-408 0 0 POSITIVE DNL: +0.31 LSB NEGATIVE DNL: –0.38 LSB 0.8 11755-409 0.8 INL (LSB) 1.0 POSITIVE INL: +0.35 LSB NEGATIVE INL: –0.39 LSB Figure 7. FFT Plot, VREF = 5 V –180 0 100 200 300 FREQUENCY (kHz) Figure 10. FFT Plot, VREF = 2.5 V Rev. B | Page 8 of 28 400 500 11755-410 1.0 AD7903 45000 45000 40000 40000 35000 35000 NUMBER OF OCCURRENCES 30000 25000 20000 15000 10000 5000 30000 25000 20000 15000 10000 5000 FFE1 FFE2 FFE3 FFE4 FFE5 FFE6 FFE7 FFE8 FFE9 FFEA CODES IN HEX 0 11755-411 0 11755-414 NUMBER OF OCCURRENCES Data Sheet FFF1 FFF2 FFF3 FFF4 FFF5 FFF6 FFF7 FFF8 FFF9 FFFA FFFB CODES IN HEX Figure 11. Histogram of a DC Input at the Code Center, VREF = 5 V Figure 14. Histogram of a DC Input at the Code Center, VREF = 2.5 V 40000 98 35000 96 25000 SNR (dB) 20000 95 15000 94 10000 FFD2 FFD3 FFD4 FFD5 FFD6 FFD7 FFD8 FFD9 FFDA FFDB CODES IN HEX 92 11755-412 0 –10 –9 –4 –3 –2 –1 0 –95 115 –100 110 15.5 96 15.0 SFDR 92 90 14.0 88 13.5 THD (dB) 14.5 ENOB (Bits) 94 –105 105 –110 100 –115 86 95 THD 13.0 84 –120 90 12.5 82 80 12.0 2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25 REFERENCE VOLTAGE (V) 11755-413 SNR, SINAD (dB) –5 Figure 15. SNR vs. Input Level 16.0 SNR SINAD ENOB –6 SFDR (dB) 98 –7 INPUT LEVEL (dB) Figure 12. Histogram of a DC Input at the Code Transition, VREF = 5 V 100 –8 11755-415 93 5000 –125 2.25 2.75 3.25 3.75 4.25 4.75 REFERENCE VOLTAGE (V) Figure 16. THD, SFDR vs. Reference Voltage Figure 13. SNR, SINAD, and ENOB vs. Reference Voltage Rev. B | Page 9 of 28 85 5.25 11755-416 NUMBER OF OCCURRENCES 97 30000 AD7903 Data Sheet 96 –80 95 –85 94 –90 93 –95 THD (dB) SINAD (dB) 92 91 90 –100 –105 89 88 –110 87 –120 10 11755-417 85 10 100 INPUT FREQUENCY (kHz) 11755-420 –115 86 100 INPUT FREQUENCY (kHz) Figure 17. SINAD vs. Input Frequency Figure 20. THD vs. Input Frequency 94.8 –100 94.6 –105 THD (dB) SNR (dB) 94.4 94.2 94.0 –110 –115 93.8 –120 –35 –15 5 25 45 85 65 105 125 TEMPERATURE (°C) –125 –55 11755-418 93.4 –55 –35 –15 5 45 25 85 65 105 125 TEMPERATURE (°C) Figure 18. SNR vs. Temperature 11755-421 93.6 Figure 21. THD vs. Temperature 1.6 1.4 TA = 25°C IVDD 1.4 1.2 1.2 CURRENT (mA) 0.8 0.6 IREF 0.4 1.0 0.8 IVDD 0.6 0.4 IVIO 0 2.375 0.2 2.425 2.475 2.525 VDD VOLTAGE (V) 2.575 2.625 0 10 IVIO 100 1000 SAMPLE RATE (kSPS) Figure 22. Operating Currents of Each ADC vs. Sample RateCr Figure 19. Operating Currents of Each ADC vs. VDD Supply Voltage Rev. B | Page 10 of 28 11755-422 0.2 11755-050 CURRENT (mA) 1.0 Data Sheet AD7903 8 1.4 IVDD 7 1.2 6 CURRENT (µA) CURRENT (mA) 1.0 0.8 0.6 IREF 0.4 5 4 3 IVDD + IVIO 2 IVIO 0.2 –15 5 25 45 65 TEMPERATURE (°C) 85 105 125 0 –55 0.10 0.10 0.08 0.08 0.06 0.06 0.04 0.02 0 –0.02 –0.04 –0.06 85 105 125 0.04 0.02 0 –0.02 –0.04 –0.06 –0.08 –15 5 25 45 65 85 105 125 –0.10 –55 11755-424 –35 TEMPERATURE (°C) –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) Figure 24. Offset Error vs. Temperature Figure 27. Offset Error Match vs. Temperature 0.05 0.010 GAIN ERROR MATCH (% FS) 0.03 0.01 –0.01 0.005 0 –0.005 –0.05 –55 –35 –15 5 25 45 65 85 TEMPERATURE (°C) 105 125 –0.010 –55 –35 –15 5 25 45 65 85 TEMPERATURE (°C) Figure 28. Gain Error Match vs. Temperature Figure 25. Gain Error vs. Temperature Rev. B | Page 11 of 28 105 125 11755-428 –0.03 11755-425 GAIN ERROR (% FS) 45 25 5 65 TEMPERATURE (°C) 11755-427 –0.08 –0.10 –55 –15 Figure 26. Power-Down Current of Each ADC vs. Temperature OFFSET ERROR MATCH (mV) OFFSET ERROR (mV) Figure 23. Operating Currents of Each ADC vs. Temperature –35 11755-054 –35 11755-053 0 –55 1 AD7903 Data Sheet –112 –114 –115 –116 –117 –118 –119 –120 –121 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) Figure 29. Channel-to-Channel Isolation vs. Temperature –114 –116 –118 –120 –122 –124 10 100 INPUT FREQUENCY (MHz) Figure 30. Channel-to-Channel Isolation vs. Input Frequency Rev. B | Page 12 of 28 11755-430 CHANNEL-TO-CHANNEL ISOLATION (dB) fIN = 10kHz –113 fSAMPLE = 1MSPS 11755-429 CHANNEL-TO-CHANNEL ISOLATION (dB) –112 Data Sheet AD7903 TERMINOLOGY Integral Nonlinearity Error (INL) INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. ENOB is expressed in bits. Offset Error Offset error is the difference between the ideal midscale voltage (that is, 0 V) and the actual voltage producing the midscale output code (that is, 0 LSB). Offset Error Match It is the difference in offsets, expressed in millivolts between the channels of a multichannel converter. It is computed with the following equation: Offset Matching = VOFFSETMAX − VOFFSETMIN Offset matching is usually expressed in millivolts with the fullscale input range stated in the product data sheet. Gain Error The first transition (from 100 … 00 to 100 … 01) should occur at a level ½ LSB above nominal negative full scale (−4.999981 V for the ±5 V range). The last transition (from 011 … 10 to 011 … 11) occurs for an analog voltage that is 1½ LSB below the nominal full scale (4.999943 V for the ±5 V range). The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. Gain Error Match It is the ratio of the maximum full scale to the minimum full scale of a multichannel ADC. It is expressed as a percentage of full scale using the following equation: × 100% where: FSRMAX is the most positive gain error of the ADC. FSRMIN is the most negative gain error. ENOB = (SINADdB − 1.76)/6.02 Noise Free Code Resolution Noise free code resolution is the number of bits beyond which it is impossible to distinctly resolve individual codes. It is calculated as follows: Noise Free Code Resolution = log2(2N/Peak-to-Peak Noise) Noise free code resolution is expressed in bits. Effective Resolution Effective resolution is calculated as follows: Effective Resolution = log2(2N/RMS Input Noise) Effective resolution is expressed in bits. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels (dB). where: VOFFSETMAX is the most positive offset error. VOFFSETMIN is the most negative offset error. FSR MAX − FSRMIN Gain Matching = FSRMAX + FSRMIN 2 Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD by the following formula: Dynamic Range Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together. The value for dynamic range is expressed in decibels (dB). It is measured with a signal at −60 dBFS to include all noise sources and DNL artifacts. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels (dB). Signal-to-(Noise + Distortion) (SINAD) Ratio SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels (dB). Aperture Delay Aperture delay is the measure of the acquisition performance. It is the time between the rising edge of the CNVx input and when the input signal is held for a conversion. Transient Response Transient response is the time required for the ADC to accurately acquire its input after a full-scale step function is applied. Rev. B | Page 13 of 28 AD7903 Data Sheet THEORY OF OPERATION INx+ MSB LSB 32,768C 16,384C 4C 2C C SWITCHES CONTROL SWx+ C BUSY REFx CONTROL LOGIC COMP GND 32,768C 16,384C 4C 2C C OUTPUT CODE C LSB MSB SWx– 11755-011 CNVx INx– Figure 31. ADC Simplified Schematic The AD7903 is a fast, low power, precise, dual 16-bit ADC using a successive approximation architecture. The AD7903 is capable of simultaneously converting 1,000,000 samples per second (1 MSPS) and powers down between conversions. When operating at 10 kSPS, for example, it typically consumes 70 μW per ADC, making it ideal for battery-powered applications. The AD7903 provides the user with an on-chip track-and-hold and does not exhibit any pipeline delay or latency, making it ideal for multichannel multiplexed applications. the comparator input varies by binary-weighted voltage steps (VREF/2, VREF/4 ... VREF/65,536). The control logic toggles these switches, starting with the MSB, to bring the comparator back into a balanced condition. After the completion of this process, the part returns to the acquisition phase, and the control logic generates the ADC output code and a busy signal indicator. Because the AD7903 has an on-board conversion clock, the serial clock, SCKx, is not required for the conversion process. Transfer Functions The ideal transfer characteristic for the AD7903 is shown in Figure 32 and Table 7. ADC CODE (TWOS COMPLEMENT) The AD7903 can be interfaced to any 1.8 V to 5 V digital logic family. It is available in a 20-lead QSOP that allows flexible configurations. The device is pin-for-pin compatible with the pseudo differential, 16-bit AD7902. CONVERTER OPERATION The AD7903 is a dual successive approximation ADC based on a charge redistribution DAC. Figure 31 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 16 binary-weighted capacitors, which are connected to the two comparator inputs. During the acquisition phase of each ADC, terminals of the array tied to the input of the comparator are connected to GND via SWx+ and SWx−. All independent switches are connected to the analog inputs. Therefore, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the INx+ and INx− inputs. When the acquisition phase is complete and the CNVx input goes high, a conversion phase is initiated. When the conversion phase begins, SWx+ and SWx− are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the GND input. Therefore, the differential voltage between the INx+ and INx− inputs, captured at the end of the acquisition phase, is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between GND and REFx, 011...111 011...110 011...101 100...010 100...001 100...000 –FSR –FSR + 1 LSB –FSR + 0.5 LSB +FSR – 1 LSB +FSR – 1.5 LSB ANALOG INPUT 11755-112 CIRCUIT INFORMATION Figure 32. ADC Ideal Transfer Function Table 7. Output Codes and Ideal Input Voltages Description FSR − 1 LSB Midscale + 1 LSB Midscale Midscale − 1 LSB −FSR + 1 LSB −FSR 1 2 Analog Input, VREF = 5 V +4.999962 V +38.15 μV 0V −38.15 μV −4.999962 V −5 V Digital Output Code (Hex) 0x7FFF1 0x0001 0x0000 0xFFFF 0x8001 0x80002 This is also the code for an overranged analog input (VIN+ − VIN− above VREF − VGND). This is also the code for an underranged analog input (VIN+ − VIN− below VGND). Rev. B | Page 14 of 28 Data Sheet AD7903 90 TYPICAL CONNECTION DIAGRAM 85 ANALOG INPUTS 80 CMRR (dB) Figure 35 shows an example of the recommended connection diagram for the AD7903 when multiple supplies are available. Figure 33 shows an equivalent circuit of the input structure of the AD7903. The two diodes, D1 and D2, provide ESD protection for the analog inputs, INx+ and INx−. The analog input signal must never exceed the reference input voltage (VREF) by more than 0.3 V. If the analog input signal exceeds this level, the diodes become forward biased and start conducting current. These diodes can handle a forward-biased current of 130 mA maximum. However, if the supplies of the input buffer (for example, the supplies of the ADA4841-1 in Figure 35) are different from those of the VREF, the analog input signal may eventually exceed the supply rails by more than 0.3 V. In such a case (for example, an input buffer with a short circuit), the current limitation can be used to protect the device. 70 60 1k D1 Figure 33. Equivalent Analog Input Circuit When the source impedance of the driving circuit is low, the AD7903 can be driven directly. Large source impedances significantly affect the ac performance, especially THD. The dc performances are less sensitive to the input impedance. The maximum source impedance depends on the amount of THD that can be tolerated. The THD degrades as a function of the source impedance and the maximum input frequency. The analog input structure allows for the sampling of the differential signal between INx+ and INx−. By using these differential inputs, signals common to both inputs, and within the allowable common-mode input range, are rejected. V+ REF1 2.5V 100nF 10µF2 V+ 1.8V TO 5V 100nF 20Ω 0V TO VREF REFx 2.7nF V– 10M During the sampling phase, where the switches are closed, the input impedance is limited to CPIN. RIN and CIN make a one-pole, low-pass filter that reduces undesirable aliasing effects and limits noise. D2 GND 1M During the acquisition phase, the impedance of the analog inputs (INx+ or INx−) can be modeled as a parallel combination of the CPIN capacitor and the network formed by the series connection of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically 400 Ω and is a lumped component composed of serial resistors and the on resistance of the switches. CIN is typically 30 pF and is mainly the ADC sampling capacitor. 11755-114 CPIN 100k FREQUENCY (Hz) Figure 34. Analog Input CMRR vs. Frequency CIN RIN 10k VDDx INx+ VIOx SDIx 4 SCKx AD7903 ADCx V+ INx– 20Ω VREF TO 0V ADA4841-1 3 V– 11755-040 65 REFx INx+ OR INx– 75 GND SDOx 3-WIRE INTERFACE CNVx 2.7nF 4 SEE RECOMMENDED LAYOUT IN FIGURE 54. 3 SEE THE DRIVER AMPLIFIER CHOICE SECTION. 4 OPTIONAL FILTER. SEE THE ANALOG INPUTS SECTION. Figure 35. Typical Application Diagram with Multiple Supplies Rev. B | Page 15 of 28 11755-013 1 SEE THE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION. 2C REF IS USUALLY A 10µF CERAMIC CAPACITOR (X5R). AD7903 Data Sheet DRIVER AMPLIFIER CHOICE Table 8. Recommended Driver Amplifiers Although the AD7903 is easy to drive, the driver amplifier must meet the following requirements: Amplifier ADA4941-1 ADA4841-x AD8021 AD8022 OP184 AD8655 AD8605, AD8615 The noise generated by the driver amplifier must be kept as low as possible to preserve the SNR and transition noise performance of the AD7903. The noise from the driver is filtered by the one-pole, low-pass filter of the AD7903 analog input circuit, made by RIN and CIN or by the external filter, if one is used. Because the typical noise of the AD7903 is 40 µV rms, the SNR degradation due to the amplifier is SNRLOSS • • 40 = 20 log π 2 2 40 + f − 3dB (NeN ) 2 SINGLE-TO-DIFFERENTIAL DRIVER For applications using a single-ended analog signal, either bipolar or unipolar, the ADA4941-1 single-ended-to-differential driver allows a differential input to the device. The schematic is shown in Figure 36. R1 and R2 set the attenuation ratio between the input range and the ADC range (VREF). R1, R2, and CF are chosen depending on the desired input resistance, signal bandwidth, antialiasing, and noise contribution. For example, for the ±10 V range with a 4 kΩ impedance, R1 = 4 kΩ and R2 = 1 kΩ. where: f−3dB is the input bandwidth, in megahertz, of the AD7903 (10 MHz) or the cutoff frequency of the input filter, if one is used. N is the noise gain of the amplifier (for example, gain = 1 in buffer configuration; see Figure 35). eN is the equivalent input noise voltage of the op amp, in nV/√Hz. For ac applications, the driver must have a THD performance that is commensurate with the AD7903. For multichannel, multiplexed applications, the driver amplifier and the AD7903 analog input circuit must settle for a full-scale step onto the capacitor array at a 16-bit level (0.0015%, 15 ppm). In the amplifier data sheet, settling at 0.1% to 0.01% is more commonly specified. This may differ significantly from the settling time at a 16-bit level. Be sure to verify the settling time prior to driver selection. R5 R6 R3 R4 R3 and R4 set the common mode on the INx− input, and R5 and R6 set the common mode on the INx+ input of the ADC. The common mode must be close to VREF/2. For example, for the ±10 V range with a single supply, R3 = 8.45 kΩ, R4 = 11.8 kΩ, R5 = 10.5 kΩ, and R6 = 9.76 kΩ. +5V REF 10µF +5.2V 100nF REF OUTN 20Ω 2.7nF 2.7nF OUTP 100nF 20Ω IN +2.5V REFx INx+ VDDx AD7903 ADCx INx– GND FB ADA4941-1 ±10V, ±5V, .. R1 –0.2V R2 11755-115 • Typical Application Very low noise, low power, single to differential Very low noise, small, and low power Very low noise and high frequency Low noise and high frequency Low power, low noise, and low frequency 5 V single supply, low noise 5 V single supply, low power CF Figure 36. Single-Ended-to-Differential Driver Circuit Rev. B | Page 16 of 28 Data Sheet AD7903 VOLTAGE REFERENCE INPUT 10 When REF is driven by a very low impedance source (for example, a reference buffer using the AD8031 or the AD8605), a 10 µF (X5R, 0805 size) ceramic chip capacitor is appropriate for optimum performance. If an unbuffered reference voltage is used, the decoupling value depends on the reference used. For instance, a 22 µF (X5R, 1206 size) ceramic chip capacitor is appropriate for optimum performance using a low temperature drift ADR43x reference. If desired, a reference decoupling capacitor with values as small as 2.2 µF can be used with a minimal impact on performance, especially DNL. Regardless, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nF) between the REFx and GND pins. POWER SUPPLY The AD7903 uses two power supply pins per ADC: a core supply (VDDx) and a digital input/output interface supply (VIOx). VIOx allows direct interface with any logic between 1.8 V and 5.5 V. To reduce the number of supplies needed, VIOx and VDDx can be tied together. The AD7903 is independent of power supply sequencing between VIOx and VDDx. Additionally, it is very insensitive to power supply variations over a wide frequency range, as shown in Figure 37. 95 90 PSRR (dB) 85 IVDD IREF 0.1 IVIO 0.01 0.001 10000 100000 SAMPLING RATE (SPS) 1000000 Figure 38. Operating Currents per ADC vs. Sampling Rate DIGITAL INTERFACE Although the AD7903 has a reduced number of pins, it offers flexibility in its serial interface modes. When in CS mode, the AD7903 is compatible with SPI, QSPI, digital hosts, and DSPs. In this mode, the AD7903 can use either a 3-wire or 4-wire interface. A 3-wire interface using the CNVx, SCKx, and SDOx signals minimizes wiring connections useful, for instance, in isolated applications. A 4-wire interface using the SDIx, CNVx, SCKx, and SDOx signals allows CNVx, which initiates the conversions, to be independent of the readback timing (SDIx). This is useful in low jitter sampling or simultaneous sampling applications. When in chain mode, the AD7903 provides a daisy-chain feature using the SDIx input for cascading multiple ADCs on a single data line similar to a shift register. With the AD7903 housing two ADCs in one package, chain mode can be utilized to acquire data from both ADCs while using only one set of 4-wire user interface signals. The mode in which the device operates depends on the SDIx level when the CNVx rising edge occurs. CS mode is selected if SDIx is high, and chain mode is selected if SDIx is low. The SDIx hold time is such that when SDIx and CNVx are connected together, chain mode is always selected. 80 75 70 In either mode, the AD7903 offers the option of forcing a start bit in front of the data bits. This start bit can be used as a busy signal indicator to interrupt the digital host and trigger the data reading. Otherwise, without a busy indicator, the user must time out the maximum conversion time prior to readback. 10k 100k FREQUENCY (Hz) 1M 11755-139 65 60 1k 1 11755-137 OPERATING CURRENTS (mA) The AD7903 voltage reference input, REF, has a dynamic input impedance and must therefore be driven by a low impedance source with efficient decoupling between the REFx and GND pins, as explained in the Layout section. Figure 37. PSRR vs. Frequency The AD7903 powers down automatically at the end of each conversion phase; therefore, the power scales linearly with the sampling rate. This makes the part ideal for low sampling rates (of even a few hertz) and low battery-powered applications. The busy indicator feature is enabled as follows: • • Rev. B | Page 17 of 28 In CS mode if CNVx or SDIx is low when the ADC conversion ends (see Figure 42 and Figure 46). In chain mode if SCKx is high during the CNVx rising edge (see Figure 50). AD7903 Data Sheet CS MODE However, to avoid generation of the busy signal indicator, CNVx must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time. When the conversion is complete, the AD7903 enters the acquisition phase and powers down. When CNVx goes low, the MSB is automatically output onto SDOx. The remaining data bits are clocked by subsequent SCKx falling edges. The data is valid on both SCKx edges. Although the rising edge can be used to capture the data, a digital host using the falling edge of SCKx allows a faster reading rate, provided that it has an acceptable hold time. After the 16th SCKx falling edge or when CNVx goes high (whichever occurs first), SDOx returns to high impedance. CS Mode, 3-Wire Interface Without Busy Indicator CS mode, using a 3-wire interface without a busy indicator, is usually used when a single AD7903 is connected to a SPIcompatible digital host. The connection diagram is shown in Figure 39, and the corresponding timing diagram is shown in Figure 40. With SDIx tied to VIOx, a rising edge on CNVx initiates a conversion, selects CS mode, and forces SDOx to high impedance. When a conversion is initiated, it continues until completion, irrespective of the state of CNVx. This can be useful, for instance, to bring CNVx low to select other SPI devices, such as analog multiplexers. CONVERT DIGITAL HOST CNVx VIOx SDIx AD7903 DATA IN SDOx 11755-116 SCKx CLK Figure 39. CS Mode, 3-Wire Interface Without Busy Indicator Connection Diagram (SDIx High) SDIx = 1 tCYC tCNVH CNVx ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSCK tSCKL 2 3 14 tHSDO 16 tSCKH tEN SDOx 15 tDSDO D15 D14 D13 tDIS D1 D0 Figure 40. CS Mode, 3-Wire Interface Without Busy Indicator Serial Interface Timing (SDI High) Rev. B | Page 18 of 28 11755-216 1 SCKx Data Sheet AD7903 CS Mode, 3-Wire Interface with Busy Indicator When the conversion is complete, SDO goes from high impedance to low impedance. With a pull-up on the SDOx line, this transition can be used as an interrupt signal to initiate the data reading controlled by the digital host. The AD7903 then enters the acquisition phase and powers down. The data bits are then clocked out, MSB first, by subsequent SCKx falling edges. The data is valid on both SCKx edges. Although the rising edge can be used to capture the data, a digital host using the SCKx falling edge allows a faster reading rate, provided that it has an acceptable hold time. After the optional 17th SCKx falling edge or when CNVx goes high (whichever occurs first), SDOx returns to high impedance. CS mode, using a 3-wire interface with a busy indicator, is usually used when a single AD7903 is connected to an SPIcompatible digital host having an interrupt input. The connection diagram is shown in Figure 41, and the corresponding timing is shown in Figure 42. With SDIx tied to VIOx, a rising edge on CNVx initiates a conversion, selects CS mode, and forces SDOx to high impedance. SDOx is maintained in high impedance until the completion of the conversion, irrespective of the state of CNVx. Prior to the minimum conversion time, CNVx can be used to select other SPI devices, such as analog multiplexers, but CNVx must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. If multiple ADCs are selected at the same time, the SDOx output pin handles this contention without damage or induced latch-up. Meanwhile, it is recommended that this contention be kept as short as possible to limit extra power dissipation. CONVERT VIOx DIGITAL HOST CNVx VIOx 47kΩ AD7903 DATA IN SDOx IRQ SCKx 11755-118 SDIx CLK Figure 41. CS Mode, 3-Wire Interface with Busy Indicator Connection Diagram (SDIx High) SDIx = 1 tCYC tCNVH CNVx ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSCK tSCKL 1 2 3 15 tHSDO 16 17 tSCKH tDIS tDSDO SDOx D15 D14 D1 D0 Figure 42. CS Mode, 3-Wire Interface with Busy Indicator Serial Interface Timing (SDIx High) Rev. B | Page 19 of 28 11755-218 SCKx AD7903 Data Sheet CS Mode, 4-Wire Interface Without Busy Indicator minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. When the conversion is complete, the AD7903 enters the acquisition phase and powers down. Each ADC result can be read by bringing its respective SDIx input low, which consequently outputs the MSB onto SDOx. The remaining data bits are then clocked by subsequent SCKx falling edges. The data is valid on both SCKx edges. Although the rising edge can be used to capture the data, a digital host using the SCKx falling edge allows a faster reading rate, provided it has an acceptable hold time. After the 16th SCKx falling edge or when SDIx goes high (whichever occurs first), SDOx returns to high impedance, and another ADC result can be read. CS mode, using a 4-wire interface without a busy indicator, is usually used when both ADCs within the AD7903 are connected to a SPI-compatible digital host. See Figure 43 for an AD7903 connection diagram example. The corresponding timing diagram is shown in Figure 44. With SDIx high, a rising edge on CNVx initiates a conversion, selects CS mode, and forces SDOx to high impedance. In this mode, CNVx must be held high during the conversion phase and the subsequent data readback. (If SDIx and CNVx are low, SDOx is driven low.) Prior to the minimum conversion time, SDIx can be used to select other SPI devices, such as analog multiplexers, but SDIx must be returned high before the CS2 CS1 CONVERT CNV1 AD7903 SDO1 SDI2 AD7903 ADC1 ADC2 SCK1 SCK2 DIGITAL HOST SDO2 11755-120 SDI1 CNV2 DATA IN CLK Figure 43. CS Mode, 4-Wire Interface Without Busy Indicator Connection Diagram tCYC CNVx ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSSDICNV SDI1 (CS1) tHSDICNV SDI2 (CS2) tSCK tSCKL 1 2 3 14 tHSDO tEN SDOx 15 16 17 18 30 31 32 tSCKH tDIS tDSDO D115 D114 D113 D11 D10 D215 D214 Figure 44. CS Mode, 4-Wire Interface Without Busy Indicator Serial Interface Timing Rev. B | Page 20 of 28 D21 D20 11755-220 SCKx Data Sheet AD7903 CS Mode, 4-Wire Interface with Busy Indicator SDIx can be used to select other SPI devices, such as analog multiplexers, but SDIx must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. When the conversion is complete, SDOx goes from high impedance to low impedance. With a pull-up on the SDOx line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. The AD7903 then enters the acquisition phase and powers down. The data bits are then clocked out, MSB first, by subsequent SCKx falling edges. The data is valid on both SCKx edges. Although the rising edge can be used to capture the data, a digital host using the SCKx falling edge allows a faster reading rate, provided that it has an acceptable hold time. After the optional 17th SCKx falling edge or SDIx going high (whichever occurs first), SDOx returns to high impedance. CS mode, using a 4-wire interface with a busy indicator, is usually used when an AD7903 is connected to a SPI-compatible digital host with an interrupt input. This CS mode is also used when it is desirable to keep CNVx, which is used to sample the analog input, independent of the signal that is used to select the data reading. This independence is particularly important in applications where low jitter on CNVx is desired. The connection diagram is shown in Figure 45, and the corresponding timing is given in Figure 46. With SDIx high, a rising edge on CNVx initiates a conversion, selects CS mode, and forces SDOx to high impedance. In this mode, CNVx must be held high during the conversion phase and the subsequent data readback. (If SDIx and CNVx are low, SDOx is driven low.) Prior to the minimum conversion time, CS1 CONVERT VIOx DIGITAL HOST CNVx 47kΩ AD7903 DATA IN SDOx IRQ SCKx 11755-122 SDIx CLK Figure 45. CS Mode, 4-Wire Interface with Busy Indicator Connection Diagram tCYC CNVx ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSSDICNV SDIx tSCK tHSDICNV tSCKL 2 3 15 tHSDO 16 17 tSCKH tDIS tDSDO tEN SDOx D15 D14 D1 Figure 46. CS Mode, 4-Wire Interface with Busy Indicator Serial Interface Timing Rev. B | Page 21 of 28 D0 11755-222 1 SCKx AD7903 Data Sheet held high during the conversion phase and the subsequent data readback. When the conversion is complete, the MSB is output onto SDOx and the AD7903 enters the acquisition phase and powers down. The remaining data bits stored in the internal shift register are clocked by subsequent SCKx falling edges. For each ADC, SDIx feeds the input of the internal shift register and is clocked by the SCKx falling edge. Each ADC in the chain outputs its data MSB first, and 16 × N clocks are required to read back the N ADCs. The data is valid on both SCKx edges. Although the rising edge can be used to capture the data, a digital host using the SCKx falling edge allows a faster reading rate and, consequently, more AD7903 devices in the chain, provided that the digital host has an acceptable hold time. The maximum conversion rate may be reduced due to the total readback time. CHAIN MODE Chain Mode Without Busy Indicator Chain mode without a busy indicator can be used to daisychain both ADCs within an AD7903 on a 3-wire serial interface. This feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register. See Figure 47 for a connection diagram example using both ADCs in an AD7903. The corresponding timing is shown in Figure 48. When SDIx and CNVx are low, SDOx is driven low. With SCKx low, a rising edge on CNVx initiates a conversion, selects chain mode, and disables the busy indicator. In this mode, CNVx is CONVERT CNV2 AD7903 ADC1 SDO1 SDI2 SCK1 DIGITAL HOST ADC2 SDO2 DATA IN SCK2 11755-124 SDI1 CNV1 AD7903 CLK Figure 47. Chain Mode Without Busy Indicator Connection Diagram SDI1 = 0 tCYC CNVx ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSCK tSCKL tSSCKCNV SCKx 1 2 3 15 16 17 18 30 31 32 D11 D10 tSCKH tHSDISCK tEN SDO1 = SDI2 14 tSSDISCK tHSCKCNV D115 D114 D113 D 11 D 10 D21 D20 tHSDO SDO2 D215 D214 D213 D115 D114 Figure 48. Chain Mode Without Busy Indicator Serial Interface Timing Rev. B | Page 22 of 28 11755-224 tDSDO Data Sheet AD7903 Chain Mode with Busy Indicator conversions, the SDOx pin of the ADC closest to the digital host (see the ADC labeled ADCx in the AD7903 B box in Figure 49) is driven high. This transition on SDOx can be used as a busy indicator to trigger the data readback controlled by the digital host. The AD7903 then enters the acquisition phase and powers down. The data bits stored in the internal shift register are clocked out, MSB first, by subsequent SCKx falling edges. For each ADC, SDIx feeds the input of the internal shift register and is clocked by the SCKx falling edge. Each ADC in the chain outputs its data MSB first, and 16 × N + 1 clocks are required to read back the N ADCs. Although the rising edge can be used to capture the data, a digital host using the SCKx falling edge allows a faster reading rate and, consequently, more ADCs in the chain, provided that the digital host has an acceptable hold time. Chain mode with a busy indicator can also be used to daisychain both ADCs within an AD7903 on a 3-wire serial interface while providing a busy indicator. This feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with limited interfacing capacity. Data readback is analogous to clocking a shift register. See Figure 49 for a connection diagram example using three AD7903 ADCs. The corresponding timing is shown in Figure 50. When SDIx and CNVx are low, SDOx is driven low. With SCKx high, a rising edge on CNVx initiates a conversion, selects chain mode, and enables the busy indicator feature. In this mode, CNVx is held high during the conversion phase and the subsequent data readback. When all ADCs in the chain have completed their CONVERT SDI1A CNVx CNVx CNVx AD7903 AD7903 AD7903 ADC1 SDO1A SDI2A ADC2 SDO2A SDIxB SCKx SCKx DIGITAL HOST ADCx SDOxB DATA IN SCKx IRQ CLK AD7903 A AD7903 B 11755-126 NOTES 1. DASHED LINE DENOTED ADCs ARE WITHIN A GIVEN PACKAGE. 2. SDI1A AND SDO1A REFER TO THE SDI1 AND SDO1 PINS IN ADC1 IN THE FIRST AD7903 OF THE CHAIN (AD7903 A). SDI2A AND SDO2A REFER TO THE SDI2 AND SDO2 PINS IN ADC2 OF AD7903 A. LIKEWISE, SDIxB AND SDOxB REFER TO THE SDIx AND SDOx PINS IN BOTH ADC1 AND ADC2 OF THE SECOND AD7903 IN THE CHAIN (AD7903 B) Figure 49. Chain Mode with Busy Indicator Connection Diagram tCYC CNVx = SDI1A ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSCK tSCKH SCKx 1 2 3 4 15 16 tSSDISCK tHSCKCNV 17 18 19 31 32 33 34 35 tSCKL DA115 SDO1A = SDI2A DA114 DA113 DA11 tDSDOSDI tDSDO SDO2A = SDIxB DA215 DA214 DA213 DA21 DA20 DA115 DA114 DA11 DA10 DBx15 DBx14 DBx13 DBx1 DBx0 DA215 DA214 DA21 DA20 tDSDOSDI SDOxB 49 DA10 tHSDO tDSDOSDI 48 tDSDOSDI tHSDISCK tEN 47 tDSDODSI Figure 50. Chain Mode with Busy Indicator Serial Interface Timing Rev. B | Page 23 of 28 DA115 DA114 DA11 DA10 11755-226 tSSCKCNV AD7903 Data Sheet APPLICATIONS INFORMATION Alternatively, for applications where simultaneous sampling is required but pins on the digital host are limited, the two user interfaces on the AD7903 can be connected in one of the daisychain configurations shown in Figure 47 and Figure 49. This daisy chaining allows the user to implement simultaneous sampling functionality while requiring only one digital host input pin. This scenario requires 31 or 32 SCKx falling edges (depending on the status of the busy indicator) to acquire data from the ADC. SIMULTANEOUS SAMPLING By having two unique user interfaces, the AD7903 provides maximum flexibility with respect to how conversion results are accessed from the device. The AD7903 provides an option for the two user interfaces to share the convert start (CNVx) signal from the digital host, creating a 2-channel, simultaneous sampling device. In applications such as control applications, where latency between the sampling instant and the availability of results in the digital host is critical, it is recommended that the AD7903 be configured as shown in Figure 51. This configuration allows simultaneous data reads, in addition to simultaneous sampling. However, this configuration also requires an additional data input pin on the digital host. This scenario allows the fastest throughput because it requires only 15 or 16 SCKx falling edges (depending on the status of the busy indicator) to acquire data from the ADC. Figure 51 shows an example of a simultaneous sampling system using two data inputs for the digital host. The corresponding timing diagram in Figure 52 shows a CS mode, 3-wire simultaneous sampling serial interface without a busy indicator. However, any of the 3-wire or 4-wire serial interface timing options can be used. CONVERT CNV1 SDI1 ADC1 CNV2 VIO2 AD7903 SDO1 DIGITAL HOST AD7903 SDI2 SCK1 ADC2 SDO2 DATA IN 2 DATA IN 1 SCK2 11755-324 VIO1 CLK Figure 51. Potential Simultaneous Sampling Connection Diagram SDIx = 1 tCYC tCNVH CNVx ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSCK tSCKL 2 3 14 tHSDO 15 16 tSCKH tEN tDSDO tDIS SDO1 D15 D14 D13 D1 D0 SDO2 D15 D14 D13 D1 D0 Figure 52. Potential Simultaneous Sampling Serial Interface Timing Rev. B | Page 24 of 28 11755-316 1 SCKx Data Sheet AD7903 FUNCTIONAL SAFETY CONSIDERATIONS The AD7903 contains two physically isolated ADCs, making it ideally suited for functional safety applications. Because of this isolation, each ADC features an independent user interface, an independent reference input, an independent analog input, and independent supplies. Physical isolation renders the device suitable for taking verification/backup measurements while separating the verification ADC from the system under control. Although the Simultaneous Sampling section describes how to operate the device in a simultaneous nature, the circuit is actually composed of two individual signal chains. This separation makes the AD7903 ideal for handling redundant measurement applications. Implementing a signal chain with redundant ADC measurement can contribute to a no single error system. Figure 53 shows a typical functional safety application circuit consisting of a redundant measurement with the employment of monitoring the inverted signal. The inversion is applied to detect common cause failures where it is expected that the circuit output moves in the same direction during a fault condition, instead of moving in the opposite direction as expected. In addition, the QSOP package that houses the device provides access to the leads for inspection. REF = 2.5V TO 5V 2.5V REF IN1+ ADC1 ±10V, ±5V, ... PHYSICALLY ISOLATED ADCs IN1– ADA4941-1 IN2+ ADC2 IN2– GND VDD1 VDD2 VIO1 VIO1 SDI1 SDI1 SCK1 SCK1 CNV1 CNV1 SDO1 SDO1 VIO2 VIO2 SDI2 SDI2 SCK2 SCK2 CNV2 CNV2 SDO2 SDO2 AD7903 Figure 53. Typical Functional Safety Block Diagram Rev. B | Page 25 of 28 11755-146 REF1 REF2 ADA4941-1 AD7903 Data Sheet LAYOUT ceramic capacitor in close proximity to (ideally, right up against) the REFx and GND pins and then connecting them with wide, low impedance traces. Design the printed circuit board (PCB) of the AD7903 such that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD7903, with its analog signals on the left side and its digital signals on the right side, eases this task. Finally, decouple the power supplies, VDDx and VIOx, with ceramic capacitors, typically 100 nF. Place them in close proximity to the AD7903 and connect them using short, wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines. Avoid running digital lines under the device because these couple noise onto the die unless a ground plane under the AD7903 is used as a shield. Do not run fast switching signals, such as CNVx or clocks, near analog signal paths. Avoid crossover of digital and analog signals. To avoid signal fidelity issues, take care to ensure monotonicity of digital edges in the PCB layout. See Figure 54 for an example of layout following these rules. EVALUATING PERFORMANCE OF THE AD7903 Other recommended layouts for the AD7903 are outlined in User Guide UG-609. The package for the evaluation board (EVAL-AD7903SDZ) includes a fully assembled and tested evaluation board, user guide, and software for controlling the board from a PC via the EVAL-SDP-CB1Z. Use at least one ground plane. It can be shared between or split between the digital and analog sections. In the latter case, join the planes underneath the AD7903. The AD7903 voltage reference inputs, REF1 and REF2, have a dynamic input impedance. Decouple these reference inputs with minimal parasitic inductances by placing the reference decoupling GND REF VDD VIO GND GND REF REF1 VIO1 VDD1 SDI1 IN1+ SCK1 IN1– GND REF REF2 SDO1 CNV1 GND VIO2 VDD2 SDI2 IN2+ SCK2 IN2– SDO2 GND CNV2 VIO VDD GND Figure 54. Example Layout of the AD7903 (Top Layer) Rev. B | Page 26 of 28 11755-147 GND Data Sheet AD7903 OUTLINE DIMENSIONS 0.345 (8.76) 0.341 (8.66) 0.337 (8.55) 20 11 1 10 0.010 (0.25) 0.006 (0.15) 0.069 (1.75) 0.053 (1.35) 0.065 (1.65) 0.049 (1.25) 0.010 (0.25) 0.004 (0.10) COPLANARITY 0.004 (0.10) 0.158 (4.01) 0.154 (3.91) 0.150 (3.81) 0.244 (6.20) 0.236 (5.99) 0.228 (5.79) 0.025 (0.64) BSC SEATING PLANE 0.012 (0.30) 0.008 (0.20) 8° 0° 0.020 (0.51) 0.010 (0.25) 0.050 (1.27) 0.016 (0.41) 0.041 (1.04) REF 08-19-2008-A COMPLIANT TO JEDEC STANDARDS MO-137-AD CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 55. 20-Lead Shrink Small Outline Package [QSOP] (RQ-20) Dimensions shown in inches and (millimeters) ORDERING GUIDE Model1 AD7903BRQZ AD7903BRQZ-RL7 EVAL-AD7903SDZ EVAL-SDP-CB1Z 1 Temperature Range −40°C to +125°C −40°C to +125°C Package Description 20-Lead Shrink Small Outline Package (QSOP) 20-Lead Shrink Small Outline Package (QSOP) Evaluation Board Controller Board Z = RoHS Compliant Part. Rev. B | Page 27 of 28 Package Option RQ-20 RQ-20 Ordering Quantity Tube, 56 Reel, 1,000 AD7903 Data Sheet NOTES ©2013–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11755-0-8/14(B) Rev. B | Page 28 of 28