10-Bit, 200 MSPS/250 MSPS/300 MSPS, 1.8 V Analog-to-Digital Converter AD9211 FEATURES FUNCTIONAL BLOCK DIAGRAM RBIAS PWDN AGND AD9211 REFERENCE VIN+ VIN– DRVDD DGND TRACK-AND-HOLD ADC 10-BIT CORE CLK+ CLK– AVDD (1.8V) 10 OUTPUT 10 STAGING LVDS CLOCK MANAGEMENT D9 TO D0 OR+ OR– SERIAL PORT DCO+ DCO– RESET SCLK SDIO CSB 06041-001 SNR = 60.1 dBFS @ fIN up to 70 MHz @ 300 MSPS ENOB of 9.7 @ fIN up to 70 MHz @ 300 MSPS (−1.0 dBFS) SFDR = −80 dBc @ fIN up to 70 MHz @ 300 MSPS (−1.0 dBFS) Excellent linearity DNL = ±0.1 LSB typical INL = ±0.2 LSB typical LVDS at 300 MSPS (ANSI-644 levels) 700 MHz full power analog bandwidth On-chip reference, no external decoupling required Integrated input buffer and track-and-hold Low power dissipation 437 mW @ 300 MSPS—LVDS SDR mode 410 mW @ 300 MSPS—LVDS DDR mode Programmable input voltage range 1.0 V to 1.5 V, 1.25 V nominal 1.8 V analog and digital supply operation Selectable output data format (offset binary, twos complement, Gray code) Clock duty cycle stabilizer Integrated data capture clock Figure 1. APPLICATIONS Wireless and wired broadband communications Cable reverse path Communications test equipment Radar and satellite subsystems Power amplifier linearization GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD9211 is a 10-bit monolithic sampling analog-to-digital converter optimized for high performance, low power, and ease of use. The product operates at up to a 300 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a track-and-hold (T/H) and voltage reference, are included on the chip to provide a complete signal conversion solution. 1. The ADC requires a 1.8 V analog voltage supply and a differential clock for full performance operation. The digital outputs are LVDS (ANSI-644) compatible and support either twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing. 4. Fabricated on an advanced CMOS process, the AD9211 is available in a 56-lead LFCSP, specified over the industrial temperature range (−40°C to +85°C). 2. 3. 5. High Performance—Maintains 60.1 dBFS SNR @ 300 MSPS with a 70 MHz input. Low Power—Consumes only 410 mW @ 300 MSPS. Ease of Use—LVDS output data and output clock signal allow interface to current FPGA technology. The on-chip reference and sample-and-hold provide flexibility in system design. Use of a single 1.8 V supply simplifies system power supply design. Serial Port Control—Standard serial port interface supports various product functions, such as data formatting, disabling the clock duty cycle stabilizer, powerdown, gain adjust, and output test pattern generation. Pin-Compatible Family—12-bit pin-compatible family offered as AD9230. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. AD9211 TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 19 Applications....................................................................................... 1 Analog Input and Voltage Reference ....................................... 19 Functional Block Diagram .............................................................. 1 Clock Input Considerations...................................................... 20 General Description ......................................................................... 1 Power Dissipation and Power-Down Mode ........................... 21 Product Highlights ........................................................................... 1 Digital Outputs ........................................................................... 21 Revision History ............................................................................... 2 Timing ......................................................................................... 22 Specifications..................................................................................... 3 RBIAS........................................................................................... 22 DC Specifications ......................................................................... 3 AD9211 Configuration Using the SPI ..................................... 22 AC Specifications.......................................................................... 4 Hardware Interface..................................................................... 23 Digital Specifications ................................................................... 5 Configuration Without the SPI ................................................ 23 Switching Specifications .............................................................. 6 Memory Map .................................................................................. 25 Timing Diagrams.......................................................................... 7 Reading the Memory Map Table.............................................. 25 Absolute Maximum Ratings............................................................ 8 Reserved Locations .................................................................... 25 Thermal Resistance ...................................................................... 8 Default Values ............................................................................. 25 ESD Caution.................................................................................. 8 Logic Levels................................................................................. 25 Pin Configurations and Function Descriptions ........................... 9 Outline Dimensions ....................................................................... 28 Typical Performance Characteristics ........................................... 13 Ordering Guide .......................................................................... 28 Equivalent Circuits ......................................................................... 18 REVISION HISTORY 5/07—Revision 0: Initial Version Rev. 0 | Page 2 of 28 AD9211 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted. Table 1. Parameter 1 RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error ANALOG INPUTS (VIN+, VIN−) Differential Input Voltage Range 2 Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance POWER SUPPLY AVDD DRVDD Supply Currents IAVDD 3 IDRVDD3/SDR Mode 4 IDRVDD3/DDR Mode 5 Power Dissipation3 SDR Mode4 DDR Mode5 Temp Full 25°C Full 25°C Full 25°C Full 25°C Full Min AD9211-200 Typ Max 10 Min Guaranteed 4.3 −12 Min Guaranteed 4.6 +12 −13 +4.3 −2.2 1.0 ±0.1 −0.5 +13 −13 +4.3 −2.2 +0.5 −0.5 −0.35 +0.5 −0.45 ±8 0.018 +4.3 ±0.1 −0.5 ±0.2 0.35 +13 1.1 ±0.1 ±0.2 AD9211-300 Typ Max 10 Guaranteed 4.4 1.3 −2.2 Full Full AD9211-250 Typ Max 10 +0.5 ±0.2 0.45 −0.7 ±7 0.018 +0.7 ±6 0.018 Unit Bits mV mV % FS % FS LSB LSB LSB LSB μV/°C %/°C Full Full Full 25°C 0.98 1.25 1.4 4.3 2 1.5 0.98 1.25 1.4 4.3 2 1.5 0.98 1.25 1.4 4.3 2 1.5 V p-p V kΩ pF Full Full 1.7 1.7 1.8 1.8 1.9 1.9 1.7 1.7 1.8 1.8 1.9 1.9 1.7 1.7 1.8 1.8 1.9 1.9 V V 134 51 35 144 54 158 53 38 169 55 189 54 39 203 57 333 304 356 380 353 403 437 410 468 mA mA mA mW mW mW Full Full Full Full Full Full See the AN-835 application note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. The input range is programmable through the SPI, and the range specified reflects the nominal values of each setting. See the Memory Map section. IAVDD and IDRVDD are measured with a −1 dBFS, 10.3 MHz sine input at rated sample rate. 4 Single data rate mode; this is the default mode of the AD9211. 5 Double data rate mode; user-programmable feature. See the Memory Map section. 1 2 3 Rev. 0 | Page 3 of 28 AD9211 AC SPECIFICATIONS 1 AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted. Table 2. Parameter 2 SNR fIN = 10 MHz fIN = 70 MHz fIN = 170 MHz SINAD fIN = 10 MHz fIN = 70 MHz fIN = 170 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 10 MHz fIN = 70 MHz fIN = 170 MHz WORST HARMONIC (Second or Third) fIN = 10 MHz fIN = 70 MHz fIN = 170 MHz WORST OTHER (SFDR Excluding Second and Third) fIN = 10 MHz fIN = 70 MHz fIN = 170 MHz TWO-TONE IMD 140.2 MHz/141.3 MHz @ −7 dBFS 170.2 MHz/171.3 MHz @ −7 dBFS ANALOG INPUT BANDWIDTH 1 2 Temp Min 25°C Full 25°C Full 25°C Full 59.0 58.9 58.9 58.8 58.5 58.4 25°C Full 25°C Full 25°C Full 59.0 58.9 58.8 58.7 58.2 58.1 AD9211-200 Typ Max 59.5 59.0 59.5 58.8 25°C Full 25°C Full 25°C Full −85 25°C 25°C 25°C 58.9 58.7 58.8 58.6 58.2 58.1 59.2 9.8 9.7 9.6 25°C Full 25°C Full 25°C Full 58.9 58.7 58.8 58.7 58.5 58.4 59.3 25°C 25°C 25°C −77 −77 −86 −83 −81 Min AD9211-250 Typ Max 59.4 58.6 57.5 58.5 57.0 58.3 57.0 59.3 59.0 59.4 58.6 57.3 58.4 57.0 58.2 56.7 59.2 59.0 9.7 9.7 9.7 −78 −78 −75 −75 −72 −72 −82 −82 −81 −81 −74 −74 −78 −86 700 −86 −80 −79 −82 −82 −79 −87 −82 700 Min AD9211-300 Typ Max 59.2 dB dB dB dB dB dB 59.1 58.7 59.1 dB dB dB dB dB dB 59.0 58.8 9.7 9.7 9.6 −79 −77 −76 −74 −70 −70 −80 −77 −79 −77 −77 −75 −80 −80 −80 −82 −80 −80 Bits Bits Bits −75 −70 −74 −67 −73 −67 dBc dBc dBc dBc dBc dBc −75 −70 −75 −71 −75 −70 dBc dBc dBc dBc dBc dBc −81 −82 700 All ac specifications tested by driving CLK+ and CLK− differentially. See the AN-835 application note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. Rev. 0 | Page 4 of 28 Unit dBc dBc MHz AD9211 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted. Table 3. Parameter 1 CLOCK INPUTS Logic Compliance Internal Common-Mode Bias Differential Input Voltage Input Voltage Range Input Common-Mode Range High Level Input Voltage (VIH) Low Level Input Voltage (VIL) High Level Input Current (IIH) Low Level Input Current (IIL) Input Resistance (Differential) Input Capacitance LOGIC INPUTS Logic 1 Voltage Logic 0 Voltage Logic 1 Input Current (SDIO) Logic 0 Input Current (SDIO) Logic 1 Input Current (SCLK, PWDN, CSB, RESET) Logic 0 Input Current (SCLK, PWDN, CSB, RESET) Input Capacitance LOGIC OUTPUTS 2 VOD Differential Output Voltage VOS Output Offset Voltage Output Coding 1 2 AD9211-200 Typ Max Full Full Full Full CMOS/LVDS/LVPECL 1.2 0.2 6 AVDD − AVDD + 0.3 1.6 1.1 AVDD 1.2 3.6 0 0.8 −10 +10 −10 +10 16 20 24 4 CMOS/LVDS/LVPECL 1.2 0.2 6 AVDD − AVDD + 0.3 1.6 1.1 AVDD 1.2 3.6 0 0.8 −10 +10 −10 +10 16 20 24 4 CMOS/LVDS/LVPECL 1.2 0.2 6 AVDD − AVDD + 0.3 1.6 1.1 AVDD 1.2 3.6 0 0.8 −10 +10 −10 +10 16 20 24 4 0.8 × VDD 0.8 × VDD 0.8 × VDD Full Full 0.2 × AVDD Min AD9211-300 Typ Max Min Full Full Full Full Full Full Full Min AD9211-250 Typ Max Temp Unit V V p-p V V V V μA μA kΩ pF V 0.2 × AVDD 0.2 × AVDD V Full Full Full 0 −60 55 0 −60 55 0 −60 50 μA μA μA Full 0 0 0 μA 25°C 4 4 4 pF Full Full 247 1.125 454 247 454 247 1.375 1.125 1.375 1.125 Twos complement, Gray code, or offset binary (default) 454 1.375 See the AN-835 application note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. LVDS RTERMINATION = 100 Ω. Rev. 0 | Page 5 of 28 mV V AD9211 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted. Table 4. Parameter (Conditions) Maximum Conversion Rate Minimum Conversion Rate CLK+ Pulse Width High (tCH) CLK+ Pulse Width Low (tCL) Output (LVDS − SDR Mode) 1 Data Propagation Delay (tPD) Rise Time (tR) (20% to 80%) Fall Time (tF) (20% to 80%) DCO Propagation Delay (tCPD) Data to DCO Skew (tSKEW) Latency Output (LVDS − DDR Mode) 2 Data Propagation Delay (tPD) Rise Time (tR) (20% to 80%) Fall Time (tF) (20% to 80%) DCO Propagation Delay (tCPD) Data to DCO Skew (tSKEW) Latency Aperture Uncertainty (Jitter, tJ) 1 2 Temp Full Full Full Full Full 25°C 25°C Full Full Full Full 25°C 25°C Full Full Full 25°C Min 200 AD9211-200 Typ Max Min 250 AD9211-250 Typ Max 40 2.25 2.25 −0.3 −0.5 2.5 2.5 3.0 0.2 0.2 3.9 +0.1 7 3.8 0.2 0.2 3.9 +0.1 7 0.2 +0.3 AD921-300 Typ Max 1.7 1.7 Unit MSPS MSPS ns ns 3.0 0.2 0.2 3.9 +0.1 7 ns ns ns ns ns Cycles 40 1.8 1.8 +0.5 Min 300 −0.3 −0.5 See Figure 2. See Figure 3. Rev. 0 | Page 6 of 28 2.0 2.0 3.0 0.2 0.2 3.9 +0.1 7 3.8 0.2 0.2 3.9 +0.1 7 0.2 40 1.5 1.5 +0.5 +0.3 −0.3 −0.5 3.8 0.2 0.2 3.9 +0.1 7 +0.5 +0.3 ns ns ns ns ns Cycles ps rms AD9211 TIMING DIAGRAMS N–1 tA N+4 N+5 N N+3 VIN N+1 tCH tCL N+2 1/fS CLK+ CLK– tCPD DCO+ DCO– tSKEW tPD Dx+ N–6 N–5 N–4 N–3 06041-002 N–7 Dx– Figure 2. Single Data Rate Mode N–1 tA N+4 N+5 N N+3 VIN N+1 tCH tCL N+2 1/fS CLK+ CLK– tCPD DCO+ DCO– tSKEW tPD D0/D5+ D5 N–8 D0 N–7 D5 N–7 D0 N–6 D5 N–6 D0 N–5 D5 N–5 D0 N–4 D5 N–4 D0 N–3 D9 N–8 D4 N–7 D9 N–7 D4 N–6 D9 N–6 D4 N–5 D9 N–5 D4 N–4 D9 N–4 D4 N–3 D4/D9+ D4/D9– 5 MSBs 5 LSBs Figure 3. Double Data Rate Mode Rev. 0 | Page 7 of 28 06041-003 D0/D5– AD9211 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter ELECTRICAL AVDD to AGND DRVDD to DRGND AGND to DRGND AVDD to DRVDD D0+/D0− through D9+/D9− to DRGND DCO to DRGND OR to DGND CLK+ to AGND CLK− to AGND VIN+ to AGND VIN− to AGND SDIO/DCS to DGND PWDN to AGND CSB to AGND SCLK/DFS to AGND ENVIRONMENTAL Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering 10 sec) Junction Temperature Rating −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +0.3 V −2.0 V to +2.0 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to +3.9 V −0.3 V to +3.9 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to DRVDD + 0.3 V −0.3 V to +3.9 V −0.3 V to +3.9 V −0.3 V to +3.9 V −65°C to +125°C −40°C to +85°C 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the customer board increases the reliability of the solder joints, maximizing the thermal capability of the package. Table 6. Package Type 56-Lead LFCSP (CP-56-2) θJA 30.4 θJC 2.9 Unit °C/W Typical θJA and θJC are specified for a 4-layer board in still air. Airflow increases heat dissipation, effectively reducing θJA. In addition, metal in direct contact with the package leads from metal traces, and through holes, ground, and power planes reduces the θJA. ESD CAUTION 150°C Rev. 0 | Page 8 of 28 AD9211 56 55 54 53 52 51 50 49 48 47 46 45 44 43 D0+ (LSB) D0– (LSB) DNC DNC DNC DNC DCO+ DCO– DRGND DRVDD AVDD CLK– CLK+ AVDD PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIN 1 INDICATOR AD9211 TOP VIEW (Not to Scale) PIN 0 (EXPOSED PADDLE) = AGND 42 41 40 39 38 37 36 35 34 33 32 31 30 29 AVDD AVDD CML AVDD AVDD AVDD VIN– VIN+ AVDD AVDD AVDD RBIAS AVDD PWDN DNC = DO NOT CONNECT 06041-004 D7– D7+ D8– D8+ (MSB) D9– (MSB) D9+ OR– OR+ DRGND DRVDD SDIO/DCS SCLK/DFS CSB RESET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 D1– D1+ D2– D2+ D3– D3+ DRVDD DRGND D4– D4+ D5– D5+ D6– D6+ Figure 4. AD9211 Single Data Rate Mode Pin Configuration Table 7. Single Data Rate Mode Pin Function Descriptions Pin No. 30, 32 to 34, 37 to 39, 41 to 43, 46 7, 24, 47 0 8, 23, 48 35 36 40 Mnemonic AVDD Description 1.8 V Analog Supply. DRVDD AGND 1 DRGND1 VIN+ VIN− CML 44 45 31 28 25 CLK+ CLK− RBIAS RESET SDIO/DCS 26 27 29 49 50 51 to 54 55 56 1 2 3 4 5 6 9 10 SCLK/DFS CSB PWDN DCO− DCO+ DNC D0− D0+ D1− D1+ D2− D2+ D3− D3+ D4− D4+ 1.8 V Digital Output Supply. Analog Ground. Digital Output Ground. Analog Input—True. Analog Input—Complement. Common-Mode Output Pin. Enabled through the SPI, this pin provides a reference for the optimized internal bias voltage for VIN+/VIN−. Clock Input—True. Clock Input—Complement. Set Pin for Chip Bias Current. (Place 1% 10 kΩ resistor terminated to ground.) Nominally 0.5 V. CMOS-Compatible Chip Reset (Active Low). Serial Port Interface (SPI) Data Input/Output (Serial Port Mode); Duty Cycle Stabilizer Select (External Pin Mode). Serial Port Interface Clock (Serial Port Mode); Data Format Select Pin (External Pin Mode). Serial Port Chip Select (Active Low). Chip Power-Down. Data Clock Output—Complement. Data Clock Output—True. Do Not Connect. D0 Complement Output Bit (LSB). D0 True Output Bit (LSB). D1 Complement Output Bit. D1 True Output Bit. D2 Complement Output Bit. D2 True Output Bit. D3 Complement Output Bit. D3 True Output Bit. D4 Complement Output Bit. D4 True Output Bit. Rev. 0 | Page 9 of 28 AD9211 Pin No. 11 12 13 14 15 16 17 18 19 20 21 22 1 Mnemonic D5− D5+ D6− D6+ D7− D7+ D8− D8+ D9− D9+ OR− OR+ Description D5 Complement Output Bit. D5 True Output Bit. D6 Complement Output Bit. D6 True Output Bit. D7 Complement Output Bit. D7 True Output Bit. D8 Complement Output Bit. D8 True Output Bit. D9 Complement Output Bit (MSB). D9 True Output Bit (MSB). Overrange Complement Output Bit. Overrange True Output Bit. AGND and DRGND should be tied to a common quiet ground plane. Rev. 0 | Page 10 of 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 D1/D6+ D1/D6– D0/D5+ (LSB) D0/D5– (LSB) DNC DNC DCO+ DCO– DRGND DRVDD AVDD CLK– CLK+ AVDD AD9211 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIN 1 INDICATOR AD9211 TOP VIEW (Not to Scale) PIN 0 (EXPOSED PADDLE) = AGND 42 41 40 39 38 37 36 35 34 33 32 31 30 29 AVDD AVDD CML AVDD AVDD AVDD VIN– VIN+ AVDD AVDD AVDD RBIAS AVDD PWDN DNC = DO NOT CONNECT 06041-005 DNC DNC DNC DNC DNC DNC DNC/(OR–) DNC/(OR+) DRGND DRVDD SDIO/DCS SCLK/DFS CSB RESET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 D2/D7– D2/D7+ D3/D8– D3/D8+ (MSB) D4/D9– (MSB) D4/D9+ DRVDD DRGND OR– OR+ DNC DNC DNC DNC Figure 5. AD9211 Double Data Rate Pin Configuration Table 8. Double Data Rate Mode Pin Function Descriptions Pin No. 30, 32 to 34, 37 to 39, 41 to 43, 46 7, 24, 47 0 8, 23, 48 35 36 40 Mnemonic AVDD Description 1.8 V Analog Supply. DRVDD AGND 1 DRGND1 VIN+ VIN− CML 44 45 31 28 25 CLK+ CLK− RBIAS RESET SDIO/DCS 26 27 29 49 50 53 54 55 56 1 2 3 4 5 6 SCLK/DFS CSB PWDN DCO− DCO+ D0/D5− D0/D5+ D1/D6− D1/D6+ D2/D7− D2/D7+ D3/D8− D3/D8+ D4/D9− D4/D9+ 1.8 V Digital Output Supply. Analog Ground. Digital Output Ground. Analog Input—True. Analog Input—Complement. Common-Mode Output Pin. Enabled through the SPI, this pin provides a reference for the optimized internal bias voltage for VIN+/VIN−. Clock Input—True. Clock Input—Complement. Set Pin for Chip Bias Current. (Place 1% 10 kΩ resistor terminated to ground.) Nominally 0.5 V. CMOS-Compatible Chip Reset (Active Low). Serial Port Interface (SPI) Data Input/Output (Serial Port Mode); Duty Cycle Stabilizer Select (External Pin Mode). Serial Port Interface Clock (Serial Port Mode); Data Format Select Pin (External Pin Mode). Serial Port Chip Select (Active Low). Chip Power-Down. Data Clock Output—Complement. Data Clock Output—True. D1/D7 Complement Output Bit (LSB). D1/D7 True Output Bit (LSB). D2/D8 Complement Output Bit. D2/D8 True Output Bit. D3/D9 Complement Output Bit. D3/D9 True Output Bit. D4/D10 Complement Output Bit. D4/D10 True Output Bit. D5/D11 Complement Output Bit (MSB). D5/D11 True Output Bit (MSB). Rev. 0 | Page 11 of 28 AD9211 Pin No. 9 10 11 to 20, 51, 52 21 Mnemonic OR− OR+ DNC DNC/(OR−) 22 DNC/(OR+) 1 Description D6 Complement Output Bit. (This pin is disabled if Pin 21 is reconfigured through the SPI to be OR−.) D6 True Output Bit. (This pin is disabled if Pin 22 is reconfigured through the SPI to be OR+.) Do Not Connect. Do Not Connect. (This pin can be reconfigured as the Overrange Complement Output Bit through the serial port register.) Do Not Connect. (This pin can be reconfigured as the Overrange True Output Bit through the serial port register.) AGND and DRGND should be tied to a common quiet ground plane. Rev. 0 | Page 12 of 28 AD9211 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DRVDD = 1.8 V, rated sample rate, DCS enabled, TA = 25°C, 1.25 V p-p differential input, AIN = −1 dBFS, unless otherwise noted. 95 0 200MSPS 10.3MHz @ –1.0dBFS SNR: 59.5dB ENOB: 9.8BITS SFDR: 85dBc 90 85 SNR AND SFDR (dB) –20 (dBFS) –40 –60 –80 80 SFDR 75 70 65 SNR (dB) –100 0 25 50 75 55 100 06041-016 06041-012 –120 60 0 20 40 60 Figure 6. AD9211-200 64k Point Single-Tone FFT; 200 MSPS, 10.3 MHz 100 120 140 160 180 Figure 9. AD9211-200 Single-Tone SNR/SFDR vs. Input Frequency (fIN) with 1.25 V p-p Full Scale; 200 MSPS 0 90 200MSPS 70.3MHz @ –1.0dBFS SNR: 59.3dB ENOB: 9.7BITS SFDR: –77dBc SFDR (dBFS) 80 70 SNR AND SFDR (dB) –20 –40 (dBFS) 80 FREQUENCY (MHz) FREQUENCY (MHz) –60 –80 60 SNR (dBFS) 50 40 30 SNR (dB) SFDR (dB) 20 –100 0 25 50 75 0 –90 100 06041-017 06041-013 –120 10 –80 –70 Figure 7. AD9211-200 64k Point Single-Tone FFT; 200 MSPS, 70.3 MHz –40 –30 –20 –10 0 0.25 200MSPS 170.3MHz @ –1.0dBFS SNR: 59.0dB ENOB: 9.6BITS SFDR: 77dBc –20 0.20 0.15 0.10 DBL (LSB) –40 –60 –80 0.05 0 –0.05 –0.10 –0.15 06041-014 –100 0 25 50 75 06041-018 (dBFS) –50 Figure 10. AD9211-200 SNR/SFDR vs. Input Amplitude; 170.3 MHz 0 –120 –60 AMPLITUDE (dBFS) FREQUENCY (MHz) –0.20 –0.25 100 FREQUENCY (MHz) 0 256 512 768 OUTPUT CODE Figure 8. AD9211-200 64k Point Single-Tone FFT; 200 MSPS, 170.3 MHz Rev. 0 | Page 13 of 28 Figure 11. AD9211-200 INL; 200 MSPS 1024 AD9211 0.5 0 250MSPS 170.3MHz @ –1.0dBFS SNR: 59.0dB ENOB: 9.7BITS SFDR: –79dBc 0.4 –20 0.3 –40 0.1 (dBFS) 0 –60 –0.1 –80 –0.2 –0.3 06041-021 –100 –0.4 –0.5 0 256 512 –120 1024 768 06041-025 DBL (LSB) 0.2 0 31.25 62.50 Figure 12. AD9211-200 DNL; 200 MSPS Figure 15. AD9211-250 64k Point Single-Tone FFT; 250 MSPS, 170.3 MHz 95 0 250MSPS 10.3MHz @ –1.0dBFS SNR: 59.4dB ENOB: 9.7BITS SFDR: 86dBc 90 85 SNR AND SFDR (dB) –20 –40 (dBFS) 125.00 93.75 FREQUENCY (MHz) OUTPUT CODE –60 –80 SFDR 80 75 70 65 –100 0 31.25 62.50 93.75 55 125.00 06041-027 06041-023 –120 SNR (dB) 60 0 20 40 60 Figure 13. AD9211-250 64k Point Single-Tone FFT; 250 MSPS, 10.3 MHz 120 140 160 180 100 250MSPS 70.3MHz @ –1.0dBFS SNR: 59.2dB ENOB: 9.7BITS SFDR: 80dBc 90 SFDR (dBFS) 80 SNR AND SFDR (dB) –20 –40 –60 –80 70 60 SNR (dBFS) 50 40 30 SFDR (dB) SNR (dB) 20 06041-024 –100 0 31.25 62.50 93.75 06041-028 (dBFS) 100 Figure 16. AD9211-250 Single-Tone SNR/SFDR vs. Input Frequency (fIN) with 1.25 V p-p Full Scale; 250 MSPS 0 –120 80 FREQUENCY (MHz) FREQUENCY (MHz) 10 0 –90 125.00 FREQUENCY (MHz) –80 –70 –60 –50 –40 –30 –20 –10 0 AMPLITUDE (dBFS) Figure 14. AD9211-250 64k Point Single-Tone FFT; 250 MSPS, 70.3 MHz Figure 17. AD9211-250 SNR/SFDR vs. Input Amplitude; 250 MSPS, 170.3 MHz Rev. 0 | Page 14 of 28 AD9211 0.25 0 300MSPS 70.3MHz @ –1.0dBFS SNR: 59.1dB ENOB: 9.7BITS SFDR: 80dBc 0.20 –20 0.15 –40 0.05 (dBFS) 0 –60 –0.05 –80 –0.10 –0.15 06041-029 –100 –0.20 –0.25 0 256 512 –120 1024 768 06041-035 DBL (LSB) 0.10 0 25 50 Figure 18. AD9211-250 INL; 250 MSPS 150 125 0 300MSPS 170.3MHz @ –1.0dBFS SNR: 58.7dB ENOB: 9.7BITS SFDR: 80dBc 0.4 –20 0.3 0.2 –40 0.1 (dBFS) 0 –60 –0.1 –80 –0.2 –0.3 06041-032 –100 –0.4 –0.5 0 256 512 –120 1024 768 06041-036 DBL (LSB) 100 Figure 21. AD9211-300 64k Point Single-Tone FFT; 300 MSPS, 70.3 MHz 0.5 0 25 50 75 100 150 125 FREQUENCY (MHz) OUTPUT CODE Figure 19. AD9211-250 DNL; 250 MSPS Figure 22. AD9211-300 64k Point Single-Tone FFT; 300 MSPS, 170.3 MHz 0 95 300MSPS 10.3MHz @ –1.0dBFS SNR: 59.2dB ENOB: 9.7BITS SFDR: 80dBc 90 85 SNR AND SFDR (dB) –20 –40 (dBFS) 75 FREQUENCY (MHz) OUTPUT CODE –60 –80 SFDR 80 75 70 65 –100 0 25 50 75 100 125 55 150 06041-038 06041-034 –120 SNR (dB) 60 0 20 40 60 80 100 120 140 160 180 FREQUENCY (MHz) FREQUENCY (MHz) Figure 20. AD9211-300 64k Point Single-Tone FFT; 300 MSPS, 10.3 MHz Figure 23. AD9211-300 Single-Tone SNR/SFDR vs. Input Frequency (fIN) with 1.25 V p-p Full Scale; 300 MSPS Rev. 0 | Page 15 of 28 AD9211 90 0.25 0.20 SFDR (dBFS) 80 0.15 0.10 60 SNR (dBFS) 0.05 DBL (LSB) 50 40 SFDR (dB) 0 –0.05 30 –0.10 SNR (dB) 20 –0.15 0 –90 06041-039 10 –80 –70 –60 –50 –40 –30 –20 –10 06041-043 SNR AND SFDR (dB) 70 –0.20 –0.25 0 0 256 512 AMPLITUDE (dBFS) Figure 24. AD9211-300 SNR/SFDR vs. Input Amplitude; 300 MSPS, 170.3 MHz Figure 27. AD9211-300 DNL; 300 MSPS 0.25 100 0.20 90 0.15 80 0.10 70 0.05 60 SFDR (dB) DBL (LSB) 1024 768 OUTPUT CODE 0 –0.05 SFDR (dBFS) 50 40 –0.15 20 06041-040 30 –0.20 –0.25 0 256 512 10 0 –80 1024 768 06041-044 SFDR (dBc) –0.10 –70 –60 –50 –40 –30 –20 –10 0 AMPLITUDE (dBFS) OUTPUT CODE Figure 25. AD9211-300 INL; 300 MSPS Figure 28. AD9211-300 Two-Tone SFDR vs. Input Amplitude; 300 MSPS, 170.1 MHz, 171.1 MHz 0 0 –20 –40 –40 –60 –60 –80 –80 –100 –100 –120 0 20 40 60 80 100 120 –120 140 FREQUENCY (MHz) 06041-045 (dBFS) –20 06041-041 (dBFS) 245.76MSPS 190.1MHz 0 30.72 61.44 92.16 122.88 FREQUENCY (MHz) Figure 26. AD9211-300 64k Point, Two-Tone FFT; 300 MSPS, 170.1 MHz, 171.1 MHz Figure 29. AD9211-300 64k Point FFT; Three W-CDMA Carriers, IF = 190.1 MHz, 245.6 MSPS Rev. 0 | Page 16 of 28 AD9211 85 2.5 80 2.0 SFDR (dBc) GAIN (%FS) 1.5 70 65 1.0 0.5 60 SNR (dB) 50 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 –0.5 –60 1.8 06041-050 0 55 06041-046 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) VCM (V) Figure 31. Gain vs. Temperature Figure 30. SNR/SFDR vs. Common-Mode Voltage; 300 MSPS, 70.3 MHz @ −1 dBFS 6.0 5.5 5.0 OFFSET (mV) 4.5 4.0 3.5 3.0 2.5 2.0 –40 –30 –20 –10 06041-051 SNR/SFDR (dB) 75 0 10 20 30 40 50 TEMPERATURE (°C) Figure 32. Offset vs. Temperature Rev. 0 | Page 17 of 28 60 70 80 90 AD9211 EQUIVALENT CIRCUITS AVDD AVDD 26kΩ CSB 1.2V 10kΩ CLK– 06041-006 06041-064 10kΩ CLK+ 1kΩ Figure 36. Equivalent CSB Input Circuit Figure 33. Clock Inputs AVDD DRVDD VIN+ BUF AVDD 2kΩ AVDD VCML ~1.4V V+ 2kΩ V– DATAOUT– DATAOUT+ V– V+ 06041-009 BUF 06041-007 VIN– BUF Figure 37. LVDS Outputs (Dx+, Dx−, OR+, OR−, DCO+, DCO−) Figure 34. Analog Inputs (VCML = ~1.4 V) DRVDD SCLK/DFS RESET PWDN 1kΩ 30kΩ 1kΩ 06041-065 06041-008 SDIO/DCS Figure 38. Equivalent SDIO/DCS Input Circuit Figure 35. Equivalent SCLK/DFS, RESET, PWDN Input Circuit Rev. 0 | Page 18 of 28 AD9211 THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE The analog input to the AD9211 is a differential buffer. For best dynamic performance, the source impedances driving VIN+ and VIN− should be matched such that common-mode settling errors are symmetrical. The analog input is optimized to provide superior wideband performance and requires that the analog inputs be driven differentially. SNR and SINAD performance degrades significantly if the analog input is driven with a singleended signal. A wideband transformer, such as Mini-Circuits® ADT1-1WT, can provide the differential analog inputs for applications that require a single-ended-to-differential conversion. Both analog inputs are self-biased by an on-chip resistor divider to a nominal 1.3 V. An internal differential voltage reference creates positive and negative reference voltages that define the 1.25 V p-p fixed span of the ADC core. This internal voltage reference can be adjusted by means of SPI control. See the AD9211 Configuration Using the SPI section for more details. 49.9Ω 499Ω AD8138 523Ω AD9211 20pF 0.1µF VIN– 33Ω CML 499Ω Figure 39. Differential Input Configuration Using the AD8138 At input frequencies in the second Nyquist zone and above, the performance of most amplifiers may not be adequate to achieve the true performance of the AD9211. This is especially true in IF undersampling applications where frequencies in the 70 MHz to 100 MHz range are being sampled. For these applications, differential transformer coupling is the recommended input configuration. The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few MHz, and excessive signal power can also cause core saturation, which leads to distortion. In any configuration, the value of the shunt capacitor, C, is dependent on the input frequency and may need to be reduced or removed. 15Ω 1.25V p-p 50Ω 2pF VIN+ AD9211 VIN– 15Ω 0.1µF Figure 40. Differential Transformer—Coupled Configuration As an alternative to using a transformer-coupled input at frequencies in the second Nyquist zone, the AD8352 differential driver can be used (see Figure 41). VCC 0.1µF 0.1µF 0Ω 16 1 ANALOG INPUT 8, 13 11 0.1µF R 2 VIN+ 200Ω Differential Input Configurations CD RD AD8352 RG 3 Optimum performance is achieved while driving the AD9211 in a differential input configuration. For baseband applications, the AD8138 differential driver provides excellent performance and a flexible interface to the ADC. The output common-mode AVDD VIN+ 33Ω 499Ω 0.1µF 200Ω C R 4 ANALOG INPUT Rev. 0 | Page 19 of 28 10 5 0.1µF 0Ω AD9211 VIN– CML 14 0.1µF 0.1µF Figure 41. Differential Input Configuration Using the AD8352 06041-066 The input stage contains a differential SHA that can be ac- or dc-coupled in differential or single-ended mode. The outputstaging block aligns the data, carries out the error correction, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. During power-down, the output buffers go into a high impedance state. 1V p-p 06041-055 Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. voltage of the AD8138 is easily set to AVDD/2 + 0.5 V, and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. 06041-056 The AD9211 architecture consists of a front-end sample and hold amplifier (SHA) followed by a pipelined switched capacitor ADC. The quantized outputs from each stage are combined into a final 10-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample, while the remaining stages operate on preceding samples. Sampling occurs on the rising edge of the clock. AD9211 For optimum performance, the AD9211 sample clock inputs (CLK+ and CLK−) should be clocked with a differential signal. This signal is typically ac-coupled into the CLK+ pin and CLK− pin via a transformer or capacitors. These pins are biased internally and require no additional bias. Figure 42 shows one preferred method for clocking the AD9211. The low jitter clock source is converted from single-ended to differential using an RF transformer. The back-to-back Schottky diodes across the secondary transformer limit clock excursions into the AD9211 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9211 and preserves the fast rise and fall times of the signal, which are critical to low jitter performance. MINI-CIRCUITS ADT1–1WT, 1:1Z 0.1µF XFMR 50Ω CLOCK INPUT AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515 0.1µF CLK 50Ω* CMOS DRIVER 0.1µF CLK– 0.1µF Figure 45. Single-Ended 1.8 V CMOS Sample Clock ADC AD9211 06041-059 SCHOTTKY DIODES: HSM2812 CLOCK INPUT AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515 If a low jitter clock is available, another option is to ac couple a differential PECL signal to the sample clock input pins, as shown in Figure 43. The AD9510/AD9511/AD9512/AD9513/ AD9514/AD9515 family of clock drivers offers excellent jitter performance. 100Ω 0.1µF PECL DRIVER AD9211 CLK– 06041-060 240Ω Figure 43. Differential PECL Sample Clock 0.1µF CLK+ CLK 100Ω 0.1µF CLK ADC AD9211 CLK– 50Ω* *50Ω RESISTORS ARE OPTIONAL. Figure 44. Differential LVDS Sample Clock 06041-067 CLOCK INPUT 50Ω* AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515 LVDS DRIVER ADC 0.1µF AD9211 CLK– Figure 46. Single-Ended 3.3 V CMOS Sample Clock ADC *50Ω RESISTORS ARE OPTIONAL. 0.1µF CLK+ *50Ω RESISTOR IS OPTIONAL. CLK+ CLK 0.1µF OPTIONAL 0.1µF 100Ω CLK 0.1µF CLK CLOCK INPUT CMOS DRIVER Clock Duty Cycle Considerations 0.1µF 240Ω CLK 0.1µF AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515 50Ω* 0.1µF 50Ω* Figure 42. Transformer-Coupled Differential Clock 50Ω* 39kΩ CLK+ 0.1µF 0.1µF CLOCK INPUT ADC *50Ω RESISTOR IS OPTIONAL. 100Ω 0.1µF CLK+ AD9211 CLK CLK– CLOCK INPUT OPTIONAL 0.1µF 100Ω 06041-069 0.1µF CLOCK INPUT In some applications, it is acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applications, CLK+ should be directly driven from a CMOS gate, and the CLK− pin should be bypassed to ground with a 0.1 μF capacitor in parallel with a 39 kΩ resistor (see Figure 45). Although the CLK+ input circuit supply is AVDD (1.8 V), this input is designed to withstand input voltages up to 3.3 V, making the selection of the drive logic voltage very flexible. 06041-068 CLOCK INPUT CONSIDERATIONS Typical high speed ADCs use both clock edges to generate a variety of internal timing signals. As a result, these ADCs may be sensitive to clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9211 contains a duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9211. When the DCS is on, noise and distortion performance are nearly flat for a wide range of duty cycles. However, some applications may require the DCS function to be off. If so, keep in mind that the dynamic range performance can be affected when operated in this mode. See the AD9211 Configuration Using the SPI section for more details on using this feature. The duty cycle stabilizer uses a delay-locked loop (DLL) to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately eight clock cycles to allow the DLL to acquire and lock to the new rate. Rev. 0 | Page 20 of 28 AD9211 Clock Jitter Considerations DIGITAL OUTPUTS High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fA) due only to aperture jitter (tJ) can be calculated by Digital Outputs and Timing SNR Degradation = 20 × log10[½ × π × fA × tJ] In this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter specifications. IF undersampling applications are particularly sensitive to jitter (see Figure 47). The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9211. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. Refer to the AN-501 application note and the AN-756 application note for more in-depth information about jitter performance as it relates to ADCs (visit www.analog.com). RMS CLOCK JITTER REQUIREMENT 120 90 14 BITS 80 An example of the LVDS output using the ANSI standard (default) data eye and a time interval error (TIE) jitter histogram with trace lengths less than 24 inches on regular FR-4 material is shown in Figure 48. Figure 49 shows an example of when the trace lengths exceed 24 inches on regular FR-4 material. Notice that the TIE jitter histogram reflects the decrease of the data eye opening as the edge deviates from the ideal position. It is up to the user to determine if the waveforms meet the timing budget of the design when the trace lengths exceed 24 inches. 12 BITS 70 10 BITS 60 8 BITS 50 40 30 1 0.125ps 0.25ps 0.5ps 1.0ps 2.0ps 10 100 ANALOG INPUT FREQUENCY (MHz) 1000 14 Figure 47. Ideal SNR vs. Input Frequency and Jitter POWER DISSIPATION AND POWER-DOWN MODE The power dissipated by the AD9211 is proportional to its sample rate. The digital power dissipation does not vary much because it is determined primarily by the DRVDD supply and bias current of the LVDS output drivers. By asserting PWDN (Pin 29) high, the AD9211 is placed in standby mode or full power-down mode, as determined by the contents of Serial Port Register 08. Reasserting the PWDN pin low returns the AD9211 to its normal operational mode. An additional standby mode is supported by means of varying the clock input. When the clock rate falls below 20 MHz, the AD9211 assumes a standby state. In this case, the biasing network and internal reference remain on, but digital circuitry is powered down. Upon reactivating the clock, the AD9211 resumes normal operation after allowing for the pipeline latency. 500 12 400 300 200 100 0 –100 –200 –300 –400 10 8 6 4 2 –500 –3 –2 –1 0 1 TIME (ns) 2 3 0 –40 –20 0 TIME (ps) 20 40 06041-070 16 BITS TIE JITTER HISTOGRAM (Hits) 100 06041-061 SNR (dB) 110 The AD9211 LVDS outputs facilitate interfacing with LVDS receivers in custom ASICs and FPGAs that have LVDS capability for superior switching performance in noisy environments. Single point-to-point net topologies are recommended with a 100 Ω termination resistor placed as close to the receiver as possible. No far-end receiver termination and poor differential trace routing may result in timing errors. It is recommended that the trace length is no longer than 24 inches and that the differential output traces are kept close together and at equal lengths. EYE DIAGRAM: VOLTAGE (mV) 130 The AD9211 differential outputs conform to the ANSI-644 LVDS standard on default power-up. This can be changed to a low power, reduced signal option similar to the IEEE 1596.3 standard using the SPI. This LVDS standard can further reduce the overall power dissipation of the device, which reduces the power by ~39 mW. See the Memory Map section for more information. The LVDS driver current is derived on-chip and sets the output current at each output equal to a nominal 3.5 mA. A 100 Ω differential termination resistor placed at the LVDS receiver inputs results in a nominal 350 mV swing at the receiver. Figure 48. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths Less than 24 Inches on Standard FR-4, AD9211-250 Rev. 0 | Page 21 of 28 600 12 400 10 200 0 –200 OR DATA OUTPUTS 1 1111 1111 1111 0 1111 1111 1111 0 1111 1111 1110 +FS – 1 LSB OR –FS + 1/2 LSB 8 0 0 1 0000 0000 0001 0000 0000 0000 0000 0000 0000 6 –FS –FS – 1/2 LSB 4 +FS +FS – 1/2 LSB 06041-062 TIE JITTER HISTOGRAM (Hits) Figure 50. OR Relation to Input Voltage and Output Data –400 2 TIMING –600 –3 0 –100 The AD9211 provides latched data outputs with a pipeline delay of seven clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of the clock signal. –2 –1 0 1 TIME (ns) 2 3 0 06041-071 EYE DIAGRAM: VOLTAGE (mV) AD9211 100 TIME (ps) Figure 49. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths Greater than 24 Inches on Standard FR-4, AD9211-250 The format of the output data is offset binary by default. An example of the output coding format can be found in Table 12. If it is desired to change the output data format to twos complement, see the AD9211 Configuration Using the SPI section. An output clock signal is provided to assist in capturing data from the AD9211. The DCO is used to clock the output data and is equal to the sampling clock (CLK) rate. In single data rate mode (SDR), data is clocked out of the AD9211 and must be captured on the rising edge of the DCO. In double data rate mode (DDR), data is clocked out of the AD9211 and must be captured on the rising and falling edges of the DCO. See the timing diagrams shown in Figure 2 and Figure 3 for more information. Output Data Rate and Pinout Configuration The output data of the AD9211 can be configured to drive 10 pairs of LVDS outputs at the same rate as the input clock signal (single data rate, or SDR, mode), or five pairs of LVDS outputs at 2× the rate of the input clock signal (double data rate, or DDR, mode). SDR is the default mode; the device may be reconfigured for DDR by setting Bit 3 in Register 14 (see Table 13). Out-of-Range (OR) An out-of-range condition exists when the analog input voltage is beyond the input range of the ADC. OR is a digital output that is updated along with the data output corresponding to the particular sampled input voltage. Thus, OR has the same pipeline latency as the digital data. OR is low when the analog input voltage is within the analog input range and high when the analog input voltage exceeds the input range, as shown in Figure 50. OR remains high until the analog input returns to within the input range and another conversion is completed. By logically ANDing OR with the MSB and its complement, overrange high or underrange low conditions can be detected. The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9211. These transients can degrade the converter’s dynamic performance. The AD9211 also provides data clock output (DCO) intended for capturing the data in an external register. The data outputs are valid on the rising edge of DCO. The lowest typical conversion rate of the AD9211 is 40 MSPS. At clock rates below 1 MSPS, the AD9211 assumes the standby mode. RBIAS The AD9211 requires the user to place a 10 kΩ resistor between the RBIAS pin and ground. This resister should have a 1% tolerance and is used to set the master current reference of the ADC core. AD9211 CONFIGURATION USING THE SPI The AD9211 SPI allows the user to configure the converter for specific functions or operations through a structured register space inside the ADC. This gives the user added flexibility to customize device operation depending on the application. Addresses are accessed (programmed or readback) serially in one-byte words. Each byte may be further divided down into fields, which are documented in the Memory Map section. There are three pins that define the serial port interface or SPI to this particular ADC. They are the SPI SCLK/DFS, SPI SDIO/DCS, and CSB pins. The SCLK/DFS (serial clock) is used to synchronize the read and write data presented the ADC. The SDIO/DCS (serial data input/output) is a dual-purpose pin that allows data to be sent and read from the internal ADC memory map registers. The CSB is an active low control that enables or disables the read and write cycles (see Table 9). Rev. 0 | Page 22 of 28 AD9211 Table 9. Serial Port Pins HARDWARE INTERFACE Mnemonic SCLK The pins described in Table 9 comprise the physical interface between the user’s programming device and the serial port of the AD9211. All serial pins are inputs with an open-drain configuration and should be tied to an external pull-up or pulldown resistor (suggested value of 10 kΩ). SDIO CSB RESET Function SCLK (Serial Clock) is the serial shift clock in. SCLK is used to synchronize serial interface reads and writes. SDIO (Serial Data Input/Output) is a dual-purpose pin. The typical role for this pin is an input and output depending on the instruction being sent and the relative position in the timing frame. CSB (Chip Select Bar) is an active low control that gates the read and write cycles. Master Device Reset. When asserted, device assumes default settings. Active low. This interface is flexible enough to be controlled by either PROMS or PIC mirocontrollers as well. This provides the user with an alternate method to program the ADC other than a SPI controller. If the user chooses not to use the SPI interface, some pins serve a dual function and are associated with a specific function when strapped externally to AVDD or ground during device power on. The Configuration Without the SPI section describes the strappable functions supported on the AD9230. The falling edge of the CSB, in conjunction with the rising edge of the SCLK, determines the start of the framing. An example of the serial timing and its definitions can be found in Figure 51 and Table 11. CONFIGURATION WITHOUT THE SPI During an instruction phase, a 16-bit instruction is transmitted. Data then follows the instruction phase and is determined by the W0 and W1 bits, which is 1 or more bytes of data. All data is composed of 8-bit words. The first bit of each individual byte of serial data indicates whether this is a read or write command. This allows the serial data input/output (SDIO) pin to change direction from an input to an output. In applications that do not interface to the SPI control registers, the SPI SDIO/DCS and SPI SCLK/DFS pins can alternately serve as standalone CMOS-compatible control pins. When the device is powered up, it is assumed that the user intends to use the pins as static control lines for the duty cycle stabilizer. In this mode, the SPI CSB chip select should be connected to ground, which disables the serial port interface. Data may be sent in MSB or in LSB first mode. MSB first is default on power-up and can be changed by changing the configuration register. For more information about this feature and others, see the AN-877, Interfacing to High Speed ADCs via SPI. Table 10. Mode Selection Mnemonic SPI SDIO/DCS SPI SCLK/DFS tDS tS tHI External Voltage AVDD AGND AVDD AGND Configuration Duty cycle stabilizer enabled Duty cycle stabilizer disabled Twos complement enabled Offset binary enabled tCLK tDH tH tLO CSB SDIO DON’T CARE DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 Figure 51. Serial Port Interface Timing Diagram Rev. 0 | Page 23 of 28 D4 D3 D2 D1 D0 DON’T CARE 06041-063 SCLK DON’T CARE AD9211 Table 11. Serial Timing Definitions Parameter tDS tDH tCLK tS tH tHI tLO tEN_SDIO Timing (minimum, ns) 5 2 40 5 2 16 16 1 tDIS_SDIO 5 Description Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the clock Setup time between CSB and SCLK Hold time between CSB and SCLK Minimum period that SCLK should be in a logic high state Minimum period that SCLK should be in a logic low state Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 51) Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 51) Table 12. Output Data Format Input (V) VIN+ − VIN− VIN+ − VIN− VIN+ − VIN− VIN+ − VIN− VIN+ − VIN− Condition (V) < 0.62 = 0.62 =0 = 0.62 > 0.62 + 0.5 LSB Offset Binary Output Mode D11 to D0 0000 0000 00 0000 0000 00 0000 0000 00 1111 1111 11 1111 1111 11 Twos Complement Mode D11 to D0 0000 0000 00 0000 0000 00 0000 0000 00 1111 1111 11 1111 1111 11 Rev. 0 | Page 24 of 28 Gray Code Mode (SPI Accessible) D11 to D0 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 00 OR 1 0 0 0 1 AD9211 MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS Each row in the memory map table has eight address locations. The memory map is roughly divided into three sections: chip configuration register map (Address 0x00 to Address 0x02), transfer register map (Address 0xFF), and program register map (Address 0x08 to Address 0x2A). Undefined memory locations should not be written to other than their default values suggested in this data sheet. Addresses that have values marked as 0 should be considered reserved and have a 0 written into their registers during power-up. The Addr. (Hex) column of the memory map indicates the register address in hexadecimal, and the Default Value (Hex) column shows the default hexadecimal value that is already written into the register. The Bit 7 (MSB) column is the start of the default hexadecimal value given. For example, Hexadecimal Address 0x09, clock, has a hexadecimal default value of 0x01. This means Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in binary. The default value enables the duty cycle stabilizer. Overwriting this default so that Bit 0 = 0 disables the duty cycle stabilizer. For more information on this and other functions, consult the AN-877 application note, Interfacing to High Speed ADCs via SPI. Coming out of reset, critical registers are preloaded with default values. These values are indicated in Table 13. Other registers do not have default values and retain the previous value when exiting reset. DEFAULT VALUES LOGIC LEVELS An explanation of various registers follows: “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” Similarly, “clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit.” Table 13. Memory Map Register Addr. Bit 7 (Hex) Parameter Name (MSB) Chip Configuration Registers 00 chip_port_config 0 01 chip_id 02 chip_grade Transfer Register FF device_update Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) LSB first Soft reset 1 1 Soft reset LSB first 0 8-bit chip ID, Bits[7:0] AD9211 = 0x06 0 0 0 0 0 0 Speed grade: 00 = 300 MSPS 01 = 250 MSPS 10 = 200 MSPS 0 0 Rev. 0 | Page 25 of 28 Default Value (Hex) 0x18 Readonly X X X Readonly 0 0 SW transfer 0x00 Default Notes/ Comments The nibbles should be mirrored by the user so that LSB or MSB first mode registers correctly, regardless of shift mode. Default is unique chip ID, different for each device. This is a readonly register. Child ID used to differentiate graded devices. Synchronously transfers data from the master shift register to the slave. AD9211 Addr. (Hex) Parameter Name ADC Functions 08 modes Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 0 0 PWDN: 0 = full (default) 1= standby 0 0 09 clock 0 0 0 0 OD test_io Reset PN23 gen: 1 = on 0 = off (default) Reset PN9 gen: 1 = on 0 = off (default) OF ain_config 0 0 0 14 output_mode 0 0 Output enable: 0= enable (default) 1= disable 15 output_adjust 0 0 16 output_phase Output clock polarity 1= inverted 0= normal (default) 0 0 Bit 1 Internal power-down mode: 000 = normal (power-up, default) 001 = full power-down 010 = standby 011 = normal (power-up) Note: External PWDN pin overrides this setting. 0 0 0 Duty cycle stabilizer: 0= disabled 1= enabled (default) Output test mode: 0000 = off (default) 0001 = midscale short 0010 = +FS short 0011 = −FS short 0100 = checker board output 0101 = PN 23 sequence 0110 = PN 9 0111 = one/zero word toggle 1000 = unused 1001 = unused 1010 = unused 1011 = unused 1100 = unused (Format determined by output_mode) CML 0 0 Analog enable: input disable: 1 = on 1 = on 0 = off 0 = off (default) (default) Data format select: Output DDR: 00 = offset binary invert: 1= (default) 1 = on enabled 01 = twos 0 = off 0= complement disabled (default) 10 = Gray code (default) LVDS course adjust: 0= 3.5 mA (default) 1= 2.0 mA 0 Bit 2 Bit 0 (LSB) 0 LVDS fine adjust: 001 = 3.50 mA 010 = 3.25 mA 011 = 3.00 mA 100 = 2.75 mA 101 = 2.50 mA 110 = 2.25 mA 111 = 2.00 mA Default Value (Hex) 0x00 Determines various generic modes of chip operation. 0x01 0x00 When set, the test data is placed on the output pins in place of normal data. 0x00 0x00 0 0x00 0 0x03 Rev. 0 | Page 26 of 28 Default Notes/ Comments AD9211 Addr. (Hex) 17 Parameter Name flex_output_delay 18 flex_vref 2A ovr_config Bit 7 (MSB) Output delay enable: 0= enable 1= disable Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Output clock delay: 00000 = 0.1 ns 00001 = 0.2 ns 00010 = 0.3 ns … 11101 = 3.0 ns 11110 = 3.1 ns 11111 = 3.2 ns Input voltage range setting: 10000 = 0.98 V 10001 = 1.00 V 10010 = 1.02 V 10011 = 1.04 V … 11111 = 1.23 V 00000 = 1.25 V 00001 = 1.27 V … 01110 = 1.48 V 01111 = 1.50 V OR position (DDR mode only): 0 = Pin 9, Pin 10 1= Pin 21, Pin 22 Rev. 0 | Page 27 of 28 Bit 0 (LSB) Default Value (Hex) 0 Default Notes/ Comments 0 OR enable: 1 = on (default) 0 = off 00000001 AD9211 OUTLINE DIMENSIONS 8.00 BSC SQ 0.60 MAX 14 29 28 15 0.30 MIN 6.50 REF 0.80 MAX 0.65 TYP 0.50 BSC PIN 1 INDICATOR 4.45 4.30 SQ 4.15 EXPOSED PAD (BOTTOM VIEW) 7.75 BSC SQ 0.50 0.40 0.30 SEATING PLANE 1 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-VLLD-2 112805-0 TOP VIEW 12° MAX 56 43 42 PIN 1 INDICATOR 1.00 0.85 0.80 0.30 0.23 0.18 0.60 MAX Figure 52. 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 8 mm × 8 mm Body, Very Thin Quad (CP-56-2) Dimensions shown in millimeters ORDERING GUIDE Model AD9211BCPZ-200 1 AD9211BCPZ-2501 AD9211BCPZ-3001 AD9211-200EBZ1 AD9211-250EBZ1 AD9211-300EBZ1 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] LVDS Evaluation Board with AD9211BCPZ-200 LVDS Evaluation Board with AD9211BCPZ-250 LVDS Evaluation Board with AD9211BCPZ-300 Z = RoHS Compliant Part. ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06041-0-5/07(0) Rev. 0 | Page 28 of 28 Package Option CP-56-2 CP-56-2 CP-56-2