UT54ACS132E*

UT54ACS132E
Quadruple 2-Input NAND Schmitt Triggers
October 2008
www.aeroflex.com/Logic
FUNCTION TABLE
FEATURES
• 0.6μm CRH CMOS Process
- Latchup immune
• High speed
• Low power consumption
• Wide operating power supply from 3.0V to 5.5V
• Available QML Q or V processes
• 14-lead flatpack
INPUTS
OUTPUT
An
Bn
Yn
L
L
H
L
H
H
H
L
H
H
H
L
PINOUT
DESCRIPTION
14-Lead Flatpack
Top View
The UT54ACS132 is a quadruple 2-input NAND gate with
Schmitt Trigger input levels. A high applied on both the inputs
forces the output to a low state.
A1
B1
The devices are characterized over full HiRel temperature range
of -55°C to +125°C.
Y1
A2
B2
Y2
VSS
LOGIC SYMBOL
A1
B1
A2
B2
A3
B3
A4
B4
(1)
(2)
&
(3)
1
14
2
13
3
12
4
11
5
10
Y4
B3
6
9
A3
7
8
VDD
B4
A4
Y3
Y1
(4)
(5)
(9)
(6)
(8)
(10)
(12)
(13)
(11)
Y2
LOGIC DIAGRAM
Y3
A1
B1
Y4
A2
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984
and IEC Publication 617-12.
B2
Y1
Y2
A3
B3
Y3
A4
B4
1
Y4
OPERATIONAL ENVIRONMENT1
PARAMETER
LIMIT
UNITS
Total Dose
1.0E6
rads(Si)
SEU Threshold 2
80
MeV-cm2/mg
SEL Threshold
120
MeV-cm2/mg
Neutron Fluence
1.0E14
n/cm2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
LIMIT
UNITS
VDD
Supply voltage
-0.3 to 7.0
V
VI/O
Voltage any pin
-.3 to VDD + .3
V
TSTG
Storage Temperature range
-65 to +150
°C
TJ
Maximum junction temperature
+175
°C
TLS
Lead temperature (soldering 5 seconds)
+300
°C
ΘJC
Thermal resistance junction to case
20
°C/W
II
DC input current
±10
mA
PD
Maximum power dissipation
1
W
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these
or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMIT
UNITS
VDD
Supply voltage
3.0 to 5.5
V
VIN
Input voltage any pin
0 to VDD
V
TC
Temperature range
-55 to +125
°C
2
DC ELECTRICAL CHARACTERISTICS FOR THE UT54ACS132E7
( VDD = 3.0V to 5.5V; VSS = 0V6; -55°C < TC < +125°C)
SYMBOL
VT+
VT-
VH
IIN
VOL
VOH
IOS
IOL
IOH
Ptotal
Description
CONDITION
VDD
MIN
MAX
UNIT
V
Schmitt trigger positive-going
threshold 1
3.0V
2.1
5.5V
3.85
Schmitt trigger negative-going
threshold 1
3.0V
0.9
5.5V
1.65
Hysteresis2
3.0V
0.3
1.2
(VT+ - VT-)
4.5V
.6
1.5
-1
1
μA
V
V
Input leakage current
VIN = VDD or VSS
5.5V
Low-level output voltage 3
IOL = 100μA
3.0V
0.25
4.5V
0.25
High-level output voltage 3
Short-circuit output current 2 ,4
Low level output current9
High level output current9
Power dissipation 2, 8
IOH = -100μA
V
3.0V
2.75
4.5V
4.25
3.0V
-100
100
5.5V
-200
200
VIN = VDD or VSS
3.0V
6
VOL = 0.4V
5.5V
8
VIN = VDD or VSS
3.0V
-6
VOH = VDD-0.4V
5.5V
-8
CL = 50pF
5.5V
3.0V
1.9
0.76
mW/
MHz
5.5V
10
μA
VO = VDD and VSS
V
mA
mA
mA
IDDQ
Quiescent Supply Current
VIN = VDD or VSS
CIN
Input capacitance 5
ƒ = 1MHz
0V
15
pF
Output capacitance 5
ƒ = 1MHz
0V
15
pF
COUT
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%,
as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed
to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density ≤5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765pF/
MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose ≤ 1E6 rads(Si) per MIL-STD-883 Method 1019 Condition A and section 3.11.2.
8. Power dissipation specified per switching output.
9. This value is guaranteed based on characterization data, but not tested.
3
AC ELECTRICAL CHARACTERISTICS FOR THE UT54ACS132E2
(VDD = 3.0V to 5.5V; VSS = 0V 1, -55°C < TC < +125°C)
SYMBOL
tPHL
PARAMETER
Input to Yn
VDD
CL = 30pF
CL = 50pF
tPLH
Input to Yn
CL = 30pF
CL = 50pF
MINIMUM
UNIT
ns
3.0V & 3.6V
2
12
4.5V & 5.5V
2
8
3.0V & 3.6V
2
16
4.5V & 5.5V
2
12
3.0V & 3.6V
2
15
4.5V & 5.5V
2
11
3.0V & 3.6V
2
19
4.5V & 5.5V
2
15
Notes:
1. Maximum allowable relative shift equals 50mV.
2. All specifications valid for radiation dose ≤ 1E6 rads(Si) per MIL-STD-883 Method 1019 Condition A and section 3.11.2.
4
MAXIMUM
ns
ns
ns
Packaging
Ordering Information: UT54ACS132E: SMD
5962 * ***** ** * * *
Lead Finish: (Notes 1 & 2)
A = Solder
C = Gold
X = Optional
Package Type:
X = 14-lead ceramic bottom-brazed dual-in-line Flatpack
Class Designator:
Q = QML Class Q
V = QML Class V
Device Type:
02 = 1 rad(Si)/sec
03 = 50 to 300 rads(Si/Sec)
Drawing Number:
96542 = UT54ACS132E
Total Dose: (Note 3 & 4)
R = 1E5 rads(Si)
F = 3E5 rads(Si)
G = 5E5 rads(Si)
H = 1E6 rads(Si)
Notes:
1. Lead finish (A,C, or X) must be specified.
2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. For prototype inquiries, contact
factory.
4. Device type 02 is only offered with a TID tolerance guarantee of 3E5 rads(Si) or 1E6 rads(Si) and is tested in accordance with MIL-STD-883 Test
Method 1019 Condition A and section 3.11.2. Device type 03 is only offered with a TID tolerance guarantee of 1E5 rads(Si), 3E5 rads(Si), and 5E5
rads(Si), and is tested in accordance with MIL-STD-883 Test Method 1019 Condition A.
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Aeroflex Colorado Springs - Datasheet Definition
Advanced Datasheet - Product In Development
Preliminary Datasheet - Shipping Prototype
Datasheet - Shipping QML & Reduced HiRel
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