ACT-DP16K32A 512K Dual-Port SRAM Module Features Preliminary ■ High-density 512K CMOS Dual-Port SRAM module CIRCUIT TECHNOLOGY www.aeroflex.com ■ Fast access times Commercial: 30, 35ns Military: 40, 45ns MIL-PRF-38534 Compliant MCMs Available Fully asynchronous read/write operation from either port Easy to expand data bus width to 64 bits or more using the Master / Slave function Separate byte read/write signals for byte control On-chip port arbitration logic INT flag for port-to-port communication Full on-chip hardware support of semaphore signaling between ports Single 5V (±10%) power supply Inputs/outputs directly TTL-compatible Internal Decoupling Capacitors -55°C to +125°C Operating Temperature Packaging – Hermetic • 121 Pin PGA Package, 1.35" x 1.35" x .175" • ■ ■ ■ ■ ■ ■ ■ ■ ■ C X LA ISO 9001 E I NC . ■ LE S ■ F B ■ A E RO • RTIFIE D Description The Aeroflex ACTDP16K32A is a 16K x 32 high-speed CMOS Dual-Port Static RAM Module constructed on a co-fired ceramic 121 pin PGA (Pin Grid Array) 1.35 inches using four 16K x 8 (IDT7006 Die) Dual-Port Static RAMs. The ACTDP16K32A module is designed to be used as stand-alone 512K Dual-Port RAM or as a combination Master/Slave Dual-Port RAM for 64-bit or more word width systems. Using the Master/Slave approach in such system applications results in full-speed, error free operation without the need for additional discrete logic. The module provides two independent ports with separate control, address, and I/O pins that permit independent and asynchronous access for reads or writes to any location in memory. System performance is enhanced by facilitating port-to-port communication via additional control signals SEM and INT. Maximum access times as fast as 30ns are available over the commercial temperature range and 40ns over the military temperature range. The ACT-DP16K32A is manufactured in Aeroflex’s 80,000 square foot MIL-PRF-38534 certified facility in Plainview, N.Y. eroflex Circuit Technology – Static RAM Modules For The Future © SCD7300 REV B 3/27/03 Functional Block Diagram M/S L_A(0-13) R_A(0-13) L_I/O(0-7) R_I/O(0-7) L_CS L_OE R_CS R_OE IDT7006 16K x 8 (Arbitration Logic) L_SEM L_INT L_BUSY R_SEM R_INT R_BUSY L_R/W (1) R_R/W (1) L_I/O(8-15) R_I/O(8-15) IDT7006 16K x 8 (Arbitration Logic) L_R/W (2) R_R/W (2) L_I/O(16-23) R_I/O(16-23) IDT7006 16K x 8 (Arbitration Logic) L_R/W (3) R_R/W (3) R_I/O(24-31) L_I/O(24-31) IDT7006 16K x 8 (Arbitration Logic) L_R/W (4) R_R/W (4) Pin Names Left Port Aeroflex Circuit Technology Right Port Description L_A (0–13) R_A (0–13) Address Inputs L_I/O (0–31) R_I/O (0–31) Data Inputs/Outputs L_R/W (1–4) R_R/W (1–4) Read/Write Enables L_CS R_CS Chip Select L_OE R_OE Output Enable L_BUSY R_BUSY Busy Flag L_INT R_INT Interrupt Flag L_SEM R_SEM Semaphore Control M/S Master/Slave Control VCC Power GND Ground 2 SCD7300 REV B 3/27/03 Plainview NY (516) 694-6700 Absolute Maximum Ratings1 Symbol Commercial Military Units Terminal Voltage with respect to GND -0.5 to 7 -0.5 to 7 V TC Operating Temperature 0 to +70 -55 to +125 °C TBIAS Temperature under Bias -55 to +125 -65 to +135 °C TSTG Storage Temperature -55 to +125 -65 to +150 °C IOUT DC Output Current 50 50 mA TTERM Rating Notes: 1. Stresses above those listed under "Absolute Maximums Rating" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operating Temperature and Supply Voltage1 Grade Case Temperature GND VCC Military -55 to +125°C 0V 5.0V±10% Commercial 0 to +70°C 0V 5.0V±10% Notes: 1. This is the parameter TC. Recommended DC Operating Conditions Symbol Parameter Minimum Maximum Units VCC Supply Voltage +4.5 +5.5 V GND Supply Voltage 0 0 V VIH Input High Voltage 2.2 6.0 V VIL Input Low Voltage -0.51 0.8 V Notes: 1. VIL > -3.0V for pulse width less than 20ns. DC Electrical Characteristics (VCC = 5.0V±10%, Tc = -55°C to +125°C or 0°C to +70°C) Commercial Parameter Sym Military Conditions Units Min Max Min Max Output Low Voltage VOL VCC = Min, IOL = 4 mA - 0.4 - 0.4 V Output High Voltage VOH VCC = Min, IOH = -4 mA 2.4 - 2.4 - V Input Leakage Current (Address & Control) Input Leakage Current (Data) Output Leakage Current (Data) Dynamic Operating Current (Both Ports Active) Standby Suppy Current (Both Ports In-Active) Standby Suppy Current (One Port Active) Standby Suppy Current (Both Ports Inactive) Aeroflex Circuit Technology ILI VCC = Max, VIN = GND to Vcc - 40 - 40 µA ILI VCC = Max, VIN = GND to Vcc - 10 - 10 µA ILO VCC = Max, CS > VIH, Vout = GND to Vcc - 10 - 10 µA ICC2 VCC = Max, CS < VIL, SEM = Don’t Care, Outputs Open, f = fMAX - 1360 - 1600 mA ISB VCC = Max, L_CS and R_CS > VIH Outputs Open, f = fMAX - 280 - 340 mA ISB1 VCC = Max, L_CS and R_CS > VIH Outputs Open, f = fMAX - 1000 - 1160 mA ISB2 L_CS and R_CS > VCC – 0.2V, VIN > VCC – 0.2V or < 0.2V L_SEM and R_SEM > VCC – 0.2V - 60 - 120 mA 3 SCD7300 REV B 3/27/03 Plainview NY (516) 694-6700 Capacitance 1 +5V (Tc = +25°C, f = 1.0MHz) Sym Parameter Conditions Max Units CIN (1) Input Capacitance (CS, OE, SEM, Address) VIN = 0V 40 pF CIN (2) Input Capacitance (R/W, I/O, INT) VIN = 0V 12 pF CIN (3) Input Capacitance (BUSY, M/S) VIN = 0V 45 pF Output Capacitance (I/O) VOUT = 0V COUT 480Ω BUSY, INT 30pF* 255Ω *Includes scope and jig capacitance. 12 pF Figure 1 – Output Load +5V NOTE: 1. This parameter is guaranteed by design but not tested. 480Ω AC Test Conditions Input Pulse Levels DATAOUT GND to 3.0V Input Rise/Fall Times 5ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load 5pF* 255Ω *Includes scope and jig capacitance. See Figures 1 and 2 Figure 2 – Output Load (For tchz, tclz, tohz, tolz, twhz, tow) AC Characteristics (VCC = 5.0V ±10%, Tc = -55°C to +125°C or 0°C to +70°C) Parameter Sym Commercial –030 –035 Min Max Min Max Military –040 –045 Min Max Min Max Units Read Cycle Read Cycle Time tRC 30 - 35 - 40 - 45 - ns Address Access Time tAA - 30 - 35 - 40 - 45 ns tACS2 - 35 - 35 - 35 - 35 ns Output Enable Access Time tOE - 17 - 20 - 22 - 25 ns Output Hold from Address Change tOH 3 - 3 - 3 - 3 - ns Output to Low-Z tLZ1 3 - 3 - 3 - 5 - ns Output to High-Z tHZ1 - 15 - 15 - 17 - 20 ns Chip Select to Power Up Tim tPU1 0 - 0 - 0 - 0 - ns Chip Deselect to Power Up Time tPD1 - 50 - 50 - 50 - 50 ns Sem. Flag Update Pulse (OE or SEM) tSOP 15 - 15 - 15 - 15 - Write Cycle Time tWC 30 - 35 - 40 - 45 - ns Chip Enable to End of Write tCW2 25 - 30 - 35 - 40 - ns Address Valid to End of Write tAW 25 - 30 - 35 - 40 - ns Address Set-Up Time tAS 0 - 0 - 0 - 0 - ns Write Pulse Width tWP 25 - 30 - 35 - 40 - ns Chip Select Access Time Write Cycle Aeroflex Circuit Technology 4 SCD7300 REV B 3/27/03 Plainview NY (516) 694-6700 AC Characteristics (con’t) (VCC = 5.0V ±10%, Tc = -55°C to +125°C or 0°C to +70°C) Commercial –030 –035 Min Max Min Max Military –040 –045 Min Max Min Max Parameter Sym Units Write Recovery Time tWR 0 - 0 - 0 - 0 - ns Data Valid to End-of-Write tDW 22 - 25 - 25 - 25 - ns Data Hold Time tDH 0 - 0 - 0 - 0 - ns Output to High-Z tHZ1 - 15 - 15 - 17 - 20 ns Output Active from End of Write tOW1 0 - 0 - 0 - 0 - ns SEM Flag Write to Read Time tSWRD 10 - 10 - 10 - 10 - ns SEM Flag Contention Window tSPS 10 - 10 - 10 - 10 - ns BUSY Access Time to Address tBAA - 30 - 35 - 35 - 35 ns BUSY Disable Time to Address tBDA - 25 - 30 - 30 - 30 ns BUSY Access Time to Chip Select tBAC - 25 - 30 - 30 - 30 ns BUSY Disable Time to Chip Deselect tBDC - 25 - 25 - 25 - 25 ns tWDD5 - 55 - 60 - 65 - 70 ns Write Data Valid to Read Data Delay tDDD - 40 - 45 - 50 - 55 ns Arbitration Priority Set-Up Time tAPS6 5 - 5 - 5 - 5 - ns BUSY Disable to Valid Time tBDD - Note 9 - Note 9 - Note 9 - Note 9 ns Write to BUSY Input tWB7 0 - 0 - 0 - 0 - ns Write Hold after BUSY tWH8 25 - 25 - 25 - 25 - ns Write Pulse to Data Delay tWDD5 - 55 - 60 - 65 - 70 ns Address Set-Up Time tAS 0 - 0 - 0 - 0 - ns Write Recovery Time tWR 0 - 0 - 0 - 0 - ns Interrupt Set Time tINS - 25 - 30 - 32 - 35 ns Interrupt Reset Time tINR - 25 - 30 - 32 - 35 ns Busy Cycle-Master Mode 3 Write Pulse to Data Delay Busy Cycle-Slave Mode 4 Interrupt Timing NOTES: 1. This parameter is guaranteed by design but not tested. 2. To access RAM, CS ≤ VIL and SEM ≥ VIH. To access semaphore, CS ≥ VIH and SEM ≤ VIL. 3. When the module is being used in the Master Mode (M/S ≥ VIH). 4. When the module is being used in the Slave Mode (M/S ≤ VIL). 5. Port-to-Port delay through the RAM cells from the writing port to the reading port. 6. To ensure that the earlier of the two ports wins. 7. To ensure that the write cycle is inhibited during contention. 8. To ensure that a write cycle is completed after contention. 9. tBDD is a calculated parameter and is the greater of 0, tWDD - tWP (actual), or tDDD - tWP (actual). Aeroflex Circuit Technology 5 SCD7300 REV B 3/27/03 Plainview NY (516) 694-6700 Timing Waveform of Read Cycle No. 1, Either Side 1,2,4 tRC ADDRESS tOH tAA DATAOUT PREVIOUS DATA VALID DATA VALID tOH Timing Waveform of Read Cycle No. 2, Either Side 1,3,5 tSOP tACE CS tSOP tCHZ 6 tAOE OE tOLZ 6 tOHZ 6 DATAOUT DATA VALID tCLZ 6 tPD 6 ICC 50% CURRENT ISB 50% tPU 6 NOTES: 1. R/W is HIGH for Read Cycles 2. Device is continuously enabled CS < VIL. This waveform cannot be used for semaphore reads. 3. Addresses valid prior to or coincident with CS transition LOW. 4. OE < VIL 5. To access RAM, CS < VIL and SEM > VIH. To access semaphore, CS > VIH and SEM < VIL. 6. This parameter is guaranteed by design but not tested. Aeroflex Circuit Technology 6 SCD7300 REV B 3/27/03 Plainview NY (516) 694-6700 Timing Waveform of Write Cycle No. 1 (R/W Controlled Timing)1,2,4 tWC ADDRESS tCHZ 9 OE tAW CS tWR 7 tWP 2 tAS 6 R/W tOW 9 tWHZ 9 DATAOUT (4) tDW DATAIN tDH DATA VALID Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)1,2,4 tWC ADDRESS tAW CS tAS 6 tWP 2 tWR 7 R/W tDW DATAIN tDH DATA VALID NOTES: 1. R/W must be HIGH during all address transitions. 2. A write occurs during the overlap (tWP) of a LOW CS and a LOW R/W. 3. tWR is measured from the earlier of CS or R/W (or SEM or R/W) going HIGH to the end of write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CS or SEM low transition occurs simultaneously with or after the R/W low transition, the outputs remain in the high impedance state. 6. Timing depends on which enable signal is asserted last. 7. Timing depends on which enable signal is de-asserted first. 8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. Aeroflex Circuit Technology 7 SCD7300 REV B 3/27/03 Plainview NY (516) 694-6700 Timing Waveform of Semaphore Read after Write, Either Side1 tAW A0–A2 tWR tAA VALID ADDRESS tOH VALID ADDRESS tWP tSOP tACE SEM tDW DATA0 DATAOUT VALID DATAIN VALID tAS tWP tDH R/W tSWRD tAOE OE tSOP Write Cycle Read Cycle NOTE: 1. CS ≥ VIH for the duration of the above timing (both write and read cycle). Timing Waveform of Semaphore Contention1,3,4 A0A—A2A SIDE 2 "A" MATCH R / WA SEMA tSPS A0B—A2B SIDE 2 "B" R / WB SEMB NOTES: 1. DOR = DOL ≤ VIL, (L_ CS = R_ CS) ≥ VIH Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start. 2. “A” may be either left or right port. “B” is the opposite port from “A”. 3. This parameter is measured from R/WA or SEMA going HIGH to R/WB or SEMB going HIGH. 4. If tSPS is violated, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag. Aeroflex Circuit Technology 8 SCD7300 REV B 3/27/03 Plainview NY (516) 694-6700 Timing Waveform of Read with BUSY (M/S > VIH) 2 tWC MATCH ADDR R tWP R/W R tDW DATA IN R tDH VALID tAPS 1 tBDA MATCH ADDR L tBDD BUSY L tDDD 3 VALID DATAOUT L tWDD NOTES: 1. To ensure that the earlier of the two ports wins. 2. (L_ CS = R_ CS) < VIL. 3. OE < VIL for the reading port. Timing Waveform of Write with Port-to-Port Delay (M/S < VIH) 1,2 tWC ADDR R MATCH tWP R/W R tDW DATA IN R tDH VALID ADDR L MATCH tDDD VALID DATAOUT L tWDD NOTES: 1. BUSY input equals HIGH for the writing port. 2. (L_ CS = R_ CS) < VIL. Aeroflex Circuit Technology 9 SCD7300 REV B 3/27/03 Plainview NY (516) 694-6700 Timing Waveform of Write with BUSY Input (M/S < VIL) tWP R/W tWH tWB BUSY DATA INR Timing Waveform of BUSY Arbitration (CS Controlled Timing) ADDR "A" AND "B" 1 ADDRESS MATCH CS "A" tAPS 2 tBDC CS "B" tBAC BUSY "B" Timing Waveform of BUSY Arbitration (Controlled by Address Match Timing) ADDR "A" 1 ADDRESS "N" tAPS 2 ADDR "B" MATCHING ADDRESS "N" tBAA tBDA BUSY "B" NOTES: 1. All timing is the same for the left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. 2. If tAPS is violated, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted. Aeroflex Circuit Technology 10 SCD7300 REV B 3/27/03 Plainview NY (516) 694-6700 Timing Waveform of Interrupt Cycle 1 tWC INTERRUPT SET ADDRESS 2 ADDR "A" tWR 4 tAS 3 CE "A" R/W 1"A" tINS 3 INT "B" tRC INTERRUPT CLEAR ADDRESS 2 ADDR "B" tAS 3 CE "B" OE "B" tINR 3 INT "B" NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. 2. See Interrupt truth table. 3. Timing depends on which enable signal is asserted last. 4. Timing depends on which enable signal is de-asserted first. Truth Table I – Non-Contention Read/Write Control 1 Inputs Outputs Mode Description CS R/W OE SEM I/O H X X H High-Z Deselected or Power Down L L X H Data_In Write L H L H Data_OUT Read X X H X High-Z Outputs Disabled NOTE: 1. The conditions for non-contention are L_A (0–13) ≠ R_A (0–13). denotes a LOW to HIGH waveform transition. 2. Truth Table II – Semaphore Read/Write Control Inputs2 Outputs Mode Description CS R/W OE SEM I/O H H L L Data_OUT X L Data_In X L - L L Aeroflex Circuit Technology X 11 Read Data in Semaphore Flag Write Data_IN (0, 8, 16, 24) Not Allowed SCD7300 REV B 3/27/03 Plainview NY (516) 694-6700 Pin Numbers & Functions 121 Pins — PGA Aeroflex Circuit Technology Pin # Function Pin # Function Pin # Function A1 L_IO24 D3 A2 L_IO26 D4 L_A4 K1 L_IO11 GND K2 M/S A3 L_IO28 D11 R_A4 K3 GND A4 L_IO30 D12 R_IO20 K4 L_A10 A5 L_CS D13 R_IO19 K5 L_A11 A6 L_OE E1 L_IO17 K6 L_A12 A7 L_RW3 E2 L_IO18 K7 GND A8 R_OE E3 L_A5 K8 R_A12 A9 R_CS E11 R_A5 K9 R_A11 A10 R_IO30 E12 R_IO18 K10 R_A10 A11 R_IO28 E13 R_IO17 K11 VCC A12 R_IO26 F1 L_SEM K12 GND A13 R_IO24 F2 L_IO16 K13 R_IO11 B1 L_IO23 F3 L_A6 L1 L_IO10 B2 L_IO25 F11 R_A6 L2 L_IO8 B3 L_IO27 F12 R_IO16 L3 L_IO6 B4 L_IO29 F13 R_SEM L4 L_IO4 B5 L_IO31 G1 L_BUSY L5 L_IO2 B6 L_A0 G2 L_INT L6 L_A13 B7 L_RW4 G3 GND L7 R_RW4 B8 R_A0 G11 GND L8 R_A13 B9 R_IO31 G12 R_INT L9 R_IO2 B10 R_IO29 G13 R_BUSY L10 R_IO4 B11 R_IO27 H1 L_RW1 L11 R_IO6 B12 R_IO25 H2 L_RW2 L12 R_IO8 B13 R_IO23 H3 L_A7 L13 R_IO10 C1 L_IO21 H11 R_A7 M1 L_IO9 C2 L_IO22 H12 R_RW2 M2 L_IO7 C3 VCC H13 R_RW1 M3 L_IO5 C4 L_A3 I1 L_IO15 M4 L_IO3 C5 L_A2 I2 L_IO14 M5 L_IO1 C6 L_A1 I3 L_A8 M6 L_IO0 C7 GND I11 R_A8 M7 R_RW3 C8 R_A1 I12 R_IO14 M8 R_IO0 C9 R_A2 I13 R_IO15 M9 R_IO1 C10 R_A3 J1 L_IO13 M10 R_IO3 C11 GND J2 L_IO12 M11 R_IO5 C12 R_IO22 J3 L_A9 M12 R_IO7 C13 R_IO21 J11 R_A9 M13 R_IO9 D1 L_IO19 J12 R_IO12 D2 L_IO20 J13 R_IO13 12 SCD7300 REV B 3/27/03 Plainview NY (516) 694-6700 Package Outline — 121 Pin PGA "P12" Top View 1 2 3 4 5 6 7 8 Side View 9 10 11 12 .175 MAX 13 .125 .200 .100 BSC A B C D E F 1.200 1.325 BSC 1.355 G .016 .020 H I J K L M 1.200 BSC .235 MAX 1.325 1.355 .040 .060 Specification subject to change without notice Aeroflex Circuit Technology 13 SCD7300 REV B 3/27/03 Plainview NY (516) 694-6700 CIRCUIT TECHNOLOGY Sample Ordering Information Model Number Speed Package ACT–DP16K32A–030P12C 30ns 1.35 SQ PGA ACT–DP16K32A–035P12C 35ns 1.35 SQ PGA ACT–DP16K32A–040P12M 40ns 1.35 SQ PGA ACT–DP16K32A–045P12M 45ns 1.35 SQ PGA Part Number Breakdown ACT– DP 16K 32 A– 035 P12 Q Aeroflex Circuit Technology Screening Level C = Commercial Temp, 0°C to +70°C T = Military Temp, -55°C to +125°C M = Military Temp, -55°C to +125°C, Screened * Q = MIL-PRF-38534 Compliant/SMD Memory Type DP = Dual Port Memory Depth, Locations * Screened to the individual test methods of MIL-STD-883 Memory Width, Bits Package Type & Size Options A = Asynchronous Thru-Hole Package P12 = 1.35"SQ PGA 121 Pins Memory Speed, ns (+5V Vcc) Specifications subject to change without notice Aeroflex Circuit Technology 35 South Service Road Plainview New York 11803 www.aeroflex.com Aeroflex Circuit Technology Telephone: (516) 694-6700 FAX: (516) 694-6715 Toll Free Inquiries: (800) 843-1553 E-Mail: [email protected] 14 SCD7300 REV B 3/27/03 Plainview NY (516) 694-6700