UTMC Application Note _______________________________________________________________ Modification List for the Intel EV80C196KD Evaluation Board This application note describes modifications that must be made to the Intel EV80C196KD Evaluation Board so that it will work with the UTMC UT80CRH196KD Microcontroller. Each modification has been verified to work properly with the Intel device installed. This modification list is broken into the following categories: 1. Parts List (Describes the required hardware to complete the board modifications) 2. Modification Instructions 3. Jumper Settings (Describes how specific jumpers should be configured) Parts list: Quantity: Description: 1 13 1 1 20.00Mhz digital oscillator 5 Kohm leaded resistors UTMC supplied High-Byte monitor PROM UTMC supplied Low-Byte monitor PROM Modification Instructions: 1. Remove C4, C5 and X1 (20mhz crystal). Install a digital 20MHz oscillator to the pad where X1-right was connected. Short the power pin of the oscillator to R1-right. Short the ground pin of the oscillator to C4-left. Short a jumper wire from C4-left to X1-left. This will ground pin 66 on the processor. If you modify this board and use the Intel 80C196KD, you must remove this jumper to ensure proper operation. 2. Lift (isolate) U15-9. Connect U15-11 to U15-9 pad. In the beta version of the UT80CRH196KD device BHE is not valid until WR goes valid. This modification allows BHE to be used, as well as allowing proper operation of the Intel device. 3. Remove C15. (Pin 37 is the EDACEN digital input to the UT80CRH196KD). 4. Remove the C2 array of capacitors. (Port 0 is a digital signal port). 5. Replace U1 and U8 with the UTMC supplied monitor PROMs. U1 is the high byte PROM, and U8 is the low byte PROM. 6. UTMC suggests defining Port0 inputs by tying ACH0-ACH7 to ANGND (actually VSS) through 5K Ohm pulldown resistors (the UT80CRH196KD drives these as outputs during EDAC writes, do not directly connect these pins to power or ground). *ACH0: *ACH1: *ACH2: *ACH3: ACH4: ACH5: *ACH6: ACH7: JP1-2 JP1-6 JP1-8 JP1-12 JP1-14 JP1-18 JP1-20 JP1-24 => => => => => => => => 5K resistor 5K resistor 5K resistor 5K resistor 5K resistor 5K resistor 5K resistor 5K resistor => => => => => => => => JP1-1 JP1-5 JP1-7 JP1-11 JP1-13 JP1-17 JP1-19 JP1-23 Note: The jumper pins JP1-1, 5, 7, 11, 13, 17, 19, and 23 are connected to VSS. Latest Revision Date: 6/7/00 Original Publication Date: 2/5/1999 Page 1 of 2 UTMC Application Note _______________________________________________________________ * => These signals are driven by the UT80CRH196KD when the EDACEN is active 7. UTMC suggests defining Port2(4:1) by tying to VSS through 5K Ohm resistors. P2.1: P2.2: P2.3: P2.4: JP2-20 JP2-22 JP2-24 JP2-26 -> -> -> -> 5K resistor 5K resistor 5K resistor 5K resistor -> -> -> -> JP2-19 JP2-21 JP2-23 JP2-25 Note: The jumper pins JP2-19, 21, 23, and 25 are connected to VSS. Jumper Settings: 1. E6: A-B => U5-14 requires a connection to GND. (CDE pin on Intel part, VSS pin on the UT80CRH196KD part). 2. E4: A-B => U5-13 requires a connection to VCC. (Vref on Intel part, VDD on the UT80CRH196KD part). 3. E2: A-B => U5-12 requires a connection to GND. (ANGND on Intel, VSS on the UT80CRH196KD). 4. E19: removed. RXD driven by 80196, not the RS232 conn P2. 5. E3: Remove the jumper and install a 5K Ohm resistor (pulldown) between A-B. Defines U5-2 (EA on Intel, ECB5 on the UT80CRH196KD). 6. E7: B-C enables the NMI to be driven by the UART. 7. E16: A-B enables Port1 to drive the LEDs. 8. E20: B-C enables the reset to be driven by the UART 9. E21: B-C disables wait states. (Necessary for the CCB read at address 2018h) 10. E11: A-B enables the HOLD/HOLDA feature. 11. E9: A-B connects the A15 input of the monitor PROMs, which will be low for all monitor addresses. 12. Keep the default settings for the rest of the memory jumpers: E1, E5, E8, E10, E12-E15, E17, E18. Latest Revision Date: 6/7/00 Original Publication Date: 2/5/1999 Page 2 of 2