Standard Products ACT4430PC / ACT4431SC Superpipelined 64-Bit R4400 RISC Microprocessor Multichip Module www.aeroflex.com/Avionics April 15, 2005 FEATURES ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ ❑ Full militarized MIPS R4400 microprocessor Low power dissipation, 3.3 Volt powered, 64 bit superpipelined RISC R4400 microprocessor - Highly integrated CPU with integer unit, FPA, MMU, I&D cache - Balanced integer & floating point performance - Exploits 2-level instruction-level parallelism - No issue restrictions on the instructions used Integer unit - 32 entry, 64 bit wide register - ALU - Dedicated multiplier/divider Super pipelined FPA - 32/16 entry 32/64 bit register file in a 32 bit mode - 32 entry 64 bit register file in 64 bit mode - Supports single and double precision - Supports ANSI/IEEE Standard 754-1985 Memory management unit - 48 entry TLB for fast virtual-to-physical address translation, software managed cntrl regstrs - Programmable page sizes from 4K bytes to 16M bytes - Total physical address space encompasses 64G bytes - One pair of pages per TLB entry, each programable in size from 4K bytes to 16M bytes JTAG boundary scan capability for testing module interconnects Internal 1M byte secondary cache SRAM configured as a split cache with instruction and data sections separate. Can be factory configured as unified. Provides 16 bit ECC on secondary cache data line, 7 bit ECC on tag line Minimum clock rate 50 mHz with no wait states +3.3V (10 Watts max power dissipation) operation is standard Full military operating temperature range of -55°C to +125°C, case temperature Designed to meet military specifications, manufactured and tested in Aeroflex’s MIL-PRF-38534 certified facility Designed for Commercial, Industrial and Aerospace Applications Aeroflex-Plainview is a Class H & K MIL-PRF-38534 manufacturer 280-lead CQFP, Flat package (F10) 179-Pin PGA, Plug-In (P10) DESCRIPTION The Aeroflex Plainview ACT4431SC is a full military temperature range 64 bit, super-pipelined RISC microprocessor with 1M Byte of secondary cache memory packaged in a high speed multichip module (MCM). The modules contains the following components: • (1) R4400SC, a 3.3V powered RISC microprocessor • (11) SRAMs, 64K by 16 • (3) Buffers and (3) Passive components for phase lock loop operation A Primary cache only version, the ACT4430PC is available in the same package or 179 pin PGA (Use with “MIPS R4000 Microprocessor Users Manual”© MIPS 1993) SCD4430 Rev B SCData(127:0) SCDchk(15:0) DQ143-DQ0 CE (9) 64K by 16 SRAMs OE SCDCS SCOE INTEGER EXECUTION UNIT SCAddr0 A0 General Registers ALU/Multiply/Divide DATA/INSTRUCTION CACHE A14:A1 Pipeline/Control CACHE/MMU A15 WE BWH 16K Byte 16K Byte Data Instruction Cache Cache BWL 48 Entry TLB GND SCAddr (14:1) Cache Control MMU FLOATING POINT FPU ALU BWH OE SCAddr 17 BWL (2) 64K by 16 SRAMs A15 Multiply/Divide Square Root FP Register CACHE TAG A14:A1 CE Pipeline Control A0 WE R4400SC Microprocessor DQ0-DQ31 SCTag(24:0) SCTchk(6:0) SCTCS BLOCK DIAGRAM (SC VERSION) SCD4430 Rev B 2 SCWE System Interface 2 8 9 Int(5:1)* Int0* NMI* R4400 Multichip Module JTDI JTDO JTMS JTCK JTAG Interface ModeClock ModeIn VCCOk ColdReset* Reset* 256K/1M* 2 Vcc Gnd 8 Note: Int(5:1)* available on ACT4430PC version ‡ IvdAck, IvdErr used in “MC” mode MODULE SYMBOLIC INTERFACE CONNECTIONS SCD4430 Rev B 3 Initialization Interface TClock(1:0) RClock(1:0) MasterClock MasterOut SyncOut SyncIn IOOut IOIn Fault* VccP VssP Status(7:0) VccSense VssSense 5 Interrupt Interface 64 Power System Interface Clock/Control Interface SysAD(63:0) SysAD(7:0) SysCmd(8:0) SysCmdP ValidIn* ValidOut* ExtRqst* Release* RdRdy* WrRdy* IvdAck* ‡ IvdErr* ‡ SIGNAL DESCRIPTIONS System Interface Signals SysADy(63:0) SysADC (7:0) SysCmd (8:0) SysCmdP I/O System address/data bus: A 64 bit address and data bus for communication between the processor and an external agent I/O System address/data check bus: An 8 bit bus containing check bits for the SysAD bus I/O System command/identifier bus parity: A 9 bit bus for command and data identifier transmission between the processor and an external agent I/O System command /data identifier bus parity: A single, even parity bit for thr SysCmd bus Validin* I Valid Input: An external agent asserts ValidIn* when it is driving a valid address or data on the SysAD bus and a valid command or data identifier on the SysCmd bus O Valid Output: The processor asserts ValidOut* when it is driving a valid address or data on the SysAD bus and a valid command or data identifier on the SYSCMD bus I External Request: An external agent asserts ExtRqst* to request the use of the system interface. The processor grants the request by asserting Release*. O Release Interface: In response to the assertion of ExtRqst*, the processor asserts Release* to signal the requesting device that the system interface is available I Read ready: The external agent asserts RdRdy* to indicate that it can accept processor read, invalidate, or update requests in both overlap and non-overlap mode or can accept a read followed by a potential invalidate or update request in the overlap mode I Write ready: An external agent asserts WrRdy* when it can accept a processor write request I Invalidate acknowledge: An external agent asserts IvdAck* to signal successful completion of a processor invalidate or update request (MC only) I Invalidate error: An external agent asserts InvErr* to signal unsuccessful completion of a processor invalidate or update request (MC only) ValidOut* ExtRqst* Release* RdRdy* WrRdy* IvdAck* IvdErr* SCD4430 Rev B 4 SIGNAL DESCRIPTIONS con’t Clock/Control Interface Signals TClock (1:0) O Transmit clocks: Two identical transmit clocks that establish the system interface frequency O Receive clocks: Two identical receive clocks that establish the system interface frequency MasterClock I Master clock: Master clock input establishes the processor operating frequency Masterout O Master clock out: Master clock output aligned with MasterClock O Synchronization clock out: Synchronization clock output must be connected to SyncIn through an interconnect that models the interconnect between MasterOut, TClock, RClock, and the external agent I Synchronization clock in: Synchronization clock input O I/O output: Output slew rate control feedback loop output. Must be connected to IOIn through a delay loop that models the I/O path from the processor to an external agent. I I/O input: Output slew rate control feedback loop input (see IOOut) O Fault: The processor asserts Fault to indicate a mismatch output of boundry comparators VccP I Quiet Vcc for the PLL: Quiet Vcc for the internal phase lock loop VssP I Quiet Vss for the PLL: Quiet Vss for the internal phase lock loop Status(7:0) O Status: An 8 bit bus that indicates the current operation status of the processor RClock (1:0) SyncOut SyncIn IOOut IOIn Fault* VccSense I/O Vcc Sense: This is a special pin used for testing and characterization. The voltage at this pin directly shows the behavior of the on chip Vcc. I/O Vss Sense: VssSense provides a separate, direct connection fron the on-chip Vss node to a package pin without attaching to the in-package ground planes. VssSense should be connected to Vss in functional system designs. VssSense SCD4430 Rev B 5 SIGNAL DESCRIPTIONS con’t Interrupt Interface Signals: These signals comprise the interface used by external agents to interrupt the R4400 processor Int (5:1)* Int0* NMI* I Interrupt: Five of six general processor interrupts, bit-wise ORed with bits 5:1 of the interrupt register. This feature available on the R4400PC version only. I Interrupt: One of six general processor interrupts, bit wise ORed with bit 0 of the interrupt register I Nonmaskable interrupt: Nonmaskable interrupt ORed with bit 6 of the interrupt register Initialization Interface: These signals comprise the interface by which an external agent initializes the R4400 operating parameters ColdReset* ModeClock ModeIn I Cold Reset: This signal must be asserted for a power on reset or a cold reset. The clocks SClock, TClock, and RClock begin to cycle and are synchronized with the de-assertion edge of ColdReset*. ColdReset must be de-asserted synchronously with MasterOut. O Boot Mode Clock: Serial boot-mode data clock output at the system clock frequency divided by 256 I Boot mode data in: Serial boot-mode data input I Reset: This signal must be asserted for any reset sequence. It may be asserted synchronously or asynchronously for a cold reset, or synchronously to initate a warm reset. Reset must be de-asserted synchronously with MasterOut. I Vcc is OK: When asserted, this signal tells the R4400 that the 3.3 Volt power supply has been above 3.15 Volts for more than 100 milliseconds & will remain stable. Assertion of VccOK starts initialization sequence. I Cache size Select: Must be connected to ground to enable the full 1M Byte of cache. Cache size will be 256K if pin is left unconnected. Reset* VccOk 256K/1M* JTAG Interface Signals JTDI JTCK JTDO JTMS I JTAG data in: Data is serial, scanned in thru this pin I JTAG clock input: The processor outputs a serial clock on JTCK. On the rising edge of JTCK, both JTDI and JTMS are sampled. O JTAG data out: Data is serial, scanned out thru this pin I JTAG: JTAG command signal indicates that the incomming serial data is command clear SCD4430 Rev B 6 ACT4431SC – CQFP – PINOUTS Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Function TClock 0 Vss Sys AD 45 Vss TClock 1 Vss Sys AD 13 Vss Sys AD 14 Vcc JTMS Vcc Sys AD 46 Vcc JTDO Vcc Sys AD 15 Vcc Sys AD 47 Vss Status 0 Vcc JTDI Vss Sys ADC 1 Vcc Sys ADC 5 Vcc Status 2 Vcc Status 1 Vcc JTCK Vss Sync In Vss Vss Sense Vss Vcc Sense Vss MasterClock Vss Status 3 Vcc IvdErr* Vcc Status 4 Pin # 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 Function Vss VssP Vcc IvdAck* Vss VccP Vcc Status 5 Vss Status 6 Vcc Status 7 Vcc Sys ADC 7 Vcc Sys ADC 3 Vcc VCC Ok Vcc Sys AD 63 Vss MasterOut Vss Sys AD 31 Vcc Sys AD 30 Vcc Sys AD 62 Vss Sync Out Vss Sys AD 29 Vss RClock 1 Vss Sys AD61 Vss RClock 0 Vss Vcc Reset* Vcc Sys AD 60 Vss Sys AD 28 Vcc Cold_Reset* ✪ Do not connect, factory test only, ✦ Connect to +V Volts SCD4430 Rev B 7 Pin # 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 Function Vss Sys AD 59 Vcc Sys AD 27 Vss IO In Vcc Sys AD 58 Vss Sys AD 26 Vcc IO Out Vss Sys AD 57 Vcc Sys AD 25 Vss GRPRUN ✪ Vcc Sys AD 56 Vss Sys AD 24 Vcc GRPSTALL ✦ Vss Sys ADC 6 Vcc Sys ADC 2 Vss NMI* Vcc Sys AD 55 Vss Sys AD 23 Vcc Release * Vss Sys AD 22 Vcc Sys AD 54 Vss Mode In Vcc Rd Rdy * Vss Sys AD 53 Sys AD 21 ACT4431SC – CQFP – PINOUTS (con’t) Pin # Function Pin # 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 Vss Ext RQST* Vcc Sys AD 52 Vss Valid Out* Vcc Sys AD 20 Vss Sys AD 19 Vcc Sys AD 51 Vss ValidIn* Vcc Sys AD 18 Vss Sys AD 50 Vcc Int 0* Vss Sys AD 49 Vcc Sys AD 17 Vss Sys AD 16 Vcc Sys AD 48 Vss SPARE SPARE SPARE SPARE SPARE SPARE SPARE Vss Int 1* Vcc Int 2* Vss SPARE SPARE Int 3* SPARE SPARE Vss 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 Function Int 4* Vcc Int 5* Vss Vcc 256K/1M* SPARE SPARE SPARE CASE GROUND Vss Sys AD 32 Vcc Sys AD 0 Vss Sys AD 1 Vcc Sys AD 33 Vss Sys AD 34 Vcc Sys AD 2 Vss Sys Cmd 0 Vcc Sys AD 35 Vss Sys AD 3 Vcc Sys AD 4 Vss Sys Cmd 1 Vcc Sys AD 36 Vss Sys Cmd 2 Vcc Sys AD 5 Sys AD 37 Vss Mode Clock Vcc WR RDY* Vss Sys AD 6 Vcc Sys AD 38 ✪ Do not connect, factory test only, ✦ Connect to +V Volts SCD4430 Rev B 8 Pin # Function 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 Vss Sys Cmd 3 Vcc Sys AD 7 Vss Sys AD 39 Vcc Sys Cmd 4 Vss Sys ADC 0 Vcc Sys ADC 4 Vss Sys Cmd 5 Vcc Sys AD 8 Vss Sys AD 40 Vcc Sys Cmd 6 Vss Sys AD 9 Vcc Sys AD 41 Vss Sys CMD 7 Vcc Sys AD 10 Vss Sys AD 42 Vcc Sys Cmd 8 Vss Sys AD 11 Vcc Sys AD 43 Vss Sys Cmd P Vcc Sys AD 12 Vss Sys AD 44 Vcc Fault* Vss ACT4430PC – PGA – PINOUTS Function Pin # Function Pin # Function Pin # Function Pin # Coldreset ExtRqst Fault Reserved (NC) Vcc IOIn IOOut Int 0 Int l Int 2 Int 3 Int 4 lnt 5 JTCK JTDI JTDO JTMS MasterClock MasterOut ModeClock ModeIn NMI PLLCap 0 PLLCap 1 RClock 0 RClock l RdRdy Release Reset SyncIn SyncOut SysAD 0 SysAD 1 SysAD 2 SysAD 3 SysAD 4 SysAD 5 SysAD 6 SysAD 7 SysAD 8 SysAD 9 SysAD 10 SysAD 11 SysAD 12 SysAD 13 T14 U2 B16 U10 T9 T13 U12 N2 L3 K3 J3 H3 F2 H17 G16 F16 E16 J17 P17 B4 U4 U7 .... .... T17 R16 T5 V5 U16 J16 P16 J2 G2 El E3 C2 C4 B5 B6 B9 B11 C12 B14 B15 C16 SysAD 14 SysAD 15 SysAD 16 SysAD 17 Syr.AD 18 SysAD 19 SysAD 20 SysAD 21 SysAD 22 SysAD 23 SysAD 24 SysAD 25 SysAD 26 SysAD 27 SysAD 28 SysAD 29 SysAD 30 SysAD 31 SysAD 32 SysAD 33 SysAD 34 SysAD 35 SysAD 36 SysAD 37 SysAD 38 SysAD 39 SysAD 40 SysAD 41 SysAD 42 SysAD 43 SysAD 44 SysAD 45 SysAD 46 SysAD 47 SysAD 48 SysAD 49 SysAD 50 SysAD 51 SysAD 52 SysAD 53 SysAD 54 SysAD 55 SysAD 56 SysAD 57 SysAD 58 D17 EIB K2 M2 Pi P3 T2 T4 U5 U6 U9 Ull T12 U14 U15 T16 R17 M16 H2 G3 F3 D2 C3 B3 C6 C7 C10 C11 B13 A15 C15 B17 E17 F17 L2 M3 N3 R2 T3 U3 T6 T7 T10 T11 U13 SysAD 59 SysAD 60 SysAD 61 SysAD 62 SysAD 63 SysADC0 SysADC 1 SysADC 2 SysADC 3 SysADC 4 SysADC 5 SysADC 6 SysADC 7 SysCmd 0 SysCmd 1 SysCmd 2 SysCmd 3 SysCmd 4 SysCmd 5 SysCmd 6 SysCmd 7 SysCmd 8 SysCmd 9 TClock 0 TClock l VCCOk ValidIn ValidOut WrRdy VccP VssP Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc V15 T15 U17 N16 N17 C8 G17 T8 L16 B8 H16 U8 L17 E2 D3 B2 A5 B7 C9 B10 B12 C13 C14 C17 D16 M17 P2 R3 C5 K17 K16 A2 A4 A9 A11 A13 A16 B18 C1 D18 Fl G18 Hl J18 K1 Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss L18 M1 N18 R1 T18 Ul V3 V6 V8 V10 V12 V14 V17 A3 A6 A8 A10 A12 A14 A17 A18 B1 C18 D1 F18 GI H18 J1 K18 Ll M18 Nl P18 R18 Tl U18 V1 V2 V4 V7 V9 V11 V13 V16 V18 SCD4430 Rev B 9 Package Figure — ACT4431SC — CQFP 280 Leads “F10” Package 2.525 MAX 85 Spaces at 0.025 Pin 226 Pin 141 Pin 227 Pin 140 ACT4431SC MCM 53 Spaces at 0.025 1.768 MAX .010 Pin 280 Pin 87 Pin 1 Pin 86 .175 MAX .006 .072 ±.01 Note: Outside ceramic tie bars not shown for clarity. Contact factory for details Package Figure — ACT4430PC — PGA 179 Pins “P10” Package Bottom View 1 2 3 4 5 6 7 8 Side View 9 10 11 12 13 14 15 16 17 18 .100 BSC V U T R P N M L 1.700 1.840 BSC 1.880 K J .018 H G F E D C B A .050 1.700 BSC .221 MAX 1.840 1.880 SCD4430 Rev B 10 ORDERING INFORMATION Microprocessor Module Description Aeroflex Part Number ACT4430PC Primary Cache, +3.3 Volt P.S. PGA Package ACT4430PC P10 MCM ACT4431SC 1Meg Secondary Cache, +3.3 Volt Flat Package ACT4431SC 1M F10 MCM PLAINVIEW, NEW YORK Toll Free: 800-THE-1553 Fax: 516-694-6715 INTERNATIONAL Tel: 805-778-9229 Fax: 805-778-1980 NORTHEAST Tel: 603-888-3975 Fax: 603-888-4585 SE AND MID-ATLANTIC Tel: 321-951-4164 Fax: 321-951-4254 WEST COAST Tel: 949-362-2260 Fax: 949-362-2266 CENTRAL Tel: 719-594-8017 Fax: 719-594-8468 www.aeroflex.com [email protected] Aeroflex Microelectronic Solutions reserves the right to change at any time without notice the specifications, design, function, or form of its products described herein. All parameters must be validated for each customer's application by engineering. No liability is assumed as a result of use of this product. No patent licenses are implied. All trademarks are acknowledged. Parent company Aeroflex, Inc. 2003. SCD4430 Rev B 11 Our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused