Standard Products UT200SpWPHY01 SpaceWire Physical Layer Transceiver Datasheet February 2008 INTRODUCTION FEATURES 2-bit Serializer/Deserializer (SerDes) functionality LVDS physical layer Data rates to 200 Mbits/sec Data/Strobe transmit skew <500pS 3.3V power supply Cold spare on LVDS pins Radiation-hardened design; total dose irradiation testing to MIL-STD-883 Method 1019 - Total-dose: 100 krad(Si) - Latchup immune (LET > 109 MeV-cm2/mg) ESD rating Class 1 Packaged in a 28-pin flatpack Standard Microcircuit Drawing 5962-06232 - QML Q and V compliant part Aeroflex Colorado Springs’ UT200SpWPHY01 Physical Layer Transceiver (PHY) is designed to handle the critical timing issues associated with the SpaceWire Data/Strobe Encoding scheme. The receiver operates on both edges of the recovered RxClk and provides data on the digital outputs in bit pairs. The transmitter operation is the reverse of the receiver. Bit pairs of data and strobe are written into the device on the WrClk signal and the PHY serializes data and strobe onto the LVDS bus using the TxClk signal. The advantages of this SerDes functionality is the interfacing FPGA or ASIC can run at reduced clock rate with high-speed clock not requiring a stringent phase relationship. RmtLBE TxD0 TxD1 TxS0 TxS1 WrClk TxClk TxOE TxOE TxD+ TxD- Transmit Block TxS+ TxS- RxD+ RxDRxS+ RxSRxDR RxDF RxClk LclLBE RST Figure 1. UT200SpWPHY01 SpaceWire PHY Chip Block Diagram 1 2. Terminated Input. If the driver is disconnected (cable unplugged), or if the driver is in a three-state or power-off condition, the receiver output will again be in a HIGH state, even with the end of cable 100Ω termination resistor across the input pins. The unplugged cable can become a floating antenna which can pick up noise. If the cable picks up more than 10mV of differential noise, the receiver may see the noise as a valid signal and switch. To insure that any noise is seen as common-mode and not differential, a balanced interconnect should be used. Twisted pair cable offers better balance than flat ribbon cable. APPLICATIONS INFORMATION Aeroflex Colorado Springs’ UT200SpWPHY01 SpaceWire Physical Layer Transceiver is designed to maximize the speed of SpaceWire links implemented in Field Programmable Gate Arrays. The UT200SpWPHY01 is designed to handle the critical timing issues associated with the SpaceWire data/strobe encoding scheme. Receiver Fail-Safe The UT200SpWPHY01 SpaceWire Physical Layer Transceiver is a high gain, high speed device that amplifies a small differential signal (20mV) to TTL logic levels. Due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from appearing as a valid signal. The receiver’s internal fail-safe circuitry is designed to source/ sink a small amount of current, providing fail-safe protection (a stable known state of HIGH output voltage) for floating, terminated or shorted receiver inputs. Shorted Inputs. If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0V differential input voltage, the receiver output remains in a HIGH state. Shorted input failsafe is not supported across the common-mode range of the device (VSS to 2.4V). It is only supported with inputs shorted and no external common-mode voltage applied. 1. Open Input Pins. If an application requires an unused channel, the inputs should be left OPEN. Do not tie unused receiver inputs to ground or any other voltages. The input is biased by internal high value pull up and pull down resistors to set the output to a HIGH state. This internal circuitry will guarantee a HIGH, stable output state for open inputs. 2 Table 1: SpaceWire Physical Layer Transceiver Device Operation Truth Table TxOE RST LclLBE RmtLBE Tx Outputs Rx Outputs 0 0 X X Hi-Z Hi-Z 1 1 0 0 CMOS Tx Inputs LVDS Rx Inputs 0 1 0 X Hi-Z LVDS Rx Inputs 0 1 1 X Hi-Z CMOS Tx Inputs 1 0 X 0 0 Hi-Z 1 0 X 1 LVDS Rx Inputs Hi-Z 1 1 0 1 LVDS Rx Inputs LVDS Rx Inputs 1 1 1 0 CMOS Tx Inputs CMOS Tx Inputs 1 1 1 1 LVDS Rx Inputs CMOS Tx Inputs RADIATION Parameter Limit Units Total Ionizing Dose (TID) >3E5 and 1E6 rads(Si) Single Event Latchup (SEL) 1, 2 >109 MeV-cm2/mg 1.0E-8 cm2/device 109 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Dose Rate Upset TBD rads(Si)/sec Dose Rate Survivability TBD rads(Si)/sec SEU Saturated Cross-Section (σsat) Onset Single Event Upset (SEU) LET Threshold 3 Notes: 1. The UT200SpW02 are latchup immune to particle LETs >109 MeV-cm2/mg. 2. Worst case temperature and voltage of TC = +125oC, VDD = 3.6V, VDDQ1/Q3/Q4 = 3.6V for SEL. 3. Worst case temperature and voltage of TC = +25oC, VDD = 3.0V, VDDQ1/Q3/Q4 = 3.0V for SEU. 4.Adams 90% worst case particle environment, Geosynchronous orbit, 100mils of Aluminum shielding. 3 28-pin Flatpack Pin Description Pin Name Pin Number Pin Type Description LclLBE 1 LVCMOS Input1 Local Loopback Enable 0: No loopback, received data comes from LVDS Rx inputs (RxD+, ...) 1: Local loopback, received data comes from LVCMOS Tx inputs (TxD0, ...) RmtLBE 2 LVCMOS Input1 Remote Loopback Enable 0: No loopback, Transmit LVDS data comes from the LVCMOS Tx inputs (TxD0, ...) 1. Remote Loopback, Transmit LVDS data comes from LVDS Rx inputs. RxD+ 3 LVDS Input LVDS Rx differential positive Data input RxD- 4 LVDS Input LVDS Rx differential negative Data input RxS+ 5 LVDS Input LVDS Rx differential positive Strobe input RxS- 6 LVDS Input LVDS Rx differential negative Strobe input VDD 7, 22, 28 GND 8,14,21,27 TxS+ 9 LVDS Output LVDS Tx differential positive Strobe output TxS- 10 LVDS Output LVDS Tx differential negative Strobe output TxD+ 11 LVDS Output LVDS Tx differential positive Data output TxD- 12 LVDS Output LVDS Tx differential negative Data output TxOE 13 LVCMOS Input1 RxDR 26 LVCMOS Output Receiver rising edge (even) bit output (See Figure 7) RxDF 25 LVCMOS Output Receiver falling edge (odd) bit output (See Figure 7) RxClk 24 LVCMOS Output Receiver clock output RST 23 TxClk VDD 3.3V power supply Vss 0V TxOE=High: Enables LVDS transmit TxOE=Low: Tri-states LVDS transmit LVCMOS Input1 RST must remain low for 3 clock cycles before transitioning high, and must transition high 3 clock cycles before valid data. 20 LVCMOS Input1 Clock input to transmitter used to clock LVDS output. Any phase relationship is allowed between TxClk & WrClk but both must come from the same clock source and TxClk must be twice the frequency of the WrClk. WrClk 19 LVCMOS Input1 Transmitter input data Clock used to clock CMOS input to transmitter. Any phase relationship is allowed between TxClk & WrClk but both must come from the same clock source and WrClk must 1/2 of TxClk. TxS0 18 LVCMOS Input First (even) bit of 2bit parallel strobe input to transmitter TxS1 17 LVCMOS Input Second (odd) bit of 2bit parallel strobe input to transmitter TxD0 16 LVCMOS Input First, even bit of 2bit parallel data input to transmitter TxD1 15 LVCMOS Input Second, odd bit of 2bit parallel data input to transmitter Note 1. LVTTL compatible 4 PIN CONFIGURATION VDD LclLBE 1 28 RmtLBE 2 3 27 GND RxDR 4 5 26 25 24 RxS- 6 23 RST VDD 7 22 VDD RxD+ RxDRxS+ RxDF RxClk GND 8 21 GND TxS+ 9 20 TxClk TxS- 10 19 WrClk TxD+ 11 18 TxS0 TxD- 12 17 TxS1 TxOE GND 13 16 TxD0 14 15 TxD1 ABSOLUTE MAXIMUM RATINGS1 (Referenced to VSS) SYMBOL PARAMETER VDD DC supply voltage VI/O Voltage on any pin during operation -0.3 to 4.0V Voltage on any LVDS pin during cold spare2 TSTG LIMITS Storage temperature -0.3 to (VDD + 0.3V) -.3 to 4.0V -65 to +150°C PD Maximum power dissipation 432 mW ΘJC Thermal resistance, junction-to-case3 10°C/W DC input current ±10mA II Notes: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. 2. LVCMOS pins are not cold spare. 3. Test per MIL-STD-883, Method 1012. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS VDD VIN DC Supply Voltage DC input voltage 3.0V to 3.6V 0V to VDD 5 DC ELECTRICAL CHARACTERISTICS1 (VDD = 3.3V + 0.3V; -55°C < TC < +125°C) SYMBOL PARAMETER CONDITION MIN MAX UNIT VIH High-level input voltage (CMOS) VIL Low-level input voltage (CMOS) VOL Low-level output voltage (LVCMOS) IOL = 12mA VOH High-level output voltage (LVCMOS) IOH = -12mA 2.4 IINLVDS Input leakage current VIN = VDD or GND, VDD = 3.6V -20 +20 μA IINCMOS Input leakage current VIN = VDD or GND, VDD = 3.6V -10 +10 μA ICS Cold Spare Leakage Current VIN=3.6V, VDD = VSS = 0V -20 +20 μΑ VTH Differential Input High Threshold VCM = +1.2V +100 mV VTL Differential Input Low Threshold VCM = +1.2V -100 VOD Differential Output Voltage RL = 100Ω 250 Change in Magnitude of VOD for Complementary Output States RL = 100Ω Offset Voltage Voh + Vol RL = 100Ω, ⎛⎝ Vos = ---------------------------⎞⎠ ΔVOD VOS 2.0 1.125 V 0.8 V 0.4 V V mV 400 mV 35 mV 1.450 V 25 mV +10 μΑ 2 ΔVOS Change in Magnitude of VOS for Complementary Output States RL = 100Ω IOZ LVDS Output Three-State Current TxOE = Gnd VOUT = 0V or VDD, VDD = 3.6V ICCL Loaded supply current, drivers enabled RTEST = 50Ω all channels, running in full duplex VIN = VDD or VSS(all inputs) CL = 37pF, F = 200MHz 120 mA ICCZ Loaded supply current, drivers disabled DIN = VDD or VSS Clock and Data not toggling 10 mA ICCI Supply current, data toggling, clocks running, device in standby Clock @ 200 Mhz, TxOE = 0 Data @ 200 Mbits/sec, RST = 0 25 mA CIN2 LVCMOS input capacitance f = 1MHz @ 0V 7 pF COUT2 LVCMOS output capacitance f = 1MHz @ 0V 15 pF LVDS input capacitance f = 1MHz @ 0V 6 pF f = 1MHz @ 0V 7 pF CINLVDS2 COUTLVDS2 LVDS output capacitance -10 Notes: 1. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except differential voltages. 2. Capacitance is measured for initial qualification and when design changes may affect the input/output capacitance. Capacitance is measured between the designated terminal and VSS at a frequency of 1MHz and a signal amplitude of 50mV maximum. 3. RTEST is the tester load. RL is the LVDS termination load. 6 AC SWITCHING CHARACTERISTICS (VDD = +3.3V + 0.3V, TA = -55 °C to +125 °C) SYMBOL PARAMETER MIN MAX UNIT tCDLH TxClk to differential Data output low to high prop delay RTEST =50, CL = 37pF (figure 2) 2 4 ns tCDHL TxClk to differential Data output high to low prop delay RTEST =50, CL = 37pF (figure 2) 2 4 ns tCSLH TxClk to differential Strobe output low to high prop delay RTEST =50, CL = 37pF (figure 2) 2 4 ns tCSHL TxClk to differential Strobe output high to low prop delay RTEST =50, CL = 37pF (figure 2) 2 4 ns tDCS Differential Channel Skew 0.4 ns tCCS1 Channel to Channel Skew 0.5 ns tTLH2 Rise time LVDS Driver (figure 2) RL=100, CL = 37pF 1.5 ns tTHL2 Fall time LVDS Driver (figure 2) RL=100, CL = 37pF 1.5 ns tOEHZ Output Enable Low to Data or Strobe High to Z (figure 3, 4) RTEST = 50, CL = 37pF 5 ns tOELZ Output Enable Low to Data or Strobe Low to Z (figure 3, 4) RTEST = 50, CL = 37pF 5.0 ns tOEZH Output Enable High to Data or Strobe Z to High (figure 3, 4) RTEST = 50, CL = 37pF 5 ns tOEZL Output Enable High to Data or Strobe Z to Low (figure 3, 4) RTEST = 50, CL = 37pF 5.0 ns tSETUP TX Minimum required setup of Data or Strobe with respect to WrClk (figure 6) 2 ns tHOLD TX Minimum required hold of Data or Strobe with respect to WrClk (figure 6) 0 ns tINRISE3 Maximum rise time into Data/Strobe inputs (0.8V to 2V) 14 % of bit width tINFALL3 Maximum fall time into Data/Strobe inputs (0.8V to 2V) 14 % of bit width tDRST Minimum number of full clock cycles (WrClk) between rising edge of RST and rising edge of first valid data or strobe (TxDO, TxD1, TxS0, TxS1) (figure 5) 3 WrClk cycles tCRST Minimum number of full clock cycles (WrClk) that RST must remain low before RST can transition high (figure 5) 3 WrClk cycles tCO Delay between RxClk falling and data edge (figure 7) 1 ns tRLZ Delay between RST going low and CMOS output tri-state (figure 7) RTEST = 50, CL = 37pF 5 ns tRHV Delay between RST going high and CMOS output valid (figure 7)RTEST = 50, CL = 37pF 5 ns tRISE CMOS 20-80% Receiver output rise time (figure 8) CL = 37pF 1 ns tFALL CMOS 20-80% Receiver output fall time (figure 8) CL = 37pF 1 ns t S3 TxClkPMIN LVDS Rx input data to strobe separation (figure 9) 2.5 Minimum Transmit Clock period WrClkPMIN Minimum Write Clock period tCPMIN Minimum High or Low Clock Pulse Width 2 Notes: 1. Includes differential skew 2. Guaranteed by characterization 3. Specified as a design guidelines only, not tested. 4. 2.5 ns of separation requires a RXOUT Load of <= 10pF . 7 ns 5 ns 10 ns ns 50% TxClk tCDLH or tCDHL TxD+ 0V (Differential) TxDtCSS TxS+ 0V (Differential) TxStCSLH or tCSHL 80% 80% VDIFF = DOUT+ - DOUT- 0V 0V VDIFF 20% 20% tTHL tTLH Figure 2. Driver Rise and Fall times and Channel Skew DOUT+ 10pF VDD Transmit Block VSS Generator RL=100Ω 10pF TxOE RTEST 50Ωρ Figure 3. Driver Three-State Delay Time Test or Equivalent Circuit 8 DOUT- TxOE VDD VDD/2 VDD/2 0V tOEHZ tOEZH TxD+ or TxDor TxS+ or TxS- VOH 50% 50% VOS VOS 50% 50% TxD+ or TxDor TxS+ or TxS- VOL tOEZL tOELZ Figure 4. Output Enable to Data Out Timing TxClk WrClk RST tCRST tDRST TxD0 TxD1 TxS0 TxS1 Figure 5. Reset Timing Diagram T setup (Tx) T hold (Tx) TxD0 TxD1 TxS0 TxS1 WrCLK 50% Figure 6. Transmitter Input Timing Diagram 9 Do Bit Times D1 D3 D2 RxD+ RxDRxS+ RxS- RST RxClk D0 Unknown Data for first RXClk RxDR Unknown Data for first RXClk RxDF tRLZ D1 TCO tRHV Figure 7. Receiver Output Timing Diagram 10 D2 D3 VDD 80% 80% 50% 50% RxDR or RxDF 20% 20% VSS tFALL tRISE Figure 8. Receiver Output Rise and Fall Times Waveform Data tS Strobe tS Recovered Clock Figure 9. Data/Strobe Separation 11 PACKAGING 0.380 SQ. Notes: 1. All exposed metallized areas are gold plated over electrically plated nickel per MIL-PRF-38535. 2. The lid is electrically connected to VSS. 3. Lead finishes are in accordance with MIL-PRF-38535. 4. Dimension symbology is in accordance with MIL-PRF-38535. 5. Lead position and coplanarity are not measured. 6. ID mark symbol is vendor option: no alphanumerics. Figure 10. 28-pin Flatpack 12 ORDERING INFORMATION UT200SpWPHY01: SpaceWire Physical Layer Transceiver UT ***** * * * Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory option (gold or solder) Screening: (C) = Military Temperature Range flow (P) = Prototype flow (W) = Extended Industrial Temperature Range Flow (-40oC to +125oC) (X) = 28-pin Ceramic Flatpack Device Type: (200SpWPHY01) = SpaceWire Physical Layer Transceiver Notes: 1. Lead finish (A,C, or X) must be specified. 2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold). 3. Prototype flow per Aeroflex Manufacturing Flows Document. Tested at 25°C only. Lead finish is GOLD ONLY. Radiation neither tested nor guaranteed. 4. Military Temperature Range flow per Aeroflex Manufacturing Flows Document. Devices are tested at -55°C, room temp, and 125°C. Radiation neither tested nor guaranteed. 5. Extended Industrial Range flow per Aeroflex Colorado Springs Manufacturing Flows Document. Devices are tested at -40°C, room temp, and 125°C. Radiation neither tested nor guaranteed. 13 UT200SpWPHY01: SMD 5962 - 06232 * * * * Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory Option (gold or solder) Case Outline: (X) = 28-pin Ceramic Flatpack Class Designator: (Q) = QML Class Q (V) = QML Class V Device Type 01 = UT200SpWPHY01 Military Temperature Range 02 = UT200SpWPHY01 Extended Industrial Temperature Range Flow (-40oC to +125oC) Drawing Number: 06232 Total Dose: (R) = 1E5 (100 Krad)(Si) Federal Stock Class Designator: No options Notes: 1.Lead finish (A,C, or X) must be specified. 2.If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold). 3.Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. 14 Aeroflex Colordo Springs - Datasheet Definition Advanced Datasheet - Product In Development Preliminary Datasheet - Shipping Prototype Datasheet - Shipping QML & Reduced Hi-Rel COLORADO Toll Free: 800-645-8862 Fax: 719-594-8468 INTERNATIONAL Tel: 805-778-9229 Fax: 805-778-1980 NORTHEAST Tel: 603-888-3975 Fax: 603-888-4585 SE AND MID-ATLANTIC Tel: 321-951-4164 Fax: 321-951-4254 WEST COAST Tel: 949-362-2260 Fax: 949-362-2266 CENTRAL Tel: 719-594-8017 Fax: 719-594-8468 www.aeroflex.com [email protected] Aeroflex Colorado Springs, Inc., reserves the right to make changes to any products and services herein at any time without notice. Consult Aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. 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