REVISIONS LTR DESCRIPTION A DATE (YR-MO-DA) APPROVED 14-02-24 C. SAFFLE Make corrections to delta limits for VIL and VIH parameters in Table IIB. -rrp REV SHEET REV A A A A A A A A A A A SHEET 15 16 17 18 19 20 21 22 23 24 25 REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY RAJESH PITHADIA STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http://www.landandmaritime.dla.mil CHECKED BY RAJESH PITHADIA APPROVED BY CHARLES F. SAFFLE DRAWING APPROVAL DATE 14-02-11 REVISION LEVEL A MICROCIRCUIT, DIGITAL-LINEAR, VOLTAGE SUPERVISOR, MONOLITHIC SILICON SIZE CAGE CODE A 67268 SHEET DSCC FORM 2233 APR 97 5962-13206 1 OF 25 5962-E197-14 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device class Q) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 F Federal stock class designator \ 13206 RHA designator (see 1.2.1) 01 Q X C Device type (see 1.2.2) Device class designator (see 1.2.3) Case outline (see 1.2.4) Lead finish (see 1.2.5) / \/ Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device types. The device types identify the circuit function as follows: Device type Generic number 01 UT04VS33P 02 UT04VS50P Circuit function Radiation hardened, 3.3 V voltage supervisor Radiation hardened, 5.0 V voltage supervisor 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline. The case outline is as designated in MIL-STD-1835 and as follows: Outline letter X Descriptive designator See figure 1 Terminals 28 Package style Flat pack 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-13206 A REVISION LEVEL A SHEET 2 1.3 Absolute maximum ratings. 1/ Positive supply voltage (VDD): Device type 01 .............................................................................. Device type 02 .............................................................................. Voltage range on any I/O pin (VIO)..................................................... DC I/O current (IIO) ........................................................................... Power dissipation (PD) ...................................................................... Lead temperature (soldering, 10 seconds) ....................................... Junction temperature (TJ) ................................................................. Storage temperature range .............................................................. Thermal resistance, junction-to-case (θJC) ........................................ 4.8 V 7.2 V -0.3 V to (VDD + 0.3 V) ±10 mA 1.0 W +300°C +175°C -65°C to +150°C 16°C/W 1.4 Recommended operating conditions. Positive supply voltage range (VDD): Device type 01 ......................................................................... Device type 02 ......................................................................... Negative supply voltage (VSS) ........................................................... Analog input voltage range (VIN) ....................................................... Digital input voltage range (VIN) ........................................................ Case operating temperature range (TC) ............................................ 3.0 V to 3.6 V 4.5 V to 5.5 V 0V 0.6 V to 3.6 V VSS to VDD -55°C to +125°C 1.5 Radiation features. Maximum total dose available (dose rate = 50 – 300 rads(Si)/s): ........................... 300 krads(Si) 2/ Single event phenomena (SEP): 2 No single event latchup (SEL) occurs at effective LET ....................................... ≤ 110 MeV/mg/cm 3/ _____ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Radiation end point limits for the noted parameters are guaranteed only for the conditions as specified in MIL-STD-883, Method 1019, condition A to maximum total dose of 300 krads(Si). 3/ Limits are characterized at initial qualification and after any design or process changes which may affect the SEP characteristics but are not production tested. See manufacturer’s Single Event Effects test report for more information. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-13206 A REVISION LEVEL A SHEET 3 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 MIL-STD-1835 - Test Method Standard Microcircuits. Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 MIL-HDBK-780 - List of Standard Microcircuit Drawings. Standard Microcircuit Drawings. (Copies of these documents are available online at http://quicksearch.dla.mil/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. ASTM INTERNATIONAL (ASTM) ASTM F1192 - Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion Irradiation of semiconductor Devices. (Copies of these documents are available online at http://www.astm.org or from ASTM International, 100 Barr Harbor Drive, P.O. Box C700, West Conshohocken, PA, 19428-2959). 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth tables. The truth tables shall be as specified on figure 3. 3.2.4 Quad input voltage threshold selection table. The quad input voltage threshold selection table shall be as specified on figure 4. 3.2.5 Analog input resistance referenced to Vss table. The analog input resistance referenced to VSS table shall be as specified on figure 5. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-13206 A REVISION LEVEL A SHEET 4 3.2.6 Block diagrams. The block diagrams shall be as specified on figure 6. 3.2.7 Timing waveforms. The timing waveforms shall be as specified on figures 7 through 9. 3.2.8 Radiation exposure circuit. The radiation exposure circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing and acquiring activity upon request. 3.3 Electrical performance characteristics and post irradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and post irradiation parameter limits are as specified in table IA and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table IA. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in MIL-PRF-38535. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 shall be provided with each lot of microcircuits delivered to this drawing. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-13206 A REVISION LEVEL A SHEET 5 TABLE IA. Electrical performance characteristics. Test Symbol Conditions 1/ 2/ 3/ Group A Device subgroups type -55°C ≤ TC ≤ +125°C unless otherwise specified Limits Min Unit Max Power supply section Supply current IDD All VOUTX high 1, 2, 3 01, 02 1250 μA Digital inputs and outputs section Digital input low voltage VIL 1, 2, 3 01, 02 -0.3 0.3xVDD V Digital input high voltage VIH 1, 2, 3 01, 02 0.7xVDD VDD+0.3 V Manual reset (MRB) digital input low voltage VILMRB 1, 2, 3 01, 02 -0.3 0.8 V Manual reset (MRB) digital input high voltage VIHMRB 1, 2, 3 01, 02 2.0 VDD+0.3 V Manual reset (MRB) input voltage hysteresis VHYSTMRB 1, 2, 3 01, 02 60 Manual reset (MRB) pull-up current IMRB MRB = 0 V, VDD = 3.6 V for max IMRB 1, 2, 3 01 225 MRB = 0 V, VDD = 5.5 V for max IMRB 1, 2, 3 02 330 VDD = 3.6 V, ISINK = 1 mA 1, 2, 3 01 0.3 02 0.3 Open drain digital output low VOL voltage VDD = 5.5 V, ISINK = 1 mA Charge current CRESET 4/ ICH_RESET mV VDD = 3.0 V 1, 2, 3 01 0.35 1.25 VDD = 5.0 V 1, 2, 3 02 0.35 1.25 μA V μA μA Digital output leakage current low IOZL 1, 2, 3 01, 02 -1 1 Digital output leakage current high IOZH 1, 2, 3 01, 02 -1 1 Digital input leakage current low IIL 1, 2, 3 01, 02 -1 1 Digital input leakage current high IIH 1, 2, 3 01, 02 -1 1 Charge current CDLY 4/ ICH_CDLY VDD = 3.0 V 1, 2, 3 01 0.55 1.90 VDD = 5.0 V 1, 2, 3 02 0.55 1.90 μA μA μA μA Threshold voltage CDLYX 4/ VTH_CDLY CDLY rising 1, 2, 3 01, 02 1.17 1.23 V Threshold voltage CRESET 4/ VTH_CRESET CRESET rising 1, 2, 3 01, 02 1.17 1.23 V Reference threshold voltage 4/ VRFTH 1, 2, 3 01, 02 585 615 mV See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-13206 A REVISION LEVEL A SHEET 6 TABLE IA. Electrical performance characteristics – Continued. Test Symbol Conditions 1/ 2/ 3/ -55°C ≤ TC ≤ +125°C unless otherwise specified Group A Device subgroups type 3.3 V threshold, TOL = 0 1, 2, 3 Limits Unit Min Max 2.97 3.135 3.3 V threshold, TOL = 1 2.805 2.970 2.5 V threshold, TOL = 0 2.25 2.375 2.5 V threshold, TOL = 1 2.125 2.250 1.8 V threshold, TOL = 0 1.620 1.710 1.8 V threshold, TOL = 1 1.530 1.620 1.5 V threshold, TOL = 0 1.350 1.425 1.5 V threshold, TOL = 1 1.275 1.350 1.2 V threshold, TOL = 0 1.080 1.140 1.2 V threshold, TOL = 1 1.020 1.080 1.0 V threshold, TOL = 0 0.90 0.950 1.0 V threshold, TOL = 1 0.85 0.915 Analog inputs section Analog threshold under-voltage case VTH_VIN Functional tests 01, 02 7, 8 See 4.4.1c V 01, 02 AC characteristics section VIN+ to VOUT propagation delay 4/ tDELAY+ VIN rising, CDLY open 9, 10, 11 01, 02 11 60 VIN+ to VOUT propagation delay tDELAY+ VIN rising, Cdly capacitance 9, 10, 11 value on CDLYx = 112 pF, 01, 02 81 263 VIN- to VOUT propagation delay tDELAY- VIN falling, see figure 9 9, 10, 11 01, 02 Reset timeout period tRP CRESET open 9, 10, 11 01, 02 37 170 tRP Creset capacitance value on CRESET = 65 pF, 9, 10, 11 01, 02 100 283 μs μs see figure 9 4/ Reset timeout period μs 40 μs μs see figures 7 and 9 EN+ to VOUT propagation delay 4/ tON EN rising to VOUT going high, CDLY open 9, 10, 11 01, 02 11 60 EN+ to VOUT propagation delay tON EN rising to VOUT going high, Cdly capacitance value on CDLYx = 112 pF, 9, 10, 11 01, 02 81 263 EN- to VOUT propagation delay tOFF 9, 10, 11 01, 02 μs μs see figure 7 EN falling to VOUT deasserted, see figure 7 μs 4 See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-13206 A REVISION LEVEL A SHEET 7 TABLE IA. Electrical performance characteristics – Continued. Test Symbol Conditions 1/ 2/ 3/ Group A Device subgroups type -55°C ≤ TC ≤ +125°C unless otherwise specified Limits Min Unit Max AC characteristics section – continued. MRB- to RESET/RESETB propagation delay tMRST MRB falling to 9, 10, 11 01, 02 μs 5 RESET/RESETB asserted, see figure 8 μs Minimum MRB input pulse width tMPW See figure 8 9, 10, 11 01, 02 2.5 MRB+ to RESET/RESETB propagation delay tMRP MRB rising to RESET/RESETB deasserted, 9, 10, 11 01, 02 3 VINx to RESET/RESETB asserted tRST_DELAY 9, 10, 11 01, 02 40 ENx or MRB glitch rejection tGLITCH 9, 10, 11 01, 02 270 ns VINx glitch rejection 4/ tGLITCH_VINx 9, 10, 11 01, 02 800 ns μs see figure 8 VIN falling, see figure 9 μs 1/ Unless otherwise specified, VDD = 3.0 V to 3.6 V for device type 01. VDD = 4.5 V to 5.5 V for device type 02. 2/ RHA device types 01 and 02 supplied to this drawing will meet all levels M, D, P, L, R, and F of irradiation. However, device types 01 and 02 are only tested at the F level in accordance with MIL-STD-883, method 1019, condition A (see 1.5 herein). Pre and Post irradiation values are identical unless otherwise specified in Table IA. When performing post irradiation electrical measurements for any RHA level, TA = +25°C. 3/ RESET, RESETB, VOUT1, VOUT2, VOUT3, and VOUT4 guaranteed to be in the correct state for VDD down to 1.2 V 4/ Guaranteed by design or process but not tested. TABLE IB. SEP test limits. 1/ Device type 01 02 No SEL, effective linear energy transfer (LET) SEP Temperature (TC) VDD SEL +125°C 3.6 V ≤ 110 MeV/mg/cm SEL +125°C 5.5 V ≤ 110 MeV/mg/cm 2 2 1/ For SEP test conditions, see 4.4.4.2 herein. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-13206 A REVISION LEVEL A SHEET 8 Case X FIGURE 1. Case outline. FIGURE 1. Case outline. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-13206 A REVISION LEVEL A SHEET 9 Case X Dimensions Inches Millimeters Min Max Min Max A ---- 0.110 ---- 2.80 b 0.006 0.010 0.15 0.25 c 0.004 0.007 0.10 0.18 D 0.375 0.384 9.55 9.75 E 0.375 0.384 9.55 9.75 E2 0.274 0.286 6.96 7.26 E3 0.030 --- 0.76 --- e 0.025 BSC 0.635 BSC H 0.002 0.014 0.05 0.35 L 0.270 0.360 6.86 9.14 Q 0.002 0.020 0.05 0.51 S1 0.009 ---- 0.13 ---- T 0.033 NOM 0.84 NOM T1 0.018 NOM 0.46 NOM N 28 28 NOTES: 1. The U.S. government preferred system of measurement is the metric SI system. However, since this item was originally designed using the inch-pound units of measurement, in the event of conflict between the metric and inch-pound units, the inch-pound units shall take precedence. 2. All exposed metallized areas are gold plated over electrically plated nickel per MIL-PRF-38535. 3. The seal ring is electrically connected to VSS. 4. Lead finishes are in accordance with MIL-PRF-38535. 5. Dimension symbology is in accordance with MIL-PRF-38535. 6. N is the maximum number of terminal positions. FIGURE 1. Case outline – Continued. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-13206 A REVISION LEVEL A SHEET 10 Device types 01 Case Outline 02 X Terminal Number Terminal symbol Terminal symbol 1 EN1 EN1 2 VIN1 VIN1 3 EN3 EN3 4 VIN3 VIN3 5 NC VDD_3V 6 OVSH OVSH 7 TH1 TH1 8 TH0 TH0 9 TOL TOL 10 EN2 EN2 11 VIN2 VIN2 12 EN4 EN4 13 VIN4 VIN4 14 VSS VSS 15 CDLY4 CDLY4 16 VOUT4 VOUT4 17 CDLY2 CDLY2 18 VOUT2 VOUT2 19 RESET RESET 20 CRESET CRESET 21 RESETB RESETB 22 INV INV 23 MRB MRB 24 CDLY3 CDLY3 25 VOUT3 VOUT3 26 CDLY1 CDLY1 27 VOUT1 VOUT1 28 VDD VDD NC = No connection. FIGURE 2. Terminal connections. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-13206 A REVISION LEVEL A SHEET 11 Terminal symbol Type EN1 Digital input VIN1 Analog input EN3 Digital input VIN3 Analog input Description Active high enable for VIN1. Setting this pin low forces VOUT1 low regardless of the value of VIN1. Setting this pin high enables the monitor circuitry for VIN1. Analog input VIN1. When enabled, the voltage input is monitored for an under-voltage condition. The condition is output on VOUT1. Active high enable for VIN3. Setting this pin low forces VOUT3 low when OVSH = 0 (VOUT3 is forced low when OVSH = 1) regardless of the value of VIN3. Setting this pin high enables the monitor circuitry for VIN3. Analog input VIN3. When enabled and dependent on the mode of operation (OVSH), the voltage input is monitored for an under-voltage or over-voltage condition. The condition is output on VOUT3 when OVSH = 0 and on VOUT1 when OVSH = 1. NC NC VDD_3V 3 V regulated supply 3.3 V internal regulator output voltage. This is an internal voltage reference only. It is not provided as a regulated supply for external use. OVSH Digital input Over-voltage pin. When OVSH = 1, the over-voltage mode is enabled. This allows for the monitoring of both over-voltage and under-voltage of two supplies. Inputs VIN1 and VIN2 function normally, while VIN3 is used to monitor an over-voltage condition in conjunction with the VIN1 source and VIN4 likewise for the VIN2 source. When OVSH = 0 all four inputs, VIN1, VIN2, VIN3, and VIN4 monitor under-voltage. TH1 Digital input Digital Threshold select 1. Used with TH0 to select one of four analog input voltage thresholds. See figure 4. TH0 Digital input Digital Threshold select 0. Used with TH1 to select one of four analog input voltage thresholds. See figure 4. TOL Digital input Threshold tolerance select sets the accuracy of the threshold to 5 percent below the nominal value by connecting TOL to logic 0. Connecting TOL to logic 1 sets the threshold voltage to 10 percent below the nominal value. EN2 Digital input Active high enable for VIN2. Setting this pin low forces VOUT2 low regardless of the value of VIN2. Setting this pin high enables the monitor circuitry for VIN2. VIN2 Analog input Analog input VIN2. When enabled, the voltage input is monitored for an under-voltage condition. The condition is output on VOUT2. EN4 Digital input Active high enable for VIN4. Setting this pin low forces VOUT4 low when OVSH = 0 (VOUT4 is forced low when OVSH = 1) regardless of the value of VIN4. Setting this pin high enables the monitor circuitry for VIN4. No connection. FIGURE 2. Terminal connections – Continued. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-13206 A REVISION LEVEL A SHEET 12 Terminal symbol VIN4 Type Description Analog input Analog input VIN4. When enabled and dependent on the mode of operation (OVSH), the voltage input is monitored for an under-voltage or over-voltage condition. The condition is output on VOUT4 when OVSH = 0 and on VOUT2 when OVSH = 1. VSS Supply GND CDLY4 Analog output External capacitor delay connection. Allows adjustment of the VOUT4 timing after VIN4 becomes valid, when OVSH = 0. VOUT4 Open drain digital output Output of VIN4 monitor when OVSH = 0; inactive when OVSH = 1. With INV = 0, logic 1 indicates that the VIN4 input is at a valid level. With INV = 1, logic 0 indicates that VIN4 is at a valid level. Device contains active pull-down device; requires external pull-up. CDLY2 Analog output External capacitor delay connection. Allows adjustment of the VOUT2 timing after VIN2 becomes valid. VOUT2 Open drain digital output When OVSH = 0, it indicates the signal state of the VIN2 monitor. When OVSH = 1, it indicates the combined signal states for VIN2 and VIN4 (under-voltage and over-voltage detection). Device contains active pull-down device; requires external pull-up. RESET Open drain digital output Active high output indicating a system reset condition is activated by appropriate condition on VOUTx, ENx, or MRB pin. Device contains active pull-down device; requires external pull-up. CRESET Analog output External capacitor delay connection. Allows adjustment of RESET timeout, which is the time RESET is held after all reset input conditions are cleared. RESETB Open drain digital output Active low output indicating a system reset condition is activated by appropriate condition on VOUTx, ENx, or MRB pin. Device contains active pull-down device; requires external pull-up. INV Digital input When logic 1, inverts the sense of the VOUT3 and VOUT4 outputs. MRB Digital input internal pull-up Manual Reset active low input. This forces the RESET/RESETB pins to their active state. CDLY3 Analog output External capacitor delay connection. Allows adjustment of the VOUT3 timing after VIN3 becomes valid, when OVSH = 0. ASIC ground connection. FIGURE 2. Terminal connections – Continued. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-13206 A REVISION LEVEL A SHEET 13 Terminal symbol Type Description VOUT3 Open drain digital output Output of VIN3 monitor when OVSH = 0; inactive when OVSH = 1. With INV = 0, logic 1 indicates that the VIN3 input is at a valid level. With INV = 1, logic 0 indicates that VIN3 is at a valid level. Device contains active pull-down device; requires external pull-up. CDLY1 Analog output External capacitor delay connection. Allows adjustment of the VOUT1 timing after VIN1 becomes valid. VOUT1 Open drain digital output When OVSH = 0, it indicates the signal state of the VIN1 monitor. When OVSH = 1, it indicates the combined signal states for VIN1 and VIN3 (under-voltage and over-voltage detection). Device contains active pull-down device; requires external pull-up. VDD Supply ASIC supply voltage. FIGURE 2. Terminal connections – Continued. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-13206 A REVISION LEVEL A SHEET 14 Inputs Outputs ENx INV VINx VOUT1 VOUT2 VOUT3 VOUT4 0 0 VINx < VTH 0 0 0 0 1 0 VINx < VTH 0 0 0 0 0 0 VINx > VTH 0 0 0 0 1 0 VINx > VTH 1 1 1 1 0 1 VINx < VTH 0 0 1 1 1 1 VINx < VTH 0 0 1 1 0 1 VINx > VTH 0 0 1 1 1 1 VINx > VTH 1 1 0 0 NOTE: Effect of INV on VOUT (TOL = X and OVSH = 0). ENx and VINx refer to the corresponding output. Inputs Outputs ENx/ENy INV VINx/VINy VOUT1 VOUT2 VOUT3 VOUT4 0 0 Any VINx and VINy 0 0 X X 1 0 0 0 X X 0 0 Any VINx and VINy 0 0 X X 1 0 VTH < VINx and VINy < VTH_OVRV 1 1 X X 0 1 Any VINx and VINy 0 0 X X 1 1 0 0 X X 0 1 Any VINx and VINy 0 0 X X 1 1 VTH < VINx and VINy < VTH_OVRV 1 1 X X VINx < VTH or VINy > VTH_OVRV VINx < VTH or VINy > VTH_OVRV NOTES: 1. Effect of INV on VOUT (TOL = X and OVSH = 1). ENx/ENy refers to EN1 and EN3 or EN2 and EN4 respectively. VINx/VINy refers to VIN1 and VIN3 or VIN2 and VIN4 respectively. VOUT3/VOUT4 are not used in over-voltage mode. 2. Having all four enables low is an invalid state for the device operation. This state will not cause any harm to the device or system, but operation may not be as expected. 3. For OVSH = 1, VTH_OVRV is the threshold which is set with external resistors to either the VIN3 or VIN4 input to monitor an over-voltage condition in conjunction with the under-voltage monitor by VIN1 or VIN2, respectively. FIGURE 3. Truth tables. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-13206 A REVISION LEVEL A SHEET 15 TH1 TH0 VIN1 VIN2 VIN3 VIN4 0 0 3.3 V 2.5 V 1.8 V 1.5 V 0 1 3.3 V 1.8 V 1.5 V 1.2 V 1 0 3.3 V 1.5 V 1.2 V 1.0 V 1 1 ADJ ADJ ADJ ADJ NOTE: In adjustable mode (ADJ, TH1=TH0=1), external RT & RB resistors are used to adjust the analog threshold voltage. VTH = [(RB/(RT+RB) ± 2.5%]*VRFTH. RT is the external resistor from the analog threshold voltage monitored to the VINx pin. RB is the external resistor from the VINx pin to ASIC GND. FIGURE 4. Quad input voltage threshold selection. ANALOG INPUT RESISTANCE NOTE: THRESHOLD SELECT MIN MAX UNIT TH1 TH0 RIN1 0 0 94 160 kΩ RIN2 0 0 282 485 kΩ RIN3 0 0 205 355 kΩ RIN4 0 0 172 295 kΩ RIN1 0 1 94 160 kΩ RIN2 0 1 205 355 kΩ RIN3 0 1 172 295 kΩ RIN4 0 1 137 235 kΩ RIN1 1 0 94 160 kΩ RIN2 1 0 172 295 kΩ RIN3 1 0 137 235 kΩ RIN4 1 0 114 197 kΩ Resistance values listed are the estimated input resistances, referenced to VSS, seen at each of the VInx pins. The resistance can be used to estimate the expected load current at that VInx input. FIGURE 5 . Analog input resistance referenced to Vss. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-13206 A REVISION LEVEL A SHEET 16 Device type 01 FIGURE 6. Block diagrams. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-13206 A REVISION LEVEL A SHEET 17 Device type 02 FIGURE 6. Block diagrams – continued. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-13206 A REVISION LEVEL A SHEET 18 FIGURE 7. ENx timing waveform. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-13206 A REVISION LEVEL A SHEET 19 FIGURE 8. MRB timing waveform. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-13206 A REVISION LEVEL A SHEET 20 FIGURE 9. VINx timing waveform. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-13206 A REVISION LEVEL A SHEET 21 4. VERIFICATION 4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. 4.2.1 Additional criteria for device classes Q and V. a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. b. Interim and final electrical test parameters shall be as specified in table IIA herein. c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in MIL-PRF-38535, appendix B. 4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). 4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. 4.4.1 Group A inspection. a. Tests shall be as specified in table IIA herein. b. Subgroups 4, 5, and 6 in table I, method 5005 of MIL-STD-883 shall be omitted. c. For device classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the device. 4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein. 4.4.2.1 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-STD-883. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-13206 A REVISION LEVEL A SHEET 22 TABLE IIA. Electrical test requirements. Test requirements Interim electrical parameters (see 4.2) Final electrical parameters (see 4.2) Group A test requirements (see 4.4) Group C end-point electrical parameters (see 4.4) Group D end-point electrical parameters (see 4.4) Group E end-point electrical parameters (see 4.4) Subgroups (in accordance with MIL-PRF-38535, table III) Device Device class Q class V 1, 7, 9 1, 7, 9 1, 2, 3, 7, 8, 9, 10, 11 1/ 1, 2, 3, 7, 8, 9, 10, 11 1, 2, 3, 7, 8, 9, 10, 11 1, 2, 3, 7, 8, 9, 10, 11 1, 7, 9 1, 2, 3, 7, 8, 9, 10, 11 2/ 3/ 1, 2, 3, 7, 8, 9, 10, 11 1, 2, 3, 7, 8, 9, 10, 11 3/ 1, 2, 3, 7, 8, 9, 10, 11 1, 7, 9 1/ PDA applies to subgroup 1. 2/ PDA applies to subgroups 1 and 9. 3/ Delta limits as specified in table IIB shall be required where specified, and the delta values shall be computed with reference to previous interim electrical parameters. For device class V, performance of delta limits shall be specified in the manufacturer’s QM plan. TABLE IIB. Burn-in and operating life test delta parameters. TA = +25°C. 1/ Parameters Symbol Device types Delta limits Supply current IDD 01, 02 ±125 µA IIL, IIH 01, 02 ±100 nA IMRB 01 ±22.5 µA IMRB 02 ±33 µA VIL 01 ±150mV VIL 02 ±250mV VIH 01 ±150mV VIH 02 ±250mV VILMRB 01, 02 ±150mV VIHMRB 01, 02 ±150mV Digital input leakage current Manual reset (MRB) pull-up current Manual reset (MRB) pull-up current Digital input low voltage Digital input low voltage Digital input high voltage Digital input high voltage Manual reset (MRB) digital input low voltage Manual reset (MRB) digital input high voltage 1/ These parameters shall be recorded before and after the required burn-in and life tests to determine delta limits. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-13206 A REVISION LEVEL A SHEET 23 4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein. 4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured (see 3.5 herein). a. End-point electrical parameters shall be as specified in table IIA herein. b. For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as specified in MIL-PRF-38535 for the RHA level being tested. All device classes must meet the postirradiation end-point electrical parameter limits as defined in table IA at TA = +25°C ±5°C, after exposure, to the subgroups specified in table IIA herein. 4.4.4.1 Total dose irradiation testing. Total dose irradiation testing shall be performed in accordance with MIL-STD-883 method 1019, condition A, and as specified herein. 4.4.4.1.1 Accelerated annealing test. Accelerated annealing tests shall be performed on all devices requiring a RHA level greater than 5k rads (Si). The post-anneal end-point electrical parameter limits shall be as specified in table IA herein and shall be the pre-irradiation end-point electrical parameter limit at 25°C ±5°C. Testing shall be performed at initial qualification and after any design or process changes which may affect the RHA response of the device. 4.4.4.2 Single event phenomena (SEP). When specified in the purchase order or contract, SEP testing shall be required on class V devices. SEP testing shall be performed on the Standard Evaluation Circuit (SEC) or alternate SEP test vehicle as approved by the qualifying activity at initial qualification and after any design or process changes which may affect the upset or latchup characteristics. Test four devices with zero failures. ASTM F1192 may be used as a guideline when performing SEP testing. The test conditions for SEP are as follows: a. The ion beam angle of incidence shall be between normal to the die surface and 60° to the normal, inclusive (for example, 0° ≤ angle ≤ 60°). No shadowing of the ion beam due to fixturing or package related effects is allowed. 7 2 b. The fluence shall be ≥ 100 errors or ≥ 10 ions/cm . 2 5 2 c. The flux shall be between 10 and 10 ions/cm /s. The cross-section shall be verified to be flux independent by measuring the cross-section at two flux rates which differ by at least an order of magnitude. d. The particle range shall be ≥ 20 micron in silicon. e. The test temperature shall be +125°C and the maximum rated operating temperature ±10°C. f. Bias conditions shall be defined by the manufacturer for latchup measurements. g. For SEL test limits, see Table IB herein. 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes Q and V. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-13206 A REVISION LEVEL A SHEET 24 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor prepared specification or drawing. 6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal. 6.3 Record of users. Military and industrial users should inform DLA Land and Maritime when a system application requires configuration control and which SMD's are applicable to that system. DLA Land and Maritime will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic devices (FSC 5962) should contact DLA Land and Maritime-VA, telephone (614) 692-8108. 6.4 Comments. Comments on this drawing should be directed to DLA Land and Maritime-VA , Columbus, Ohio 43218-3990, or telephone (614) 692-0540. 6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in MIL-PRF-38535 and MIL-HDBK-1331. 6.6 Sources of supply. 6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in MIL-HDBK-103 and QML-38535. The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DLA Land and Maritime -VA and have agreed to this drawing. 6.7 Additional information. When applicable, a copy of the following additional data shall be maintained and available from the device manufacturer: a. RHA upset levels. b. Test conditions (SEP). c. Occurrence of latchup (SEL). STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-13206 A REVISION LEVEL A SHEET 25 STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 14-02-24 Approved sources of supply for SMD 5962-13206 are listed below for immediate acquisition information only and shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DLA Land and Maritime -VA. This information bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. DLA Land and Maritime maintains an online database of all current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/. Standard microcircuit drawing PIN 1/ Vendor CAGE number Vendor similar PIN 2/ 5962R1320601QXC 65342 UT04VS33PQXC 5962F1320601QXC 65342 UT04VS33PQXC 5962R1320601VXC 65342 UT04VS33PVXC 5962F1320601VXC 65342 UT04VS33PVXC 5962R1320602QXC 65342 UT04VS50PQXC 5962F1320602QXC 65342 UT04VS50PQXC 5962R1320602VXC 65342 UT04VS50PVXC 5962F1320602VXC 65342 UT04VS50PVXC 1/ The lead finish shown for each PIN representing a hermetic package is the most readily available from the manufacturer listed for that part. If the desired lead finish is not listed contact the vendor to determine its availability. 2/ Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. Vendor CAGE number 65342 Vendor name and address Aeroflex Colorado Springs, Inc. 4350 Centennial Blvd. Colorado Springs, CO 80907-3486 The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in the information bulletin.