LTC3418 8A, 4MHz, Monolithic Synchronous Step-Down Regulator DESCRIPTION FEATURES n n n n n n n n n n n n n n High Efficiency: Up to 95% 8A Output Current 2.25V to 5.5V Input Voltage Range Low RDS(ON) Internal Switch: 35mΩ Tracking Input to Provide Easy Supply Sequencing Programmable Frequency: 300kHz to 4MHz 0.8V ±1% Reference Allows Low Output Voltage Quiescent Current: 380μA Selectable Forced Continuous/Burst Mode® Operation with Adjustable Burst Clamp Synchronizable Switching Frequency Low Dropout Operation: 100% Duty Cycle Power Good Output Voltage Monitor Overtemperature Protected 38-Lead Low Profile (0.75mm) Thermally Enhanced QFN (5mm × 7mm) Package APPLICATIONS n n n n n Microprocessor, DSP and Memory Supplies Distributed 2.5V, 3.3V and 5V Power Systems Automotive Applications Point of Load Regulation Notebook Computers The LTC®3418 is a high efficiency, monolithic synchronous step-down DC/DC converter utilizing a constant frequency, current mode architecture. It operates from an input voltage range of 2.25V to 5.5V and provides a regulated output voltage from 0.8V to 5V while delivering up to 8A of output current. The internal synchronous power switch increases efficiency and eliminates the need for an external Schottky diode. Switching frequency is set by an external resistor or can be synchronized to an external clock. OPTI-LOOP® compensation allows the transient response to be optimized over a wide range of loads and output capacitors. The LTC3418 can be configured for either Burst Mode operation or forced continuous operation. Forced continuous operation reduces noise and RF interference while Burst Mode operation provides high efficiency by reducing gate charge losses at light loads. In Burst Mode operation, external control of the burst clamp level allows the output voltage ripple to be adjusted according to the requirements of the application. A tracking input in the LTC3418 allows for proper sequencing with respect to another power supply. L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Burst Mode and OPTI-LOOP are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131, 6724174. TYPICAL APPLICATION 2.5V/8A Step-Down Regulator Efficiency and Power Loss vs Load Current 100 CIN 47μF ×4 SVIN TRACK PVIN 2.2M SW COUT 100μF ×2 LTC3418 30.1k RUN/SS ITH 1000pF 0.2μH 4.99k 820pF PGOOD PGND SGND SYNC/MODE VFB 332Ω VOUT 2.5V 8A 100000 EFFICIENCY 70 60 1000 POWER LOSS 100 50 40 4.32k 10 30 VIN = 3.3V VOUT = 2.5V 3418 TA01a 1.69k 10000 80 20 0.01 POWER LOSS (mW) RT 90 EFFICIENCY (%) VIN 2.8V TO 5.5V 0.1 1 LOAD CURRENT (A) 1 10 3418 TA01b 3418fb 1 LTC3418 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) Input Supply Voltage ................................... –0.3V to 6V ITH, RUN/SS, VFB Voltages ......................... –0.3V to VIN SYNC/MODE Voltages ................................ –0.3V to VIN TRACK Voltage ........................................... –0.3V to VIN SW Voltage .................................. –0.3V to (VIN + 0.3V) Operating Temperature Range (Note 2) ...............................................–40°C to 85°C Junction Temperature (Note 5) ............................. 125°C Storage Temperature Range.................. –65°C to 125°C PGND PGND PGND TRACK PGND PGND PGND TOP VIEW 38 37 36 35 34 33 32 SW 1 31 SW SW 2 30 SW PVIN 3 29 PVIN PVIN 4 28 PVIN PGOOD 5 27 SYNC/MODE RT 6 26 ITH 39 RUN/SS 7 25 VFB SGND 8 24 SVIN PVIN 9 23 PVIN PVIN 10 22 PVIN SW 11 21 SW 20 SW SW 12 PGND PGND PGND VREF PGND PGND PGND 13 14 15 16 17 18 19 UHF PACKAGE 38-LEAD (7mm × 5mm) PLASTIC QFN TJMAX = 125°C, θJA = 34°C/W, θJC = 1°C/W EXPOSED PAD (PIN 39) IS PGND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3418EUHF#PBF LTC3418EUHF#TRPBF 3418 38-Lead (7mm × 5mm) Plastic QFN –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ELECTRICAL CHARACTERISTICS The l indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 3.3V. (Note 2) SYMBOL PARAMETER VIN Input Voltage Range VFB Regulated Feedback Voltage IFB Feedback Input Current ΔVFB Reference Voltage Line Regulation VIN = 2.5V to 5.5V (Note 3) VLOADREG Output Voltage Load Regulation Measured in Servo Loop, VITH = 0.36V Measured in Servo Loop, VITH = 0.84V V TRACK Tracking Voltage Offset V TRACK = 0.4V Tracking Voltage Range CONDITIONS MIN TYP 2.25 0°C ≤ TA ≤ 85°C (Note 3) l 0.792 0.784 l l 0 MAX UNITS 5.5 V 0.800 0.800 0.808 0.816 V V 100 200 nA 0.04 0.2 %/V 0.02 –0.02 0.2 –0.2 % % 15 mV 0.8 V 3418fb 2 LTC3418 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 3.3V. (Note 2) SYMBOL PARAMETER TYP MAX UNITS ITRACK TRACK Input Current CONDITIONS MIN 100 200 nA ΔVPGOOD Power Good Range ±7.5 ±9 % RPGOOD Power Good Resistance 100 150 Ω IQ Input DC Bias Current Active Current Shutdown (Note 4) VFB = 0.7V, VITH = 1V VRUN = 0V 380 0.03 450 1.5 μA μA fOSC Switching Frequency Switching Frequency Range ROSC = 69.8kΩ (Note 6) 0.88 0.3 1 1.12 4 MHz MHz fSYNC SYNC Capture Range (Note 6) 0.3 4 MHz RPFET RDS(ON) of P-Channel FET ISW = 600mA 35 50 mΩ RNFET RDS(ON) of N-Channel FET ISW = – 600mA 25 35 mΩ ILIMIT Peak Current Limit VUVLO Undervoltage Lockout Threshold VREF Reference Output ILSW SW Leakage Current VRUN RUN Threshold Internal Reference Voltage vs Temperature 0.7995 40 45 0.7990 35 1.219 1.250 1.281 V 0.1 1 μA 0.65 0.8 V 0.7985 0.7980 0.7975 0.7970 0.7965 100 120 3418 G01 PFET 30 NFET 25 20 15 VIN = 3.3V 35 20 15 10 5 3.25 3.75 4.25 4.75 INPUT VOLTAGE (V) 5.25 3418 G02 NFET 25 5 2.75 PFET 30 10 0 2.25 V 40 ON-RESISTANCE (mΩ) ON-RESISTANCE (mΩ) REFERENCE VOLTAGE (V) 2.25 On-Resistance vs Temperature 50 20 40 60 80 TEMPERATURE (°C) 2 TA = 25°C unless otherwise noted. Switch On-Resistance vs Input Voltage VIN = 3.3V A Note 3: The LTC3418 is tested in a feedback loop that adjusts VFB to achieve a specified error amplifier output voltage (ITH). Note 4: Dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. Note 5: TJ is calculated from the ambient temperature TA and power dissipation PD as follows: LTC3418: TJ = TA + (PD)(34°C/W) Note 6: This parameter is guaranteed by design and characterization. 45 0 1.75 0.5 TYPICAL PERFORMANCE CHARACTERISTICS 0.7960 –40 –20 17 VRUN = 0V, VIN = 5.5V Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3418 is guaranteed to meet performance specifications from 0°C to 85°C. Specifications over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. 0.8000 12 0 –40 –20 0 20 40 60 80 TEMPERATURE (°C) 100 120 3418 G03 3418fb 3 LTC3418 TYPICAL PERFORMANCE CHARACTERISTICS Quiescent Current vs Input Voltage Frequency vs ROSC 5.0 500 4500 4.5 450 4000 4.0 400 3.5 3.0 2.5 2.0 NFET 1.5 1.0 PFET 300 250 200 150 0 2.25 500 3.25 3.75 4.25 4.75 INPUT VOLTAGE (V) 2.75 2.5 5.25 3 4 4.5 3.5 INPUT VOLTAGE (V) 980 960 1080 90 1000 980 960 940 920 920 100000 EFFICIENCY 70 1000 60 POWER LOSS 10 2.75 3.25 3.75 4.25 4.75 INPUT VOLTAGE (V) VIN = 3.3V VOUT = 2.5V 20 0.01 5.25 0.1 1 LOAD CURRENT (A) Efficiency vs Load Current Efficiency vs Load Current 100 100 90 90 90 80 80 70 70 Burst Mode OPERATION 60 50 40 70 60 50 40 30 30 30 20 20 20 VIN = 3.3V VOUT = 2.5V 0 0.01 10 0.1 1 LOAD CURRENT (A) 10 3418 G10 0 0.01 5V 80 5V EFFICIENCY (%) EFFICIENCY (%) 40 10 3.3V 3.3V 50 FORCED CONTINUOUS VOUT = 2.5V 0.1 1 LOAD CURRENT (A) 1 10 3418 G09 3418 G08 Efficiency vs Load Current FORCED CONTINUOUS 100 50 30 3418 G07 60 10000 40 900 2.25 250 210 80 1020 940 100 120 130 170 ROSC (kΩ) Efficiency and Power Loss vs Load Current EFFICIENCY (%) FREQUENCY (kHz) 1000 90 POWER LOSS (mW) 1020 50 3418 G06 100 1040 20 40 60 80 TEMPERATURE (°C) 10 1100 1040 0 0 5.5 Frequency vs Input Voltage VIN = 3.3V 900 –40 –20 5 3418 G05 1060 EFFICIENCY (%) 1500 0 1060 100 2000 50 Frequency vs Temperature 1080 2500 1000 3418 G04 1100 3000 100 0.5 VIN = 3.3V 3500 350 FREQUENCY (kHz) QUIESCENT CURRENT (μA) LEAKAGE CURRENT (nA) Switch Leakage vs Input Voltage FREQUENCY (kHz) TA = 25°C unless otherwise noted. 10 3418 G11 10 Burst Mode OPERATION VOUT = 2.5V 0 0.01 0.1 1 LOAD CURRENT (A) 10 3418 G12 3418fb 4 LTC3418 TYPICAL PERFORMANCE CHARACTERISTICS Load Regulation 12 0 10 –0.05 8 –0.10 ΔVOUT/VOUT (%) PEAK INDUCTOR CURRENT (A) Peak Inductor Current vs Burst Clamp Voltage 6 4 Load Step Transient VIN = 3.3V VOUT = 1.8V f = 1MHz OUTPUT VOLTAGE 100mV/DIV –0.15 INDUCTOR CURRENT 5A/DIV –0.20 5V 2 0 TA = 25°C unless otherwise noted. –0.25 3.3V 0 0.1 0.2 0.3 0.4 0.5 VBCLAMP (V) 0.6 0.7 0.8 VIN = 3.3V 20μs/DIV VOUT = 2.5V LOAD STEP: 800mA TO 8A –0.30 0 1 2 6 5 4 3 LOAD CURRENT (A) 3418 G13 7 Burst Mode Operation Start-Up Transient OUTPUT VOLTAGE 100mV/DIV INDUCTOR CURRENT 5A/DIV OUTPUT VOLTAGE 500mV/DIV INDUCTOR CURRENT 1A/DIV VIN = 3.3V 40μs/DIV VOUT = 2.5V LOAD STEP: 3A TO 8A 8 3418 G14 Load Step Transient OUTPUT VOLTAGE 100mV/DIV 3418 G16 3418 G15 INDUCTOR CURRENT 2A/DIV VIN = 3.3V VOUT = 2.5V LOAD: 200mA 20μs/DIV 3418 G17 VIN = 3.3V VOUT = 2.5V LOAD: 8A 1ms/DIV 3418 G18 PIN FUNCTIONS SW (Pins 1, 2, 11, 12, 20, 21, 30, 31): Switch Node Connection to Inductor. This pin connects to the drains of the internal main and synchronous power MOSFET switches. PVIN (Pins 3, 4, 9, 10, 22, 23, 28, 29): Power Input Supply. Decouple these pins to PGND with capacitors on all four corners of the package. PGOOD (Pin 5): Power Good Output. Open-drain logic output that is pulled to ground when the output voltage is not within ±7.5% of regulation point. RT (Pin 6): Oscillator Resistor Input. Connecting a resistor to ground from this pin sets the switching frequency. RUN/SS (Pin 7): Run Control and Soft-Start Input. Forcing this pin below 0.5V shuts down the LTC3418. In shutdown all functions are disabled drawing <1.5μA of supply current. A capacitor to ground from this pin sets the ramp time to full output current. SGND (Pin 8): Signal Ground. All small-signal components and compensation components should connect to this ground, which in turn connects to PGND at one point. PGND (Pins 13, 14, 15, 17, 18, 19, 32, 33, 34, 36, 37, 38): Power Ground. Connect this pin closely to the (–) terminal of CIN and COUT. 3418fb 5 LTC3418 PIN FUNCTIONS VREF (Pin 16): Reference Output. Decouple this pin with a 2.2μF capacitor. SVIN (Pin 24): Signal Input Supply. Decouple this pin to SGND with a capacitor. VFB (Pin 25): Feedback Pin. Receives the feedback voltage from a resistive divider connected across the output. ITH (Pin 26): Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. Nominal voltage range for this pin is from 0.2V to 1.4V with 0.4V corresponding to the zero-sense voltage (zero current). SYNC/MODE (Pin 27): Mode Select and External Clock Synchronization Input. To select Forced Continuous, tie to SVIN. Connecting this pin to a voltage between 0V and 1V selects Burst Mode operation with the burst clamp set to the pin voltage. TRACK (Pin 35): Voltage Tracking Input. Feedback voltage will regulate to the voltage on this pin during start-up power sequencing. Exposed Pad (Pin 39): The Exposed Pad is PGND and must be soldered to the PCB ground for electrical connection and rated thermal performance. BLOCK DIAGRAM 24 8 SVIN 16 35 PVIN ITH VREF VOLTAGE REFERENCE ERROR AMPLIFIER – VFB PMOS CURRENT COMPARATOR SLOPE COMPENSATION RECOVERY TRACK + 25 26 SGND BCLAMP BURST COMPARATOR 3 29 4 28 9 23 10 22 + – – + + SYNC/MODE + 0.74V SLOPE COMPENSATION OSCILLATOR – – + RUN 12 20 21 30 31 PGND PGOOD CURRENT REVERSE COMPARATOR RT 6 SYNC/MODE 27 + 5 RUN/SS 11 – 7 NMOS CURRENT COMPARATOR – 0.86V 2 + LOGIC SW 1 13 32 14 33 15 34 17 36 18 37 19 38 3418 BD 3418fb 6 LTC3418 OPERATION Main Control Loop Burst Mode Operation The LTC3418 is a monolithic, constant frequency, current mode step-down DC/DC converter. During normal operation, the internal top power switch (P-channel MOSFET) is turned on at the beginning of each clock cycle. Current in the inductor increases until the current comparator trips and turns off the top power MOSFET. The peak inductor current at which the current comparator shuts off the top power switch is controlled by the voltage on the ITH pin. The error amplifier adjusts the voltage on the ITH pin by comparing the feedback signal from a resistor divider on the VFB pin with an internal 0.8V reference. When the load current increases, it causes a reduction in the feedback voltage relative to the reference. The error amplifier raises the ITH voltage until the average inductor current matches the new load current. When the top power MOSFET shuts off, the synchronous power switch (N-channel MOSFET) turns on until either the bottom current limit is reached or the beginning of the next clock cycle. The bottom current limit is set at –8A for force continuous mode and 0A for Burst Mode operation. Connecting the SYNC/MODE pin to a voltage in the range of 0V to 1V enables Burst Mode operation. In Burst Mode operation, the internal power MOSFETs operate intermittently at light loads. This increases efficiency by minimizing switching losses. During Burst Mode operation, the minimum peak inductor current is externally set by the voltage on the SYNC/MODE pin and the voltage on the ITH pin is monitored by the burst comparator to determine when sleep mode is enabled and disabled. When the average inductor current is greater than the load current, the voltage on the ITH pin drops. As the ITH voltage falls below 350mV, the burst comparator trips and enables sleep mode. During sleep mode, the top power MOSFET is held off while the load current is solely supplied by the output capacitor. When the output voltage drops, the top and bottom power MOSFETs begin switching to bring the output back into regulation. This process repeats at a rate that is dependent on the load demand. The operating frequency is externally set by an external resistor connected between the RT pin and ground. The practical switching frequency can range from 300kHz to 4MHz. Overvoltage and undervoltage comparators will pull the PGOOD output low if the output voltage comes out of regulation by ±7.5%. In an overvoltage condition, the top power MOSFET is turned off and the bottom power MOSFET is switched on until either the overvoltage condition clears or the bottom MOSFET’s current limit is reached. Forced Continuous Connecting the SYNC/MODE pin to SVIN will disable Burst Mode operation and force continuous current operation. At light loads, forced continuous mode operation is less efficient than Burst Mode operation, but may be desirable in some applications where it is necessary to keep switching harmonics out of a signal band. The output voltage ripple is minimized in this mode. Pulse skipping operation can be implemented by connecting the SYNC/MODE pin to ground. This forces the burst clamp level to be at 0V. As the load current decreases, the peak inductor current will be determined by the voltage on the ITH pin until the ITH voltage drops below 400mV. At this point, the peak inductor current is determined by the minimum on-time of the current comparator. If the load demand is less than the average of the minimum on-time inductor current, switching cycles will be skipped to keep the output voltage in regulation. Frequency Synchronization The internal oscillator of the LTC3418 can by synchronized to an external clock connected to the SYNC/MODE pin. The frequency of the external clock can be in the range of 300kHz to 4MHz. For this application, the oscillator timing resistor should be chosen to correspond to a frequency that is 25% lower than the synchronization frequency. During synchronization, the burst clamp is set to 0V, and each switching cycle begins at the falling edge of the clock signal. 3418fb 7 LTC3418 OPERATION Dropout Operation Short-Circuit Protection When the input supply voltage decreases toward the output voltage, the duty cycle increases toward the maximum on-time. Further reduction of the supply voltage forces the main switch to remain on for more than one cycle eventually reaching 100% duty cycle. The output voltage will then be determined by the input voltage minus the voltage drop across the internal P-channel MOSFET and the inductor. When the output is shorted to ground, the inductor current decays very slowly during a single switching cycle. To prevent current runaway from occurring, a secondary current limit is imposed on the inductor current. If the inductor valley current increases larger than 15A, the top power MOSFET will be held off and switching cycles will be skipped until the inductor current is reduced. Voltage Tracking Low Supply Operation The LTC3418 is designed to operate down to an input supply voltage of 2.25V. One important consideration at low input supply voltages is that the RDS(ON) of the P-channel and N-channel power switches increases. The user should calculate the power dissipation when the LTC3418 is used at 100% duty cycle with low input voltages to ensure that thermal limits are not exceeded. Slope Compensation and Inductor Peak Current Slope compensation provides stability in constant frequency architectures by preventing subharmonic oscillations at duty cycles greater than 50%. It is accomplished internally by adding a compensating ramp to the inductor current signal. Normally, the maximum inductor peak current is reduced when slope compensation is added. In the LTC3418, however, slope compensation recovery is implemented to keep the maximum inductor peak current constant throughout the range of duty cycles. This keeps the maximum output current relatively constant regardless of duty cycle. Some microprocessors and DSP chips need two power supplies with different voltage levels. These systems often require voltage sequencing between the core power supply and the I/O power supply. Without proper sequencing, latch-up failure or excessive current draw may occur that could result in damage to the processor’s I/O ports or the I/O ports of a supporting system device such as memory, an FPGA or a data converter. To ensure that the I/O loads are not driven until the core voltage is properly biased, tracking of the core supply and the I/O supply voltage is necessary. Voltage tracking is enabled by applying a ramp voltage to the TRACK pin. When the voltage on the TRACK pin is below 0.8V, the feedback voltage will regulate to this tracking voltage. When the tracking voltage exceeds 0.8V, control over the feedback voltage is gradually released. Full release of tracking control over the feedback voltage is achieved when the tracking voltage exceeds 1.05V. Voltage Reference Output The LTC3418 provides a 1.25V reference voltage that is capable of sourcing up to 5mA of output current. This reference voltage is generated from a linear regulator and is intended for applications requiring a low noise reference voltage. To ensure that the output is stable, the reference voltage pin should be decoupled with a minimum of 2.2μF. 3418fb 8 LTC3418 APPLICATIONS INFORMATION The basic LTC3418 application circuit is shown on the front page of this data sheet. External component selection is determined by the maximum load current and begins with the selection of the operating frequency and inductor value followed by CIN and COUT. Having a lower ripple current reduces the core losses in the inductor, the ESR losses in the output capacitors and the output voltage ripple. Highest efficiency operation is achieved at low frequency with small ripple current. This, however, requires a large inductor. Operating Frequency A reasonable starting point for selecting the ripple current is ΔIL = 0.4(IMAX). The largest ripple current occurs at the highest VIN. To guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation: Selection of the operating frequency is a tradeoff between efficiency and component size. High frequency operation allows the use of smaller inductor and capacitor values. Operation at lower frequencies improves efficiency by reducing internal gate charge losses but requires larger inductance values and/or capacitance to maintain low output ripple voltage. The operating frequency of the LTC3418 is determined by an external resistor that is connected between the RT pin and ground. The value of the resistor sets the ramp current that is used to charge and discharge an internal timing capacitor within the oscillator and can be calculated by using the following equation: ROSC = 7.3 • 1010 ⎡ ⎤ ⎣Ω⎦ – 2.5kΩ f Although frequencies as high as 4MHz are possible, the minimum on-time of the LTC3418 imposes a minimum limit on the operating duty cycle. The minimum on-time is typically 80ns. Therefore, the minimum duty cycle is equal to: 100 • 80ns • f(Hz) Inductor Selection For a given input and output voltage, the inductor value and operating frequency determine the ripple current. The ripple current ΔIL increases with higher VIN or VOUT and decreases with higher inductance: V V IL = OUT 1– OUT VIN fL V V L = OUT 1– OUT fIL(MAX) VIN(MAX) The inductor value will also have an effect on Burst Mode operation. The transition from low current operation begins when the peak inductor current falls below a level set by the burst clamp. Lower inductor values result in higher ripple current which causes this to occur at lower load currents. This causes a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to increase. Inductor Core Selection Once the value for L is known, the type of inductor must be selected. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on the inductance selected. As the inductance increases, core losses decrease. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! 3418fb 9 LTC3418 APPLICATIONS INFORMATION Different core materials and shapes will change the size/current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don’t radiate much energy, but generally cost more than powdered iron core inductors with similar characteristics. The choice of which style inductor to use mainly depends on the price vs size requirements and any radiated field/EMI requirements. New designs for surface mount inductors are available from Coiltronics, Coilcraft, Toko and Sumida. CIN and COUT Selection The input capacitance, CIN, is needed to filter the trapezoidal wave current at the source of the top MOSFET. To prevent large voltage transients from occurring, a low ESR input capacitor sized for the maximum RMS current should be used. The maximum RMS current is given by: V IRMS =IOUT(MAX) OUT VIN VIN –1 VOUT This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. The selection of COUT is determined by the effective series resistance (ESR) that is required to minimize voltage ripple and load step transients as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. Loop stability can be checked by viewing the load transient response as described in a later section. The output ripple, ΔVOUT, is determined by: 1 VOUT IL ESR+ 8fCOUT The output ripple is highest at maximum input voltage since ΔIL increases with input voltage. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Special polymer capacitors offer very low ESR but have lower capacitance density than other types. Tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR, but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient and audible piezoelectric effects. The high Q of ceramic capacitors with trace inductance can also lead to significant ringing. Using Ceramic Input and Output Capacitors Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. However, care must be taken when these capacitors are used at the input and output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, VIN. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN large enough to damage the part. When choosing the input and output ceramic capacitors, choose the X5R or X7R dielectric formulations. These dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size. Output Voltage Programming The output voltage is set by an external resistive divider according to the following equation: R2 VOUT = 0.8 1+ R1 The resistive divider allows pin VFB to sense a fraction of the output voltage as shown in Figure 1. 3418fb 10 LTC3418 APPLICATIONS INFORMATION VOUT R2 VFB LTC3418 R1 SGND 3418 F01 pin to ground. This sets IBURST to 0A. In this condition, the peak inductor current is limited by the minimum on-time of the current comparator; and the lowest output voltage ripple is achieved while still operating discontinuously. During very light output loads, pulse skipping allows only a few switching cycles to be skipped while maintaining the output voltage in regulation. Figure 1. Setting the Output Voltage Voltage Tracking Pulse skipping, which is a compromise between low output voltage ripple and efficiency during low load current operation, can be implemented by connecting the SYNC/MODE VOUT2 OUTPUT VOLTAGE If the voltage on the SYNC/MODE pin is less than VIN by 1V, Burst Mode operation is enabled. During Burst Mode operation, the voltage on the SYNC/MODE pin determines the burst clamp level, which sets the minimum peak inductor current, IBURST, for each switching cycle. A graph showing the relationship between the minimum peak inductor current and the voltage on the SYNC/MODE pin can be found in the Typical Performance Characteristics section. In the graph, VBURST is the voltage on the SYNC/MODE pin. IBURST can only be programmed in the range of 0A to 10A. For values of VBURST less than 0.4V, IBURST is set at 0A. As the output load current drops, the peak inductor currents decrease to keep the output voltage in regulation. When the output load current demands a peak inductor current that is less than IBURST, the burst clamp will force the peak inductor current to remain equal to IBURST regardless of further reductions in the load current. Since the average inductor current is greater than the output load current, the voltage on the ITH pin will decrease. When the ITH voltage drops to 350mV, sleep mode is enabled in which both power MOSFETs are shut off and switching action is discontinued to minimize power consumption. All circuitry is turned back on and the power MOSFETs begin switching again when the output voltage drops out of regulation. The value for IBURST is determined by the desired amount of output voltage ripple. As the value of IBURST increases, the sleep period between pulses and the output voltage ripple increase. The burst clamp voltage, VBURST, can be set by a resistor divider from the VFB pin to the SGND pin as shown in the Typical Application on the front page of this data sheet. The LTC3418 allows the user to program how its output voltage ramps during start-up by means of the TRACK pin. Through this pin, the output voltage can be set up to either track coincidentally or ratiometrically follow another output voltage as shown in Figure 2. If the voltage on the TRACK pin is less than 0.8V, voltage tracking is enabled. During voltage tracking, the output voltage regulates to the tracking voltage through a resistor divider network. VOUT1 TIME 3418 F02a Figure 2a. Coincident Tracking VOUT2 OUTPUT VOLTAGE Burst Clamp Programming VOUT1 TIME 3418 F02a Figure 2b. Ratiometric Sequencing 3418fb 11 LTC3418 APPLICATIONS INFORMATION The output voltage during tracking can be calculated with the following equation: R2 VOUT = VTRACK 1+ ,VTRACK < 0.8V R1 To implement the coincident tracking in Figure 2a, connect an extra resistor divider to the output of VOUT2 and connect its midpoint to the TRACK pin of the LTC3418 as shown in Figure 3. The ratio of this divider should be selected the same as that of VOUT1’s resistor divider. To implement the ratiometric sequencing in Figure 2b, the extra resistor divider’s ratio should be set so that the TRACK pin voltage exceeds 1.05V by the end of the start-up period. The LTC3418 utilizes a method in which the TRACK pin’s control over the output voltage is gradually released as the TRACK pin voltage approaches 0.8V. With this technique, some overdrive will be required on the TRACK pin to ensure that the tracking function is completely disabled at the end of the start-up period. For coincident tracking, the following condition should be satisfied to ensure that tracking is disabled at the end of start-up. VOUT2 ≥ 1.32 VOUT1 For ratiometric tracking, the following equation can be used to calculate the resistor values: top MOSFET turn-on is locked to the falling edge of the external frequency source. The synchronization frequency range is 300kHz to 4MHz. Synchronization only occurs if the external frequency is greater than the frequency set by the external resistor. Because slope compensation is generated by the oscillator’s RC circuit, the external frequency should be set 25% higher than the frequency set by the external resistor to ensure that adequate slope compensation is present. Soft-Start The RUN/SS pin provides a means to shut down the LTC3418 as well as a timer for soft-start. Pulling the RUN/ SS pin below 0.5V places the LTC3418 in a low quiescent current shutdown state (IQ < 1.5μA). The LTC3418 contains a soft-start clamp that can be set externally with a resistor and capacitor on the RUN/SS pin as shown in Typical Application on the front page of this data sheet. The soft-start duration can be calculated by using the following formula: VIN ⎡⎣Seconds⎤⎦ t SS =RSS • CSS •In VIN – 1.8V When the voltage on the RUN/SS pin is raised above 2V, the full current range becomes available on ITH. Efficiency Considerations V R4 =R3 OUT2 – 1 VTRACK The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Efficiency can be expressed as: VTRACK 1.05V VOUT2 (MASTER) R4 Efficiency = 100% – (L1 + L2 + L3 + ...) R2 TRACK PIN VFB(MASTER) PIN R3 R1 3418 F03 Figure 3 Frequency Synchronization The LTC3418’s internal oscillator can be synchronized to an external clock signal. During synchronization, the where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses: VIN quiescent current and I2R losses. The VIN quiescent current loss dominates the efficiency loss at very low load currents whereas the I2R loss dominates the efficiency loss at medium to high load currents. In a typical efficiency plot, the efficiency curve at very low 3418fb 12 LTC3418 APPLICATIONS INFORMATION load currents can be misleading since the actual power lost is of no consequence. 1. The VIN quiescent current is due to two components: the DC bias current as given in the Electrical Characteristics and the internal main switch and synchronous switch gate charge currents. The gate charge current results from switching the gate capacitance of the internal power MOSFET switches. Each time the gate is switched from high to low to high again, a packet of charge dQ moves from VIN to ground. The resulting dQ/dt is the current out of VIN that is typically larger than the DC bias current. In continuous mode, IGATECHG = f(QT + QB) where QT and QB are the gate charges of the internal top and bottom switches. Both the DC bias and gate charge losses are proportional to VIN and thus their effects will be more pronounced at higher supply voltages. 2. I2R losses are calculated from the resistances of the internal switches, RSW, and external inductor RL. In continuous mode the average output current flowing through inductor L is “chopped” between the main switch and the synchronous switch. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows: RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus, to obtain I2R losses, simply add RSW to RL and multiply the result by the square of the average output current. Other losses including CIN and COUT ESR dissipative losses and inductor core losses generally account for less than 2% of the total loss. Thermal Considerations In most applications, the LTC3418 does not dissipate much heat due to its high efficiency. But, in applications where the LTC3418 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 150°C, both power switches will be turned off and the SW node will become high impedance. To avoid the LTC3418 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. The temperature rise is given by: TR = (PD)(θJA) where PD is the power dissipated by the regulator and θJA is the thermal resistance from the junction of the die to the ambient temperature. For the 38-Lead 5mm × 7mm QFN package, the θJA is 34°C/W. The junction temperature, TJ, is given by: TJ = TA + TR where TA is the ambient temperature. Note that at higher supply voltages, the junction temperature is lower due to reduced switch resistance (RDS(ON)). Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ΔILOAD(ESR), where ESR is the effective series resistance of COUT. ΔILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. The ITH pin external components and output capacitor shown in the Typical Application on the front page of this data sheet will provide adequate compensation for most applications. Design Example As a design example, consider using the LTC3418 in an application with the following specifications: VIN = 3.3V, VOUT = 2.5V, IOUT(MAX) = 8A, IOUT(MIN) = 200mA, f = 1MHz. 3418fb 13 LTC3418 APPLICATIONS INFORMATION Because efficiency is important at both high and low load current, Burst Mode operation will be utilized. COUT will be selected based on the ESR that is required to satisfy the output voltage ripple requirement and the bulk capacitance needed for loop stability. For this design, five 100μF ceramic capacitors will be used. First, calculate the timing resistor: ROSC = 7.3 • 1010 1• 10 6 CIN should be sized for a maximum current rating of: – 2.5k = 70.5k 2.5V 3.3V – 1= 3.43ARMS IRMS = (8A ) 3.3V 2.5V Use a standard value of 69.8k. Next, calculate the inductor value for about 40% ripple current: Decoupling the PVIN and SVIN pins with four 100μF capacitors is adequate for this application. 2.5V 2.5V 1– L = = 0.19μH (1MHz) (3.2A ) 3.3V The burst clamp and output voltage can now be programmed by choosing the values of R1, R2 and R3. The voltage on the MODE pin will be set to 0.67V by the resistor divider consisting of R2 and R3. A burst clamp voltage of 0.67V will set the minimum inductor current, IBURST, to approximately 1.2A. Using a 0.2μH inductor results in a maximum ripple current of: 2.5V 2.5V 1– IL = = 3.03A (1MHz) (0.2μH) 3.3V VIN 3.3V 3 CIN 100μF ×4 4 9 10 22 RSS 2.2M RPG 100k RSVIN 100Ω CSVIN 1μF X7R 23 28 29 24 PVIN SW PVIN SW PVIN SW PVIN SW PVIN SW PVIN SW PVIN SW PVIN SW SVIN VFB 1 TRACK SYNC/MODE PGOOD PGND RUN/SS 26 ITH ROSC 69.8k 6 RT 8 SGND 13 PGND 14 PGND 15 PGND 17 PGND PGND 5 7 CITH 820pF X7R RITH 7.5k C1 47pF X7R PGND PGND PGND PGND PGND PGND VREF COUT 100μF ×5 2 11 12 20 C1 22pF X7R VOUT 2.5V 8A R1 432k 21 30 31 25 LTC3418 35 CSS 1000pF X7R L1 0.2μH 27 R2 33.2k 38 37 36 34 33 R3 169k 32 19 18 16 CIN, COUT: AVX 18126D107MAT L1: TOKO FDV0620-R20M CREF 2.2μF X7R VREF 3418 F04 Figure 4. 2.5V, 8A Regulator at 1MHz, Burst Mode Operation 3418fb 14 LTC3418 APPLICATIONS INFORMATION If we set the sum of R2 and R3 to 200k, then the following equations can be solved. R2 + R3 = 200k R2 0.8 V 1+ = R3 0.67 V The two equations shown above result in the following values for R2 and R3: R2 = 33.2k, R3 = 169k. The value of R1 can now be determined by solving the equation: R1 2.5V = 202.2k 0.8 V R1 = 430k 1. A ground plane is recommended. If a ground plane layer is not used, the signal and power grounds should be segregated with all small-signal components returning to the SGND pin at one point which is then connected to the PGND pin close to the LTC3418. 2. Connect the (+) terminals of the input capacitor(s), CIN, as close as possible to the PVIN and PGND pins at all four corners of the package. These capacitors provide the AC current into the internal power MOSFETs. 3. Keep the switching node, SW, away from all sensitive small-signal nodes. 1+ A value of 432k will be selected for R1. Figure 4 shows the complete schematic for this design example. PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3418. Check the following in your layout. 4. Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power components. You can connect the copper areas to any DC net (PVIN, SVIN, VOUT, PGND, SGND or any other DC rail in your system). 5. Connect the VFB pin directly to the feedback resistors. The resistor divider must be connected between VOUT and SGND. 6. To minimize switching noise coupling to SVIN, place an optional local filter between SVIN and PVIN. Most designs do not require this filter. Top Layer Bottom Layer Figure 5. LTC3418 Layout Diagram 3418fb 15 LTC3418 TYPICAL APPLICATIONS 3.3V, 8A Step-Down Regulator Synchronized to 1.25MHz VIN 5V 3 CIN 100μF ×2 4 9 10 22 RSS 2.2M RPG 100k 23 28 29 24 RSVIN 100Ω CSVIN 1μF X7R CSS 1000pF X7R SW PVIN SW PVIN SW PVIN SW PVIN SW PVIN SW PVIN SW PVIN SW SVIN VFB L1 0.33μH COUT 100μF ×3 2 11 12 20 C1 1000pF X7R VOUT 3.3V 8A R1 6.34k 21 30 31 25 LTC3418 35 5 RITH 2k CITH 2200pF X7R PVIN 1 C1 47pF X7R TRACK VREF PGOOD PGND 7 RUN/SS 26 I ROSC 69.8k 6 TH RT 8 SGND 13 PGND 14 PGND 15 PGND 27 SYNC/MODE 16 CREF 2.2μF X7R 38 37 PGND 36 PGND 34 PGND R2 2k 33 PGND 32 PGND 19 PGND 18 PGND 17 PGND CIN, COUT: TDK C3225X5R0J107M L1: VISHAY DALE IHLP-2525CZ-01 1.25MHz CLOCK VREF 3418 TA02 1.2V, 8A Step-Down Regulator at 2MHz, Forced Continuous Mode 3 VIN 3.3V 4 CIN 100μF ×4 9 10 22 RSS 2.2M RPG 100k 23 28 29 24 RSVIN 100Ω CSVIN 1μF X7R 27 C1 47pF X7R PVIN SW PVIN SW PVIN SW PVIN SW PVIN SW PVIN SW PVIN SW SVIN VFB TRACK VREF SYNC/MODE PGND PGOOD PGND RUN/SS 26 I ROSC 30.1k 6 TH RT 8 SGND 14 PGND 15 PGND 13 PGND PGND 5 7 CITH 2200pF X7R SW L1 0.2μH COUT 100μF ×3 2 11 12 20 C1 1000pF X7R VOUT 1.2V 8A R1 1k 21 30 31 25 LTC3418 35 CSS 1000pF X7R RITH 4.99k PVIN 1 CIN, COUT: AVX 12106D107MAT L1: COOPER FP3-R20 PGND PGND PGND PGND PGND PGND 16 CREF 2.2μF X7R 38 37 VREF 36 34 33 R2 2k 32 19 18 17 3418 TA03 3418fb 16 LTC3418 TYPICAL APPLICATIONS 1.8V, 8A Step-Down Regulator with Tracking I/O SUPPLY 35 VIN 3.3V 3 CIN 100μF ×4 4 9 10 RSS 2.2M RPG 100k 22 23 29 28 RSVIN 100Ω 2.5V R3 2.55k R4 2k TRACK SW PVIN SW PVIN SW PVIN SW PVIN SW PVIN SW PVIN SW PVIN SW PVIN VFB 1 L1 0.2μH COUT 100μF ×2 2 11 12 20 C1 1000pF X7R VOUT 1.8V 8A R1 2.55k 21 30 31 25 LTC3418 24 CSVIN C SS 1μF 1000pF X7R X7R 5 27 7 CITH 2200pF X7R RITH 3.32k C1 47pF X7R SVIN PGOOD PGND SYNC/MODE PGND RUN/SS 26 I ROSC 69.8k 6 TH RT 8 SGND 13 PGND 14 PGND 15 PGND CIN, COUT: TDK C3225X5R0J107M L1: VISHAY DALE IHLP-2525CZ-01 VREF PGND PGND PGND PGND PGND PGND PGND 16 CREF 2.2μF X7R 38 37 VREF 36 34 33 R2 2k 32 19 18 17 3418 TA04 3418fb 17 LTC3418 TYPICAL APPLICATIONS 1.8V, 16A Step-Down Regulator VIN 3.3V 3 CIN1 100μF ×4 4 9 10 22 RSS1 2.2M RPG1 100k 23 28 29 24 RSVIN1 100W CSVIN1 1μF X7R PVIN SW PVIN SW PVIN SW PVIN SW PVIN SW PVIN SW PVIN SW PVIN SW SVIN VFB C1A 47pF X7R 5 TRACK PGND PGOOD PGND RUN/SS PGND 26 ITH ROSC1 59k 6 RT 8 SGND 13 PGND 14 PGND 15 PGND 27 SYNC/MODE RITH 2k 3 CIN2 100μF ×4 4 9 10 22 RSS2 2.2M RPG2 100k 23 28 29 24 CSVIN2 1μF X7R L1 0.2μH 2 11 12 C2 1000pF X7R 20 R1 2.55k 21 30 31 25 LTC3418 35 CSS1 1000pF X7R 7 RSVIN2 100Ω 1 PGND PGND PGND PGND PGND PGND VREF 38 37 36 COUT 100μF ×4 34 33 VOUT 1.8V 16A R2 2k 32 19 18 17 16 CREF1 2.2mF X7R CITH 2200pF X7R PVIN SW PVIN SW PVIN SW PVIN SW PVIN SW PVIN SW PVIN SW PVIN SW SVIN VFB 1 L2 0.2μH 2 11 12 C3 1000pF X7R 20 R3 2.55k 21 30 31 25 LTC3418 CSS2 1000pF X7R 35 5 7 C1B 47pF X7R TRACK PGND PGOOD PGND RUN/SS 26 ITH ROSC2 69.8k 6 RT 8 SGND 13 PGND 14 PGND 15 PGND 27 SYNC/MODE PGND PGND PGND PGND PGND PGND PGND VREF 38 37 36 34 33 R4 2k 32 19 18 17 16 CREF2 2.2μF X7R CIN1, CIN2, COUT: TDK C3225X5R0J107M L1, L2: VISHAY DALE IHLP-2525CZ-01 3418 TA06 3418fb 18 LTC3418 PACKAGE DESCRIPTION UHF Package 38-Lead Plastic QFN (5mm × 7mm) (Reference LTC DWG # 05-08-1701) 0.70 p 0.05 5.50 p 0.05 5.15 ± 0.05 4.10 p 0.05 3.15 ± 0.05 3.00 REF PACKAGE OUTLINE 0.25 p 0.05 0.50 BSC 5.5 REF 6.10 p 0.05 7.50 p 0.05 RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 5.00 p 0.10 0.75 p 0.05 PIN 1 NOTCH R = 0.30 TYP OR 0.35 s 45o CHAMFER 3.00 REF 37 0.00 – 0.05 38 0.40 p0.10 PIN 1 TOP MARK (SEE NOTE 6) 1 2 5.15 ± 0.10 7.00 p 0.10 5.50 REF 3.15 ± 0.10 (UH) QFN REF C 1107 0.200 REF 0.25 p 0.05 0.50 BSC R = 0.125 TYP R = 0.10 TYP BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE M0-220 VARIATION WHKD 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3418fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTC3418 TYPICAL APPLICATION Low Noise 1.5V, 8A Step-Down Regulator VIN 2.5V 3 CIN 100μF ×4 4 9 10 22 RSS 2.2M RPG 100k 23 28 29 24 RSVIN 100Ω CSVIN 1μF X7R CSS 1000pF X7R CITH 2200pF X7R PVIN SW PVIN SW PVIN SW PVIN SW PVIN SW PVIN SW PVIN SW PVIN SW SVIN VFB 1 L1 0.2μH COUT 100μF ×3 2 11 12 20 C1 1000pF X7R VOUT 1.5V 8A R1 1.78k 21 30 31 25 LTC3418 35 5 RITH 3.32k C1 47pF X7R TRACK VREF PGOOD PGND 7 RUN/SS 26 ITH ROSC 69.8k 6 RT 27 SYNC/MODE 8 SGND 13 PGND 14 PGND 15 PGND PGND PGND PGND PGND PGND PGND PGND PGND 16 CREF 2.2μF X7R 38 37 VREF 36 34 R2 2k 33 32 19 18 17 CIN, COUT: TDK C3225X5R0J107M L1: VISHAY DALE IHLP-2525CZ-01 3418 TA05 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1616 500mA (IOUT ), 1.4MHz, High Efficiency Step-Down DC/DC Converter 450mA (IOUT ), 100kHz, High Efficiency Step-Down DC/DC Converter 25V, 2.75A (IOUT ), 1.25MHz, High Efficiency Step-Down DC/DC Converter 1.20A (IOUT ), 550kHz, Synchronous Step-Down DC/DC Converter 300mA (IOUT ), 1.5MHz, Synchronous Step-Down DC/DC Converter 600mA (IOUT ), 1.5MHz, Synchronous Step-Down DC/DC Converter Dual 600mA (IOUT ), 1.5MHz, Synchronous Step-Down DC/DC Converter 1.25A (IOUT ), 4MHz, Synchronous Step-Down DC/DC Converter 2.5A (IOUT ), 4MHz, Synchronous Step-Down DC/DC Converter 3A (IOUT Sink/source), 2MHz, Monolithic Synchronous Regulator for DDR/QDR Memory Termination 4A (IOUT ), 4MHz, Synchronous Step-Down DC/DC Converter 4A (IOUT ), 4MHz, Synchronous Step-Down DC/DC Converter with Tracking 90% Efficiency, VIN: 3.6V to 25V, VOUT = 1.25V, IQ = 1.9mA, ISD < 1μA, ThinSOT Package 90% Efficiency, VIN: 7.4V to 60V, VOUT = 1.24V, IQ = 3.2mA, ISD < 2.5μA, S8 Package 90% Efficiency, VIN: 3V to 25V, VOUT = 1.2V, IQ = 1mA, ISD < 15μA, S8, TSSOP16E Packages 95% Efficiency, VIN: 2.7V to 10V, VOUT = 0.8V, IQ = 15μA, ISD < 1μA, TSSOP16 Package 95% Efficiency, VIN: 2.75V to 6V, VOUT = 0.8V, IQ = 20μA, ISD < 1μA, ThinSOT Package 95% Efficiency, VIN: 2.5V to 5.5V, VOUT = 0.6V, IQ = 20μA, ISD < 1μA, ThinSOT Package 95% Efficiency, VIN: 2.5V to 5.5V, VOUT = 0.6V, IQ = 40μA, ISD < 1μA, MS Package 95% Efficiency, VIN: 2.5V to 5.5V, VOUT = 0.8V, IQ = 60μA, ISD < 1μA, MS Package 95% Efficiency, VIN: 2.5V to 5.5V, VOUT = 0.8V IQ = 60μA, ISD < 1μA, TSSOP16E Package 90% Efficiency, VIN: 2.25V to 5.5V, VOUT = VREF/2, IQ = 280μA, ISD < 1μA, TSSOP16E Package 95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.8V, IQ = 64μA, ISD < 1μA, TSSOP20E Package 95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.8V, IQ = 300μA, ISD < 1μA, TSSOP20E Package LT1676 LT1765 LTC1879 LTC3405/LTC3405A LTC3406/LTC3406B LTC3407 LTC3411 LTC3412 LTC3413 LTC3414 LTC3416 3418fb 20 Linear Technology Corporation LT 0908 REV B • PRINTED IN THE USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2005