AD9639 Evaluation Board Schematic PDF

8
6
7
2
3
4
5
1
REVISIONS
AVDD_P5V
REV
DESCRIPTION
DATE
APPROVED
AGND
DNI
VGA CH
ENABLE
OFF
AIN-A
R125
0
DNI
R124
51
2 3 4 5
DNI
ADT1-1WT
T101
3
6
C109
C103
2
1
5
AGND
0.1UF
4
AGND
0.1UF
C103A
(NC)
AGND
0
1
5
SEC
PRI
ETC1-1-13
1
8
0.1UF
0.1UF
C122
C121
0.1UF
25
16
DVS1
DVS2
AVS1
AVS2
OPC1
ONC1
SDO1
0.1UF
L101
1
2
TBD0805
C113
AMP+A
0.1UF
24
23
21
R111
0
33
D
R116
AGND
130
L102
2
TBD0805
C114
AVDD_P5V 1
U101
AMP-A
0.1UF
AD8372ACPZ-WP
OPC2
ONC2
SDO2
17
18
20
AVDD_P5V
L201
1
2
TBD0805
C213
AMP+B
0.1UF
R215
130
R216
AGND
130
L202
AGND
C214
AVDD_P5V 1
2
TBD0805
AMP-B
0.1UF
AGND
R107
R115
130
AGND
R102
AGND
AGND
AGND
AMP-A
DNI
DNI
SMA-J-P-X-ST-EM1
DNI
C102
0.1UF
R132
10K
J102
1
VIN-A
C
R130
0
R101
51
2 3 4 5
DNI
C101
3
0.1UF
4
-(NC)
ETC1-1-13
T102
DNI
2
3
PRI
SEC
5
1
R113
0
J101
1
2
4
4.7PF
-(NC)
AIN+A
C106
C
ON
J103
3
2
1
0.1UF
AVDD_P5V
200
ENB1
IPC1
INC1
RXT1
REF1
CLK1
SDI1
LCH1
LCH2
SDI2
CLK2
RXT2
IPC2
INC2
ENB2
REF2
AGD2
0.1UF
R118
R122
2.0K
C115
CHANNEL A
200
R123
2.0K
C116
0.1UF
C108
R117
R120
10K
C107
26
30
31
28
29
4
SCLK_VGA
3
SDI_VGA
2
LATCH1_VGA
7
LATCH2_VGA
6
SDI_VGA
5
SCLK_VGA
13
11
10
15
12
AVDD_P5V
DGD1
DGD2
PAD
AGND
DNI
AGND
22
27
14
19
32
9
PAD
D
0.1UF
R131
10K
AGND
AGD1
OFF
0.1UF
C120
J104
3
2
1
ON
C119
VGA CH
ENABLE
R121
10K
AVDD_P5V
DNI
T103
DNI
C104
R108
R112
0
33
VIN+A
AGND
AGND
0.1UF
SMA-J-P-X-ST-EM1
AMP+A
0.1UF
C105
DNI
DNI
R109
33
R110
33
C104A
AGND
0.1UF
C207
R114
R217
200
0.1UF
CML_A
C208
0
R218
DNI
AGND
CHANNEL B
200
0.1UF
DNI
B
AIN-B
J202
1
R225
0
2 3 4 5
R224
51
DNP
DNI
T201
C209
3
1
5
R202
AGND
0
B
C203
AMP-B
DNI
AGND
SMA-J-P-X-ST-EM1
DNI
C202
2
DNI
AGND
6
0.1UF
0.1UF
4
AGND
0.1UF
C203A
(NC)
R207
R211
0
33
ADT1-1WT
1
5
SEC
PRI
3
4
0.1UF
ETC1-1-13
VIN-B
0
2 3 4 5
R201
51
AIN+B
C201
SEC
DNI
0.1UF
-(NC)
2
5
ETC1-1-13
T202 DNI
DNI
3
PRI
R213
0
R230
4.7PF
J201
1
C206
-(NC)
2
4
DNI
1
T203
C204
R208
R212
0
33
VIN+B
AGND
AGND
0.1UF
AGND
C204A
R209
33
R210
33
SMA-J-P-X-ST-EM1
AMP+B
0.1UF
C205
DNI
R214
A
CML_B
0
0.1UF
DNI
A
AGND
SCHEMATIC
A N A LO G
DE V CES
THIS DRAWING
IS THE PROPERTY
IT IS NOT TO BE REPRODUCED
OF ANALOG DEVICES
OR COPIED,
IN PART, OR USED IN FURNISHING
OR FOR ANY OTHER PURPOSE
INC.
IN WHOLE OR
INFORMATION
DETRIMENTAL
SCHEMATIC
CUSTOMER EVALUATION BD.
9239
TO OTHERS,
SHOWN HEREON MAY BE PROTECTED
OWNED OR CONTROLLED
8
7
6
5
4
3
BY OWNED ANALOG DEVICES.
REV
DRAWING NO.
<DESIGN_VIEW>
D
BY PATENTS
ROB REEDER
2
B
9239CE01
SIZE
PTD ENGINEER
OF ANALOG DEVICES.
THE EQUIPMENT
DESIGN VIEW
TO THE INTERESTS
SCALE
na
SHEET 1
1
OF 5
8
6
7
2
3
4
5
1
REVISIONS
R321
REV
200
R320
R322
200
AVDD_P5V
R317
61.9
200
R316
R318
27
200
AGND
0
10K
0.1UF
R327
10K
C315
R326
R328
0
AVDD_P5V
AGND
-FB1
-OUT1
+OUT1
+FB1
-FB2
-OUT2
+OUT2
+FB2
0
DNI
R324
51
2 3 4 5
DNI
3
R302
AGND
SMA-J-P-X-ST-EM1
AGND
AGND
C414
U301
ADA4937-2YCPZ
AGND
DNI
0.1UF
4
AGND
0.1UF
C303
(NC)
ADT1-1WT
1
ETC1-1-13
5
0.1UF
R421
R307
R311
0
33
200
R420
VIN-C
200
R301
51
2 3 4 5
DNI
3
0.1UF
4
-(NC)
ETC1-1-13
T302
DNI
2
PRI
SEC
5
DNI
C407
DNI
1
0.1UF
T303
DNI
C304
R308
R312
0
33
VIN+C
AGND
AGND
0.1UF
SMA-J-P-X-ST-EM1
AMP+C
0.1UF
C305
DNI
0.1UF
AGND
R415
R417
61.9
200
R416
R418
27
200
AGND
R309
33
R310
33
C304A
AGND
C
C415
0
3
R313
0
R330
PRI
C301
2
4
4.7PF
SEC
J301
1
AMP+D
C303A
-(NC)
AIN+C
20PF
AMP-C
C306
C
0
20PF
PAD
AGND
DNI
C302
1
5
C413
27
2
AGND
AMP-D
27
R423
DNI
DNI
R422
6
0.1UF
AMP+C
27
5
13
12
8
CML_C
T301
C309
D
20PF
R323
0.1UF
R325
AGND
C314
23
19
18
2
PAD
0
AIN-C
J302
1
+VS1
11 VOCM2
14 PD2_N
R332
AVDD_P5V
APPROVED
C313
0.1UF
+VS2
-VS2
6 +IN2
7 -IN2
0.1UF
DNI
-VS1
17 VOCM1
20 PD1_N
R331
AVDD_P5V
C308
DATE
20PF
24 +IN1
1 -IN1
AGND
DESCRIPTION
AMP-C
27
9
10
4
3
D
R315
0.1UF
C311
0.1UF
0.1UF
C316
C318
C307
0.1UF
C317
DNI
22
21
16
15
CHANNEL C
C408
R314
CML_C
AVDD_P5V
0.1UF
0
R426
R427
10K
10K
DNI
DNI
R428
0
AGND
J402
1
2 3 4 5
0
DNI
R424
51
AIN-D
B
R425
DNI
3
1
5
R402
AGND
DNI
C402
C403A
2
0
B
AMP-D
DNI
AGND
SMA-J-P-X-ST-EM1
CHANNEL D
6
0.1UF
DNI
AGND
DNI
CML_D
T401
C409
AGND
0.1UF
4
AGND
0.1UF
C403
ETC1-1-13
0.1UF
(NC)
R407
R411
0
33
ADT1-1WT
1
5
SEC
PRI
3
4
VIN-D
0
2 3 4 5
R401
51
AIN+D
C401
0.1UF
-(NC)
2
3
PRI
SEC
5
ETC1-1-13
T402
DNI
DNI
R413
0
R430
4.7PF
J401
1
C406
-(NC)
2
4
DNI
1
T403
DNI
C404
R408
R412
0
33
VIN+D
AGND
AGND
0.1UF
AGND
SMA-J-P-X-ST-EM1
R409
33
R410
33
C404A
AMP+D
0.1UF
C405
DNI
R414
A
CML_D
0
0.1UF
DNI
A
AGND
SCHEMATIC
A N A LO G
DE V CES
THIS DRAWING
IS THE PROPERTY
IT IS NOT TO BE REPRODUCED
OF ANALOG DEVICES
OR COPIED,
IN PART, OR USED IN FURNISHING
OR FOR ANY OTHER PURPOSE
INC.
IN WHOLE OR
INFORMATION
DETRIMENTAL
SCHEMATIC
CUSTOMER EVALUATION BD.
9239
TO OTHERS,
SHOWN HEREON MAY BE PROTECTED
OWNED OR CONTROLLED
8
7
6
5
4
3
BY OWNED ANALOG DEVICES.
REV
DRAWING NO.
<DESIGN_VIEW>
D
BY PATENTS
ROB REEDER
2
B
9239CE01
SIZE
PTD ENGINEER
OF ANALOG DEVICES.
THE EQUIPMENT
DESIGN VIEW
TO THE INTERESTS
SCALE
na
SHEET 2
1
OF 5
8
6
7
2
3
4
5
1
REVISIONS
REV
DESCRIPTION
DATE
APPROVED
CLOCK CIRCUITRY
OPTIONAL OSCILLATOR
P
C509
D
N
10UF
C508
R511
10K
D
0.1UF
AVDD_3P3V
AGND
AGND
C517
0.1UF
DNI
C518
GND
OPT_CLK_P
25MHZ
AGND
AGND
0.1UF
C507
DNI
AVDD_3P3V
AGND
0.1UF
R503
10K
AGND
R507
249
3
R508
249
OFF
OPT_CLK_N
Y500
VDD
4
FO
1 E_D
5
CFO
6
R510
10K
OSC
ENABLE
ON
J503
3
2
1
AGND
U501
1
VCC
C506
DOUT-
8
REFCLKN
DOUT+
7
REFCLKP
REFERENCE CLOCK/FPGA
2 DIN
0.1UF
R504
10K
GND
J501
SMA-J-P-X-ST-EM1
1
AGND
FIN1017M
AGND
C
2 3 4 5
AGND
0.1UF
J502
SMA-J-P-X-ST-EM1
1
C502
DNI
AGND
OPT_CLK_P R514
0.1UF DNI
C503
1
3
2
D501
HSMS-2812BLK
0.1UF
R506
DNI
0
DNI
DEFAULT CLOCK PATH
CLK_P
0
3 T501 6
0
DNI
R502
51
NCLK
2
R505
AGND
0.1UF
2 3 4 5
ADT1-1WT
5 (NC)
1
4
R513
OPT_CLK_N
0
CLOSE TO DUT
C505
CLK_N
0.1UF DNI
CLOSE TO DUT
AVDD_3P3V
2
3
5
6
7
S0
8
S1
9
S2
10
S3
S4 11
S5 12
S6 13
S7 14
S8 15
S9 16
S10 25
32
R520
51
DNI
R516
0 DNI
R521
10K
R522
10K
DNI
TP501
DNI
1
R523
4.12K
AGND
CLK
CLKB
SYNCB
VREF
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
RSET
AGND
R531
0
DNI R532
S1
0
DNI R534
S2
0
R533
0
DNI R536
S3
C513
VS
CLK_P_LO
U502
OUT1B
OUT1
OUT0B
OUT0
0
DNI R538
S4
0.1UF DNI
LVDS OUTPUT
C514
18
0
DNI R540
S5
0
DNI R542
S6
CLK_N_LO
19
0.1UF DNI
22
0
C515
23
DNI R544
S7
CLK_N
0
0.1UFDNI
C516
DNI R546
S8
LVPECL OUTPUT
0
CLK_P
AD9515BCPZ
DNI R548
S9
0.1UF DNI
GND
31
DNI R530
S0
AGND
R524
100
R515
0 DNI
OPT_CLK_N
0.1UF
1
4
17
20
21
24
26
29
30
DNI
0.1UF
C512
0
PAD
PAD
AGND
R526
249
B
C511
R519
10K
DNI
R517
10K
R518
10K
AVDD_3P3V
OPT_CLK_P
AVDD_3P3V
0.1UF
AGND
AGND
AD9515 PIN-STRAP SETTINGS
C510
R527
249
C501
CLOSE TO DUT
C504
R509
100
0201
AGND
R552
0
CLK
R501
51
C
4
0
R535
0
R537
B
0
R539
0
R541
0
R543
0
R545
0
R547
0
R549
DNI R550
S10
0
R551
0
0
AGND
AGND
AGND
OPTIONAL CLOCK PATH CIRCUIT
A
SCHEMATIC
A N A LO G
DE V CES
THIS DRAWING
IS THE PROPERTY
IT IS NOT TO BE REPRODUCED
OF ANALOG DEVICES
OR COPIED,
IN PART, OR USED IN FURNISHING
OR FOR ANY OTHER PURPOSE
SCHEMATIC
CUSTOMER EVALUATION BD.
9239
INC.
IN WHOLE OR
INFORMATION
DETRIMENTAL
TO OTHERS,
8
7
6
5
4
3
BY OWNED ANALOG DEVICES.
REV
DRAWING NO.
<DESIGN_VIEW>
D
BY PATENTS
ROB REEDER
2
B
9239CE01
SIZE
PTD ENGINEER
SHOWN HEREON MAY BE PROTECTED
OWNED OR CONTROLLED
DESIGN VIEW
TO THE INTERESTS
OF ANALOG DEVICES.
THE EQUIPMENT
A
SCALE
na
SHEET 3
1
OF 5
8
6
7
2
3
4
5
1
REVISIONS
REV
DESCRIPTION
DATE
APPROVED
DUT CIRCUITRY
HIGH SPEED
CONNECTION
TO FPGA (FIFO5)
PGM3
PGM2
PGM1
PGM0
D
D
R625
4.02K
R609
10K
R608
10K
AGND
10K
0.1UF
AGND
C603
DATA_C-
AGND
0.1UF
C604
Y1
6
3 A2
Y2
4
1.00K
R618
1.00K
R617
5
VCC
R619
GND
REFCLKN
DATA_C+
0.1UF
C605
DATA_B-
0.1UF
DG1
DG2
DG3
DG4
DG5
DG6
DG7
DG8
DG9
DG10
AGND
P601
1
2
TSW-102-08-G-S
0.1UF
C611
1 A1
DNI
C2
C3
C4
C5
C6
C7
C8
C9
C10
DATA_D+
R603
AVDD_DUT
U602
DNI
DNI
6469169-1
BG1 P1
BG2
BG3
BG4
BG5
BG6
BG7
BG8
BG9
BG10
AGND
6469169-1
C606
AGND
6469169-1
D1 P1
D2
D3
D4
D5
D6
D7
D8
D9
D10
PLUG HEADER
23 DRGND_1
34 DRGND_2
C602
37
3
2
P1
REFCLKP C1
0.1UF
1.00K
SDO
RBIAS
TEMPOUT
C
P1
DATA_D-
R620
6469169-1
PLUG HEADER
38
SDO_DUT
SDIO_DUT
R616
10K
SDI
AGND
R613
100
SDI (SDIO)
R604
10K
R605
10K
SDO
AGND
AGND
SDO/SDIO
SELECT
3-2 4-WIRE SPI
2-1 3-WIRE SPI
(DEFAULT)
J610
8
7
6
5
4
3
2
1
AGND
AGND
J603
3
2
1
B
25
26
C601
SCLK
CSB
CLK_NEG
CLK_POS
PGM0
PGM1
PGM2
PGM3
RESET
AGND
AGND
B1
B2
B3
B4
SDO
B5
SDI
B6
SCLK
LATCH1_VGA B7
B8
B9
LATCH2_VGA B10
R624
4.02K
R612
100
1
2
3
PDWN 4
TSW-102-08-G-D
RESET
DOUT_POS_D
DOUT_NEG_D
27
28
6469169-1
P1
4.02K
R611
100
AVDD_DUT
P600
DOUT_POS_C
DOUT_NEG_C
29
30
4.02K
R623
R607
10K
39
40
16
17
53
52
51
50
22
DOUT_POS_B
DOUT_NEG_B
31
32
6469169-1
B
DATA_B+
0.1UF
C607
AVDD_3P3V
DATA_A-
1.00K
0.1UF
2
NC7WZ07P6X
C608
SCLK
R610
100
R621
10K
C
DOUT_POS_A
DOUT_NEG_A
R622
R606
10K
SCLK_DUT
CSB_DUT
CLK_N
CLK_P
AVDD_DUT
U600
AD9239BCPZ-210
VIN_POS_A
VIN_NEG_A
VCM_A
VIN_POS_B
VIN_NEG_B
VCM_B
VIN_POS_C
VIN_NEG_C
VCM_C
VIN_POS_D
VIN_NEG_D
VCM_D
PAD AGND
44
45
47
59
58
56
67
68
70
11
10
8
NC1
NC5
NC6
NC54
NC63
NC72
NC19
NC36
NC49
VIN+A
VIN-A
CML_A
VIN+B
VIN-B
CML_B
VIN+C
VIN-C
CML_C
VIN+D
VIN-D
CML_D
PGM3 1
2
3
PGM1
4
PGM2 5
6
PGM0 7
8
J609
TSW-104-08-G-D
PDWN
1
5
6
54
63
72
19
36
49
35
PLUG HEADER
AVDD_DUT
PLUG HEADER
AVDD
PLUG HEADER
DRVDD
A1
A2
A3
A4
A5
A6
CSB
A7
SCLK_VGA
A8
A9
A10
SDI_VGA
PGM/STANDBY
PINS
4
7
9
12
13
14
15
18
20
21
41
42
43
46
48
55
57
60
61
62
64
65
66
69
71
24
33
AVDD_DUT
PLUG HEADER
P1
DRVDD_DUT
DNI
DATA_A+
AGND
AGND
0.1UF
SPI CIRCUITRY
CSB
TSW-104-08-G-D
C610
AVDD_DUT
AGND
U601
0.1UF
5
VCC
1 A1
3 A2
Y1
6
SCLK_DUT
Y2
4
CSB_DUT
GND
R614
10K
R615
10K
A
2
A
NC7WZ16P6X
SCHEMATIC
AGND
A N A LO G
DE V CES
THIS DRAWING
IS THE PROPERTY
IT IS NOT TO BE REPRODUCED
OF ANALOG DEVICES
OR COPIED,
IN PART, OR USED IN FURNISHING
OR FOR ANY OTHER PURPOSE
INC.
IN WHOLE OR
INFORMATION
DETRIMENTAL
SCHEMATIC
CUSTOMER EVALUATION BD.
9239
TO OTHERS,
SHOWN HEREON MAY BE PROTECTED
OWNED OR CONTROLLED
8
7
6
5
4
3
BY OWNED ANALOG DEVICES.
REV
DRAWING NO.
<DESIGN_VIEW>
D
BY PATENTS
ROB REEDER
2
B
9239CE01
SIZE
PTD ENGINEER
OF ANALOG DEVICES.
THE EQUIPMENT
DESIGN VIEW
TO THE INTERESTS
SCALE
na
SHEET 4
1
OF 5
8
6
7
2
3
4
5
1
REVISIONS
REV
DESCRIPTION
DATE
APPROVED
WALWART POWER SUPPLY INPUT
6VDC, 2A MAX
S2A-TP
PWR2
0.1UF
0.1UF
0.1UF
C730
C729
C734
0.1UF
L705
P702
3P3V_AVDD
4
3
P5V_AVDD
2
1
Z5.531.3425.0
1
2
AVDD_3P3V
C
C717
0.1UF
C723
0.1UF
10UF
AGND
50OHMS
C716
50OHMS
C733
3P3V_AVDD
0.1UF
OPTIONAL POWER CONNECTIONS
2
C731
*
L700
1
4.7UF
C707
.01UF
4.7UF
C706
C705
C
2 PAD
C735
AGND
AVDD_DUT
U700
ADP1706ARDZ-3.3-R7
1
EN
7
SENSE
3
5
IN
OUT
4
6
OUT2
IN2
8 SS
GND1 PAD
0.1UF
AVDD_DUT
AGND
PWR1
D
DECOUPLING CAPS
0.1UF
AGND
S2A-TP
C728
BNX016-01
D705
A
C
0.1UF
3
S2A-TP
D704
A
C
C727
4
6
5
D703
A
C PWR1
PWR0
0.1UF
D702
A
C
C726
2
S2A-TP
S2A-TP
RAPC722X
1
D701
A
C
1 2
10UF
SH1
SIG
SH2
C704
D
1 F701 2
2A
LNJ314G8TRA (GREEN)
CR702
R715
C
A
249
L704
P701
3
AVDD_DUT
2
1P8V_AVDD
0.1UF
C739
0.1UF
C738
0.1UF
C732
0.1UF
C740
2
AVDD_DUT
C719
0.1UF
0.1UF
10UF
AGND
50OHMS
C721
2
1
C718
*
L702
1
L706
P703
1P8V_AVDD
1
2
1P8V_DRVDD
3
4
Z5.531.3425.0
B
1P8V_DRVDD
AGND
AGND
50OHMS
L707
1
2
50OHMS
DRVDD_DUT
10UF
2 PAD
0.1UF
DRVDD_DUT
AGND
4.7UF
C713
.01UF
4.7UF
C712
C711
GND1 PAD
AGND
50OHMS
U702
ADP1706ARDZ-1.8-R7
1
EN
7
SENSE
3
5
IN
OUT
4
6
OUT2
IN2
8 SS
PWR2
AVDD_P5V
10UF
1
50OHMS
C722
L701
AGND
B
2
C720
2 PAD
1
*
4.7UF
GND1 PAD
C710
.01UF
4.7UF
C709
C708
PWR2
C737
AGND
L708
U701
ADP1706ARDZ-1.8-R7
1
EN
7
SENSE
3
5
IN
OUT
4
6
IN2
OUT2
8 SS
0.1UF
C736
AGND
AGND
*
L703
1
P5V_AVDD
50OHMS
GND1 PAD
2 PAD
2
*NOTE: WHEN USING P702 OR P703
WITH RAW BENCH POWER SUPPLIES
REMOVE L700/L701/L702/L703
4.7UF
A
4.7UF
R701
1.91K
C714
PWR0
C715
R700
10K
AGND
U703
ADP1708ARDZ-R7
1
EN
7
SENSE
3
5
IN
OUT
4
6
IN2
OUT2
8 ADJ
A
AGND
SCHEMATIC
A N A LO G
DE V CES
THIS DRAWING
IS THE PROPERTY
IT IS NOT TO BE REPRODUCED
OF ANALOG DEVICES
OR COPIED,
IN PART, OR USED IN FURNISHING
OR FOR ANY OTHER PURPOSE
INC.
IN WHOLE OR
INFORMATION
DETRIMENTAL
SCHEMATIC
CUSTOMER EVALUATION BD.
9239
TO OTHERS,
SHOWN HEREON MAY BE PROTECTED
OWNED OR CONTROLLED
8
7
6
5
4
3
BY OWNED ANALOG DEVICES.
REV
DRAWING NO.
<DESIGN_VIEW>
D
BY PATENTS
ROB REEDER
2
B
9239CE01
SIZE
PTD ENGINEER
OF ANALOG DEVICES.
THE EQUIPMENT
DESIGN VIEW
TO THE INTERESTS
SCALE
na
SHEET 5
1
OF 5
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