8 6 7 2 3 4 5 1 REVISIONS REV DESCRIPTION DATE APPROVED EVAL BOARD CONNECTIONS D D (J1) HS-SERIAL/SPI/AUX P3 P3 USB_5 USB_3 CSB4_M CSB3_M CSB2_M CSB1_M I/O_8 I/O_6 I/O_4 I/O_2 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 AG1 AG2 AG3 AG4 AG5 GND AG6 AG7 AG8 AG9 AG10 C 2065769-1 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 BG1 BG2 BG3 BG4 BG5 GND BG6 BG7 BG8 BG9 BG10 2065769-1 B 2065769-1 P3 USB_4 USB_2 USB_1 SDO_M SDI_M SCLK_M I/O_7 I/O_5 I/O_3 I/O_1 2065769-1 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 BG1 BG2 BG3 BG4 BG5 GND BG6 BG7 BG8 BG9 BG10 DGND DGND 2065769-1 R101 DNI DCLKA2+ 0 R102 DCLKA1+ DCLKA+ 0 R103 DNI DCLKA20 R104 DCLKA1- DCLKA- A C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 CG1 CG2 CG3 CG4 CG5 GND CG6 CG7 CG8 CG9 CG10 2065769-1 C 2065769-1 P2 DCLKB2D1BD3BD5BD7BD9BD11BD13BD15BDCLKB1- B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 BG1 BG2 BG3 BG4 BG5 GND BG6 BG7 BG8 BG9 BG10 DGND D0B+ D2B+ D4B+ D6B+ D8B+ D10B+ D12B+ D14B+ D16B+ D17B+ C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 CG1 CG2 CG3 CG4 CG5 GND CG6 CG7 CG8 CG9 CG10 P2 D0AD2AD4AD6AD8AD10AD12AD14AD16AD17A- D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 DG1 DG2 DG3 DG4 DG5 GND DG6 DG7 DG8 DG9 DG10 2065769-1 DCLKB2+ D1B+ D3B+ D5B+ D7B+ D9B+ D11B+ D13B+ D15B+ DCLKB1+ A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 AG1 AG2 AG3 AG4 AG5 GND AG6 AG7 AG8 AG9 AG10 2065769-1 P1 DCLKA2D1AD3AD5AD7AD9AD11AD13AD15ADCLKA1- P2 P2 D0A+ D2A+ D4A+ D6A+ D8A+ D10A+ D12A+ D14A+ D16A+ D17A+ 2065769-1 P1 MGTCLK2SD8SD7SD6SD5SD4SD3SD2SD1MGTCLK1- D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 DG1 DG2 DG3 DG4 DG5 GND DG6 DG7 DG8 DG9 DG10 DGND DCLKA2+ D1A+ D3A+ D5A+ D7A+ D9A+ D11A+ D13A+ D15A+ DCLKA1+ A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 AG1 AG2 AG3 AG4 AG5 GND AG6 AG7 AG8 AG9 AG10 2065769-1 P3 P1 P1 MGTCLK2+ SD8+ SD7+ SD6+ SD5+ SD4+ SD3+ SD2+ SD1+ MGTCLK1+ C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 CG1 CG2 CG3 CG4 CG5 GND CG6 CG7 CG8 CG9 CG10 (J2) DATA BUS 1 (J3) DATA BUS 2 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 DG1 DG2 DG3 DG4 DG5 GND DG6 DG7 DG8 DG9 DG10 2065769-1 DGND D0BD2BD4BD6BD8BD10BD12BD14BD16BD17B- B DGND R105 DNI DCLKB2+ 0 R106 DNI DCLKB1+ DCLKB+ 0 R107 DNI DCLKB20 R108 DNI DCLKB1- DCLKB- 0 A 0 SELECT GLOBAL CLOCK OR CLOCK CAPABLE IO AN A LO G DE V CES THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, SCHEMATIC <DRAWING_TITLE_HEADER> CVTADCFMCINTPZ ENGINEERING BOARD DESIGN VIEW REV DRAWING NO. <DESIGN_VIEW> B CVTADCFMCINTPZ01 OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. SIZE PTD ENGINEER D THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 8 7 6 5 4 3 R. Reeder 2 SCALE NONE SHEET 1 1 OF 2 8 6 7 2 3 4 5 1 REVISIONS REV DESCRIPTION DATE APPROVED NOTE: FMC CONNECTIONS SD5+ SD5- SD6+ SD6- C D5A+ D5A- D9A+ D9A- D13A+ D13A- D17A+ D17A- CSB3_C CSB4_C SCL SDA GA0 3P3V DGND SD8+ SD8- SD7+ SD7- MGTCLK2+ MGTCLK2- A D4B+ D4BD8B+ D8BD12B+ D12BD15B+ D15BI/O_8 I/O_7 VADJ DGND P201 B D0B+ D0B- E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 E32 E33 E34 E35 E36 E37 E38 E39 E40 ASP-134488-01 MGTCLK1+ MGTCLK1- D0A+ D0AD4A+ D4AD8A+ D8AD12A+ D12AD16A+ D16AI/O_3 I/O_4 CSB1_C CSB2_C TDI TDO 3P3V_AUX GA1 3P3V 3P3V 3P3V DGND D2A+ D2AD7A+ D7AD11A+ D11AD15A+ D15AUSB_3 USB_4 SCLK_C VADJ DGND P201 B1 CLK_DIR B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 ASP-134488-01 DCLKA+ DCLKA- G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 G31 G32 G33 G34 G35 G36 G37 G38 G39 G40 ASP-134488-01 DCLKB1+ DCLKB1D3B+ D3BD7B+ D7BD11B+ D11BD14B+ D14BD17B+ D17B- VADJ DGND D6B+ D6BD10B+ D10BD13B+ D13BD16B+ D16B- DGND P201 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 ASP-134488-01 D2B+ D2B- J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 J31 J32 J33 J34 J35 J36 J37 J38 J39 J40 ASP-134488-01 DCLKB+ DCLKBD1A+ D1AD3A+ D3AD6A+ D6AD10A+ D10AD14A+ D14AUSB_1 USB_2 USB_5 SDO_C SDI_C I/O_5 I/O_6 VADJ DGND DGND D1B+ D1BD5B+ D5BD9B+ D9BDCLKB2+ DCLKB2I/O_2 I/O_1 DGND VCC 1 A0 2 A1 3 A2 6 SCL 7 GA1 GA0 SCL 5 SDA WP SDA GND 4 AT24C02C-XHM-B DGND VADJ R209 3P3V 0 C202 0.1UF C201 0.1UF 19 SDO_C SDI_C SCLK_C CSB1_C CSB2_C CSB3_C CSB4_C R201 33 8 20 1 2 3 4 5 6 7 R202 33 R203 33 R204 33 R205 33 R206 33 R207 33 C DGND R208 10K DGND 18 VCCA Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 GND 9 U201 VCCY EN A1 A2 A3 A4 A5 A6 A7 A8 17 16 15 14 13 12 11 10 R212 33 R214 33 R216 33 R218 33 SDO_M R213 SDI_M 33 SCLK_M R215 CSB1_M 33 CSB2_M R217 CSB3_M 33 CSB4_M PAD PAD ADG3308BCPZ DGND P201 H1 H2 PRSNT_M2C_L H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 H31 H32 H33 H34 H35 H36 H37 H38 H39 H40 ASP-134488-01 U202 8 DGND P201 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 ASP-134488-01 C203 0.1UF K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K30 K31 K32 K33 K34 K35 K36 K37 K38 K39 K40 ASP-134488-01 TP202 1 BLK TP201 1 BLK 3P3V B VADJ A SD4+ SD4- SD1+ SD1- C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 ASP-134488-01 C SD3+ SD3- A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 ASP-134488-01 D 3P3V_AUX CR202 SD2+ SD2- P201 P201 P201 A P201 P201 C D LPC CR201 LPC 3P3V = 3.3V VADJ = 3.3V - 0V R219 249 R220 249 DGND DGND A AN A LO G DE V CES THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. DGND IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, SCHEMATIC <DRAWING_TITLE_HEADER> CVTADCFMCINTPZ ENGINEERING BOARD DESIGN VIEW REV DRAWING NO. <DESIGN_VIEW> B CVTADCFMCINTPZ01 OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. SIZE PTD ENGINEER D THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 8 7 6 5 4 3 R. Reeder 2 SCALE NONE SHEET 1 2 OF 2