Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report 2015.06.25 AN-JESD204B-AV Subscribe Send Feedback The Altera JESD204B IP core is a high-speed point-to-point serial interface intellectual property (IP). ® The JESD204B IP core has been hardware-tested with a number of selected JESD204B-compliant ADC (analog-to-digital converter) device. This report highlights the interoperability of the JESD204B IP core with the AD9250 Analog-to-Digital Converter evaluation module (EVM) from Analog Devices Inc. (ADI). The hardware checkout methodology and test results are described in the following sections. Related Information • JESD204B IP Core User Guide • ADI AD9250 Analog-to-Digital Converter Hardware Requirements The hardware checkout test requires the following hardware and software tools: • • • • Arria V GT FPGA Development Kit with 19 V power adaptor Arria V SoC Development Kit ADI AD9250 EVM (AD9250-FMC-250EBZ) Mini-USB cable ® Related Information • • • • Arria V GT FPGA Development Kit User Guide Arria V GT FPGA Development Board Reference Manual Arria V SoC Development Kit User Guide Arria V SoC Development Board Reference Manual Hardware Setup Set up the development kit with the ADI AD9250 daughter card module installed to the board's FMC connector. © 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. www.altera.com 101 Innovation Drive, San Jose, CA 95134 ISO 9001:2008 Registered 2 AN-JESD204B-AV 2015.06.25 Hardware Setup Figure 1: Hardware Setup for Arria V GT Development Kit • The AD9250 module derives power from the FMC connector on the development board. • The AD9250 module supplies the device clock to FPGA 2. • For subclass 1 mode, the FPGA generates SYSREF for the JESD204B MegaCore function as well as the AD9250 module. FPGA 1 FPGA 2 Status LED Transceiver Lanes Device Clock SYSREF rx_dev_sync_n SPI Power Arria V GT FPGA Development Board Altera Corporation ADI AD9250 Module Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report Send Feedback AN-JESD204B-AV 2015.06.25 Hardware Setup 3 Figure 2: Hardware Setup for Arria V SoC Development Kit • The AD9250 module derives power from the FMC connector on the development board. • The AD9250 module supplies clock to the FPGA and ADC. • For subclass 1 mode, the FPGA generates SYSREF for the JESD204B IP core as well as the AD9250 module. Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report Send Feedback Altera Corporation 4 AN-JESD204B-AV 2015.06.25 Hardware Checkout Methodology Figure 3: System Diagram The system-level diagram shows how the different modules connect in this design. In this setup where LMF = 222, the data rate of the both transceiver lanes is 4.915 Gbps. The AD9517 clock generator provides 122.88 MHz clock to the FPGA and 245.76 MHz sampling clock to both AD9250 devices. jesd204b_ed_top.v Arria V FPGA #2/Arria V SoC Oscillator 100 MHz mgmt_clk ISSP global_reset rx_seriallpbken FMC jesd204b_ed.v (Example Design) Qsys System JTAG to Avalon Master Bridge 4-Wire device_clk (122.88 MHz) SignalTap II Logic Analyzer LED sclk, ss_n[0], miso, mosi Avalon-MM Interface Signals Avalon-MM Slave Translator link_clk (122.88 MHz) sysref_out Sysref Generator rx_dev_sync_n JESD204B IP (Duplex) L = 2, M = 2, F = 2 AD9250-FMC-250EBZ SPI Slave CPLD 3- or 4-Wire SPI AD9517 Clock Generator Single-Ended to Differential Distribution rx_serial_data[0] (4.915 Gbps) L0 rx_serial_data[1] (4.915 Gbps) L1 AD9250 ADC#1 CLK and SYNC 3-Wire SPI ADC ADC SPI Slave AD9250 ADC#2 CLK and SYNC ADC ADC sync_n sysref ADC#2 clk (245.76 MHz) Related Information AN 696: Using the JESD204B IP Core in Arria V Devices More information on how to set up the board. Hardware Checkout Methodology The following section describes the test objectives, procedure, and the passing criteria. The test covers the following areas: • • • • Receiver data link layer Receiver transport layer Descrambling Deterministic latency (Subclass 1) Receiver Data Link Layer This test area covers the test cases for code group synchronization (CGS) and initial frame and lane synchronization. On link start up, the receiver issues a synchronization request and the transmitter transmits /K/ (K28.5) characters. The SignalTap II Logic Analyzer tool is used to monitor the operation of receiver data link layer. Altera Corporation Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report Send Feedback AN-JESD204B-AV 2015.06.25 Code Group Synchronization (CGS) 5 Code Group Synchronization (CGS) Table 1: CGS Test Cases Test Case Objective Description Passing Criteria CGS.1 Check whether sync request is deasserted after correct reception of four successive /K/ characters. The following signals in <ip_variant_ • /K/ character (0xBC) is name>_inst_phy.v are tapped: observed at each octet of the jesd204_rx_pcs_data bus. • jesd204_rx_pcs_data[(L*32)• The jesd204_rx_pcs_data_ 1:0] valid signal is asserted to • jesd204_rx_pcs_data_valid[Lindicate that data from the PCS 1:0] is valid. • jesd204_rx_pcs_kchar_ • The jesd204_rx_pcs_kchar_ data[(L*4)-1:0] (1) data signal is asserted The following signals in <ip_variant_ whenever control characters name>.v are tapped: like /K/, /R/, /Q/, or /A/ are observed. • rx_dev_sync_n • The rx_dev_sync_n signal is • jesd204_rx_int deasserted after correct The rxframe_clk is used as the reception of at least four SignalTap II sampling clock. successive /K/ characters. • The jesd204_rx_int signal is Each lane is represented by 32-bit deasserted if there is no error. data bus in jesd204_rx_pcs_data. The 32-bit data bus is divided into 4 octets. CGS.2 Check full CGS at the receiver after correct reception of another four 8B/10B characters. The following signals in <ip_variant_ The jesd204_rx_pcs_errdetect, jesd204_rx_pcs_disperr, and name>_inst_phy.v are tapped: jesd204_rx_int signals should • jesd204_rx_pcs_ not be asserted during CGS phase. errdetect[(L*4)-1:0] • jesd204_rx_pcs_disperr[(L*4) -1:0] (1) The following signal in <ip_variant_ name>.v is tapped: • jesd204_rx_int The rxframe_clk is used as the SignalTap II sampling clock. (1) L is the number of lanes. Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report Send Feedback Altera Corporation 6 AN-JESD204B-AV 2015.06.25 Initial Frame and Lane Synchronization Initial Frame and Lane Synchronization Table 2: Initial Frame and Lane Synchronization Test Cases Test Case Objective Description Passing Criteria ILA.1 Check whether the initial frame synchronization state machine enters FS_DATA state upon receiving non /K/ characters. The following signals in <ip_variant_ • /R/ character or K28.0 (0x1C) name>_inst_phy.v are tapped: is observed after /K/ character at the jesd204_rx_pcs_data • jesd204_rx_pcs_data[(L*32)bus. 1:0] • The jesd204_rx_pcs_data_ • jesd204_rx_pcs_data_valid[Lvalid signal must be asserted 1:0] to indicate that data from the • jesd204_rx_pcs_kchar_ PCS is valid. data[(L*4)-1:0] (1) • The rx_dev_sync_n and The following signals in <ip_variant_ jesd204_rx_int signal are name>.v are tapped: deasserted. • Each multiframe in the ILAS • rx_dev_sync_n phase ends with /A/ character • jesd204_rx_int or K28.3 (0x7C). The rxframe_clk is used as the • The jesd204_rx_pcs_kchar_ SignalTap II sampling clock. data signal is asserted whenever control characters Each lane is represented by 32-bit like /K/, /R/, /Q/, or /A/ are data bus in jesd204_rx_pcs_data. observed. The 32-bit data bus is divided into 4 octets. ILA.2 Check the JESD204B configuration parameters from ADC in the second multiframe. The following signals in <ip_variant_ • /R/ character is followed by /Q/ name>_inst_phy.v are tapped: character or K28.4 (0x9C) at the beginning of the second • jesd204_rx_pcs_data[(L*32)multiframe. 1:0] • The jesd204_rx_int signal is • jesd204_rx_pcs_data_valid[L(1) deasserted if there is no error. 1:0] • Octets 0-13 read from these The following signal in <ip_variant_ registers match with the name>.v is tapped: JESD204B parameters in each test setup. • jesd204_rx_int The rxframe_clk is used as the SignalTap II sampling clock. The System Console accesses the following registers: • • • • Altera Corporation ilas_octet0 ilas_octet1 ilas_octet2 ilas_octet3 Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report Send Feedback AN-JESD204B-AV 2015.06.25 Receiver Transport Layer Test Case ILAS.3 Objective Description 7 Passing Criteria The following signals in <ip_variant_ • The dev_lane_aligned signal name>_inst_phy.v are tapped: is asserted after the end of the fourth multiframe in ILAS • jesd204_rx_pcs_data[(L*32)phase but before the first rx_ 1:0] somf signal is asserted. • jesd204_rx_pcs_data_valid[L(1) • The rx_somf signal marks the 1:0] start of multiframe in user data The following signal in <ip_variant_ phase. name>.v is tapped: • The jesd204_rx_int signal is deasserted if there is no error. • rx_somf[3:0] • dev_lane_aligned • jesd204_rx_int Check the lane alignment The rxframe_clk is used as the SignalTap II sampling clock. Receiver Transport Layer To check the data integrity of the payload data stream through the RX JESD204B IP core and transport layer, the ADC is configured to output PRBS-9 test data pattern. The ADC is also set to operate with the same configuration as set in the JESD204B IP core. The PRBS checker in the FPGA fabric checks data integrity for one minute. Figure 4 shows the conceptual test setup for data integrity checking. Figure 4: Data Integrity Check Using PRBS Checker AD9250 PRBS Generator TX Transport Layer TX JESD204B IP Core PHY and Link Layer RX Transport Layer RX JESD204B IP Core PHY and Link Layer FPGA PRBS Checker The SignalTap II Logic Analyzer tool is used to monitor the operation of the RX transport layer. Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report Send Feedback Altera Corporation 8 AN-JESD204B-AV 2015.06.25 Descrambling Table 3: Transport Layer Test Cases Test Case TL.1 Objective Check the transport layer mapping. Description The following signals in altera_ jesd204_transport_rx_top.v are tapped: • jesd204_rx_data_valid • jesd204_rx_link_data_valid • jesd204_rx_link_error Passing Criteria • The jesd204_rx_data_valid and jesd204_rx_link_data_ valid signals is asserted. • The jesd204_rx_link_error and jesd204_rx_int signals is deasserted. The following signals in jesd204b_ ed.v are tapped: • data_error[M-1:0] • jesd204_rx_int M is the number of converters. The rxframe_clk is used as the SignalTap II sampling clock. The data_error signal is the PRBS checker's pass or fail indicator. Descrambling The PRBS checker at the RX transport layer checks the data integrity of descrambler. The SignalTap II Logic Analyzer tool is used to monitor the operation of the RX transport layer. Table 4: Descrambler Test Cases Test Case SCR.1 Objective Check the functionality of the descrambler. Description Passing Criteria Enable scrambler at the ADC and descrambler at the RX JESD204B IP core. • The jesd204_rx_data_valid and jesd204_rx_link_data_ valid signals is asserted. The signals that are tapped in this test • The jesd204_rx_link_error and jesd204_rx_int signals is case are similar to test case TL.1 deasserted. Deterministic Latency (Subclass 1) Figure 5 shows the block diagram of deterministic latency test setup. A SYSREF generator provides a periodic SYSREF pulse for both the AD9250 and JESD204B IP core. The SYSREF generator is running in link clock domain and the period of SYSREF pulse is configured to the desired multiframe size. The SYSREF pulse restarts the LMF counter and realigns it to the LMFC boundary. Altera Corporation Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report Send Feedback AN-JESD204B-AV 2015.06.25 9 Deterministic Latency (Subclass 1) Figure 5: Deterministic Latency Test Setup Block Diagram jesd204b_ed_top.v Arria V FPGA #2/Arria V SoC Oscillator 100 MHz FMC jesd204b_ed.v (Example Design) mgmt_clk global_rst_n USER2_DIPSW[0] (SW3) Deterministic Latency Measurement 4-Wire link_clk (122.88 MHz) Sysref Generator sysref_out rx_dev_sync_n JESD204B IP (Duplex) L = 2, M = 2, F = 2 SPI Slave CPLD 3- or 4-Wire SPI AD9517 Clock Generator device_clk (122.88 MHz) SignalTap II Logic Analyzer USER2_PB0 (S11) sclk, ss_n[0], miso, mosi AD9250-FMC-250EBZ Single-Ended to Differential Distribution rx_serial_data[0] (4.915 Gbps) L0 rx_serial_data[1] (4.915 Gbps) L1 AD9250 ADC#1 CLK and SYNC 3-Wire SPI ADC ADC SPI Slave AD9250 ADC#2 CLK and SYNC ADC ADC sync_n sysref ADC#2 clk (245.76 MHz) The deterministic latency measurement block checks the deterministic latency by measuring the number of link clock counts between the start of deassertion of SYNC~ to the first user data output. Figure 6: Deterministic Latency Measurement Timing Diagram Link Clock State ILAS USER_DATA SYNC~ RX Valid sync_to_rxvalid_cnt 1 2 3 n-1 n With the setup above, four test cases were defined to prove deterministic latency. By default, the JESD204B IP core performs a single SYSREF detection. The SYSREF N-shot mode is enabled on the AD9250 for this deterministic measurement. Table 5: Deterministic Latency Test Cases Test Case DL.1 Objective Check the LMFC alignment. Description Check that the FPGA and ADC are aligned to the desired LMF periods. SYSREF detection is always enabled. Passing Criteria The sysref_lmfc_err signal should not be triggered. Observe the sysref_lmfc_err signal from the Signal Tap II Logic Analyzer. Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report Send Feedback Altera Corporation 10 AN-JESD204B-AV 2015.06.25 JESD204B IP Core and AD9250 Configurations Test Case DL.2 Objective Check the SYSREF capture. Description Passing Criteria Check that the FPGA and ADC capture SYSREF correctly and restart the LMF counter. Both the FPGA and ADC are also repetitively reset. Observe the csr_rbd_count signal from the Signal Tap II Logic Analyzer. DL.3 Check the latency from start of deassertion of SYNC~ to the first user data output. If the SYSREF is captured correctly and the LMF counter restarts, the csr_rbd_count value should only drift a little for every reset due to word alignment. Check that the latency is fixed for Consistent latency from the start every FPGA reset. Repetitively reset of deassertion of SYNC~ to the the FPGA upon assertion of RX valid. first user data output latency. Record the number of link clocks count from start of deassertion of SYNC~ to the first user data output. Continuously compare the current test (n) that records the number of link clocks from deassertion of SYNC~ to the first user data output with the previous test (n-1) record. JESD204B IP Core and AD9250 Configurations The JESD204B IP core parameters (L, M and F) in this hardware checkout are natively supported by the AD9250 module's quick configuration register at address 0x5E. The transceiver data rate, sampling clock frequency, and other JESD204B parameters complies with the AD9250 operating conditions. The hardware checkout testing implements the JESD204B IP core with the following parameter configu‐ ration. Table 6: Parameter Configuration Configuration JESD204B Parameters Altera Corporation Setting LMF 112 124 222 211 HD 0 0 0 1 S 1 1 1 1 N 14 14 14 14 N' 16 16 16 16 CS 0 0 0 0 CF 0 0 0 0 Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report Send Feedback AN-JESD204B-AV 2015.06.25 11 Test Results Configuration FPGA Clock Setting Device Clock (MHz) (2) 122.88 Management Clock (MHz) 100 Frame Clock/Sampling Clock (MHz) (3) 245.76 Link Clock (MHz) (3) 122.88 /K/ Character Replacement Enabled Data Pattern PRBS-9 122.88 245.76 245.76 61.44 Ramp (4) Test Results The following table contains the possible results and their definition. Table 7: Results Definition Result Definition PASS The Device Under Test (DUT) was observed to exhibit conformant behavior. PASS with comments The DUT was observed to exhibit conformant behavior. However, an additional explanation of the situation is included, such as due to time limitations, only a portion of the testing was performed. FAIL The DUT was observed to exhibit non-conformant behavior. Warning The DUT was observed to exhibit behavior that is not recommended. Refer to comments From the observations, a valid pass or fail could not be determined. An additional explanation of the situation is included. The following table shows the results for test cases CGS.1, CGS.2, ILA.1, ILA.2, ILA.3, TL.1, and SCR.1 with different values of L, M, F, K, subclass, data rate, sampling clock, link clock and SYSREF frequencies. Table 8: Test Results Test (2) (3) (4) L M F Subclass SCR K Data rate Sampling (Mbps) Clock (MHz) Link Clock (MHz) SYSREF (MHz) Result 1 1 1 2 0 0 16 4915 245.76 122.88 — PASS 2 1 1 2 0 0 32 4915 245.76 122.88 — PASS 3 1 1 2 0 1 16 4915 245.76 122.88 — PASS 4 1 1 2 0 1 32 4915 245.76 122.88 — PASS The device clock is used to clock the transceiver. The frame clock and link clock is derived from the device clock using an internal PLL. The ramp pattern is used in deterministic latency measurement test cases DL.1, DL.2, and DL.3 only. Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report Send Feedback Altera Corporation 12 AN-JESD204B-AV 2015.06.25 Test Results Test (5) L M F Subclass SCR K Data rate Sampling (Mbps) Clock (MHz) Link Clock (MHz) SYSREF (MHz) Result 5 1 1 2 1 0 16 4915 245.76 122.88 15.36 PASS 6 1 1 2 1 0 32 4915 245.76 122.88 7.68 PASS 7 (5) 1 1 2 1 1 16 4915 245.76 122.88 15.36 PASS 8 (5) 1 1 2 1 1 32 4915 245.76 122.88 7.68 PASS 9 1 2 4 0 0 16 4915 122.88 122.88 — PASS 10 1 2 4 0 0 32 4915 122.88 122.88 — PASS 11 1 2 4 0 1 16 4915 122.88 122.88 — PASS 12 1 2 4 0 1 32 4915 122.88 122.88 — PASS 13 1 2 4 1 0 16 4915 122.88 122.88 7.68 PASS 14 1 2 4 1 0 32 4915 122.88 122.88 3.84 PASS 15 (5) 1 2 4 1 1 16 4915 122.88 122.88 7.68 PASS 16 (5) 1 2 4 1 1 32 4915 122.88 122.88 3.84 PASS 17 2 1 1 0 0 20 2457 245.76 61.44 — PASS 18 2 1 1 0 0 32 2457 245.76 61.44 — PASS 19 2 1 1 0 1 20 2457 245.76 61.44 — PASS 20 2 1 1 0 1 32 2457 245.76 61.44 — PASS 21 2 1 1 1 0 20 2457 245.76 61.44 12.288 PASS 22 2 1 1 1 0 32 2457 245.76 61.44 7.68 PASS 23 (5) 2 1 1 1 1 20 2457 245.76 61.44 12.288 PASS 24 (5) 2 1 1 1 1 32 2457 245.76 61.44 7.68 PASS 25 2 2 2 0 0 16 4915 245.76 122.88 — PASS 26 2 2 2 0 0 32 4915 245.76 122.88 — PASS 27 2 2 2 0 1 16 4915 245.76 122.88 — PASS 28 2 2 2 0 1 32 4915 245.76 122.88 — PASS 29 2 2 2 1 0 16 4915 245.76 122.88 15.36 PASS 30 2 2 2 1 0 32 4915 245.76 122.88 7.68 PASS 31 (5) 2 2 2 1 1 16 4915 245.76 122.88 15.36 PASS 32 (5) 2 2 2 1 1 32 4915 245.76 122.88 7.68 PASS Results for both Arria V GT and Arria V SoC devices. Altera Corporation Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report Send Feedback AN-JESD204B-AV 2015.06.25 13 Test Results Table 9: Deterministic Latency Measurement for Arria V GT Test L M F Subclass K Data rate (Mbps) Sampling Clock (MHz) Link Clock (MHz) SYSREF (MHz) Result DL.1 2 2 2 1 32 4915 245.76 122.88 7.68 PASS DL.2 2 2 2 1 32 4915 245.76 122.88 7.68 PASS DL.3 2 2 2 1 32 4915 245.76 122.88 7.68 PASS with comments. Link clock observed: 131-132 Table 10: Deterministic Latency Measurement for Arria V SoC Test L M F Subclass SCR K Data Rate Link Clock (Msps) (MHz) Result DL.1 PASS DL.2 PASS DL.3 1 1 2 1 1 16 4915 122.88 PASS with comments. Link clock observed: 83 DL.1 PASS DL.2 PASS DL.3 1 1 2 1 1 32 4915 122.88 PASS with comments. Link clock observed: 131 DL.1 PASS DL.2 PASS DL.3 1 2 4 1 1 16 4915 122.88 PASS with comments. Link clock observed: 131 Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report Send Feedback Altera Corporation 14 AN-JESD204B-AV 2015.06.25 Test Results Test L M F Subclass SCR K Data Rate Link Clock (Msps) (MHz) Result DL.1 PASS DL.2 PASS DL.3 1 2 4 1 1 32 4915 122.88 PASS with comments. Link clock observed: 227 DL.1 PASS DL.2 PASS DL.3 2 1 1 1 1 20 2457 61.44 PASS with comments. Link clock observed: 63 DL.1 PASS DL.2 PASS DL.3 2 1 1 1 1 32 2457 61.44 PASS with comments. Link clock observed: 83 DL.1 PASS DL.2 PASS DL.3 2 2 2 1 1 16 4915 122.88 PASS with comments. Link clock observed: 83 DL.1 PASS DL.2 PASS DL.3 2 2 2 1 1 32 4915 122.88 PASS with comments. Link clock observed: 131 The following figure shows the SignalTap II waveform of the clock count from the deassertion of SYNC~ in the first output of the ramp test pattern. The clock count measures the first user data output latency. Altera Corporation Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report Send Feedback AN-JESD204B-AV 2015.06.25 Test Result Comments 15 Figure 7: Deterministic Latency Measurement Ramp Test Pattern 002h 001h 1Fh 00h 03h 000h 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 131 test_fail test_cnt sysref test_k rx_sync_n rx_valid csr_rbd_count csr_rbd_offset sync_to_nvalid_cnt sync_to_rxvalid_cnt_pre 0000000h 001h 002h 1Fh 00h 000h 0 131 03h 131 jesd204_rx_dataout[13:0] jesd204_rx_dataout[27:14] Test Result Comments In each test case, the RX JESD204B IP core successfully initialize from CGS phase, ILA phase, and until user data phase. No data integrity issue is observed by the PRSB checker. For test case with LMF = 211, the data rate is reduced to 2457 Mbps to limit the ADC sample clock to less than 250 MHz. The following table describes the scenarios where there is a difference in the data rate. Table 11: Sample Rate Implication for Test Case with LMF = 211 Item Data rate Scenario 1 4915 Mbps Scenario 2 2457 Mbps Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report Send Feedback Remark Data rate is within the operating condition of AD9250. Altera Corporation 16 AN-JESD204B-AV 2015.06.25 Document Revision History Item Scenario 1 Link clock = data rate/40 Scenario 2 122.88 MHz ADC sample clock must be 491.52 MHz ≤ ADC maximum sampling rate Remark 61.44 MHz Link clock frequency is determined by the data rate. 245.76 MHz Sample clock frequency in scenario 1 is beyond the operating condition of AD9250. The link clock count variation in the deterministic latency measurement is caused by the word alignment, where control characters fall into the next cycle of data some time after realignment. This makes the duration of the ILAS phase longer by one link clock some time after reset. Document Revision History Date Version Changes June 2015 2015.06.25 Added new information on hardware setup, parameter configurations, and test results for Arria V SoC device. December 2013 2013.12.02 Initial release. How to Contact Altera Table 12: How to Contact Altera To locate the most up-to-date information about Altera products, refer to this table. You can also contact your local Altera sales office or sales representative. Contact Contact Method Address Website www.altera.com/support Website www.altera.com/training Email [email protected] Product literature Website www.altera.com/literature Nontechnical support: general Email [email protected] Nontechnical support: software licensing Email [email protected] Technical support Technical training Altera Corporation Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report Send Feedback