AD9257-EP Data Sheet

Octal, 14-Bit, 65 MSPS, Serial LVDS,
1.8 V Analog-to-Digital Converter
AD9257-EP
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
AVDD
AD9257-EP
ADC
VIN+ B
VIN– B
ADC
VIN+ C
VIN– C
ADC
VIN+ D
VIN– D
ADC
VIN+ E
VIN– E
ADC
VIN+ F
VIN– F
ADC
VIN+ G
VIN– G
ADC
VIN+ H
VIN– H
ADC
Medical imaging and nondestructive ultrasound
Portable ultrasound and digital beam forming systems
Quadrature radio receivers
Diversity radio receivers
Optical networking
Test equipment
GENERAL DESCRIPTION
The AD9257-EP is an octal, 14-bit, 65 MSPS analog-to-digital
converter (ADC) with an on-chip sample-and-hold circuit
designed for low cost, low power, small size, and ease of use.
The product operates at a conversion rate of up to 65 MSPS and
is optimized for outstanding dynamic performance and low
power in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock output (DCO) for
capturing data on the output and a frame clock output (FCO) for
signaling a new output byte are provided. Individual channel
Rev. A
D+ A
D– A
SERIAL
LVDS
14
SERIAL
LVDS
D+ B
D– B
SERIAL
LVDS
D+ C
D– C
SERIAL
LVDS
D+ D
D– D
SERIAL
LVDS
D+ E
D– E
SERIAL
LVDS
D+ F
D– F
SERIAL
LVDS
D+ G
D– G
SERIAL
LVDS
D+ H
D– H
14
14
14
14
14
14
VREF
SENSE
ENHANCED PRODUCT FEATURES
APPLICATIONS
DRVDD
14
VIN+ A
VIN– A
VCM
Supports defense and aerospace applications (AQEC standard)
Military temperature range (−55°C to +125°C)
Controlled manufacturing baseline
Qualification data available on request
PDWN
1.0V
SERIAL PORT
INTERFACE
REF
SELECT
DATA RATE
MULTIPLIER
SYNC
RBIAS
AGND
CSB
SDIO/ SCLK/
DFS
DTP
CLK+ CLK–
FCO+
FCO–
DCO+
DCO–
12740-001
Low power: 55 mW per channel at 65 MSPS with scalable
power options
SNR = 75.5 dB (to Nyquist)
SFDR = 91 dBc (to Nyquist)
DNL = ±0.6 LSB (typical), INL = ±1.1 LSB (typical)
Serial LVDS (ANSI-644, default)
Low power, reduced signal option (similar to IEEE 1596.3)
Data and frame clock outputs
650 MHz full power analog bandwidth
2 V p-p input voltage range
1.8 V supply operation
Serial port control
Full chip and individual channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Programmable clock and data alignment
Programmable output resolution
Standby mode
Figure 1.
power-down is supported and typically consumes 1 mW when
all channels are disabled. The ADC contains several features
designed to maximize flexibility and minimize system cost, such as
programmable clock and data alignment and programmable digital
test pattern generation. The available digital test patterns include
built-in deterministic and pseudorandom patterns, along with
custom user defined test patterns entered via the serial port
interface (SPI).
The AD9257-EP is available in an RoHS-compliant, 64-lead
LFCSP. It is specified over the −55°C to +125°C temperature. This
product is protected by a U.S. patent. Additional application and
technical information can be found in the AD9257 data sheet.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
Small Footprint. Eight ADCs are contained in a small,
space-saving package.
Low Power of 55 mW/Channel at 65 MSPS with Scalable
Power Options.
Ease of Use. A DCO is provided that operates at frequencies of up to 455 MHz and supports double data rate
(DDR) operation.
User Flexibility. The SPI control offers a wide range of
flexible features to meet specific system requirements.
Pin Compatible with the AD9637 (12-Bit Octal ADC).
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD9257-EP
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Switching Specifications ...............................................................6
Enhanced Product Features ............................................................ 1
Timing Specifications ...................................................................6
Applications ....................................................................................... 1
Absolute Maximum Ratings ............................................................9
General Description ......................................................................... 1
Thermal Characteristics ...............................................................9
Functional Block Diagram .............................................................. 1
ESD Caution...................................................................................9
Product Highlights ........................................................................... 1
Pin Configuration and Function Descriptions........................... 10
Revision History ............................................................................... 1
Typical Performance Characteristics ........................................... 12
Specifications..................................................................................... 3
Outline Dimensions ....................................................................... 13
DC Specifications ......................................................................... 3
Ordering Guide .......................................................................... 13
AC Specifications.......................................................................... 4
Digital Specifications ................................................................... 5
REVISION HISTORY
6/15—Rev. 0 to Rev. A
Changes to Table 2 ............................................................................ 4
Changes to Table 3 ............................................................................ 5
Changes to Table 6 ............................................................................ 9
Changes to Figure 6 ........................................................................ 10
2/15—Revision 0: Initial Version
Rev. A | Page 2 of 13
Data Sheet
AD9257-EP
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 1.
Parameter1
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Offset Matching
Gain Error
Gain Matching
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
INTERNAL VOLTAGE REFERENCE
Output Voltage (1 V Mode)
Load Regulation at 1.0 mA (VREF = 1 V)
Input Resistance
INPUT REFERRED NOISE
VREF = 1.0 V
ANALOG INPUTS
Differential Input Voltage (VREF = 1 V)
Common-Mode Voltage
Common-Mode Range
Differential Input Resistance
Differential Input Capacitance
POWER SUPPLY
AVDD
DRVDD
IAVDD
IDRVDD (ANSI-644 Mode)
IDRVDD (Reduced Range Mode)
TOTAL POWER CONSUMPTION
Total Power Dissipation (Eight Channels, ANSI-644 Mode)
Total Power Dissipation (Eight Channels, Reduced Range Mode)
Power-Down Dissipation
Standby Dissipation2
1
2
Temp
Full
Full
Full
Full
Full
Full
Full
Min
14
−0.7
0
−7.0
−1.0
−0.95
−4.5
Full
Full
Full
Full
Typ
Max
Unit
Bits
Guaranteed
−0.3
0.23
−2.9
+1.6
±0.6
±1.1
+0.1
0.6
+1.0
+5.0
+1.6
+4.5
% FSR
% FSR
% FSR
% FSR
LSB
LSB
±2
0.98
0.99
2
7.5
ppm/°C
1.01
V
mV
kΩ
25°C
0.94
LSB rms
Full
Full
Full
2
0.9
V p-p
V
V
kΩ
pF
0.5
Full
Full
Full
Full
Full
25°C
Full
25°C
25°C
25°C
1.3
5.2
3.5
1.7
1.7
1.8
1.8
198
60
45
1.9
1.9
211
93
V
V
mA
mA
mA
464
437
1
92
547
mW
mW
mW
mW
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
Can be controlled via the SPI.
Rev. A | Page 3 of 13
AD9257-EP
Data Sheet
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted. CLK
divider = 8 used for typical characteristics at input frequency ≥ 19.7 MHz.
Table 2.
Parameter1
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 9.7 MHz
fIN = 19.7 MHz
fIN = 30.5 MHz
fIN = 63.5 MHz
fIN = 123.4 MHz
SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD)
fIN = 9.7 MHz
fIN = 19.7 MHz
fIN = 30.5 MHz
fIN = 63.5 MHz
fIN = 123.4 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 9.7 MHz
fIN = 19.7 MHz
fIN = 30.5 MHz
fIN = 63.5 MHz
fIN = 123.4 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 9.7 MHz
fIN = 19.7 MHz
fIN = 30.5 MHz
fIN = 63.5 MHz
fIN = 123.4 MHz
WORST HARMONIC (SECOND OR THIRD)
fIN = 9.7 MHz
fIN = 19.7 MHz
fIN = 30.5 MHz
fIN = 63.5 MHz
fIN = 123.4 MHz
WORST OTHER (EXCLUDING SECOND OR THIRD)
fIN = 9.7 MHz
fIN = 19.7 MHz
fIN = 30.5 MHz
fIN = 63.5 MHz
fIN = 123.4 MHz
TWO-TONE INTERMODULATION DISTORTION (IMD)—AIN1 AND AIN2 = −7.0 dBFS
fIN1 = 30 MHz, fIN2 = 32 MHz
CROSSTALK2
Crosstalk (Overrange Condition)3
POWER SUPPLY REJECTION RATIO (PSRR)4
AVDD
DRVDD
ANALOG INPUT BANDWIDTH, FULL POWER
Temp
25°C
Full
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
Min
72.8
70.9
11.5
78
Typ
Max
Unit
75.7
75.6
75.5
74.9
73.2
dBFS
dBFS
dBFS
dBFS
dBFS
75.6
75.6
75.4
74.8
72.8
dBFS
dBFS
dBFS
dBFS
dBFS
12.3
12.3
12.2
12.1
11.8
Bits
Bits
Bits
Bits
Bits
96
96
91
95
83
dBc
dBc
dBc
dBc
dBc
25°C
Full
25°C
25°C
25°C
−99
−98
−91
−98
−83
25°C
Full
25°C
25°C
25°C
−96
−96
−98
−95
−94
25°C
25°C
25°C
25°C
92
−98
−94
dBc
dB
dB
52
71
650
dB
dB
MHz
25°C
−78
−86
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
Crosstalk is measured at 10 MHz with −1.0 dBFS analog input on one channel and no input on the adjacent channel.
Overrange condition is 3 dB above the full-scale input range.
4
PSRR is measured by injecting a sinusoidal signal at 10 MHz to the power supply pin and measuring the output spur on the FFT. PSRR is calculated as the ratio of the
amplitudes of the spur voltage over the pin voltage, expressed in decibels.
1
2
3
Rev. A | Page 4 of 13
Data Sheet
AD9257-EP
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 3.
Parameter1, 2
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Differential Input Voltage3
Input Voltage Range
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
LOGIC INPUTS (PDWN, SYNC, SCLK)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (CSB)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (SDIO)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC OUTPUT (SDIO)4
Logic 1 Voltage (IOH = 800 μA)
Logic 0 Voltage (IOL = 50 μA)
DIGITAL OUTPUTS (D± x), ANSI-644
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
DIGITAL OUTPUTS (D± x), LOW POWER, REDUCED SIGNAL OPTION
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
Temp
Min
Full
Full
Full
25°C
25°C
CMOS/LVDS/LVPECL
0.2
3.6
AGND − 0.2
AVDD + 0.2
0.9
15
4
Full
Full
25°C
25°C
1.2
0
Full
Full
25°C
25°C
1.2
0
Full
Full
25°C
25°C
1.2
0
Typ
Max
V p-p
V
V
kΩ
pF
AVDD + 0.2
0.8
V
V
kΩ
pF
AVDD + 0.2
0.8
V
V
kΩ
pF
AVDD + 0.2
0.8
V
V
kΩ
pF
30
2
26
2
26
5
Full
Full
Unit
1.79
0.05
V
V
Full
Full
±247
1.13
LVDS
±350
±454
1.21
1.38
Twos complement
mV
V
Full
Full
±150
1.13
LVDS
±200
±250
1.21
1.38
Twos complement
mV
V
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
When referencing a single function of a multifunction pin in the parameters, only the portion of the pin name that is relevant to the specification is listed. For full pin
names of multifunction pins, refer to the Pin Configuration and Function Descriptions section.
3
This is specified for LVDS and LVPECL only.
4
This is specified for 13 SDIO/DFS pins sharing the same connection.
1
2
Rev. A | Page 5 of 13
AD9257-EP
Data Sheet
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 4.
Parameter1, 2
CLOCK3
Input Clock Rate
Conversion Rate
Clock Pulse Width High (tEH)
Clock Pulse Width Low (tEL)
OUTPUT PARAMETERS3
Propagation Delay (tPD)
Rise Time (tR) (20% to 80%)
Fall Time (tF) (20% to 80%)
FCO Propagation Delay (tFCO)
DCO Propagation Delay (tCPD)4
DCO to Data Delay (tDATA)4
DCO to FCO Delay (tFRAME)4
Data to Data Skew
(tDATA-MAX − tDATA-MIN)
Wake-Up Time (Standby)
Wake-Up Time (Power-Down)5
Pipeline Latency
APERTURE
Aperture Delay (tA)
Aperture Uncertainty (Jitter)
Out-of-Range Recovery Time
Temp
Min
Full
Full
Full
Full
10
10
Full
Full
Full
Full
Full
Full
Full
Full
1.5
Typ
Max
Unit
520
65
MHz
MSPS
ns
ns
3.1
ns
ps
ps
ns
ns
ps
ps
ps
7.69
7.69
1.5
(tSAMPLE/28) − 300
(tSAMPLE/28) − 300
2.3
300
300
2.3
tFCO + (tSAMPLE/28)
(tSAMPLE/28)
(tSAMPLE/28)
±50
3.1
(tSAMPLE/28) + 300
(tSAMPLE/28) + 300
±200
25°C
25°C
Full
35
375
16
μs
μs
Clock cycles
25°C
25°C
25°C
1
0.1
1
ns
ps rms
Clock cycles
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
Measured on standard FR-4 material.
3
Can be adjusted via the SPI.
4
tSAMPLE/28 is based on the number of bits divided by 2 because the delays are based on half duty cycles. tSAMPLE = 1/fS.
5
Wake-up time is defined as the time required to return to normal operation from power-down mode.
1
2
TIMING SPECIFICATIONS
Table 5.
Parameter
SYNC TIMING REQUIREMENTS
tSSYNC
tHSYNC
SPI TIMING REQUIREMENTS1
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tEN_SDIO
tDIS_SDIO
1
Description
Limit
Unit
SYNC to rising edge of CLK+ setup time
SYNC to rising edge of CLK+ hold time
See Figure 4
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
SCLK pulse width high
SCLK pulse width low
Time required for the SDIO pin to switch from an input to an output relative to the SCLK
falling edge (not shown in Figure 4)
Time required for the SDIO pin to switch from an output to an input relative to the SCLK
rising edge (not shown in Figure 4)
0.24
0.40
ns typ
ns typ
2
2
40
2
2
10
10
10
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
10
ns min
When referring to a single function of a multifunction pin, only the portion of the pin name that is relevant to the specification is listed. For full pin names of
multifunction pins, refer to the Pin Configuration and Function Descriptions section.
Rev. A | Page 6 of 13
Data Sheet
AD9257-EP
Timing Diagrams
N–1
VIN± x
tA
N
tEH
tEL
CLK–
CLK+
tCPD
DCO–
DCO+
tFCO
tFRAME
FCO–
FCO+
tPD
tDATA
MSB D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
MSB
D12
N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16
D+ x
12740-002
D– x
Figure 2. Word Wise DDR,1× Frame, 14-Bit Output Mode (Default)
N–1
VIN± x
tA
N
tEH
tEL
CLK–
CLK+
tCPD
DCO–
DCO+
tFRAME
tFCO
FCO–
FCO+
tPD
tDATA
MSB
N – 17
D10
N – 17
D9
N – 17
D8
N – 17
D7
N – 17
D6
N – 17
D5
N – 17
D4
N – 17
D+ x
Figure 3. Word Wise DDR, 1× Frame, 12-Bit Output Mode
Rev. A | Page 7 of 13
D3
N – 17
D2
N – 17
D1
N – 17
D0
N – 17
MSB
N – 16
D10
N – 16
12740-003
D– x
AD9257-EP
Data Sheet
tHIGH
tDS
tS
tDH
CSB
tCLK
tH
tLOW
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
Figure 4. Serial Port Interface Timing Diagram
CLK+
tSSYNC
tHSYNC
12740-004
SDIO DON’T CARE
DON’T CARE
SYNC
Figure 5. SYNC Input Timing Requirements
Rev. A | Page 8 of 13
D1
D0
DON’T CARE
12740-021
SCLK DON’T CARE
Data Sheet
AD9257-EP
ABSOLUTE MAXIMUM RATINGS
THERMAL CHARACTERISTICS
Table 6.
Parameter
Electrical
AVDD to AGND
DRVDD to AGND
Digital Outputs (D± x, DCO+, DCO−, FCO+,
FCO−) to AGND
CLK+, CLK− to AGND
VIN+ x, VIN− x to AGND
SCLK/DTP, SDIO/DFS, CSB to AGND
SYNC, PDWN to AGND
RBIAS, VCM to AGND
VREF, SENSE to AGND
Environmental
Operating Temperature Range (Ambient)
Maximum Junction Temperature
Lead Temperature (Soldering, 10 sec)
Storage Temperature Range (Ambient)
Rating
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
The exposed pad must be soldered to the ground plane for the
LFCSP package. Soldering the exposed pad to the PCB increases
the reliability of the solder joints and maximizes the thermal
capability of the package.
Table 7. Thermal Resistance
Package Type
64-Lead LFCSP
9 mm × 9 mm
(CP-64-4)
Airflow
Velocity
(m/sec)
0
1.0
2.5
θJA1, 2
22.3
19.5
17.5
θJC1, 3
1.4
N/A
N/A
θJB1, 4
N/A
11.8
N/A
JT1, 2
0.1
0.2
0.2
Unit
°C/W
°C/W
°C/W
1
Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
Per MIL-Std 883, Method 1012.1.
4
Per JEDEC JESD51-8 (still air).
2
3
−55°C to +125°C
150°C
300°C
−65°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Typical θJA is specified for a 4-layer PCB with a solid ground
plane. As shown Table 7, airflow improves heat dissipation,
which reduces θJA. In addition, metal in direct contact with the
package leads from metal traces, through holes, ground, and
power planes reduces θJA.
ESD CAUTION
Rev. A | Page 9 of 13
AD9257-EP
Data Sheet
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VIN+ F
VIN– F
AVDD
VIN– E
VIN+ E
AVDD
SYNC
VCM
VREF
SENSE
RBIAS
VIN+ D
VIN– D
AVDD
VIN– C
VIN+ C
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AD9257-EP
TOP VIEW
(Not to Scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AVDD
VIN+ B
VIN– B
AVDD
VIN– A
VIN+ A
AVDD
PDWN
CSB
SDIO/DFS
SCLK/DTP
AVDD
NIC
DRVDD
D+ A
D– A
NOTES
1. NIC = NOT INTERNALLY CONNECTED. THESE PINS CAN BE CONNECTED TO GROUND.
2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE
ANALOG GROUND FOR THE DEVICE. THIS EXPOSED PAD MUST BE CONNECTED TO
GROUND FOR PROPER OPERATION.
12740-005
D– G
D+ G
D– F
D+ F
D– E
D+ E
DCO–
DCO+
FCO–
FCO+
D– D
D+ D
D– C
D+ C
D– B
D+ B
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AVDD
VIN+ G
VIN– G
AVDD
VIN– H
VIN+ H
AVDD
AVDD
CLK–
CLK+
AVDD
AVDD
NIC
DRVDD
D– H
D+ H
Figure 6. Pin Configuration, Top View
Table 8. Pin Function Descriptions
Pin No.
0
Mnemonic
AGND, EP
1, 4, 7, 8, 11, 12, 37,
42, 45, 48, 51, 59, 62
13, 36
14, 35
2, 3
5, 6
9, 10
15, 16
17, 18
19, 20
21, 22
23, 24
25, 26
27, 28
29, 30
31, 32
33, 34
38
39
40
41
43, 44
46, 47
49, 50
AVDD
Description
Analog Ground, Exposed Pad. The exposed thermal pad on the bottom of the package provides
the analog ground for the device. This exposed pad must be connected to ground for proper
operation.
1.8 V Analog Supply.
NIC
DRVDD
VIN+ G, VIN− G
VIN− H, VIN+ H
CLK−, CLK+
D− H, D+ H
D− G, D+ G
D− F, D+ F
D− E, D+ E
DCO−, DCO+
FCO−, FCO+
D− D, D+ D
D− C, D+ C
D− B, D + B
D− A, D+ A
SCLK/DTP
SDIO/DFS
CSB
PDWN
VIN+ A, VIN− A
VIN− B, VIN+ B
VIN+ C, VIN− C
Not Internally Connected. These pins can be connected to ground.
1.8 V Digital Output Driver Supply.
ADC G Analog Input True, ADC G Analog Input Complement.
ADC H Analog Input Complement, ADC H Analog Input True.
Input Clock Complement, Input Clock True.
ADC H Digital Output Complement, ADC H Digital Output True.
ADC G Digital Output Complement, ADC G Digital Output True.
ADC F Digital Output Complement, ADC F Digital Output True.
ADC E Digital Output Complement, ADC E Digital Output True.
Data Clock Digital Output Complement, Data Clock Digital Output True.
Frame Clock Digital Output Complement, Frame Clock Digital Output True.
ADC D Digital Output Complement, ADC D Digital Output True.
ADC C Digital Output Complement, ADC C Digital Output True.
ADC B Digital Output Complement, ADC B Digital Output True.
ADC A Digital Output Complement, ADC A Digital Output True.
Serial Clock (SCLK)/Digital Test Pattern (DTP).
Serial Data Input/Output (SDIO)/Data Format Select (DFS).
Chip Select Bar.
Power-Down.
ADC A Analog Input True, ADC A Analog Input Complement.
ADC B Analog Input Complement, ADC B Analog Input True.
ADC C Analog Input True, ADC C Analog Input Complement.
Rev. A | Page 10 of 13
Data Sheet
Pin No.
52, 53
54
55
56
57
58
60, 61
63, 64
AD9257-EP
Mnemonic
VIN− D, VIN+ D
RBIAS
SENSE
VREF
VCM
SYNC
VIN+ E, VIN− E
VIN− F, VIN+ F
Description
ADC D Analog Input Complement, ADC D Analog Input True.
Analog Current Bias Setting. Connect to 10 kΩ (1% tolerance) resistor to ground.
Reference Mode Selection.
Voltage Reference Input/Output.
Analog Output Voltage at Midsupply. This pin sets the common mode of the analog inputs.
Digital Input. SYNC input to clock divider. 30 kΩ internal pull-down resistor.
ADC E Analog Input True, ADC E Analog Input Complement.
ADC F Analog Input Complement, ADC F Analog Input True.
Rev. A | Page 11 of 13
AD9257-EP
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
See the AD9257 data sheet for a full set of Typical Performance Characteristics plots.
105
SNR/SFDR (dBFS/dBc)
100
SFDR (dBc)
95
90
85
80
SNR (dBFS)
70
–55
–35
–15
5
25
45
65
TEMPERATURE (°C)
85
105
125
12740-015
75
Figure 7. SNR/SFDR vs. Temperature, fIN = 9.7 MHz, fSAMPLE = 65 MSPS
Rev. A | Page 12 of 13
Data Sheet
AD9257-EP
OUTLINE DIMENSIONS
9.10
9.00 SQ
8.90
0.30
0.25
0.18
PIN 1
INDICATOR
49
PIN 1
INDICATOR
64
1
48
0.50
BSC
EXPOSED
PAD
6.30
6.20 SQ
6.10
33
16
PKG-004559
0.80
0.75
0.70
0.45
0.40
0.35
32
17
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.203 REF
SEATING
PLANE
0.20 MIN
7.50 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WMMD
06-06-2014-A
TOP VIEW
Figure 8. 64-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
9 mm × 9 mm Body, Very Very Thin Quad
(CP-64-17)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD9257TCPZ-65-EP
1
Temperature Range
−55°C to +125°C
Package Description
64-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Z = RoHS Compliant Part.
©2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12740-0-6/15(A)
Rev. A | Page 13 of 13
Package Option
CP-64-17
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