CS51411EVB CS51411 Buck Regulator 5.0V-16V to 3.3V/1.0A Evaluation Board User's Manual http://onsemi.com EVAL BOARD USER’S MANUAL Introduction Features The CS51411 demonstration board is a 1.0 A/3.3 V buck regulator running at 260 kHz (CS51411) or 520 kHz (CS51413). The switching frequency can be synchronized to a higher frequency through feeding clock signals to the SYNC input. Driving SHDNB input low shuts down the converter output and minimizes the power consumption. The regulator has superior line and load regulation due to the use of V2t control. This control method also enhances the load transient response. V2 Control for Superior Line and Load Regulation Small Board Space Requiring Only 1.0 x 0.7 in.2 Total of 11 Components Including IC Shutdown Mode Disables the Output and Reduces the Operating Current Frequency Synchronization to Higher Frequency 1.5 A Peak Current Protection which Folds Back 30% During Overload Conditions Built-In Soft Start to Eliminate Any In-Rush Current High Energy Transfer Efficiency of 83% at 1.0 A Load Line Regulation Better Than 0.1% Load Regulation Better Than 0.4% Figure 1. CS51411/3 Demonstration Board Semiconductor Components Industries, LLC, 2012 January, 2012 − Rev. 1 1 Publication Order Number: EVBUM2043/D CS51411EVB Table 1. ABSOLUTE MAXIMUM RATINGS Pin Name Maximum Voltage Maximum Current VIN 16 V 2.0 A VO 16 V 2.0 A SHDNB 7.0 V 1.0 mA SYNC 7.0 V 1.0 mA Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 2. ELECTRICAL CHARACTERISTICS (TA = 25C, 5.0 V VIN 16 V, 0.1 A IOUT 1.0 A, unless otherwise specified) Characteristic Test Conditions Typ Units − 4.0 % Line Regulation IOUT = 1.0 A 0.1 % Load Regulation VIN = 5.0 V 0.3 % Minimum Load − 0.1 A Transient Response − 3.0 % Load Toggle between 0.1 A and 1.0 A 10.0 ms − 5.0 ms − 3.3 V CS51411 CS51413 290 to 470 575 to 900 kHz Minimum Sync Threshold Voltage − 1.0 V Minimum Shutdown Threshold Voltage − 0.3 V Maximum Shutdown Bias Current − 12.0 mA CS51411 CS51413 260 520 kHz ILOAD = 100 mA ILOAD = 1.0 A 77.5 83.0 % − 100 mA Output Voltage Voltage Accuracy Transient Response Time Startup Time Input Voltage Start Threshold Sync and Shutdown Sync Frequency General Switching Frequency Efficiency Shutdown Current http://onsemi.com 2 CS51411EVB D1 1N4148 J2 VIN 4−16 V C5 0.1 mF C2 100 mF 2 VIN J1 GND 5 C1 0.1 mF 1 BOOST VSW L1 15 mH 3 J3 SWNODE CS51411/3 SYNC SHDNB VC 8 VFB GND 7 6 J4 VOUT 3.3 V 4 C6 3300 pF D3 B230DKT_ND C4 0.1 mF C3 100 mF R1 205 W R2 127 W J8 GND J5 GND J7 SHDNB J6 SYNC Figure 2. Application Diagram Operation Guidelines approximately equal to VIN. Now the voltage of the Boost pin, which connects to C1, is equal to VIN + VO. Diode D1 is reverse biased. The Boost pin voltage provides adequate base current to the power transistor, which lowers VCE(SAT) and improves the energy transfer efficiency. 2. Soft Start: The soft–start is implemented on the VC pin. During the startup, the limited source current (25 mA) of the error amplifier charges the VC pin capacitor. The rising slope of the VC pin voltage clamps the duty cycle through the PWM comparator. The VC pin voltage eventually settles down to a voltage roughly equal to the reference voltage 1.27 V. Therefore, the startup time can be easily calculated. 3. Feedback Network: V2 control relies on the output ripple to provide pulse width modulation. When the output ripple is inadequate, pulse skipping or instability may be observed. Adding a capacitor C6 in parallel with R1 provides a low impedance pass for the output ripple. Therefore, the output ripple is not attenuated by the resistor divider. The use of this capacitor is optional. 1. Connect input voltage between J2 and J1 on the left side of the board. The maximum input voltage is limited by the voltage rating of the input capacitor. 2. Connect the load between J4 and J5. The regulator requires 100 mA as minimum load. Without this minimum load, the output may exceed the regulation voltage. 3. Connect shutdown signal between J7 and J8. When the voltage on this input is below 0.3 V, the regulator enters a sleep mode. Pull this input high or leave it open if not used. 4. The sync signal can be applied between J6 and J8. The amplitude of the sync pulses needs to be greater than 1.0 V. The duty cycle can vary from 10% to 90%. Leave it open if not used. Theory of Operation 1. Boost Strapping Circuit: The boost strapping circuit, made of C1 and D1, provides a voltage higher than the input voltage to drive the power transistor (inside IC) into saturation. The operation of the boost strapping circuit works as follows. When the power transistor turns off, diode D3 turns on and pulls the VSW node to ground. Diode D1 is forward biased, and the output voltage charges C1 to VO. When the power transistor turns on, the VSW node is pulled high and is Please see data sheet for more description on regulator operation and component selection (document number CS51411/D available via our website at http://www.onsemi.com). http://onsemi.com 3 CS51411EVB TYPICAL PERFORMANCE CHARACTERISTICS 3.290 3.289 Output Voltage 3.288 3.287 3.286 3.285 3.284 3.283 3.282 3.281 3.280 5 6 7 8 9 10 11 12 13 14 15 16 Input Voltage Figure 3. Line Regulation 3.300 Output Voltage 3.295 3.290 3.285 3.280 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.0 Output Current Figure 4. Load Regulation 88 87 86 Efficiency 85 84 83 82 81 80 79 78 77 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 Output Current Figure 5. Efficiency vs. Output Current http://onsemi.com 4 0.90 1.00 CS51411EVB Table 3. BILL OF MATERIALS Ref. Designator Vendor Part Number Type PC/Board C1, C4, C5 DIGIKEY C2, C3 AVX PCC1762CT−ND 0.1 mF Ceramic 3 TAJE107K016R 100 mF Tantalum 2 C6 D1 DIGIKEY PCC1778CT–ND 3300 pF Ceramic 1 DIGIKEY LL4148CT–ND Diode 1 D3 DIGIKEY B230DICT–ND 2.0 A Schottky 1 J1−J8 DIGIKEY V1055 Test Point 8 L1 COILTRONICS UP2.8B150 15 mH Inductor 1 R1 DIGIKEY P205CTRND 205 W Resistor 1 R2 DIGIKEY P127CTRND 127 W Resistor 1 U1 ON Semiconductor CS51411/3 Controller 1 DRAWINGS OF LAYERS Figure 6. Top Copper Figure 7. Bottom Copper Figure 8. Top Silk V2 is a trademark of Switch Power, Inc. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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