Download AD2S1210-KGD Data Sheet

FEATURES
FUNCTIONAL BLOCK DIAGRAM
Complete monolithic resolver-to-digital converter
3125 rps maximum tracking rate (10-bit resolution)
±2.5 arc minutes of accuracy
10-/12-/14-/16-bit resolution, set by user
Parallel and serial 10-bit to 16-bit data ports
Absolute position and velocity outputs
System fault detection
Programmable fault detection thresholds
Differential inputs
Incremental encoder emulation
Programmable sinusoidal oscillator on-board
Compatible with DSP and SPI interface standards
5.0 V supply with 2.3 V to 5 V logic interface
−55°C to +125°C temperature rating
REFERENCE
PINS
CRYSTAL
VOLTAGE
REFERENCE
INTERNAL
CLOCK
GENERATOR
SYNTHETIC
REFERENCE
AD2S1210-KGD
ADC
INPUTS
FROM
RESOLVER
TYPE II
TRACKING LOOP
POSITION
REGISTER
DC and ac servo motor controls
Encoder emulation
Electric power steering
Electric vehicles
Integrated starter generators/alternators
Automotive motion sensing and controls
VELOCITY
REGISTER
FAULT
DETECTION
OUTPUTS
CONFIGURATION
REGISTER
DATA I/O
MULTIPLEXER
DATA I/O
RESET
12412-001
DATA BUS OUTPUT
Figure 1.
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD2S1210-KGD-CHIPS is a complete 10-bit to 16-bit
resolution tracking resolver-to-digital (R/D) converter,
integrating an on-board programmable sinusoidal oscillator
that provides sine wave excitation for resolvers.
1.
The converter accepts 3.15 V p-p ± 27% input signals, in the range
of 2 kHz to 20 kHz on the sine and cosine inputs. A Type II
servo loop is employed to track the inputs and convert the input
sine and cosine information into a digital representation of the
input angle and velocity. The maximum tracking rate is 3125 rps.
2.
Additional application and technical information can be found
in the AD2S1210 data sheet.
3.
Known Good Die (KGD): these die are fully guaranteed to data
sheet specifications.
4.
5.
6.
Rev. 0
FAULT
DETECTION
ADC
ENCODER
EMULATION
OUTPUTS
APPLICATIONS
REFERENCE
OSCILLATOR
(DAC)
EXCITATION
OUTPUTS
ENCODER
EMULATION
Known Good Die
Variable Resolution, 10-Bit to 16-Bit R/D
Converter with Reference Oscillator
AD2S1210-KGD-CHIPS
Ratiometric tracking conversion. The Type II tracking loop
provides continuous output position data without
conversion delay. It also provides noise immunity and
tolerance of harmonic distortion on the reference and
input signals.
System fault detection. A fault detection circuit can sense
loss of resolver signals, out-of-range input signals, input
signal mismatch, or loss of position tracking. The fault
detection threshold levels can be individually programmed
by the user for optimization within a particular application.
Input signal range. The sine and cosine inputs can accept
differential input voltages of 3.15 V p-p ± 27%.
Programmable excitation frequency. Excitation frequency
is easily programmable to a number of standard frequencies
between 2 kHz and 20 kHz.
Triple format position data. Absolute 10-bit to 16-bit angular
position data is accessed via either a 16-bit parallel port or a
4-wire serial interface. Incremental encoder emulation is in
standard A-quad-B format with direction output available.
Digital velocity output. 10-bit to 16-bit signed digital velocity
accessed via either a 16-bit parallel port or a 4-wire serial
interface.
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD2S1210-KGD-CHIPS
Known Good Die
TABLE OF CONTENTS
Features .............................................................................................. 1
Timing Specifications ...................................................................5
Applications ....................................................................................... 1
Absolute Maximum Ratings ............................................................7
Functional Block Diagram .............................................................. 1
ESD Caution...................................................................................7
General Description ......................................................................... 1
Pin Configuration and Function Descriptions..............................8
Product Highlights ........................................................................... 1
Outline Dimensions ....................................................................... 12
Revision History ............................................................................... 2
Die Specifications and Assembly Recommendations ........... 12
Specifications..................................................................................... 3
Ordering Guide .......................................................................... 12
REVISION HISTORY
6/14—Revision 0: Initial Version
Rev. 0 | Page 2 of 12
Known Good Die
AD2S1210-KGD-CHIPS
SPECIFICATIONS
AVDD = DVDD = 5.0 V ± 5% and CLKIN = 8.192 MHz ± 25%. EXC, EXC frequency = 10 kHz to 20 kHz (10-bit), 6 kHz to 20 kHz (12-bit), 3 kHz
to 12 kHz (14-bit), and 2 kHz to 10 kHz (16-bit). TA = TMIN to TMAX, unless otherwise noted. Devices are guaranteed to the data sheet by wafer
probing at 25°C. Characterization at temperature performed in released package formats. Temperature range is as follows: −55°C to +125°C.
Table 1.
Parameter
SINE, COSINE INPUTS 1
Voltage Amplitude
Min
Typ
Max
Unit
Test Conditions/Comments
2.3
3.15
4.0
V p-p
Input Bias Current
Input Impedance
Phase Lock Range
8.25
485
−44
µA
kΩ
Degrees
arc sec/V
Sinusoidal waveforms, differential SIN to
SINLO, COS to COSLO
VIN = 4.0 V p-p, CLKIN = 8.192 MHz
VIN = 4.0 V p-p, CLKIN = 8.192 MHz
Sine/cosine vs. EXC output,
Control Register D3 = 0
10 Hz to 1 MHz, Control Register D4 = 0
arc min
Bits
No missing codes
Common-Mode Rejection
ANGULAR ACCURACY 2
Angular Accuracy
Resolution
Integral Nonlinearity (INL)
10-Bit
12-Bit
14-Bit
16-Bit
Differential Nonlinearity (DNL)
Repeatability
VELOCITY OUTPUT
Velocity Accuracy 3
10-Bit
12-Bit
14-Bit
16-Bit
Resolution 4
DYNAMNIC PERFORMANCE
Bandwidth
10-Bit
12-Bit
14-Bit
16-Bit
Tracking Rate
10-Bit
12-Bit
14-Bit
16-Bit
+44
±20
±2.5 + 1 LSB
10, 12, 14, 16
±7 + 1 LSB
±1
±2
±4
±16
±0.9
LSB
LSB
LSB
LSB
LSB
LSB
±2
±2
±4
±16
LSB
LSB
LSB
LSB
Bits
6600
5400
2800
2200
1500
1200
350
275
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
3125
2500
1250
1000
625
500
156.25
125
rps
±1
Zero acceleration
9, 11, 13, 15
2000
2900
900
1200
400
600
100
125
Rev. 0 | Page 3 of 12
rps
rps
rps
CLKIN = 8.192 MHz
CLKIN = 8.192 MHz
CLKIN = 8.192 MHz
CLKIN = 8.192 MHz
CLKIN = 10.24 MHz
CLKIN = 8.192 MHz
CLKIN = 10.24 MHz
CLKIN = 8.192 MHz
CLKIN = 10.24 MHz
CLKIN = 8.192 MHz
CLKIN = 10.24 MHz
CLKIN = 8.192 MHz
AD2S1210-KGD-CHIPS
Parameter
Acceleration Error
10-Bit
12-Bit
14-Bit
16-Bit
Settling Time 10° Step Input
10-Bit
12-Bit
14-Bit
16-Bit
Settling Time 179° Step Input
10-Bit
12-Bit
14-Bit
16-Bit
EXC, EXC OUTPUTS
Voltage
Center Voltage
Frequency
EXC/EXC DC Mismatch
EXC/EXC AC Mismatch
Total Harmonic Distortion (THD)
VOLTAGE REFERENCE
REFOUT
Drift
Power Supply Rejection Ratio (PSRR)
CLKIN, XTALOUT 5
VIL Voltage Input Low
VIH Voltage Input High
LOGIC INPUTS
VIL Voltage Input Low
VIH Voltage Input High
Known Good Die
Min
IOZH High Level Three-State Leakage
IOZL Low Level Three-State Leakage
POWER REQUIREMENTS
AVDD
DVDD
VDRIVE
Max
30
30
30
30
Unit
Test Conditions/Comments
arc min
arc min
arc min
arc min
At 50,000 rps2, CLKIN = 8.192 MHz
At 10,000 rps2, CLKIN = 8.192 MHz
At 2500 rps2, CLKIN = 8.192 MHz
At 125 rps2, CLKIN = 8.192 MHz
0.6
2.2
6.5
27.5
0.9
3.3
9.8
48
ms
ms
ms
ms
To settle to within ±2 LSB , CLKIN = 8.192 MHz
To settle to within ±2 LSB, CLKIN = 8.192 MHz
To settle to within ±2 LSB , CLKIN = 8.192 MHz
To settle to within ±2 LSB, CLKIN = 8.192 MHz
1.5
4.75
10.5
45
2.4
6.1
15.2
68
ms
ms
ms
ms
To settle to within ±2 LSB , CLKIN = 8.192 MHz
To settle to within ±2 LSB, CLKIN = 8.192 MHz
To settle to within ±2 LSB , CLKIN = 8.192 MHz
To settle to within ±2 LSB, CLKIN = 8.192 MHz
3.2
3.6
4.0
V p-p
Load ±100 µA, typical differential output
(EXC to EXC) = 7.2 V p-p
2.40
2
2.47
2.53
20
30
132
V
kHz
mV
mV
dB
−58
2.40
2.47
100
−60
2.53
V
ppm/°C
dB
0.8
V
V
0.8
0.7
V
V
V
V
µA
µA
2.0
2.0
1.7
IIL Low Level Input Current (Nonpull-Up)
IIL Low Level Input Current (Pull-Up)
IIH High Level Input Current
LOGIC OUTPUTS
VOL Voltage Output Low
VOH Voltage Output High
Typ
10
80
−10
±IOUT = 100 µA
VDRIVE = 2.7 V to 5.25 V
VDRIVE = 2.3 V to 2.7 V
VDRIVE = 2.7 V to 5.25 V
VDRIVE = 2.3 V to 2.7 V
RES0, RES1, RD, WR/FSYNC, A0, A1,
and RESET pins
µA
0.4
10
V
V
V
µA
µA
5.25
5.25
5.25
V
V
V
2.4
2.0
−10
4.75
4.75
2.3
First five harmonics
Rev. 0 | Page 4 of 12
VDRIVE = 2.3 V to 5.25 V
VDRIVE = 2.7 V to 5.25 V
VDRIVE = 2.3 V to 2.7 V
Known Good Die
Parameter
POWER SUPPLY
IAVDD
IDVDD
IOVDD
AD2S1210-KGD-CHIPS
Min
Typ
Max
Unit
12
35
2
mA
mA
mA
Test Conditions/Comments
The voltages, SIN, SINLO, COS, and COSLO, relative to AGND, must always be between 0.15 V and AVDD − 0.2 V.
All specifications within the angular accuracy parameter are tested at constant velocity, that is, zero acceleration.
The velocity accuracy specification includes velocity offset and dynamic ripple.
4
For example, when RES0 = 0 and RES1 = 1, the position output has a resolution of 12 bits. The velocity output has a resolution of 11 bits with the MSB indicating the
direction of rotation. In this example, with a CLKIN frequency of 8.192 MHz, the velocity LSB is 0.488 rps, that is, 1000 rps/(211).
5
The clock frequency of the AD2S1210-KGD-CHIPS can be supplied with a crystal, an oscillator, or directly from a DSP/microprocessor digital output. When using a single-ended
clock signal directly from the DSP/microprocessor, the XTALOUT pin must remain open circuit, and the logic levels outlined under the logic inputs parameter in Table 1 apply.
1
2
3
TIMING SPECIFICATIONS
AVDD = DVDD = 5.0 V ± 5%, TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
fCLKIN
Description
Frequency of clock input
tCK
Clock period ( = 1/fCLKIN)
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
A0 and A1 setup time before RD/CS low
Delay CS falling edge to WR/FSYNC rising edge
Address/data setup time during a write cycle
Address/data hold time during a write cycle
Delay WR/FSYNC rising edge to CS rising edge
Delay CS rising edge to CS falling edge
Delay between writing address and writing data
A0 and A1 hold time after WR/FSYNC rising edge
Delay between successive write cycles
Delay between rising edge of WR/FSYNC and falling edge of RD
Delay CS falling edge to RD falling edge
Enable delay RD low to data valid in configuration mode
VDRIVE = 4.5 V to 5.25 V
VDRIVE = 2.7 V to 3.6 V
VDRIVE = 2.3 V to 2.7 V
RD rising edge to CS rising edge
Disable delay RD high to data high-Z
Disable delay CS high to data high-Z
Delay between rising edge of RD and falling edge of WR/FSYNC
SAMPLE pulse width
Delay from SAMPLE before RD/CS low
Hold time RD before RD low
Enable delay RD/CS low to data valid
VDRIVE = 4.5 V to 5.25 V
VDRIVE = 2.7 V to 3.6 V
VDRIVE = 2.3 V to 2.7 V
RD pulse width
A0 and A1 set time to data valid when RD/CS low
VDRIVE = 4.5 V to 5.25 V
VDRIVE = 2.7 V to 3.6 V
VDRIVE = 2.3 V to 2.7 V
t13
t14A
t14B
t15
t16
t17
t18
t19
t20
t21
Rev. 0 | Page 5 of 12
Limit at TMIN, TMAX
6.144
10.24
98
163
2
22
3
2
2
10
2 × tCK + 20
2
6 × tCK + 20
2
2
Unit
MHz min
MHz max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
37
25
30
2
16
16
2
2 × tCK + 20
6 × tCK + 20
2
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
17
21
33
6
ns min
ns min
ns min
ns min
36
37
29
ns min
ns min
ns min
AD2S1210-KGD-CHIPS
Parameter
t22
t23
t24
t25
t26
t27
t28
t29
t30
t31
t32
t33
t34
fSCLK
1
Known Good Die
Description
Delay WR/FSYNC falling edge to SCLK rising edge
Delay WR/FSYNC falling edge to SDO release from high-Z
VDRIVE = 4.5 V to 5.25 V
VDRIVE = 2.7 V to 3.6 V
VDRIVE = 2.3 V to 2.7 V
Delay SCLK rising edge to DBx valid
VDRIVE = 4.5 V to 5.25 V
VDRIVE = 2.7 V to 3.6 V
VDRIVE = 2.3 V to 2.7 V
SCLK high time
SCLK low time
SDI setup time prior to SCLK falling edge
SDI hold time after SCLK falling edge
Delay WR/FSYNC rising edge to SDO high-Z
Delay from SAMPLE before WR/FSYNC falling edge
Delay CS falling edge to WR/FSYNC falling edge in normal mode
A0 and A1 setup time before WR/FSYNC falling edge
A0 and A1 hold time after WR/FSYNC falling edge 1
In normal mode, A0 = 0, A1 = 0/1
In configuration mode, A0 = 1, A1 = 1
Delay WR/FSYNC rising edge to WR/FSYNC falling edge
Frequency of SCLK input
VDRIVE = 4.5 V to 5.25 V
VDRIVE = 2.7 V to 3.6 V
VDRIVE = 2.3 V to 2.7 V
Limit at TMIN, TMAX
3
Unit
ns min
16
26
29
ns min
ns min
ns min
24
18
32
0.4 × tSCLK
0.4 × tSCLK
3
2
15
6 × tCK + 20 ns
2
2
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
24 × tSCLK + 5 ns
8 × tSCLK + 5 ns
10
ns min
ns min
ns min
20
25
15
MHz
MHz
MHz
A0 and A1 must remain constant for the duration of the serial readback. This may require 24 clock periods to read back the 8-bit fault information in addition to the
16 bits of position/velocity data. If the fault information is not required, A0/A1 may be released following 16 clock cycles.
Rev. 0 | Page 6 of 12
Known Good Die
AD2S1210-KGD-CHIPS
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
AVDD to AGND, DGND
DVDD to AGND, DGND
VDRIVE to AGND, DGND
AVDD to DVDD
AGND to DGND
Analog Input Voltage to AGND
Digital Input Voltage to DGND
Digital Output Voltage to DGND
Analog Output Voltage Swing
Input Current to Any Pin Except Supplies1
Operating Temperature Range (Ambient)
Storage Temperature Range
ESD
1
Rating
−0.3 V to +7.0 V
−0.3 V to +7.0 V
−0.3 V to AVDD
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to AVDD + 0.3 V
±10 mA
−55°C to +125°C
−65°C to +150°C
2 kV HBM
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Transient currents of up to 100 mA do not cause latch-up.
Rev. 0 | Page 7 of 12
AD2S1210-KGD-CHIPS
Known Good Die
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
50
49
48
47 46
45
44 43 42 41 40
39
1
2
38
37
36
3
4
35
34
5
6
7
33
32
8
9
31
30
10
11
12
13
14
27
15 16
17 18
19
20
21
22 23
24 25
26
12412-002
29
28
Figure 2. Pad Configuration
Table 4. Pad Function Descriptions
Pad
No.
1
X-Axis
(µm)
−1870
Y-Axis
(µm)
+1453
Mnemonic
RES1
Pad Type
Single
2
3
−1870
−1870
+1309
+948
CS
RD
Single
Single
4
−1870
+805
WR/FSYNC
Single
5
−1870
+550
DGND
Single
6
−1870
+410
DGND
Single
7
−1870
+191
DVDD
Single
8
−1870
−117
DVDD
Single
9
−1870
−351
CLKIN
Single
Description
Resolution Select 1. Logic input. RES1 in conjunction with RES0 allows the
programming of the resolution of the AD2S1210-KGD-CHIPS.
Chip Select. Active low logic input. When CS is held low, the device is enabled.
Edge-Triggered Logic Input. When the SOE pin is high, RD acts as a frame
synchronization signal and output enable for the parallel data outputs, DB15
to DB0. The output buffer is enabled when CS and RD are held low. When the
SOE pin is low, hold the RD pin high.
Edge-Triggered Logic Input. When the SOE pin is high, WR acts as an input
enable for the parallel data inputs, DB7 to DB0. When the SOE pin is low, the
FSYNC pin acts as a frame synchronization signal and enable for the serial
data bus.
Digital Ground. This pin is a ground reference point for the digital circuitry on
the AD2S1210-KGD-CHIPS. Refer all digital input signals to the DGND
voltage. Both DGND pins can be connected to the AGND plane of a system.
Ideally, the DGND and AGND voltages are at the same potential, and they
must not be more than 0.3 V apart, even on a transient basis.
Digital Ground. This pin is a ground reference point for the digital circuitry on
the AD2S1210-KGD-CHIPS. Refer all digital input signals to the DGND
voltage. Both DGND pins can be connected to the AGND plane of a system.
Ideally, the DGND and AGND voltages are at the same potential, and they
must not be more than 0.3 V apart, even on a transient basis.
Digital Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for all digital
circuitry on theAD2S1210-KGD-CHIPS. Ideally, the AVDD and DVDD voltages
are at the same potential, and they must not be more than 0.3 V apart, even
on a transient basis.
Digital Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for all digital
circuitry on the AD2S1210-KGD-CHIPS. Ideally, the AVDD and DVDD voltages
are at the same potential, and they must not be more than 0.3 V apart, even
on a transient basis.
Clock Input. A crystal or oscillator can be used at the CLKIN and XTALOUT
pins to supply the required clock frequency of the AD2S1210-KGD.
Alternatively, a single-ended clock can be applied to the CLKIN pin. The
input frequency of the AD2S1210-KGD-CHIPS is specified from 6.144 MHz to
10.24 MHz.
Rev. 0 | Page 8 of 12
Known Good Die
AD2S1210-KGD-CHIPS
Pad
No.
10
X-Axis
(µm)
−1870
Y-Axis
(µm)
−611
Mnemonic
XTALOUT
Pad Type
Single
11
−1870
−872
SOE
Single
12
−1870
−1016
SAMPLE
Single
13
−1870
−1376
DB15/SDO
Single
14
−1870
−1535
DB14/SDI
Single
15
−1466
−1820
DB13/SCLK
Single
16
17
18
19
20A
−1323
−962
−819
−458
−230
−1820
−1820
−1820
−1820
−1820
DB12
DB11
DB10
DB9
VDRIVE
Single
Single
Single
Single
Double
20B
−159
−1820
VDRIVE
Double
21A
+130
−1820
DGND
Double
21B
+201
−1820
DGND
Double
22
23
+519
+663
−1820
−1820
DB8
DB7
Single
Single
24
+1024
−1820
DB6
Single
25
+1167
−1820
DB5
Single
26
+1532
−1820
DB4
Single
27
+1870
−1441
DB3
Single
Description
Crystal Output. When using a crystal or oscillator to supply the clock
frequency to the AD2S1210-KGD-CHIPS , apply the crystal across the CLKIN
and XTALOUT pins. When using a single-ended clock source, consider the
XTALOUT pin a no connect pin.
Serial Output Enable. Logic input. This pin enables either the parallel or serial
interface. The serial interface is selected by holding the SOE pin low, and the
parallel interface is selected by holding the SOE pin high.
Sample Result. Logic input. Data is transferred from the position and velocity
integrators to the position and velocity registers, after a high to low transition on
the SAMPLE signal. The fault register is also updated after a high to low
transition on the SAMPLE signal.
Data Bit 15/Serial Data Output Bus. When the SOE pin is high, this pin acts as
DB15, a three-state data output pin controlled by CS and RD. When the SOE
pin is low, this pin acts as SDO, the serial data output bus controlled by CS
and WR/FSYNC. Data is clocked out on the rising edge of SCLK.
Data Bit 14/Serial Data Input Bus. When the SOE pin is high, this pin acts as
DB14, a three-state data output pin controlled by CS and RD. When the SOE
pin is low, this pin acts as SDI, the serial data input bus controlled by CS and
WR/FSYNC. Data is clocked in on the falling edge of SCLK.
Data Bit 13/Serial Clock. In parallel mode, this pin acts as DB13, a three-state
data output pin controlled by CS and RD. In serial mode, this pin acts as the
serial clock input.
Data Bit 12. Three-state data output pin controlled by CS and RD.
Data Bit 11. Three-state data output pin controlled by CS and RD.
Data Bit 10. Three-state data output pin controlled by CS and RD.
Data Bit 9. Three-state data output pin controlled by CS and RD.
Logic Power Supply Input. The voltage supplied at this pin determines at what
voltage the interface operates. Decouple this pin to DGND. The voltage
range on this pin is 2.3 V to 5.25 V and may be different to the voltage range
at AVDD and DVDD but must never exceed either by more than 0.3 V.
Logic Power Supply Input. The voltage supplied at this pin determines at
what voltage the interface operates. Decouple this pin to DGND. The voltage
range on this pin is 2.3 V to 5.25 V and may be different to the voltage range
at AVDD and DVDD but must never exceed either by more than 0.3 V.
Digital Ground. This pin is a ground reference point for the digital circuitry on
the AD2S1210-KGD-CHIPS. Refer all digital input signals to this DGND
voltage. Both DGND pins can be connected to the AGND plane of a system.
Ideally, the DGND and AGND voltages are at the same potential, and they
must not be more than 0.3 V apart, even on a transient basis.
Digital Ground. This pin is a ground reference point for the digital circuitry on
the AD2S1210-KGD-CHIPS. Refer all digital input signals to this DGND
voltage. Both DGND pins can be connected to the AGND plane of a system.
Ideally, the DGND and AGND voltages are at the same potential, and they
must not be more than 0.3 V apart, even on a transient basis.
Data Bit 8. Three-state data output pin controlled by CS and RD.
Data Bit 7. Three-state data input/output pin controlled by CS, RD, and
WR/FSYNC.
Data Bit 6. Three-state data input/output pin controlled by CS, RD, and
WR/FSYNC.
Data Bit 5. Three-state data input/output pin controlled by CS, RD, and
WR/FSYNC.
Data Bit 4. Three-state data input/output pin controlled by CS, RD, and
WR/FSYNC.
Data Bit 3. Three-state data input/output pin controlled by CS, RD, and
WR/FSYNC.
Rev. 0 | Page 9 of 12
AD2S1210-KGD-CHIPS
Known Good Die
Pad
No.
28
X-Axis
(µm)
+1870
Y-Axis
(µm)
−1080
Mnemonic
DB2
Pad Type
Single
29
+1870
−937
DB1
Single
30
+1870
−576
DB0
Single
31
+1870
−433
A
Single
32
+1870
−72
B
Single
33
+1870
+72
NM
Single
34
+1870
+432
DIR
Single
35
+1870
+576
RESET
Single
36
+1870
+937
LOT
Single
37
+1870
+1080
DOS
Single
38
+1870
+1441
A1
Single
39
+1580
+1820
A0
Single
40
+1031
+1820
EXC
Single
41
+859
+1820
EXC
Single
42A
+678
+1820
AGND
Double
42B
+607
+1820
AGND
Double
43
+440
+1820
SIN
Single
44
+262
+1820
SINLO
Single
Description
Data Bit 2. Three-state data input/output pin controlled by CS, RD, and
WR/FSYNC.
Data Bit 1. Three-state data input/output pin controlled by CS, RD, and
WR/FSYNC.
Data Bit 0. Three-state data input/output pin controlled by CS, RD, and
WR/FSYNC.
Incremental Encoder Emulation Output A. Logic output. This output is free
running and valid if the resolver format input signals applied to the
converter are valid.
Incremental Encoder Emulation Output B. Logic output. This output is free
running and valid if the resolver format input signals applied to the
converter are valid.
North Marker Incremental Encoder Emulation Output. Logic output. This output
is free running and valid if the resolver format input signals applied to the
converter are valid.
Direction. Logic Output. This output is used in conjunction with the incremental
encoder emulation outputs. The DIR output indicates the direction of the
input rotation and is high for increasing angular rotation.
Reset. Logic input. The AD2S1210-KGD-CHIPS requires an external reset
signal to hold the RESET input low until VDD is within the specified operating
range of 4.75 V to 5.25 V.
Loss of Tracking. Logic output. LOT is indicated by a logic low on the LOT pin
and is not latched.
Degradation of Signal. Logic output. Degradation of signal (DOS) is detected
when either resolver input (sine or cosine) exceeds the specified DOS sine/
cosine threshold, or when an amplitude mismatch occurs between the sine
and cosine input voltages. DOS is indicated by a logic low on the DOS pin.
Mode Select 1. Logic input. A1 in conjunction with A0 allows the selection of
the mode of the AD2S1210-KGD-CHIPS.
Mode Select 0. Logic input. A0 in conjunction with A1 allows the selection of
the mode of the AD2S1210-KGD-CHIPS.
Excitation Frequency. Analog output. An on-board oscillator provides the
sinusoidal excitation signal (EXC) and its complement signal (EXC) to the
resolver. The frequency of this reference signal is programmable via the
excitation frequency register.
Excitation Frequency Complement. Analog output. An on-board oscillator
provides the sinusoidal excitation signal (EXC) and its complement signal
(EXC) to the resolver. The frequency of this reference signal is programmable
via the excitation frequency register.
Analog Ground. This pin is the ground reference point for the analog
circuitry on the AD2S1210-KGD-CHIPS. Refer all analog input signals and any
external reference signal to this AGND voltage. Connect the AGND pin to the
AGND plane of a system. Ideally, the AGND and DGND voltages are at the same
potential and must not be more than 0.3 V apart, even on a transient basis.
Analog Ground. This pin is the ground reference point for the analog
circuitry on the AD2S1210-KGD-CHIPS. Refer all analog input signals and any
external reference signal to this AGND voltage. Connect the AGND pin to the
AGND plane of a system. Ideally, the AGND and DGND voltages are at the same
potential and must not be more than 0.3 V apart, even on a transient basis.
Positive Analog Input of Differential SIN/SINLO Pair. The input range is
2.3 V p-p to 4.0 V p-p.
Negative Analog Input of Differential SIN/SINLO Pair. The input range is
2.3 V p-p to 4.0 V p-p.
Rev. 0 | Page 10 of 12
Known Good Die
AD2S1210-KGD-CHIPS
Pad
No.
45A
X-Axis
(µm)
+12
Y-Axis
(µm)
+1820
Mnemonic
AVDD
Pad Type
Double
45B
−59
+1820
AVDD
Double
46
−411
+1820
COSLO
Single
47
−586
+1820
COS
Single
48
−876
+1820
REFBYP
Single
49
50
−1112
−1590
+1820
+1820
REFOUT
RES0
Single
Single
Description
Analog Supply Voltage, 4.75 V to 5.25 V. This pin is the supply voltage for all
analog circuitry on the AD2S1210-KGD-CHIPS. Ideally, the AVDD and DVDD
voltages ideally are at the same potential and must not be more than 0.3 V
apart, even on a transient basis.
Analog Supply Voltage, 4.75 V to 5.25 V. This pin is the supply voltage for all
analog circuitry on the AD2S1210-KGD-CHIPS. Ideally, the AVDD and DVDD
voltages ideally are at the same potential and must not be more than 0.3 V
apart, even on a transient basis.
Negative Analog Input of Differential COS/COSLO Pair. The input range is
2.3 V p-p to 4.0 V p-p.
Positive Analog Input of Differential COS/COSLO Pair. The input range is
2.3 V p-p to 4.0 V p-p.
Reference Bypass. Connect reference decoupling capacitors at this pin.
Typical recommended values are 10 µF and 0.01 µF.
Voltage Reference Output.
Resolution Select 0. Logic input. RES0 in conjunction with RES1 allows the
programming of the resolution of the AD2S1210-KGD-CHIPS.
Rev. 0 | Page 11 of 12
AD2S1210-KGD-CHIPS
Known Good Die
OUTLINE DIMENSIONS
0.38
4.00
50
49
48
45
47 46
39
44 43 42 41 40
1
2
38
37
36
3
4
35
34
5
6
3.90
7
33
32
8
9
31
30
10
11
12
29
28
13
14
27
17 18
19
20
21
22 23
24 25
26
TOP VIEW
SIDE VIEW
(CIRCUIT SIDE)
0.07 × 0.07
06-05-2014- A
15 16
Figure 3. 50-Pad Bare Die [CHIP]
(C-50-1)
Dimensions shown in millimeters
DIE SPECIFICATIONS AND ASSEMBLY RECOMMENDATIONS
Table 5. Die Specifications
Parameter
Chip Size
Scribe Line Width
Die Size
Thickness
Backside
Passivation
Bond Pads (Minimum)
Bond Pad Composition
ESD
Value
3920 (x) × 3820 (y)
80 (x) × 80 (y)
4000 (x) × 3900 (y)
380 ±10
Silicon
Nitride
70 × 70
98.5% Al, 1% Si, 0.5% Cu
2
Unit
µm
µm
µm
µm
Not applicable
Not applicable
µm
%
kV
Table 6. Assembly Recommendations
Assembly Component
Die Attach
Bonding Method
Bonding Sequence
Recommendation
No special recommendations
Gold ball or aluminum wedge
Pad 1 first
ORDERING GUIDE
Model
AD2S1210-KGD-CHIPS
Temperature Range
−55°C to +125°C
Package Description
50-Pad Bare Die [CHIP], Waffle Pack
©2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12412-0-6/14(0)
Rev. 0 | Page 12 of 12
Package Option
C-50-1
Similar pages