8 7 6 5 4 3 2 1 REVISIONS ZONE SYM DESCRIPTION DATE Assy 20361083-Revision 6 See Page 16 VSUB and Electronic Shutter D Imager Socket KAI-01050 KAI-01150 KAI-02050 KAI-02150 KAI-04050 KAI-08050 CCDinB CCDinA CCDinA CCDinC CCDinC CCDinD CCDinD AD9928 AFE AD9928 AFE HCLK DRIVERS A&B Ra H2SLa H1Sa H1Ba H2Sa H2Ba H1Sb H1Bb_SD H2Sb H2Bb_SD H2SLb Rb C Ra H2SLa H1Sa H1Ba H2Sa H2Ba H1Sb H1Bb_SD H2Sb H2Bb_SD H2SLb Rb RGBa_AFE H2SLa_AFE H1ab_AFE H2ab_AFE H1Bb_SD_AFE H2Bb_SD_AFE H2SLb_AFE RGBb_AFE April 2016 D INTERCONNECT Analog Front End CCDinB APPROVAL RGBa_AFE H2SLa_AFE H1ab_AFE H2ab_AFE H1Bb_SD_AFE H2Bb_SD_AFE H2SLb_AFE RGBb_AFE TCLKP_AB TCLKP_AB TCLKN_AB TCLKN_AB DOUT0P_A_AB DOUT0P_A_AB DOUT0N_A_AB DOUT0N_A_AB DOUT1P_A_AB DOUT1P_A_AB DOUT1N_A_AB DOUT1N_A_AB DOUT0P_B_AB DOUT0P_B_AB DOUT0N_B_AB DOUT0N_B_AB DOUT1N_B_AB DOUT1N_B_AB DOUT1P_B_AB DOUT1P_B_AB TCLKP_CD TCLKP_CD TCLKN_CD TCLKN_CD DOUT0P_A_CD DOUT0P_A_CD DOUT0N_A_CD DOUT0N_A_CD DOUT1P_A_CD DOUT1P_A_CD DOUT1N_A_CD DOUT1N_A_CD DOUT0P_B_CD DOUT0P_B_CD DOUT0N_B_CD DOUT0N_B_CD DOUT1P_B_CD DOUT1P_B_CD DOUT1N_B_CD DOUT1N_B_CD TV57 HD_AB C HD_AB VD_AB VD_AB TV58 HCLK DRIVERS C&D Rc H2SLc H1Sc H1Bc H2Sc H2Bc H1Sd H1Bd_SD H2Sd H2Bd_SD H2SLd Rd Rc H2SLc H1Sc H1Bc H2Sc H2Bc H1Sd H1Bd_SD H2Sd H2Bd_SD H2SLd Rd RGBc_AFE H2SLc_AFE H1cd_AFE H2cd_AFE H1Bd_SD_AFE H2Bd_SD_AFE H2SLd_AFE RGBd_AFE GPO1_STROBE_AB RGBc_AFE H2SLc_AFE H1cd_AFE H2cd_AFE H1Bd_SD_AFE H2Bd_SD_AFE H2SLd_AFE RGBd_AFE SYNC_AB SYNC_AB RSTB_AB RSTB_AB SYNC_CD SYNC_CD RSTB_CD RSTB_CD GPO1_STROBE_AB SUBCK SUBCK TV49 GPO3_SCKA_AB GPO4_XSUBCK_SHPA_AB VCLK DRIVERS TOP V1T_3rd_AFE V1T_AFE GPO5_SCKB_AB GPO6_XV21_SHPB_DVAL_AB V1T V2T V2T V2T_AFE V2T_AFE GPO2_CD V3T V3T V3T_AFE V3T_AFE GPO3_CD V4T V4T V4T_AFE V4T_AFE GPO4_CD V1T_AFE GPO1_CD GPO5_CD GPO6_CD GPO7_CD VCLK DRIVERS BOTTOM B V1B V1B V1B_AFE V2B V2B V2B_AFE V3B V3B V4B V4B TV51 TV50 TV48 V1T_3rd_AFE V1T V1B_3rd_AFE GPO6_XV21_SHPB_DVAL_AB TV6 TV8 TV4 TV1 TV3 TV7 TV5 SCLK V1B_3rd_AFE SCLK SDATA V1B_AFE V2B_AFE AFECS_AB V3B_AFE V3B_AFE AFECS_CD AFECS_CD V4B_AFE V4B_AFE OSC_EN OSC_EN DEV_ID DEV_ID Front End POWER B SDATA AFECS_AB VAB_ADJ VAB_ADJ VAB_EN VAB_EN ESD_EN ESD_EN VCLK_EN VCLK_EN HCLK_EN HCLK_EN V15_EN V15_EN 20361081-Revision 3 Bare Board 20361083-Revision 6 Completed Assy A UNLESS OTHERWISE SPECIFIED MATERIAL A DIMENSIONS APPLY AFTER FINISH WHERE TOTAL TOLERANCE OS .001 DIM. ARE IN Lens Mounting Holes N3 N4 N6 N5 + - FM1 FM2 Pic-n-Place Fids Top FM3 3 PL DEC TOL + - FM4 FM5 Pic-n-Place Fids Bot FM6 SURF ROUGHNESS ENGR EDGES ENGR INSIDE RADII ECN NO. NEXT ASSY USED ON APPLICATION 8 THREADS. IN ALL OTHER PLACES 2 PL DEC TOL ANGULAR TOL 7 6 5 NEXT ASSY FINAL ASSY QUANITY REQD 4 ON Semiconductor INCHES OR LESS AND ON ALL + - DIMENSIONS APPLY BEFORE FINISH. NAME DR FINISH Top Level Drawing Gen2 Evaluation System 68 Pin PGA Imager Board QA CHK Jim DiBella SIZE D DEVIATIONS FROM INTENDED SHAPE (FLATNESS,ROUNDNESS,SQUARENESS ETC.) MUST BE WITHIN STATED DIMENSIONAL TOLERANCES. 3 REL DATE 4/8/2016 2 SCALE DWG NO. 20361081 / 20361083 PROGRAM CADSTAR SHEET 1 1 of 17 __ 8 7 6 5 4 3 2 1 REVISIONS MAIN SUPPLIES ZONE DESCRIPTION DATE APPROVAL +16V +12V J2 PJ-002A-SMT LT3479_16V LTM8022_6V V12 V16 U32 LT1761ES5-SD +16V +6V V6 1 3 1 VOUT 3 V15_EN ADJ GND 4 R58 200K 1% 2 1 V12 1 C128 10UF 25V 2 V12NEG 2 -12V D 1 4 SHDN\ LT3479_N12V CCD VDD +15V Amplifier LDO 40mA +15VA 5 VIN 2 D SYM C127 1uF 25V 10% VDD_ADJa 1 2 1 2 1 C106 10UF 25V C101 .1uF 25V 2 R59 17.4K 1% 2 V Clock Rails +3.3VD +3.3VA +16V Always On JMP1 1 OPTION to run 3.3 supplies off FPGA board or have local regulation for stand alone operating 2 JMP2 +6V VIN VOUT VIN VOUT 1 6 R12 200K 1% 3 SHDN ADJ 1 C168 .1uF 25V 2 2 1 C177 .01uF 2 SHDN\ 1 Sense C178 1uF 25V 10% GNDNC NC NC C166 1uF 25V 10% C42 4.7UF 25V VOUT 5 1 GND 1 1 VIN 4 3 6 2 7 2 2 4 5 1 C54 2.2uF 16V 2 20% 2 2 1 Main 3.3V Supply 8 1 TV23 1 2 2 VCLK_EN +16V 1 7 U39 LT1521CMS8-3.3 Sequenced +Vhigh V3rd level=+12 8 1 C U7 LT1965EMS8E 9 -VESD TV34 C55 .01uF TV9 VAB +15VA R11 C TV29 2 +6V VRD TV56 23.2K 1% TV55 3 TV28 TV24 4 TV22 TV25 2 TV26 TV31 -VH -VOG TV30 -VRESET +Vhigh 1 1 2 2 U19 LT1964ES5-SD C85 .1uF 25V 2 1 2 C84 1uF 25V 10% 1 1 R38 200K 1% 4 GND ADJ 2 IN 3 ESD_EN 5 SHDN C23 .1uF 25V 2 C90 .01uF 1 2 C24 1 1 4.7UF 25V 3 GND VIN V-OUT VIN SENSE 8 1 TV10 TV11 +3.3VA -Vlow 2 TV69 4 2 ILIM2 7 1 ILIM4 6 -9V SHDN/ ADJ_VN -12V -12V R14 162K 1% 5 2 OUT 5 U8 LT1175CS8 R34 31.6Kohm 1% -12V ESD actual with 31.6K and 200K =8.9475 1 2 -9 R13 200K 1% -VESD 2 1 C59 2.2uF 16V 20% 2 C60 .01uF 1 -Vlow B B U25 LTM8022EV#PFB +12V 2 H1 G1 C103 .1uF 25V 2 2 C102 2.2uF 16V 20% H2 G3 H3 G2 C3 B3 A3 E1 D1 AUX E2 D2 G5 SHARE HCLK_EN G7 HCLK_EN_SS 2 1 BIAS E3 D3 H6 RT G6 PGOOD E4 D4 ADJ SYNC R55 15.0K 1% F5 Vout RUN/SS F7 C99 .01uF 1 1 1 C4 B4 A4 Vin H5 C91 10UF 16V C2 B2 A2 2 H7 E5 D5 C5 B5 A5 R53 309K 1% F6 E6 D6 C6 B6 A6 1 E7 D7 C7 B7 A7 1 U24 LT1964ES5-SD K CR26 1 MBRM120E 1 C1 B1 A1 R42 27K 1% .1uF 25V ADJ 2 IN GND 5 SHDN C89 1uF 25V 10% 1 2 OUT Reset: Low level -2.015 R43 93.1K 2 R52 200K 1% 4 GND 3 C92 2 1 A 1 2 1 -VH -VRESET 2 2 HClock -5V -VH 20361081-Revision 3 Bare Board 20361083-Revision 6 Completed Assy A UNLESS OTHERWISE SPECIFIED MATERIAL A DIMENSIONS APPLY AFTER FINISH WHERE TOTAL TOLERANCE OS .001 DIM. ARE IN 2 PL DEC TOL + - 3 PL DEC TOL + - ANGULAR TOL NEXT ASSY USED ON APPLICATION 8 7 6 5 NEXT ASSY FINAL ASSY QUANITY REQD 4 ON Semiconductor INCHES OR LESS AND ON ALL + - THREADS. IN ALL OTHER PLACES DIMENSIONS APPLY BEFORE FINISH. NAME DR FINISH Power page 1 Gen2 Evaluation System 68 Pin PGA Imager Board QA CHK SURF ROUGHNESS ENGR EDGES ENGR INSIDE RADII ECN NO. Jim DiBella SIZE D DEVIATIONS FROM INTENDED SHAPE (FLATNESS,ROUNDNESS,SQUARENESS ETC.) MUST BE WITHIN STATED DIMENSIONAL TOLERANCES. 3 REL DATE 4/8/2016 2 SCALE DWG NO. 20361081 / 20361083 PROGRAM CADSTAR SHEET 1 2 of 17 __ 8 7 6 5 4 3 2 1 REVISIONS ZONE SYM DESCRIPTION DATE APPROVAL +12VP D V12 1 V12 +16V CR7 MBRM120E L3 10uH 2 BoostSW1 A D +16.2V K V16 1 2 BoostL 1 1 C135 10UF 16V C134 .01uF 2 2 5 4 3 Vin Vs 7 2 L C114 4.7UF_25V SW SW 2 10 LT3479 U34 SHDN 1 1 16V_FB FBN 8 1 Vref 12 R66 of 200K and R67 of 16.5K sets up 16.2V R66 200K 1% 9 SS R67 16.5K 1% FBP 1 2 C115 .01uF Rt 6 2 GND 13 GND PwrPad 14 Vc 15 11 1 C C 1 R75 15.0K 1% 2 R65 10K 1% 2 1 1.3MHz operating freq C113 2200PF 2 +12V U40 LTM8022EV#PFB H1 G1 1 B C1 B1 A1 H2 G3 E1 D1 F7 G5 BIAS E3 D3 G6 PGOOD E4 D4 ADJ SYNC H7 E5 D5 C5 B5 A5 .1uF 25V 1 F6 E6 D6 C6 B6 A6 2 2 H6 RT 1 C167 4.7UF_25V F5 AUX E2 D2 G7 Power for local 3.3 LDO if needed Power for Mechanical Shutter if needed 1 Vout SHARE 1 C146 C4 B4 A4 RUN/SS 2 B C3 B3 A3 Vin H5 V6 C2 B2 A2 H3 G2 R88 15.0K 1% +6V R85 24.9K 1% E7 D7 C7 B7 A7 R86 75.0K 1% GND 2 2 20361081-Revision 3 Bare Board 20361083-Revision 6 Completed Assy A UNLESS OTHERWISE SPECIFIED MATERIAL A DIMENSIONS APPLY AFTER FINISH WHERE TOTAL TOLERANCE OS .001 DIM. ARE IN 2 PL DEC TOL + - 3 PL DEC TOL + - ANGULAR TOL NEXT ASSY USED ON APPLICATION 8 7 6 5 NEXT ASSY FINAL ASSY QUANITY REQD 4 ON Semiconductor INCHES OR LESS AND ON ALL + - THREADS. IN ALL OTHER PLACES DIMENSIONS APPLY BEFORE FINISH. NAME DR FINISH Power page 2 LT3471 Gen2 Evaluation System 68 Pin PGA Imager Board QA CHK SURF ROUGHNESS ENGR EDGES ENGR INSIDE RADII ECN NO. Jim DiBella SIZE D DEVIATIONS FROM INTENDED SHAPE (FLATNESS,ROUNDNESS,SQUARENESS ETC.) MUST BE WITHIN STATED DIMENSIONAL TOLERANCES. 3 REL DATE 4/8/2016 2 SCALE DWG NO. 20361081 / 20361083 PROGRAM CADSTAR SHEET 1 3 of 17 __ 8 7 6 5 4 3 2 1 REVISIONS ZONE SYM DESCRIPTION DATE APPROVAL D D K C C105 1uF 25V 10% L2 10uH 1 V12 2 CR24 MBRM120E A C104 10UF 25V L1 10uH 1 V12N_SW 1 2 2 C C93 .1uF 25V 1 1 2 V12NEG 2 -12V 1 2 C96 2.2uF 16V 20% 5 4 3 Vin Vs 2 L 1 1 2 A C83 100PF SW SW 1 7 K R46 10K 1% 10 LT3479 U26 SHDN FBN R44 95.3K 1% CR25 MBRM120E 2 8 Vref 12 2 2 9 SS FBP 1 C95 .1uF 25V 1 Vout=-1.235(R300/R400) Rt 6 GND 13 GND PwrPad 14 Vc 15 11 1 1 R45 10K 1% R47 15.0K 1% 2 1 C94 2200PF 2 B B 2 20361081-Revision 3 Bare Board 20361083-Revision 6 Completed Assy A UNLESS OTHERWISE SPECIFIED MATERIAL A DIMENSIONS APPLY AFTER FINISH WHERE TOTAL TOLERANCE OS .001 DIM. ARE IN 2 PL DEC TOL + - 3 PL DEC TOL + - ANGULAR TOL NEXT ASSY USED ON APPLICATION 8 7 6 5 NEXT ASSY FINAL ASSY QUANITY REQD 4 ON Semiconductor INCHES OR LESS AND ON ALL + - THREADS. IN ALL OTHER PLACES DIMENSIONS APPLY BEFORE FINISH. NAME DR FINISH Power page 3 LT3479 Gen2 Evaluation System 68 Pin PGA Imager Board QA CHK SURF ROUGHNESS ENGR EDGES ENGR INSIDE RADII ECN NO. Jim DiBella SIZE D DEVIATIONS FROM INTENDED SHAPE (FLATNESS,ROUNDNESS,SQUARENESS ETC.) MUST BE WITHIN STATED DIMENSIONAL TOLERANCES. 3 REL DATE 4/8/2016 2 SCALE DWG NO. 20361081 / 20361083 PROGRAM CADSTAR SHEET 1 4 of 17 __ 8 7 6 5 4 3 2 REVISIONS B-B Connector Spacing 4" B-B Mounting posts per Altera HSMC Spec N2 ZONE SYM DESCRIPTION DATE APPROVAL N1 2.8" D 1 N7 4" N8 J4-A J4-B ASP-122952-01 2 XCVR_RXp7 4 6 8 10 12 14 TCLKN_AB DOUT1P_B_AB DOUT1N_B_AB DOUT0P_B_AB DOUT0N_B_AB 22 24 XCVR_RXn6 XCVR_TXn6 XCVR_RXp5 XCVR_TXp5 XCVR_RXn5 XCVR_TXn5 XCVR_RXp4 XCVR_TXp4 XCVR_RXn4 XCVR_TXn4 XCVR_RXp3 XCVR_TXp3 XCVR_RXn3 XCVR_TXn3 XCVR_RXp2 XCVR_TXp2 XCVR_RXn2 26 28 30 32 34 XCVR_TXn2 XCVR_RXp1 XCVR_TXp1 XCVR_RXn1 XCVR_TXn1 XCVR_RXp0 XCVR_TXp0 XCVR_RXn0 XCVR_TXn0 SCL 36 38 40 SDA JTAG_TMS JTAG_TCK JTAG_TDI JTAG_TDO CLKIN0 NC C CLKOUT0 1 42 HD_AB 3 44 VD_AB 5 46 7 48 RSTB_AB 9 SYNC_AB 11 13 15 50 AFECS_AB 52 54 TV60 56 17 58 19 60 SCLK 21 23 SDATA 25 27 29 DAC_CS DAC_CLR 31 33 35 37 39 ADC_CS TV61 TV62 62 64 66 TV63 TV64 68 70 72 TV65 TV66 TV67 TV68 74 76 CS5 78 CS6 80 82 84 86 174173164163162161 88 90 92 94 96 98 Signal Signal Signal Signal 12V 3.3V Signal Signal Signal Signal 12V 3.3V Signal Signal Signal Signal 12V 3.3V Signal Signal Signal Signal 12V 3.3V Signal Signal Signal Signal 12V 3.3V Signal Signal Signal Signal 12V 3.3V Signal Signal Signal Signal 12V 3.3V Signal Signal Signal Signal 12V 3.3V Signal Signal Signal Signal 12V 3.3V Signal* Signal* Signal* Signal* 100 3.3V 12V D +3.3VA J4-C ASP-122952-01 GND TCLKP_AB XCVR_TXp6 GND DOUT0N_A_AB 18 20 XCVR_RXp6 GND DOUT0P_A_AB 16 XCVR_TXn7 GND DOUT1N_A_AB XCVR_RXn7 NC DOUT1P_A_AB XCVR_TXp7 +12V +3.3VA +12V ASP-122952-01 41 GPO6_XV21_SHPB_DVAL_AB 102 43 104 45 106 47 110 SYNC_CD 51 53 112 TV2 114 AFECS_CD 55 116 57 118 59 120 61 122 63 124 65 126 67 128 69 130 71 132 73 134 75 136 77 138 79 140 81 142 83 144 85 146 87 148 89 150 91 152 93 154 95 156 97 158 99 160 Signal Signal Signal 12V 108 RSTB_CD 49 Signal 3.3V Signal Signal Signal Signal 12V 3.3V Signal Signal Signal Signal 12V 3.3V Signal Signal Signal Signal 12V 3.3V Signal Signal Signal Signal 12V 3.3V Signal Signal Signal Signal 12V 3.3V Signal Signal Signal Signal 12V 3.3V Signal Signal Signal Signal 12V 3.3V Signal Signal Signal Signal 12V 3.3V Signal* Signal* Signal* Signal* 3.3V PSNTn 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 +3.3VD 135 137 +3.3VD 139 1 141 143 145 U38 147 149 6 2 151 2 V15_EN TV32 ESD_EN TV33 TV27 HCLK_EN VCLK_EN TV52 OSC_EN TV54 VAB_EN TV47 VAB_ADJ TV45 TV53DEV_ID_EN VoutA 153 8 155 7 DAC_CS 157 SCLK VoutB CS/LD VoutC CLR VoutD DIN VoutE Dout VoutF 4 11 DAC_CLR 159 3 5 9 12 13 14 VoutG 15 VoutH 168167166165 C Vcc GND GND GND GND GND GND GND C164 .1uF 25V Vref 10 GND 2 16 LTC1665CGN 1 C165 10UF 16V 172171170169 GND 1 1 +3.3VD R84 10K 1% U35 ADC081S021 1 2 Vdd 4 SCLK 5 DOUT0N_B_CD B DOUT1P_B_CD DOUT1N_B_CD TCLKP_CD TCLKN_CD 15 17 19 21 23 25 DOUT0P_A_CD DOUT0N_A_CD DOUT1P_A_CD DOUT1N_A_CD 27 29 31 33 35 37 39 XCVR_TXp7 XCVR_RXp7 XCVR_TXn7 XCVR_RXn7 XCVR_TXp6 XCVR_RXp6 XCVR_TXn6 XCVR_RXn6 XCVR_TXp5 XCVR_RXp5 XCVR_TXn5 XCVR_RXn5 XCVR_TXp4 XCVR_RXp4 XCVR_TXn4 XCVR_RXn4 XCVR_TXp3 XCVR_RXp3 XCVR_TXn3 XCVR_RXn3 XCVR_TXp2 XCVR_RXp2 XCVR_TXn2 XCVR_RXn2 XCVR_TXp1 XCVR_TXn1 XCVR_TXp0 XCVR_TXn0 XCVR_RXp1 XCVR_RXn1 XCVR_RXp0 XCVR_RXn0 SDA SCL JTAG_TCK JTAG_TMS JTAG_TDO JTAG_TDI CLKOUT0 CLKIN0 2 41 4 43 6 45 8 47 10 49 12 51 14 53 16 55 18 57 20 59 22 61 24 63 26 65 28 67 30 69 32 71 34 73 36 75 38 77 40 79 83 NC NC GND GND GND GND 81 85 161 162163164173174 87 89 91 93 95 97 Signal Signal Signal 3.3V 12V Signal Signal Signal Signal 3.3V 12V Signal Signal Signal Signal 3.3V 12V Signal Signal Signal Signal 3.3V 12V Signal Signal Signal Signal 3.3V 12V Signal Signal Signal Signal 3.3V 12V Signal Signal Signal Signal 3.3V 12V Signal Signal Signal Signal 3.3V 12V Signal Signal Signal Signal 3.3V 12V Signal* Signal* Signal* Signal* 3.3V GND 99 Signal 42 101 44 103 46 105 48 107 50 109 52 54 113 56 115 58 117 60 119 62 121 64 123 66 125 68 127 70 129 72 133 76 135 78 137 80 139 82 143 86 145 88 147 90 149 92 153 96 155 98 157 100 159 Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal Signal 3.3V Signal Signal Signal 3.3V Signal Signal Signal 3.3V Signal Signal Signal 3.3V Signal Signal Signal 3.3V Signal* Signal* Signal* 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 3.3V 12V 122 12V Signal* B 120 12V Signal SDATA 118 12V Signal SDATA 116 12V Signal 106 114 12V Signal SCLK 112 12V Signal SCLK 110 12V Signal 104 108 12V Signal 2GND 102 12V 3.3V 151 94 Signal 3.3V 141 84 Signal 3.3V 131 74 Signal 3.3V 111 CS\ ADC_CS PSNTn GND 13 DOUT0P_B_CD ASP-122952-01 DEV_ID Vin 6 GND 11 ASP-122952-01 GND 9 ASP-122952-01 GND 7 J1-C GND 5 J1-B GND 3 J1-A GND 1 3 DIN 20361081-Revision 3 Bare Board 165166167168 169170171 172 20361083-Revision 6 Completed Assy A UNLESS OTHERWISE SPECIFIED MATERIAL A DIMENSIONS APPLY AFTER FINISH WHERE TOTAL TOLERANCE OS .001 DIM. ARE IN 2 PL DEC TOL + - 3 PL DEC TOL + - ANGULAR TOL NEXT ASSY USED ON APPLICATION 8 7 6 5 NEXT ASSY FINAL ASSY QUANITY REQD 4 ON Semiconductor INCHES OR LESS AND ON ALL + - THREADS. IN ALL OTHER PLACES DIMENSIONS APPLY BEFORE FINISH. NAME DR FINISH Board to Board Interconnect Gen2 Evaluation System 68 Pin PGA Imager Board QA CHK SURF ROUGHNESS ENGR EDGES ENGR INSIDE RADII ECN NO. Jim DiBella SIZE D DEVIATIONS FROM INTENDED SHAPE (FLATNESS,ROUNDNESS,SQUARENESS ETC.) MUST BE WITHIN STATED DIMENSIONAL TOLERANCES. 3 REL DATE 4/8/2016 2 SCALE DWG NO. 20361081 / 20361083 PROGRAM CADSTAR SHEET 1 5 of 17 __ 8 7 6 5 4 3 2 1 REVISIONS ZONE AD Conversion Channel A,B D CCDinA CCDinA CCDinB CCDinB CCDinC CCDinD CCDinD TCLKP_AB TCLKN_AB TCLKN_AB DOUT0P_A_AB DOUT0P_A_AB DOUT0N_A_AB DOUT0N_A_AB DOUT1P_A_AB DOUT1P_A_AB DOUT1N_A_AB DOUT1N_A_AB DOUT0P_B_AB DOUT0P_B_AB DOUT0N_B_AB DOUT0N_B_AB DOUT1P_B_AB DOUT1P_B_AB DOUT1N_B_AB DOUT1N_B_AB AD Conversion Channel C,D CCDinC TCLKP_AB TCLKP_CD TCLKP_CD TCLKN_CD TCLKN_CD DOUT0P_A_CD DOUT0P_A_CD DOUT0N_A_CD DOUT0N_A_CD DOUT1P_A_CD DOUT1P_A_CD DOUT1N_A_CD DOUT1N_A_CD DOUT0P_B_CD DOUT0P_B_CD DOUT0N_B_CD DOUT0N_B_CD DOUT1P_B_CD DOUT1P_B_CD DOUT1N_B_CD DOUT1N_B_CD SYM DESCRIPTION DATE APPROVAL D BUFFERED USER ACCESS TO SIGNALS CONTROL OF THESE SIGNALS IS PROGRAMMED THROUGH THE AFE 74LVC2G04DBVR 104363-4 +3.3VD C 3 Timing Horizontal_Clocks GIO 1 OSC_VDD BD1 BLM18AG601SN1D SCLK 2 1 4 U21 40.0 MHZ C97 .1uF 25V OSC_EN OSC_EN 1 3 EN SDATA SDATA AFECS_AB AFECS_AB AFECS_CD AFECS_CD OUT U41-B HD_AB HD_AB VD_AB 1=S1 0=S2 GPO1_STROBE_AB 1 5 1 6 R91 15.0K 1% GPO1_STROBE_AB GPO3_SCKA_AB SYNC_CD GPO6_XV21_SHPB_DVAL_AB RSTB_AB RSTB_AB GPO7_XV23_VDR_EN_AB RSTB_CD RSTB_CD GND 2 AFE_CLOCK_AB U20-B 2 C 0=S1 1=S2 GPO3_SCKA_AB 1 GPO5_SCKB_AB U42 ZXMD63C03X 1=S1 0=S2 S 3 D 5 D 6 4 D 7 3 NFET D 8 G S 1 PFET 4 G 2 B R90 15.0K 1% GPO6_XV21_SHPB_DVAL_AB TV59 S2 Q2 3904 GPO4_XSUBCK_SHPA_AB GPO5_SCKB_AB SYNC_AB 4 2 U41-A GPO2_MSHUT_AB GPO1_CD 3 2 J3 74LVC2G04DBVR VD_AB E C86 .1uF 25V 2 J3 J3 GPO1_CD GPO2_CD GPO2_CD GPO3_CD GPO3_CD GPO4_CD GPO4_CD GPO5_CD GPO5_CD GPO6_CD GPO6_CD GPO7_CD GPO7_CD 2 S1 5 1 C J3 +6V +3.3VD GPO4_XSUBCK_SHPA_AB SYNC_CD VCC 1 SCLK SYNC_AB 2 4 J3 74LVC2G04DBVR 5 1 6 AFE_CLOCK_CD 2 U20-A 74LVC2G04DBVR RGBa_AFE RGBa_AFE H2SLa_AFE H2SLa_AFE H1ab_AFE H1ab_AFE H2ab_AFE B H2ab_AFE H1Bb_SD_AFE H1Bb_SD_AFE H2Bb_SD_AFE H2Bb_SD_AFE H2SLb_AFE B Change Phase to support Single or Dual clocking H2SLb_AFE RGBb_AFE Vertical Clocks RGBb_AFE Use Mode 3 Configuration H1A=H3A=/H2A=/H4A H1B=H3B=/H2B=/H4B GPO7_XV23_VDR_EN_AB V1B_3rd_AFE V1B_3rd_AFE V1B_AFE RGBc_AFE RGBc_AFE H2SLc_AFE H2cd_AFE H1Bd_SD_AFE V2B_AFE V3B_AFE V3B_AFE V4B_AFE V4B_AFE V1T_3rd_AFE V1T_AFE V1T_AFE H1cd_AFE V2T_AFE V2T_AFE H2cd_AFE V3T_AFE V3T_AFE V4T_AFE V4T_AFE H1Bd_SD_AFE H2Bd_SD_AFE V2B_AFE V1T_3rd_AFE H2SLc_AFE H1cd_AFE V1B_AFE H2Bd_SD_AFE H2SLd_AFE H2SLd_AFE RGBd_AFE RGBd_AFE Change Phase to support Single or Dual clocking SUBCK TV46 SUBCK Use Mode 3 Configuration H1A=H3A=/H2A=/H4A H1B=H3B=/H2B=/H4B 20361081-Revision 3 Bare Board 20361083-Revision 6 Completed Assy A UNLESS OTHERWISE SPECIFIED MATERIAL A DIMENSIONS APPLY AFTER FINISH WHERE TOTAL TOLERANCE OS .001 DIM. ARE IN 2 PL DEC TOL + - 3 PL DEC TOL + - ANGULAR TOL NEXT ASSY USED ON APPLICATION 8 7 6 5 NEXT ASSY FINAL ASSY QUANITY REQD 4 ON Semiconductor INCHES OR LESS AND ON ALL + - THREADS. IN ALL OTHER PLACES DIMENSIONS APPLY BEFORE FINISH. NAME DR FINISH Analog Front End page 1 Gen2 Evaluation System 68 Pin PGA Imager Board QA CHK SURF ROUGHNESS ENGR EDGES ENGR INSIDE RADII ECN NO. Jim DiBella SIZE D DEVIATIONS FROM INTENDED SHAPE (FLATNESS,ROUNDNESS,SQUARENESS ETC.) MUST BE WITHIN STATED DIMENSIONAL TOLERANCES. 3 REL DATE 4/8/2016 2 SCALE DWG NO. 20361081 / 20361083 PROGRAM CADSTAR SHEET 1 6 of 17 __ 4 3 2 1 TW TS TW D TW DIFF Pair1 TS TW DIFF Pair2 TG D D GROUND +1.8V_A +1.8V_A +1.8V_A Keep TW, TS and D constant over trace length Keep TS <2TW Avoid Vias where possible Keep D>2TS Avoid 90 deg bends Design TW and TG for 50 ohms +1.8V_A +1.8V_A +1.8V_A 1 2 2 C149 .1uF 25V 2 A2 CCDIN_A 2 CCDinA_ B10 CDS L1 AVDD_B AVDD_A DC_RESTORE-> C150 .1uF 25V 1 2 Tw = .008 (8mil) Ts = .004 (4mil) D = .008 (0mil) Tg = .005 (5 mil) 1oz copper 4.2 Dielectric Constant between layer stack. 2 2 B3 CCDinA 2 C176 .1uF 25V L2 L4 L10 LVDD_B 2 C147 4.7UF_6.3V 1 LVDD_A C158 .1uF 25V 1 C170 C175 .1uF .1uF 25V 25V DVDD 1 C160 4.7UF_6.3V 1 C171 .1uF 25V 1 DVDD 1 1 CDS and Analog to Digital Converter 14-Bit ADC VGA C Reduced Range LVDS CLAMP C157 .1uF 25V A11 CCDinB 1 CCDIN_B CDS 2 CCDinB_ 14-Bit ADC VGA TCLKP M7 TCLKP_AB TCLKP_AB TCLKN L7 TCLKN_AB TCLKN_AB DOUT0P_A M6 DOUT0P_A_AB DOUT0P_A_AB DOUT0N_A L6 DOUT0N_A_AB DOUT0N_A_AB DOUT1P_A M5 DOUT1P_A_AB DOUT1P_A_AB DOUT1N_A L5 DOUT1N_A_AB DOUT1N_A_AB DOUT0P_B M9 DOUT0P_B_AB DOUT0P_B_AB DOUT0N_B L9 DOUT0N_B_AB DOUT0N_B_AB DOUT1P_B M8 DOUT1P_B_AB DOUT1P_B_AB DOUT1N_B L8 DOUT1N_B_AB DOUT1N_B_AB C +3.3VD C151 .1uF 25V CLAMP A4 1 REFT_A(1.4V) 2 C11 LDOIN_B C153 .1uF 25V 1 1 REFB_A(0.4V) 2 C2 LDOIN_A 1 C174 4.7UF_6.3V A5 C156 .1uF 25V +1.8V_A 2 C173 .1uF 25V 2 A9 1 REFT_B(1.4V) 2 LDOOUT_A C154 .1uF 25V B B1 LDO_A B A8 1 2 REFB_B(0.4V) LDOIN_B A3 B4 B5 A10 B9 B8 M2 M4 M10 B2 LDOOUT_B B12 LDOVSS_B LDOVSS_A LVSS_B LVSS_A DVSS AVSS_3B AVSS_2B AVSS1_B AVSS_3A AVSS1_A U37-A AD9928 AVSS_2A LDO_B B11 20361081-Revision 3 Bare Board 20361083-Revision 6 Completed Assy UNLESS OTHERWISE SPECIFIED MATERIAL DIMENSIONS APPLY AFTER FINISH WHERE TOTAL TOLERANCE OS .001 DIM. ARE IN A 2 PL DEC TOL + - 3 PL DEC TOL + - ANGULAR TOL NEXT ASSY USED ON APPLICATION 4 NEXT ASSY FINAL ASSY QUANITY REQD 3 ON Semiconductor INCHES OR LESS AND ON ALL + - THREADS. IN ALL OTHER PLACES DIMENSIONS APPLY BEFORE FINISH. DR FINISH NAME Analog Front End page 2 SURF ROUGHNESS ENGR EDGES ENGR INSIDE RADII ECO NO. Jim DiBella SIZE C DEVIATIONS FROM INTENDED SHAPE (FLATNESS,ROUNDNESS,SQUARENESS ETC.) MUST BE WITHIN STATED DIMENSIONAL TOLERANCES. REL DATE 2 4/8/2016 A Gen2 Evaluation System 68 Pin PGA Imager Board QA CHK SCALE DWG NO. 20361081 / 20361083 PROGRAM CADSTAR 1 SHEET 7 of 17 __ 4 3 2 1 TW TS TW D TW DIFF Pair1 TS TW DIFF Pair2 TG D D GROUND +1.8V_B +1.8V_B +1.8V_B Keep TW, TS and D constant over trace length Keep TS <2TW Avoid Vias where possible Keep D>2TS Avoid 90 deg bends Design TW and TG for 50 ohms +1.8V_B +1.8V_B +1.8V_B 1 2 2 C36 .1uF 25V 2 A2 CCDIN_A 2 CCDinC_ B10 CDS L1 AVDD_B AVDD_A DC_RESTORE-> C34 .1uF 25V 1 2 Tw = .008 (8mil) Ts = .004 (4mil) D = .008 (0mil) Tg = .005 (5 mil) 1oz copper 4.2 Dielectric Constant between layer stack. 2 2 B3 CCDinD 2 C5 .1uF 25V L2 L4 L10 LVDD_B 2 C37 4.7UF_6.3V 1 LVDD_A C26 .1uF 25V 1 C10 C2 .1uF .1uF 25V 25V DVDD 1 C25 4.7UF_6.3V 1 C9 .1uF 25V 1 DVDD 1 1 CDS and Analog to Digital Converter 14-Bit ADC VGA C Reduced Range LVDS CLAMP C27 .1uF 25V A11 CCDinC 1 CCDIN_B CDS 2 CCDinD_ 14-Bit ADC VGA TCLKP M7 TCLKP_CD TCLKP_CD TCLKN L7 TCLKN_CD TCLKN_CD DOUT0P_A M6 DOUT0P_A_CD DOUT0P_A_CD DOUT0N_A L6 DOUT0N_A_CD DOUT0N_A_CD DOUT1P_A M5 DOUT1P_A_CD DOUT1P_A_CD DOUT1N_A L5 DOUT1N_A_CD DOUT1N_A_CD DOUT0P_B M9 DOUT0P_B_CD DOUT0P_B_CD DOUT0N_B L9 DOUT0N_B_CD DOUT0N_B_CD DOUT1P_B M8 DOUT1P_B_CD DOUT1P_B_CD DOUT1N_B L8 DOUT1N_B_CD DOUT1N_B_CD C +3.3VD C33 .1uF 25V CLAMP A4 1 REFT_A(1.4V) 2 C11 LDOIN_B C31 .1uF 25V 1 1 REFB_A(0.4V) 2 C2 LDOIN_A 1 C6 4.7UF_6.3V A5 C28 .1uF 25V +1.8V_B 2 C7 .1uF 25V 2 A9 1 REFT_B(1.4V) 2 LDOOUT_A C30 .1uF 25V B B1 LDO_A B A8 1 2 REFB_B(0.4V) LDOIN_B A3 B4 B5 A10 B9 B8 M2 M4 M10 B2 LDOOUT_B B12 LDOVSS_B LDOVSS_A LVSS_B LVSS_A DVSS AVSS_3B AVSS_2B AVSS1_B AVSS_3A AVSS1_A U1-A AD9928 AVSS_2A LDO_B B11 20361081-Revision 3 Bare Board 20361083-Revision 6 Completed Assy UNLESS OTHERWISE SPECIFIED MATERIAL DIMENSIONS APPLY AFTER FINISH WHERE TOTAL TOLERANCE OS .001 DIM. ARE IN A 2 PL DEC TOL + - 3 PL DEC TOL + - ANGULAR TOL NEXT ASSY USED ON APPLICATION 4 NEXT ASSY FINAL ASSY QUANITY REQD 3 ON Semiconductor INCHES OR LESS AND ON ALL + - THREADS. IN ALL OTHER PLACES DIMENSIONS APPLY BEFORE FINISH. DR FINISH NAME Analog Front End page 3 SURF ROUGHNESS ENGR EDGES ENGR INSIDE RADII ECO NO. Jim DiBella SIZE C DEVIATIONS FROM INTENDED SHAPE (FLATNESS,ROUNDNESS,SQUARENESS ETC.) MUST BE WITHIN STATED DIMENSIONAL TOLERANCES. REL DATE 2 4/8/2016 A Gen2 Evaluation System 68 Pin PGA Imager Board QA CHK SCALE DWG NO. 20361081 / 20361083 PROGRAM CADSTAR 1 SHEET 8 of 17 __ 8 7 6 5 4 3 2 1 REVISIONS ZONE SYM DESCRIPTION DATE APPROVAL D D +3.3VD E9 K8 HD_AB K7 VD_AB G10 SCK GPO6 H11 SDATA GPO7 SL H1A Horizontal Clock Driver SYNC H2A RSTB H3A J8 +3.3VD H4A A6 GPO7_XV23_VDR_EN_AB K7 H2ab_AFE J6 SYNC_CD HL_A RG_A B7 H2B CLO C152 .1uF 25V H3B H4B F11 HL_B 2 C8 J5 K5 H1 C5 F3 F10 D3 Horizontal Clock Driver RGVDD_B H1A SYNC H2A RSTB H3A F1 H1Bd_SD_AFE F2 H2Bd_SD_AFE E1 E2 D1 H2SLd_AFE HL_A RGBd_AFE RG_A B6 CLI H1Bb_SD_AFE H1B B7 H2Bb_SD_AFE H2B CLO 1 C32 .1uF 25V H3B H4B F12 H1cd_AFE F11 H2cd_AFE E12 E11 D12 H2SLb_AFE H2SLc_AFE HL_B 2 C12 RGBb_AFE RGBc_AFE RG_B RGVSS_B RGVSS_A HVSS_B HVSS_A TEST0_C5 TEST1_H1 TEST1_J5 TCVSS IOVSS M11 TEST1_K5 RG_B GIO VD C1 E11 C12 HD RGBa_AFE E12 D12 Timing Generator Control Registers CLIVDD AFE_CLOCK_CD F12 GPO7_CD GPO7 SL A6 CLI H1B RGVDD_A SDATA H4A B6 1 H11 +3.3VD H2SLa_AFE GPO6_CD GPO6 J8 RSTB_CD E2 C1 AFE_CLOCK_AB G10 E9 H1ab_AFE E1 D1 CLIVDD GPO5_CD GPO5 IOVSS RSTB_AB F2 GPO4_CD J10 SCK D10 M11 C8 J5 K5 B 1 1 R89 0 H1 C5 F3 F10 D3 D10 B SLAVE R87 0 MASTER C GPO3_CD GPO4 GPO5_SCKB_AB F9 2 GPO2_CD GPO2 GPO4_XSUBCK_SHPA_AB GPO6_XV21_SHPB_DVAL_AB C8 4.7UF_6.3V GPO1_CD G9 K11 K8 VD H9 H10 AFECS_CD F1 2 GPO3 J12 1 C11 .1uF 25V 2 GPO1 GPO3_SCKA_AB GIO J6 SYNC_AB GPO2_MSHUT_AB 1 C1 4.7UF_6.3V D11 U1-C AD9928 GPO1_STROBE_AB Timing Generator Control Registers HD D2 2 1 C4 .1uF 25V RGVSS_B GPO5 E10 1 C35 .1uF 25V 2 RGVSS_A J10 E3 HVSS_B GPO2 GPO4 AFECS_AB L11 HVSS_A G9 K11 SDATA 2 2 TEST0_C5 RGVDD_A H9 GPO1 H10 F9 2 1 C3 .1uF 25V A7 GPO3 SCLK 1 C29 .1uF 25V D11 U37-C AD9928 J12 2 +3.3VD 1 C172 4.7UF_6.3V TCVDD D2 2 1 C169 .1uF 25V RGVDD_B E10 HVDD_B IOVDD TCVDD C E3 HVDD_A L11 2 1 C161 4.7UF_6.3V HVDD_B 2 2 1 C159 .1uF 25V HVDD_A 1 C148 .1uF 25V TEST1_H1 1 C155 .1uF 25V +3.3VD +3.3VD +1.8V_B 1 A7 +3.3VD TEST1_K5 +1.8V_A +3.3VD +3.3VD TEST1_J5 +3.3VD IOVDD +3.3VD TCVSS +3.3VD 2 2 20361081-Revision 3 Bare Board 20361083-Revision 6 Completed Assy A UNLESS OTHERWISE SPECIFIED MATERIAL A DIMENSIONS APPLY AFTER FINISH WHERE TOTAL TOLERANCE OS .001 DIM. ARE IN 2 PL DEC TOL + - 3 PL DEC TOL + - ANGULAR TOL NEXT ASSY USED ON APPLICATION 8 7 6 5 NEXT ASSY FINAL ASSY QUANITY REQD 4 ON Semiconductor INCHES OR LESS AND ON ALL + - THREADS. IN ALL OTHER PLACES DIMENSIONS APPLY BEFORE FINISH. NAME DR FINISH Analog Front End page 4 Gen2 Evaluation System 68 Pin PGA Imager Board QA CHK SURF ROUGHNESS ENGR EDGES ENGR INSIDE RADII ECN NO. Jim DiBella SIZE D DEVIATIONS FROM INTENDED SHAPE (FLATNESS,ROUNDNESS,SQUARENESS ETC.) MUST BE WITHIN STATED DIMENSIONAL TOLERANCES. 3 REL DATE 4/8/2016 2 SCALE DWG NO. 20361081 / 20361083 PROGRAM CADSTAR SHEET 1 9 of 17 __ 8 7 6 5 4 3 2 1 REVISIONS ZONE For 3V logic levels of V clock outputs Set: Vh to > 8VDC Vm to +3.3 Vl to 0VDC SYM DESCRIPTION DATE APPROVAL +3.3VD MASTER Use GIO for Sub Clock D D 3 Level Clocks K4 VDD1 (logic supply) J4 XV16(XSG1) VDD1 (logic supply) V1A D7 V1B D6 K2 VDD2 (logic supply) +Vhigh XV1 J2 VDD2 (logic supply) E4 +3.3VD XV17(XSG2) XVVDD XV18(XSG3) 1 1 K9 C163 .1uF 25V C145 4.7UF_25V C9 VH1 V2A C3 V2B D5 V3A D4 XV2 VH2 SLAVE XV19(XSG4) 2 2 XV20(XSG5) K10 C10 2 C144 4.7UF_25V K4 XV3 V3B VM2 2 VDD1 (logic supply) G12 J4 XV4 J9 1 D9 VDD2 (logic supply) G11 VDD2 (logic supply) E4 V5 H12 XV6 GPO7_XV23_VDR_EN_AB V6 J11 XV18(XSG3) K9 C9 V2B_AFE VH1 DNC_C4 DNC_J7 C XV7 U37-B AD9928 A1 V7 J1 K10 C10 NC_A1 XV8 V8 K12 VM1 V3B_AFE XV4 XV9 V9 L12 J9 V4B_AFE H4 D9 NC_H4 J3 XV10 NC_J3 V10 H3 V11 G4 XV5 VL2 V3B G12 V4 G11 V5 H12 V6 J11 V7 J1 V8 K12 V9 L12 V10 H3 V11 G4 V12 H2 V13 G3 V14 K3 V15 L3 SUBCK D8 C XV23(XSG8) V1T_AFE XV6 XV11 D4 XV22(XSG7) NC_K6 NC_M1 V3A VL1 K6 M1 D5 XV21(XSG6) NC_A12 NC_G1 V2B XV3 VM2 A12 G1 C3 XV19(XSG4) XV20(XSG5) J7 V2A XV2 VH2 VDR_EN C4 D6 XV17(XSG2) V1B_AFE XV24(XSG9) M3 V1B XVVDD XV23(XSG8) -Vlow D7 XV1 J2 V1B_3rd_AFE VL1 VL2 V1A K2 V4 XV22(XSG7) XV5 XV16(XSG1) VDD1 (logic supply) XV21(XSG6) C162 .1uF 25V 1 VM1 3 Level Clocks V1T_3rd_AFE V2T_AFE M3 V3T_AFE C4 XV24(XSG9) VDR_EN M12 NC_M12 XV12 V12 H2 DNC_C4 U1-B AD9928 J7 XV13 V13 DNC_J7 G3 A1 V4T_AFE XV7 NC_A1 XV8 A12 XV14 V14 NC_A12 K3 G1 NC_G1 XV9 H4 XV15 V15 NC_H4 L3 J3 XV10 NC_J3 K6 NC_K6 M1 C7 XSUBCK VMM SUBCK NC_M1 D8 XV11 M12 SUBCK NC_M12 XSUBCNT(GPO8) XV12 C6 VLL G2 VSS2 VSS1 -Vlow XVVSS XV13 K1 XV14 XV15 F4 C7 XSUBCK VMM XSUBCNT(GPO8) C6 G2 VSS2 VSS1 B XVVSS VLL K1 B F4 20361081-Revision 3 Bare Board 20361083-Revision 6 Completed Assy A UNLESS OTHERWISE SPECIFIED MATERIAL A DIMENSIONS APPLY AFTER FINISH WHERE TOTAL TOLERANCE OS .001 DIM. ARE IN 2 PL DEC TOL + - 3 PL DEC TOL + - ANGULAR TOL NEXT ASSY USED ON APPLICATION 8 7 6 5 NEXT ASSY FINAL ASSY QUANITY REQD 4 ON Semiconductor INCHES OR LESS AND ON ALL + - THREADS. IN ALL OTHER PLACES DIMENSIONS APPLY BEFORE FINISH. NAME DR FINISH Analog Front End page 5 Gen2 Evaluation System 68 Pin PGA Imager Board QA CHK SURF ROUGHNESS ENGR EDGES ENGR INSIDE RADII ECN NO. Jim DiBella SIZE D DEVIATIONS FROM INTENDED SHAPE (FLATNESS,ROUNDNESS,SQUARENESS ETC.) MUST BE WITHIN STATED DIMENSIONAL TOLERANCES. 3 REL DATE 4/8/2016 2 SCALE DWG NO. 20361081 / 20361083 PROGRAM CADSTAR SHEET 1 10 of 17 __ 8 7 6 5 4 3 2 1 REVISIONS ZONE SYM DESCRIPTION DATE APPROVAL C140 .1uF 25V H1Bb_SD_AFE H1Bb_SD_AFE 1 U30 74LCX541BQX TV41 2 1 20 R80 200K 1% D 2 K2 VCC 2 CR4-B HSMS-2805 18 3 17 A2 -VH 7 13 H2SLb 8 9 C123 .1uF 25V H2SLb 12 TV42 2 H2Bb_SD 14 H2Bb_SD_AFE 1 H2Bb_SD 6 C141 .1uF 25V H2Bb_SD_AFE 15 D H1Bb_SD 16 5 -VH H1Bb_SD 4 11 Rb 1 1 RESET CLOCKS NEED TO BE LEVEL SHIFTED Rb 2 1 R81 200K 1% 2 19 K1 1 CR4-A HSMS-2805 GND K1 PPAD 10 2 21 R51 200K 1% C119 1 .1uF 25V A1 -VH -VH CR13-A HSMS-2805 A1 2 -VH -VH C142 .1uF 25V -VRESET H2SLb_AFE H2SLb_in H2SLb_AFE 1 2 TV43 U29 74LCX541BQX K2 20 CR5-B HSMS-2805 1 C R82 200K 1% VCC 2 3 A2 5 7 9 RGBb_in 1 H2Sa H2Sa 14 H2Sb H2Sb 12 H1Sb H1Sb C 11 1 RGBb_AFE RGBb_AFE 16 13 8 C143 .1uF 25V H1Sa 15 6 -VH H1Sa 17 4 2 18 19 TV44 2 1 GND K1 R83 200K 1% CR5-A HSMS-2805 2 21 C121 1 .1uF 25V -VH A1 2 PPAD 10 -VH C136 .1uF 25V -VH RGBa_AFE RGBa_AFE Single H1_AFE = H1SL,H1BL,H1SR,H2BR* H2_AFE = H2SL,H2BL,H2SR,H1BR* RGBa_in 1 TV35 2 Dual H1_AFE = H1SL,H1BL,H1SR,H1BR* H2_AFE = H2SL,H2BL,H2SR,H2BR* 1 K2 R76 200K 1% A2 2 C137 .1uF 25V H2SLa_AFE CR2-B HSMS-2805 -VH H2SLa_AFE H2SLa_in 1 2 TV36 1 B K1 R77 200K 1% C120 .1uF 25V 20 A1 2 B U28 74LCX541BQX CR2-A HSMS-2805 RESET CLOCKS NEED TO BE LEVEL SHIFTED VCC 2 18 3 Ra 1 17 Ra 2 -VH 4 C138 .1uF 25V H2ab_AFE 5 15 7 13 6 H2ab_AFE 1 16 TV37 2 14 8 1 12 9 R78 200K 1% 2 H1ab_AFE 2 1 K2 H2Ba CR13-B HSMS-2805 R50 200K 1% H1Ba A2 2 1 CR3-B HSMS-2805 19 GND PPAD 2 C122 .1uF 25V 21 -VH -VRESET 1 -VH H1ab_AFE 1 H1Ba 11 10 C139 .1uF 25V H2Ba H2SLa K2 A2 -VH H2SLa -VH TV38 1 2 A1 -VH -VH TV40 CR3-A HSMS-2805 TV39 K1 R79 200K 1% 20361081-Revision 3 Bare Board 20361083-Revision 6 Completed Assy A UNLESS OTHERWISE SPECIFIED MATERIAL A DIMENSIONS APPLY AFTER FINISH WHERE TOTAL TOLERANCE OS .001 DIM. ARE IN 2 PL DEC TOL + - 3 PL DEC TOL + - ANGULAR TOL NEXT ASSY USED ON APPLICATION 8 7 6 5 NEXT ASSY FINAL ASSY QUANITY REQD 4 ON Semiconductor INCHES OR LESS AND ON ALL + - THREADS. IN ALL OTHER PLACES DIMENSIONS APPLY BEFORE FINISH. NAME DR FINISH AB Hclock drivers Gen2 Evaluation System 68 Pin PGA Imager Board QA CHK SURF ROUGHNESS ENGR EDGES ENGR INSIDE RADII ECN NO. Jim DiBella SIZE D DEVIATIONS FROM INTENDED SHAPE (FLATNESS,ROUNDNESS,SQUARENESS ETC.) MUST BE WITHIN STATED DIMENSIONAL TOLERANCES. 3 REL DATE 4/8/2016 2 SCALE DWG NO. 20361081 / 20361083 PROGRAM CADSTAR SHEET 1 11of 17 __ 8 7 6 5 4 3 2 1 REVISIONS ZONE SYM DESCRIPTION DATE APPROVAL C48 .1uF 25V H1Bd_SD_AFE 1 H1Bd_SD_AFE U11 74LCX541BQX TV18 2 1 20 R20 200K 1% D 2 K1 VCC 2 CR17-A HSMS-2805 7 13 8 H2SLd H2Bd_SD H2Bd_SD C67 .1uF 25V 12 9 1 H2SLd 14 TV19 2 15 6 C49 .1uF 25V H2Bd_SD_AFE 1 16 5 -VH D 17 4 A1 -VH H2Bd_SD_AFE 18 3 11 H1Bd_SD RESET CLOCKS NEED TO BE LEVEL SHIFTED Rd H1Bd_SD 1 Rd 2 1 R21 200K 1% 2 19 K2 1 CR17-B HSMS-2805 GND K2 PPAD 10 2 21 C68 .1uF 25V 1 A2 -VH -VH CR14-B HSMS-2805 R40 200K 1% A2 2 -VH -VH C50 .1uF 25V -VRESET H2SLd_AFE H2SLd_AFE H2SLd_in 1 TV20 2 U10 74LCX541BQX K1 1 CR18-A HSMS-2805 20 VCC 2 C R22 200K 1% 18 3 A1 4 16 5 2 14 7 RGBd_AFE 12 9 C H2Sd H2Sc H2Sc H1Sc H1Sc 11 1 RGBd_in RGBd_AFE 1 H2Sd 13 8 C51 .1uF 25V H1Sd 15 6 -VH H1Sd 17 19 TV21 2 1 GND K2 R23 200K 1% 2 21 CR18-B HSMS-2805 C65 .1uF 25V 1 -VH A2 2 PPAD 10 -VH C44 .1uF 25V RGBc_AFE -VH Single H1_AFE = H1SL,H1BL,H1SR,H2BR* H2_AFE = H2SL,H2BL,H2SR,H1BR* RGBc_in RGBc_AFE 1 TV12 2 Dual H1_AFE = H1SL,H1BL,H1SR,H1BR* H2_AFE = H2SL,H2BL,H2SR,H2BR* 1 K1 R16 200K 1% 2 C45 .1uF 25V H2SLc_AFE CR15-A HSMS-2805 A1 -VH H2SLc_in H2SLc_AFE 1 TV13 2 1 B R17 200K 1% K2 20 A2 2 B U9 74LCX541BQX CR15-B HSMS-2805 VCC 2 18 3 H1Bc 17 H1Bc -VH 4 C46 .1uF 25V H2cd_AFE 15 7 13 6 H2cd_AFE 1 5 TV14 2 8 1 C47 .1uF 25V H1cd_AFE 2 14 H2SLc H2Bc C64 .1uF 25V H2SLc RESET CLOCKS NEED TO BE LEVEL SHIFTED Rc 1 11 Rc 2 K1 1 2 A1 -VH -VH CR16-A HSMS-2805 1 19 K1 GND PPAD 10 21 CR14-A HSMS-2805 R39 200K 1% 2 C66 .1uF 25V 1 A1 2 -VH H1cd_AFE 1 H2Bc 12 9 R18 200K 1% 16 -VH TV15 1 K2 R19 200K 1% 20361081-Revision 3 Bare Board 20361083-Revision 6 Completed Assy -VH A TV17 -VH A2 TV16 2 -VRESET CR16-B HSMS-2805 UNLESS OTHERWISE SPECIFIED MATERIAL A DIMENSIONS APPLY AFTER FINISH WHERE TOTAL TOLERANCE OS .001 DIM. ARE IN 2 PL DEC TOL + - 3 PL DEC TOL + - ANGULAR TOL NEXT ASSY USED ON APPLICATION 8 7 6 5 NEXT ASSY FINAL ASSY QUANITY REQD 4 ON Semiconductor INCHES OR LESS AND ON ALL + - THREADS. IN ALL OTHER PLACES DIMENSIONS APPLY BEFORE FINISH. NAME DR FINISH CD H Clock Drivers Gen2 Evaluation System 68 Pin PGA Imager Board QA CHK SURF ROUGHNESS ENGR EDGES ENGR INSIDE RADII ECN NO. Jim DiBella SIZE D DEVIATIONS FROM INTENDED SHAPE (FLATNESS,ROUNDNESS,SQUARENESS ETC.) MUST BE WITHIN STATED DIMENSIONAL TOLERANCES. 3 REL DATE 4/8/2016 2 SCALE DWG NO. 20361081 / 20361083 PROGRAM CADSTAR SHEET 1 12 __ of 17 8 7 6 5 4 3 2 1 REVISIONS ZONE SYM DESCRIPTION DATE APPROVAL +Vhigh 220 ohm needed to reduce AFE driver current and potential counter glitch inside AFE effects edge rate V3rd signal swings from Vmid to +9 1 2 2 S PFET V1T_3rd_AFE A TP7 TP10 D 1 K NFET D C15 1000PF 8 K S 1 1 2 5 D 7 NFET D 8 G S 1 C21 1000PF 2 G D TP12 D 6 1 2 R3 220 2 C22 1000PF 2 3 V4T_AFE 3 1 5 7 S 4 G A D 6 D 1 CR23 BAT54-04 V4T_AFE 2 3 V1T_3rd_AFE PFET 1 C13 1000PF 2 3 4 G CR19 BAT54-04 signal swings from Vhigh to Vmid (inverting drive control) 1 D U6 ZXMD63C03X V4T 2 .1uF 25V C43 2 1 1 2 PFET C16 1000PF 2 3 V1T_AFE signal swings from Vmid to Vlow (inverting drive control) 1 K C12 NOLOAD R2 100 1% 2 1 NFET C14 1000PF 2 -Vlow 2 CR22 BAT54-04 D 5 D 6 D 7 D 8 V3T_AFE TP11 3 D 5 D 6 V1T V1T D 7 NFET D 8 G S 1 1 C20 1000PF 2 3 V3T_AFE 1 K C19 1000PF 2 S 1 2 .1uF 25V C38 2 1 C 4 G A TP9 2 G S PFET 1 A 1 1 3 4 G CR20 BAT54-04 TP6 S -Vlow U5 ZXMD63C03X TP13 V3T V3T 2 R7 100 1% C V1T_AFE R8 100 1% R4 100 1% -Vlow U3 ZXMD63C03X V4T 2 R9 100 1% D C39 .1uF 25V U2 ZXMD63C03X R10 100 1% R1 220 1 2 .1uF 25V C41 2 1 1 -Vlow -Vlow -Vlow R6 100 1% -Vlow 1 U4 ZXMD63C03X 2 S 3 D 5 D 6 D 7 NFET D 8 G S 1 PFET V2T_AFE TP8 CR21 BAT54-04 4 G 1 C18 1000PF A 2 3 V2T_AFE 1 K C17 1000PF 2 R5 100 1% B 1 TP14 V2T V2T 2 2 B C40 .1uF 25V 1 2 -Vlow -Vlow 20361081-Revision 3 Bare Board 20361083-Revision 6 Completed Assy A UNLESS OTHERWISE SPECIFIED MATERIAL A DIMENSIONS APPLY AFTER FINISH WHERE TOTAL TOLERANCE OS .001 DIM. ARE IN 2 PL DEC TOL + - 3 PL DEC TOL + - ANGULAR TOL NEXT ASSY USED ON APPLICATION 8 7 6 5 NEXT ASSY FINAL ASSY QUANITY REQD 4 ON Semiconductor INCHES OR LESS AND ON ALL + - THREADS. IN ALL OTHER PLACES DIMENSIONS APPLY BEFORE FINISH. NAME DR FINISH Top V Clock Drivers Gen2 Evaluation System 68 Pin PGA Imager Board QA CHK SURF ROUGHNESS ENGR EDGES ENGR INSIDE RADII ECN NO. Jim DiBella SIZE D DEVIATIONS FROM INTENDED SHAPE (FLATNESS,ROUNDNESS,SQUARENESS ETC.) MUST BE WITHIN STATED DIMENSIONAL TOLERANCES. 3 REL DATE 4/8/2016 2 SCALE DWG NO. 20361081 / 20361083 PROGRAM CADSTAR SHEET 1 13 of 17 __ 8 7 6 5 4 3 2 1 REVISIONS ZONE D SYM DESCRIPTION DATE APPROVAL D +Vhigh 220 ohm needed to reduce AFE driver current and potential counter glitch inside AFE effects edge rate V3rd signal swings from Vmid to +9 1 2 2 S PFET 4 CR8 BAT54-04 V1B_3rd_AFE CR12 BAT54-04 V4B_AFE TP5 2 3 1 K NFET C73 1000PF 5 D 6 D 7 D 8 4 S D 5 D 6 D 7 NFET D 8 G S 1 C81 1000PF 2 3 V4B_AFE 1 K C82 1000PF 2 G 3 G 1 A 2 R25 220 2 D S PFET G C75 1000PF TP2 1 2 3 1 A V1B_3rd_AFE 1 U16 ZXMD63C03X 1 1 2 TP16 V4B 2 .1uF 25V C58 2 1 C 1 2 PFET CR9 BAT54-04 TP1 V1B_AFE 1 signal swings from Vmid to Vlow (inverting drive control) C74 1000PF 1 NFET C76 1000PF 2 R28 100 1% 2 PFET CR11 BAT54-04 V3B_AFE D 5 D 6 D 7 V1B V1B D 8 C79 1000PF 2 G S 1 2 .1uF 25V C52 2 1 5 D 7 NFET D 8 G S 1 C80 1000PF 2 D TP17 D 6 1 K 3 1 2 3 V3B_AFE S 4 G A TP4 TP15 -Vlow 1 2 1 2 K C72 NOLOAD 1 3 4 G A 3 S C -Vlow U15 ZXMD63C03X V3B V3B 2 R31 100 1% V1B_AFE R30 100 1% R26 100 1% -Vlow U13 ZXMD63C03X V4B 2 R33 100 1% signal swings from Vhigh to Vmid (inverting drive control) C53 .1uF 25V U12 ZXMD63C03X R32 100 1% R27 220 1 2 .1uF 25V C57 2 1 1 -Vlow -Vlow -Vlow R29 100 1% -Vlow 1 U14 ZXMD63C03X 2 PFET V2B_AFE TP3 CR10 BAT54-04 C77 1000PF D 7 NFET D 8 G S 1 C78 1000PF R37 100 1% 2 1 5 TP18 B D 6 1 K D 1 2 3 V2B_AFE 3 4 G A B S V2B V2B 2 2 C56 .1uF 25V 1 2 -Vlow -Vlow 20361081-Revision 3 Bare Board 20361083-Revision 6 Completed Assy A UNLESS OTHERWISE SPECIFIED MATERIAL A DIMENSIONS APPLY AFTER FINISH WHERE TOTAL TOLERANCE OS .001 DIM. ARE IN 2 PL DEC TOL + - 3 PL DEC TOL + - ANGULAR TOL NEXT ASSY USED ON APPLICATION 8 7 6 5 NEXT ASSY FINAL ASSY QUANITY REQD 4 ON Semiconductor INCHES OR LESS AND ON ALL + - THREADS. IN ALL OTHER PLACES DIMENSIONS APPLY BEFORE FINISH. NAME DR FINISH Bottom V Clock Drivers Gen2 Evaluation System 68 Pin PGA Imager Board QA CHK SURF ROUGHNESS ENGR EDGES ENGR INSIDE RADII ECN NO. Jim DiBella SIZE D DEVIATIONS FROM INTENDED SHAPE (FLATNESS,ROUNDNESS,SQUARENESS ETC.) MUST BE WITHIN STATED DIMENSIONAL TOLERANCES. 3 REL DATE 4/8/2016 2 SCALE DWG NO. 20361081 / 20361083 PROGRAM CADSTAR SHEET 1 14 of 17 __ 8 7 6 5 4 3 2 1 REVISIONS ZONE VAB_ADJ VAB_ADJ VAB_EN VAB_EN SUBCK D VSUB SYM DESCRIPTION DATE APPROVAL VSUB VSUB SUBCK GPO1_STROBE_AB D GPO1_STROBE_AB Rc Video Outputs H2SLc H1Sc H1Bc H2Sc H2Bc CCDoutC CCDinC CCDoutD CCDinD CCDinC H1Sd H1Bd_SD CCDinD H2Sd H2Bd_SD H2SLd V3T 67 C V1T 65 ESD 68 V4T GND 61 V2T 64 V1T 65 ESD 68 VDDc 63 66 V3T 67 V4T VDDc 60 GND 61 V2T 64 H2SLc 57 VOUTc RDc 62 63 66 Rc 59 OGc Rc H2SLc 57 VOUTc RDc 62 60 OGc N/C 51 52 H2Sc 53 N/C 51 52 Rd OGd 45 48 -VOG GND VDDd 39 RDd VOUTd 42 Rd 43 OGd 46 +15VA 41 44 H1Bd H2SLd 47 VRD 43 46 H1Sd H2Bd 50 Rd 45 48 H2Sd 49 H2SLd H1Bd H2SLd 47 H1Sd H2Bd 50 H1Sc SUB 54 H1Bd_SD H2Bd_SD H2Sd 49 H1Sc SUB H2Bc 56 H2Sc 54 H1Bc 55 58 -VESD V1T 56 VSUB 53 H2Bc 58 59 H1Bc 55 H2Sd H1Sd VRD H1Sc H2Sc U23 +15VA U22 KAI-02150 KAI-08050_DUALX6SOCKET H2Bc H1Bc Rc H2SLc Rd GND VDDd 41 39 RDd VOUTd 44 V2T 40 42 V2T 40 V1T 37 V4T 38 C DevID 36 V1T 37 DEV_ID V3T 35 V4T 38 DevID 36 -VOG C V2T V3T 35 D V3T V4T A V1B V2B A B +15VA V3B VRD VRD VSUB +15VA V4B 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 N/C V4B 1 V3B 2 3 V1B 4 V2B VOUTA 5 7 VDDa 6 RDa OGa 9 GND 8 11 Ra H2Ba H1Sa 13 15 H2SLa H1Ba 10 12 14 H2Sa 16 SUB 17 N/C 18 H1Sb H2Bb 19 21 H2Sb 20 OGb 23 RDb 25 H1Bb H2SLb 22 24 VOUTb V2B 27 Rb 26 29 GND VDDb 28 30 V4B 31 V1B 32 ESD 33 V3B 34 N/C GND Ra H2Ba H1Sa 13 15 H2SLa H1Ba Ra H2SLa -VOG H2Sa SUB 17 N/C H1Sb H2Bb 19 21 OGb 23 RDb 25 H2Sb H1Bb H2SLb VOUTb V2B 27 Rb 29 GND VDDb V4B 31 V1B ESD 33 V3B B -VOG Rb OGa 11 H2SLb VDDa RDa 9 H1Bb_SD H2Bb_SD 7 H2Sb H1Sb B V1B V2B VOUTA 5 H1Sa H2Sa V3B 3 H2Ba H1Ba V4B 1 -VESD Ra H2SLa H1Sa H1Ba CCDoutB CCDinB CCDoutA CCDinA CCDinB H2Sa H2Ba CCDinA H1Sb H1Bb_SD H2Sb H2Bb_SD +15VA H2SLb Rb 1 1 C98 2 .1uF 25V R41 2 49.9K VRD 1% 1 A C100 .1uF 25V 2 2 1 R48 27K 1% 20361081-Revision 3 Bare Board 2 20361083-Revision 6 Completed Assy 1 1 C87 .1uF 25V 1 +12VDC 1 C88 2 .1uF 25V 2 -VOG R54 200K 1% -2 UNLESS OTHERWISE SPECIFIED R49 39.2K 1% WHERE TOTAL TOLERANCE OS .001 + - -VH 3 PL DEC TOL + - -5V ANGULAR TOL USED ON 6 5 NEXT ASSY FINAL ASSY QUANITY REQD 4 ON Semiconductor INCHES OR LESS AND ON ALL 2 PL DEC TOL APPLICATION 7 A DIMENSIONS APPLY AFTER FINISH DIM. ARE IN NEXT ASSY 8 MATERIAL + - THREADS. IN ALL OTHER PLACES DIMENSIONS APPLY BEFORE FINISH. NAME DR FINISH Imager Interface Gen2 Evaluation System 68 Pin PGA Imager Board Imager PCB Interface QA CHK SURF ROUGHNESS ENGR EDGES ENGR INSIDE RADII ECN NO. Jim DiBella SIZE D DEVIATIONS FROM INTENDED SHAPE (FLATNESS,ROUNDNESS,SQUARENESS ETC.) MUST BE WITHIN STATED DIMENSIONAL TOLERANCES. 3 REL DATE 4/8/2016 2 SCALE DWG NO. 20361081 / 20361083 PROGRAM CADSTAR SHEET 1 15of 17 __ 8 7 6 5 4 3 2 1 REVISIONS ZONE SYM DESCRIPTION DATE Assy 20361083-Revision 5 to 6 Change R61 from 200K to 196K Change R71 from 71.5K to 63.4K C4 APPROVAL April 2016 D D VAB_ADJ U33 LT3050 +16V 6 OUT IN OUT 5 1 7 R61 196K 1% 4 VAB_EN VAB_EN VAB 8 IN SHDN 1 3 R72 100K 1% 2 2 C 9 FAULT 1 C130 1uF 25V 10% 2 1 ADJ 11 VAB_ADJ 2 1 1 Imon 1 1 1 C109 .1uF 25V C108 4.7UF_25V R70 9.09K 1% 12 Imax R71 63.4K 1% 2 2 C 2 C107 .01uF R60 2 15.0K 1% 2 1 Imin REF/BYP 1 C129 .01uF 2 GND GND 10 2 VAB LDO Current Limit programmed to 800umA Adjustable 5V to 15.5V +16V V16 +3.3VD 1 FAULT 1 Q1 BC847BVN 2 R74 4 B2 1 2 1 K2 E2 C133 .1uF 25V 100K 1% 2 2 5 Q2 C110 1uF 25V 10% 5 C2 3 4 2 GPO1_STROBE_AB 3 B 1 C1 C132 .1uF 25V U36 7SZ08 1 VSUB VSUB 2 VSUB 6 2 VSUBGND CR6-B HSMS-2805 R73 10K 1% 1 A2 C131 .1uF 25V B 1 B1 Q1 2 E1 R62 10K 1% 1 ES_LOW_CL 1 Scope GND 2 1 R64 10K 1% K1 R63 0 CR6-A HSMS-2805 2 2 2 A1 C112 .1uF 25V 1 SUBCK C111 1uF 25V 10% 1 -12V 2 Option to use TTL control for ES or To directily Drive CCD ES from AFE Populate the corrisponding coupling cap for the desired source of the ES 20361081-Revision 3 Bare Board 20361083-Revision 6 Completed Assy A UNLESS OTHERWISE SPECIFIED MATERIAL A DIMENSIONS APPLY AFTER FINISH WHERE TOTAL TOLERANCE OS .001 DIM. ARE IN 2 PL DEC TOL + - 3 PL DEC TOL + - ANGULAR TOL NEXT ASSY USED ON APPLICATION 8 7 6 5 NEXT ASSY FINAL ASSY QUANITY REQD 4 ON Semiconductor INCHES OR LESS AND ON ALL + - THREADS. IN ALL OTHER PLACES DIMENSIONS APPLY BEFORE FINISH. NAME DR FINISH VSUB and Electronic Shutter Gen2 Evaluation System 68 Pin PGA Imager Board QA CHK SURF ROUGHNESS ENGR EDGES ENGR INSIDE RADII ECN NO. Jim DiBella SIZE D DEVIATIONS FROM INTENDED SHAPE (FLATNESS,ROUNDNESS,SQUARENESS ETC.) MUST BE WITHIN STATED DIMENSIONAL TOLERANCES. 3 REL DATE 4/8/2016 2 SCALE DWG NO. 20361081 / 20361083 PROGRAM CADSTAR SHEET 1 16 of 17 __ 8 7 6 5 4 3 2 1 REVISIONS ZONE SYM DESCRIPTION DATE APPROVAL D D +15VA +15VA 49.9K with 15V sets up amplifier load of 6.865mA 1 1 R35 49.9K 1% 1 C63 .1uF 25V C 4 2 5 ISF VCC 2 C71 .1uF 25V ISF 2 1 CCDinC OUT VEE U17 ADA4800 2 4 2 5 VCC C70 .1uF 25V C 2 3 IN CCDinD OUT EPAD VEE 7 2 IDRV 1 CCDoutD C69 .1uF 25V 1 2 3 IN 1 R24 200K 1% 6 2 1 C62 .1uF 25V IDRV 1 R36 49.9K 1% 1 2 CCDoutC C61 .1uF 25V R15 200K 1% 6 2 1 1 U18 ADA4800 2 EPAD 7 B B +15VA +15VA 1 R56 49.9K 1% C116 .1uF 25V ISF 5 VCC 4 2 C118 .1uF 25V R57 49.9K 1% 2 C124 .1uF 25V C117 .1uF 25V IDRV 1 3 VEE U27 ADA4800 CCDinA OUT 2 ISF 5 VCC 4 2 C125 .1uF 25V 2 3 IN OUT VEE EPAD U31 ADA4800 7 2 IDRV 1 CCDoutB C126 .1uF 25V 1 2 2 IN 1 R69 200K 1% 6 2 1 1 2 CCDoutA 1 1 R68 200K 1% 6 2 1 1 1 2 CCDinB EPAD 7 20361081-Revision 3 Bare Board 20361083-Revision 6 Completed Assy A UNLESS OTHERWISE SPECIFIED MATERIAL A DIMENSIONS APPLY AFTER FINISH WHERE TOTAL TOLERANCE OS .001 DIM. ARE IN 2 PL DEC TOL + - 3 PL DEC TOL + - ANGULAR TOL NEXT ASSY USED ON APPLICATION 8 7 6 5 NEXT ASSY FINAL ASSY QUANITY REQD 4 ON Semiconductor INCHES OR LESS AND ON ALL + - THREADS. IN ALL OTHER PLACES DIMENSIONS APPLY BEFORE FINISH. NAME DR FINISH Video Output Buffers Gen2 Evaluation System 68 Pin PGA Imager Board QA CHK SURF ROUGHNESS ENGR EDGES ENGR INSIDE RADII ECN NO. Jim DiBella SIZE D DEVIATIONS FROM INTENDED SHAPE (FLATNESS,ROUNDNESS,SQUARENESS ETC.) MUST BE WITHIN STATED DIMENSIONAL TOLERANCES. 3 REL DATE 4/8/2016 2 SCALE DWG NO. 20361081 / 20361083 PROGRAM CADSTAR SHEET 1 17of 17 __ Gen2 Eval 68 pin Imager Bare board 20361081 REV4 Assembly 20361083 REV6 Parts List in CSV Format ======================== DO NOT POPULATE Wednesday Digikey# LT3050EDDB#PBF‐ND DO NOT POPULATE DO NOT POPULATE LT3479EDE#PBF‐ND LT3479EDE#PBF‐ND A33932‐ND LT1175CS8#BFP‐ND LT1761ES5‐SD#CT‐ND 399‐1091‐1‐ND 399‐1091‐1‐ND 399‐1091‐1‐ND 399‐1091‐1‐ND 399‐1091‐1‐ND 399‐1091‐1‐ND 399‐1091‐1‐ND 399‐1091‐1‐ND 399‐1091‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND March 28 DESCRIPTION 100mA LDO with current limit and fault detect 1206 SMT JUMPER 1206 SMT JUMPER 3A DC/DC Converter 3A DC/DC Converter 5 POS SHROUDED MTE HDR ASS ADJ REGULATOR LOW DROPOUT NEG ADJ REGULATOR LOW DROPOUT STDBY CAP .01UF 50WVDC 10% CAP .01UF 50WVDC 10% CAP .01UF 50WVDC 10% CAP .01UF 50WVDC 10% CAP .01UF 50WVDC 10% CAP .01UF 50WVDC 10% CAP .01UF 50WVDC 10% CAP .01UF 50WVDC 10% CAP .01UF 50WVDC 10% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% MFG LINEAR TECH LINEAR TECH LINEAR TECH AMP LINEAR LINEAR KEMET KEMET KEMET KEMET KEMET KEMET KEMET KEMET KEMET MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA PART_NUMBER LT3050EDDB#PBF NONE NONE LT3479EDE LT3479EDE 104363‐4 LT1175CS8#PBF LT1761‐SD#TRM C0603C103K5RAC C0603C103K5RAC C0603C103K5RAC C0603C103K5RAC C0603C103K5RAC C0603C103K5RAC C0603C103K5RAC C0603C103K5RAC C0603C103K5RAC GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD PART_NAME U33 JMP1 JMP2 U34 U26 J3 U8 U32 C55 C60 C90 C177 C99 C115 C134 C129 C107 C86 C97 C151 C153 C156 C154 C149 C170 C171 C175 C176 C158 C173 C150 C157 C152 C32 C3 C35 C4 C11 C159 C148 C169 C155 C29 C163 C162 C100 C87 C88 C98 C101 PCB_REF_NAME DFN3mmx2mm‐12 1206 1206 DFN4mmx3mm‐14 DFN4mmx3mm‐14 104363‐4 SOIC‐8_150 SOT23‐5 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 REFDES LT3050 JUMP_1206_SMT JUMP_1206_SMT LT3479EDE LT3479EDE 104363‐4 LT1175CS8 LT1761ES5‐SD C.01UF_0603 C.01UF_0603 C.01UF_0603 C.01UF_0603 C.01UF_0603 C.01UF_0603 C.01UF_0603 C.01UF_0603 C.01UF_0603 C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V PriceCT PriceTR Side 3.85 1.88 Top Top Top 3.23 3.18 Top 3.23 3.18 Top 1.04 0.46 Top 5.38 2.96 Top 2.38 1.06 Top 0.02 0.005 Top 0.02 0.005 Top 0.02 0.005 Top 0.02 0.005 Top 0.02 0.005 Top 0.02 0.005 Top 0.02 0.005 Top 0.02 0.005 Top 0.02 0.005 Top 0.39 0.09 Top 0.39 0.09 Top 0.39 0.09 Top 0.39 0.09 Top 0.39 0.09 Top 0.39 0.09 Top 0.39 0.09 Top 0.39 0.09 Top 0.39 0.09 Top 0.39 0.09 Top 0.39 0.09 Top 0.39 0.09 Top 0.39 0.09 Top 0.39 0.09 Top 0.39 0.09 Top 0.39 0.09 Top 0.39 0.09 Top 0.39 0.09 Top 0.39 0.09 Top 0.39 0.09 Top 0.39 0.09 Top 0.39 0.09 Top 0.39 0.09 Top 0.39 0.09 Top 0.39 0.09 Top 0.39 0.09 Top 0.39 0.09 Top 0.39 0.09 Top Top Top Top Top Top 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC CAP .1UF 25WVDC 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD C85 C23 C168 C103 C92 C58 C57 C56 C52 C53 C67 C50 C65 C45 C51 C44 C47 C46 C48 C68 C49 C66 C64 C146 C95 C93 C33 C31 C28 C30 C26 C36 C10 C9 C2 C5 C7 C34 C27 C124 C125 C126 C71 C70 C69 C63 C62 C61 C116 C117 C118 C133 C131 C132 C109 C112 C123 C142 C121 C137 C120 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V 0.39 0.09 0.39 0.39 0.39 0.39 0.39 0.39 0.39 0.39 0.39 0.39 0.39 0.39 0.39 0.39 0.39 0.09 0.09 0.09 0.09 0.09 0.09 0.09 0.09 0.09 0.09 0.09 0.09 0.09 0.09 0.09 Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND 478‐3726‐1‐ND PCC2243CT‐ND PCC2243CT‐ND PCC2243CT‐ND 511‐1044‐1‐ND 511‐1044‐1‐ND DO NOT POPULATE DO NOT POPULATE DO NOT POPULATE 490‐3347‐1‐ND 490‐3347‐1‐ND 490‐3347‐1‐ND PCC2422CT‐ND PCC2422CT‐ND PCC2422CT‐ND PCC2422CT‐ND PCC2422CT‐ND PCC2422CT‐ND PCC2422CT‐ND PCC2422CT‐ND PCC2422CT‐ND PCC1851TR‐ND PCC1851TR‐ND PCC1851TR‐ND PCC1851TR‐ND 587‐1373‐1‐ND 587‐1373‐1‐ND ADA4800 CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP .1UF 25WVDC 20% CAP 1000PF 50VDC 10% CAP 1000PF 50VDC 10% CAP 1000PF 50VDC 10% CAP 1000PF 50VDC 10% CAP 1000PF 50VDC 10% CAP 1000PF 50VDC 10% CAP 1000PF 50VDC 10% CAP 1000PF 50VDC 10% CAP 1000PF 50VDC 10% CAP 1000PF 50VDC 10% CAP 1000PF 50VDC 10% CAP 1000PF 50VDC 10% CAP 1000PF 50VDC 10% CAP 1000PF 50VDC 10% CAP 1000PF 50VDC 10% CAP 1000PF 50VDC 10% CAP 1000PF 50VDC 10% CAP 1000PF 50VDC 10% CAP 1000PF 50VDC 10% CAP 1000PF 50VDC 10% CAP 100PF 50WVDC 5% CAP 10UF 25WVDC 20% X5R CAP 10UF 25WVDC 20% X5R CAP 10UF 25WVDC 20% X5R CAP 2200PF 50WVDC 10% CAP 2200PF 50WVDC 10% CAP NOLOAD CAP NOLOAD CAP 10UF 16WVDC 80% CAP 10UF 16WVDC 80% CAP 10UF 16WVDC 80% CAP 1UF 25V 10% CAP 1UF 25V 10% CAP 1UF 25V 10% CAP 1UF 25V 10% CAP 1UF 25V 10% CAP 1UF 25V 10% CAP 1UF 25V 10% CAP 1UF 25V 10% CAP 1UF 25V 10% CAP 2.2UF 16WVDC 20% Y5V CAP 2.2UF 16WVDC 20% Y5V CAP 2.2UF 16WVDC 20% Y5V CAP 2.2UF 16WVDC 20% Y5V CAP 4.7UF 25WVDC 20% CAP 4.7UF 25WVDC 20% CCD BUFFER AMPLIFIER MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA MURATA AVX AVX AVX AVX AVX AVX AVX AVX AVX AVX AVX AVX AVX AVX AVX AVX AVX AVX AVX AVX KEMET Panasonic Panasonic Panasonic KEMET KEMET MURATA MURATA Murata Murata Murata Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic TAIYO YUDEN TAIYO YUDEN Analog Devices GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD GRM39Y5V104Z025AD 06035C102KAT4A 06035C102KAT4A 06035C102KAT4A 06035C102KAT4A 06035C102KAT4A 06035C102KAT4A 06035C102KAT4A 06035C102KAT4A 06035C102KAT4A 06035C102KAT4A 06035C102KAT4A 06035C102KAT4A 06035C102KAT4A 06035C102KAT4A 06035C102KAT4A 06035C102KAT4A 06035C102KAT4A 06035C102KAT4A 06035C102KAT4A 06035C102KAT4A C0603C101J5GAC ECJ‐4YB1E106M ECJ‐4YB1E106M ECJ‐4YB1E106M C0603C222K5RAC C0603C222K5RAC NOLOAD NOLOAD GDM21BF51C106ZE15L GDM21BF51C106ZE15L GDM21BF51C106ZE15L ECJ‐1VB1E105K ECJ‐1VB1E105K ECJ‐1VB1E105K ECJ‐1VB1E105K ECJ‐1VB1E105K ECJ‐1VB1E105K ECJ‐1VB1E105K ECJ‐1VB1E105K ECJ‐1VB1E105K ECJ‐2YF1C225Z ECJ‐2YF1C225Z ECJ‐2YF1C225Z ECJ‐2YF1C225Z TMK325BJ475KN‐T TMK325BJ475KN‐T ADA4800 C143 C136 C139 C138 C140 C119 C141 C122 C38 C39 C43 C41 C40 C164 C75 C73 C74 C76 C77 C78 C79 C80 C81 C82 C13 C15 C16 C14 C18 C17 C20 C19 C22 C21 C83 C106 C128 C104 C113 C94 C72 C12 C91 C135 C165 C127 C178 C166 C84 C89 C105 C130 C110 C111 C54 C59 C102 C96 C24 C42 U31 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 1210 1210 1210 603 603 603 603 805 805 805 603 603 603 603 603 603 603 603 603 805 805 805 805 1210 1210 LFCSP_6 C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C.1UF_0603_25V C1000PF_0603 C1000PF_0603 C1000PF_0603 C1000PF_0603 C1000PF_0603 C1000PF_0603 C1000PF_0603 C1000PF_0603 C1000PF_0603 C1000PF_0603 C1000PF_0603 C1000PF_0603 C1000PF_0603 C1000PF_0603 C1000PF_0603 C1000PF_0603 C1000PF_0603 C1000PF_0603 C1000PF_0603 C1000PF_0603 C100PF_0603 C10UF_1210_25V_20 C10UF_1210_25V_20 C10UF_1210_25V_20 C2200PF_0603_50V_10% C2200PF_0603_50V_10% CNOLOAD_0603 CNOLOAD_0603 C10UF_0805_16V_80 C10UF_0805_16V_80 C10UF_0805_16V_80 C1UF_0603_25V_10 C1UF_0603_25V_10 C1UF_0603_25V_10 C1UF_0603_25V_10 C1UF_0603_25V_10 C1UF_0603_25V_10 C1UF_0603_25V_10 C1UF_0603_25V_10 C1UF_0603_25V_10 C2.2UF_0805_16V C2.2UF_0805_16V C2.2UF_0805_16V C2.2UF_0805_16V C4.7UF_1210_25V20 C4.7UF_1210_25V20 ADA4800 1.26 1.26 1.26 0.07 0.56 0.56 0.56 0.01 0.34 0.34 0.34 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.13 0.38 0.38 0.38 0.38 0.66 0.66 0.54 0.05 0.05 0.05 0.03 0.03 0.03 0.03 0.03 0.03 0.03 0.03 0.03 0.15 0.15 0.15 0.15 0.22 0.22 0.31 Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top ADA4800 ADA4800 ADA4800 AD9928 AD9928 PCC2321CT‐ND PCC2321CT‐ND PCC2321CT‐ND PCC2321CT‐ND PCC2321CT‐ND PCC2396CT‐ND PCC2396CT‐ND PCC2396CT‐ND PCC2396CT‐ND PCC2396CT‐ND PCC2396CT‐ND PCC2396CT‐ND PCC2396CT‐ND PCC2396CT‐ND PCC2396CT‐ND ASP‐122952‐01 ASP‐122952‐01 CTX280LVCT‐ND 296‐13261‐1‐ND 296‐13261‐1‐ND 490‐1014‐1‐ND DO NOT POPULATE LTC1665CGN‐ND ADC081S021CIMFCT‐ND 587‐2409‐1‐ND 587‐2409‐1‐ND 587‐2409‐1‐ND CP‐002APJCT‐ND 74LCX541BQX‐ND 74LCX541BQX‐ND 74LCX541BQX‐ND 74LCX541BQX‐ND 74LCX541BQX‐ND 74LCX541BQX‐ND CCD BUFFER AMPLIFIER CCD BUFFER AMPLIFIER CCD BUFFER AMPLIFIER CCD DUAL Signal Processor with HV Timing Generator CCD DUAL Signal Processor with HV Timing Generator CERCAP 4.7UF 25WVDC 20% X5R CERCAP 4.7UF 25WVDC 20% X5R CERCAP 4.7UF 25WVDC 20% X5R CERCAP 4.7UF 25WVDC 20% X5R CERCAP 4.7UF 25WVDC 20% X5R CERCAP 4.7UF 6.3WVDC 10% CERCAP 4.7UF 6.3WVDC 10% CERCAP 4.7UF 6.3WVDC 10% CERCAP 4.7UF 6.3WVDC 10% CERCAP 4.7UF 6.3WVDC 10% CERCAP 4.7UF 6.3WVDC 10% CERCAP 4.7UF 6.3WVDC 10% CERCAP 4.7UF 6.3WVDC 10% CERCAP 4.7UF 6.3WVDC 10% CERCAP 4.7UF 6.3WVDC 10% CONNECTOR 5mm BOARD TO BOARD Mezzanine CONNECTOR 5mm BOARD TO BOARD Mezzanine CRYSTAL OSCILLATOR 40MHz 50ppm DIODE DUAL DIODE DUAL DIODE DUAL DIODE DUAL DIODE DUAL DIODE DUAL DIODE DUAL DIODE DUAL DIODE DUAL DIODE DUAL DIODE DUAL Dual TINY INVERTER Dual TINY INVERTER EMI FILTER IC N/P‐CHANNEL FAST SWITCH FET IC N/P‐CHANNEL FAST SWITCH FET IC N/P‐CHANNEL FAST SWITCH FET IC N/P‐CHANNEL FAST SWITCH FET IC N/P‐CHANNEL FAST SWITCH FET IC N/P‐CHANNEL FAST SWITCH FET IC N/P‐CHANNEL FAST SWITCH FET IC N/P‐CHANNEL FAST SWITCH FET IC N/P‐CHANNEL FAST SWITCH FET IC N/P‐CHANNEL FAST SWITCH FET IC N/P‐CHANNEL FAST SWITCH FET IC 10 BIT DAC 8CH IC 8 BIT ADC INDUCTOR 10uH 1.3A INDUCTOR 10uH 1.3A INDUCTOR 10uH 1.3A JACK POWER 2.1mm OCTAL BUFFER DQFN package OCTAL BUFFER DQFN package OCTAL BUFFER DQFN package OCTAL BUFFER DQFN package OCTAL BUFFER DQFN package OCTAL BUFFER DQFN package Quad Output Interline CCD IS230D‐97134‐75M‐R29‐L14‐A Analog Devices Analog Devices Analog Devices Analog Devices Analog Devices Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic SAMTEC SAMTEC CTS HP HP HP HP HP HP HP HP HP HP HP TI TI MURATA ERIE ZETEX ZETEX ZETEX ZETEX ZETEX ZETEX ZETEX ZETEX ZETEX ZETEX ZETEX LINEAR A/D Taiyo Taiyo Taiyo CUI On‐Semi On‐Semi On‐Semi On‐Semi On‐Semi On‐Semi ANDON ADA4800 U18 ADA4800 U17 ADA4800 U27 AD9928 U37 AD9928 U1 PCC2321CT‐ND C145 PCC2321CT‐ND C144 PCC2321CT‐ND C114 PCC2321CT‐ND C167 PCC2321CT‐ND C108 ECJ‐1VB0J475K C160 ECJ‐1VB0J475K C147 ECJ‐1VB0J475K C174 ECJ‐1VB0J475K C8 ECJ‐1VB0J475K C1 ECJ‐1VB0J475K C161 ECJ‐1VB0J475K C172 ECJ‐1VB0J475K C37 ECJ‐1VB0J475K C25 ECJ‐1VB0J475K C6 ASP‐122952‐01 J1 ASP‐122952‐01 J4 CB3LV‐3C‐40MHz U21 HSMS‐2805‐T31 CR16 HSMS‐2805‐T31 CR14 HSMS‐2805‐T31 CR17 HSMS‐2805‐T31 CR18 HSMS‐2805‐T31 CR15 HSMS‐2805‐T31 CR6 HSMS‐2805‐T31 CR2 HSMS‐2805‐T31 CR5 HSMS‐2805‐T31 CR4 HSMS‐2805‐T31 CR3 HSMS‐2805‐T31 CR13 SN74LVC2G04DBVR U20 SN74LVC2G04DBVR U41 BLM18AG601SN1D BD1 ZXMD63C03X U42 ZXMD63C03X U12 ZXMD63C03X U13 ZXMD63C03X U14 ZXMD63C03X U15 ZXMD63C03X U16 ZXMD63C03X U2 ZXMD63C03X U3 ZXMD63C03X U4 ZXMD63C03X U5 ZXMD63C03X U6 LTC1665CGN U38 ADC081S021 U35 NRS5020T100MMGJ L3 NRS5020T100MMGJ L2 NRS5020T100MMGJ L1 PJ‐002A J2 74LCX541BQX U11 74LCX541BQX U10 74LCX541BQX U9 74LCX541BQX U30 74LCX541BQX U28 74LCX541BQX U29 IS230D‐97134‐75M‐R29‐L14‐U23 LFCSP_6 LFCSP_6 LFCSP_6 CSPBGA128_.65mm_9x9 CSPBGA128_.65mm_9x9 805 805 805 805 805 603 603 603 603 603 603 603 603 603 603 ASP122952 ASP122952 F4100 SOT143 SOT143 SOT143 SOT143 SOT143 SOT143 SOT143 SOT143 SOT143 SOT143 SOT143 SOT23‐6 SOT23‐6 603 MO‐187 MO‐187 MO‐187 MO‐187 MO‐187 MO‐187 MO‐187 MO‐187 MO‐187 MO‐187 MO‐187 SSOP‐16_150 SOT23‐6 NRS5020 NRS5020 NRS5020 PJ‐002A‐SMT DQFN_20 DQFN_20 DQFN_20 DQFN_20 DQFN_20 DQFN_20 KAI‐08050W ADA4800 ADA4800 ADA4800 AD9928 AD9928 C4.7UF_0805_25V20 C4.7UF_0805_25V20 C4.7UF_0805_25V20 C4.7UF_0805_25V20 C4.7UF_0805_25V20 C4.7UF_0603_6V3_10 C4.7UF_0603_6V3_10 C4.7UF_0603_6V3_10 C4.7UF_0603_6V3_10 C4.7UF_0603_6V3_10 C4.7UF_0603_6V3_10 C4.7UF_0603_6V3_10 C4.7UF_0603_6V3_10 C4.7UF_0603_6V3_10 C4.7UF_0603_6V3_10 ASP‐122952‐01 ASP‐122952‐01 CB3‐3C‐40.0000 HSMS2805 HSMS2805 HSMS2805 HSMS2805 HSMS2805 HSMS2805 HSMS2805 HSMS2805 HSMS2805 HSMS2805 HSMS2805 SN74LVC2G04 SN74LVC2G04 BLM18AG601SN1D ZXMD63C03X ZXMD63C03X ZXMD63C03X ZXMD63C03X ZXMD63C03X ZXMD63C03X ZXMD63C03X ZXMD63C03X ZXMD63C03X ZXMD63C03X ZXMD63C03X LTC1665C ADC081 NRS5020T100MMGJ NRS5020T100MMGJ NRS5020T100MMGJ PJ‐002A‐SMT 74LCX541BQX 74LCX541BQX 74LCX541BQX 74LCX541BQX 74LCX541BQX 74LCX541BQX KAI‐08050 0.54 0.54 0.54 15.46 15.46 0.49 0.49 0.49 0.49 0.49 0.19 0.19 0.19 0.19 0.19 0.19 0.19 0.19 0.19 0.19 8.04 8.04 3.75 0.31 0.31 0.31 5.93 5.93 0.1 0.1 0.1 0.1 0.1 0.04 0.04 0.04 0.04 0.04 0.04 0.04 0.04 0.04 0.04 4.52 4.52 1.17 0 0 0 0 0.43 0.43 0.06 0 0 0 0 0 0 0 0 0 0 0 6.38 2.28 0.072 0.072 0.072 0.7 0.78 0.78 0.78 0.78 0.78 0.78 $35 0 0 0.12 0.12 0.03 0 0 0 0 0 0 0 0 0 0 0 3.2 0.94 0.16 0.16 0.16 0.25 0.35 0.35 0.35 0.35 0.35 0.35 $25 Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top LT1521CMS8‐3.3‐ND REG LDO 3.3V 300mA **LT1965EMS8E#PBF‐ND REGULATOR LOW DROPOUT NEG LT1964ES5‐SD#TRMPBFCT‐NREGULATOR LOW DROPOUT NEG with SHUTDOWN LT1964ES5‐SD#TRMPBFCT‐NREGULATOR LOW DROPOUT NEG with SHUTDOWN 541‐0.0GCT‐ND RESISTOR 0 541‐0.0GCT‐ND RESISTOR 0 541‐0.0GCT‐ND RESISTOR 0 RESISTOR 100 1/16W 1% RESISTOR 100 1/16W 1% RESISTOR 100 1/16W 1% RESISTOR 100 1/16W 1% RESISTOR 100 1/16W 1% RESISTOR 100 1/16W 1% RESISTOR 100 1/16W 1% RESISTOR 100 1/16W 1% RESISTOR 100 1/16W 1% RESISTOR 100 1/16W 1% RESISTOR 100 1/16W 1% RESISTOR 100 1/16W 1% RESISTOR 100 1/16W 1% RESISTOR 100 1/16W 1% RESISTOR 100 1/16W 1% RESISTOR 100 1/16W 1% RESISTOR 100K 1/16W 1% RESISTOR 100K 1/16W 1% P10.0KLCT‐ND RESISTOR 10K 1/16W 1% P10.0KLCT‐ND RESISTOR 10K 1/16W 1% P10.0KLCT‐ND RESISTOR 10K 1/16W 1% P10.0KLCT‐ND RESISTOR 10K 1/16W 1% P10.0KLCT‐ND RESISTOR 10K 1/16W 1% P10.0KLCT‐ND RESISTOR 10K 1/16W 1% P10.0KLCT‐ND RESISTOR 10K 1/16W 1% P15KGCT‐ND RESISTOR 15.0K 1/16W 1 P15KGCT‐ND RESISTOR 15.0K 1/16W 1 P15KGCT‐ND RESISTOR 15.0K 1/16W 1 P15KGCT‐ND RESISTOR 15.0K 1/16W 1 P15KGCT‐ND RESISTOR 15.0K 1/16W 1 P15KGCT‐ND RESISTOR 15.0K 1/16W 1 P15KGCT‐ND RESISTOR 15.0K 1/16W 1 P15KGCT‐ND RESISTOR 16.5K 1/16W 1% 541‐162KHCT‐ND RESISTOR 162K 1/16W 1% RESISTOR 17.4K 1/16W 1% RESISTOR 200K 1/16W 1% RESISTOR 200K 1/16W 1% RESISTOR 200K 1/16W 1% RESISTOR 200K 1/16W 1% RESISTOR 200K 1/16W 1% RESISTOR 200K 1/16W 1% RESISTOR 200K 1/16W 1% RESISTOR 200K 1/16W 1% RESISTOR 200K 1/16W 1% RESISTOR 200K 1/16W 1% RESISTOR 200K 1/16W 1% RESISTOR 200K 1/16W 1% RESISTOR 200K 1/16W 1% RESISTOR 200K 1/16W 1% RESISTOR 200K 1/16W 1% RESISTOR 200K 1/16W 1% RESISTOR 200K 1/16W 1% RESISTOR 200K 1/16W 1% RESISTOR 200K 1/16W 1% LINEAR LINEAR LINEAR LINEAR DALE DALE DALE DALE DALE DALE DALE DALE DALE DALE DALE DALE DALE DALE DALE DALE DALE DALE DALE DALE DALE DALE DALE DALE DALE DALE DALE DALE Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic DALE DALE DALE DALE DALE DALE DALE DALE DALE DALE DALE DALE DALE DALE DALE DALE DALE DALE DALE DALE DALE DALE LT1521CMS8‐3.3 LT1965EMS8E#PBF LT1964ES5‐SD LT1964ES5‐SD CRCW06030000Z0EA CRCW06030000Z0EA CRCW06030000Z0EA CRCW06031000FT CRCW06031000FT CRCW06031000FT CRCW06031000FT CRCW06031000FT CRCW06031000FT CRCW06031000FT CRCW06031000FT CRCW06031000FT CRCW06031000FT CRCW06031000FT CRCW06031000FT CRCW06031000FT CRCW06031000FT CRCW06031000FT CRCW06031000FT CRCW06031003FT CRCW06031003FT CRCW060310K0FKEA CRCW060310K0FKEA CRCW060310K0FKEA CRCW060310K0FKEA CRCW060310K0FKEA CRCW060310K0FKEA CRCW060310K0FKEA ERJ‐3GEYJ153V ERJ‐3GEYJ153V ERJ‐3GEYJ153V ERJ‐3GEYJ153V ERJ‐3GEYJ153V ERJ‐3GEYJ153V ERJ‐3GEYJ153V CRCW06031652FT CRCW0603162KFKEA CRCW06031742FT CRCW06032003FT CRCW06032003FT CRCW06032003FT CRCW06032003FT CRCW06032003FT CRCW06032003FT CRCW06032003FT CRCW06032003FT CRCW06032003FT CRCW06032003FT CRCW06032003FT CRCW06032003FT CRCW06032003FT CRCW06032003FT CRCW06032003FT CRCW06032003FT CRCW06032003FT CRCW06032003FT CRCW06032003FT U39 U7 U19 U24 R89 R87 R63 R26 R28 R29 R37 R30 R31 R32 R33 R4 R2 R6 R5 R8 R7 R10 R9 R74 R72 R65 R46 R45 R73 R64 R62 R84 R90 R91 R55 R75 R88 R47 R60 R67 R14 R59 R54 R13 R38 R58 R12 R52 R40 R22 R17 R19 R20 R18 R21 R23 R16 R39 R66 R15 R24 MSOP‐8 MSOP‐8‐PWRPAD SOT23‐5 SOT23‐5 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 LT1521‐3.3 LT1965EMS8E LT1964ES5‐SD LT1964ES5‐SD R0_0603 R0_0603 R0_0603 R1000_0603 R1000_0603 R1000_0603 R1000_0603 R1000_0603 R1000_0603 R1000_0603 R1000_0603 R1000_0603 R1000_0603 R1000_0603 R1000_0603 R1000_0603 R1000_0603 R1000_0603 R1000_0603 R1003_0603 R1003_0603 R1002_0603 R1002_0603 R1002_0603 R1002_0603 R1002_0603 R1002_0603 R1002_0603 R1502_0603 R1502_0603 R1502_0603 R1502_0603 R1502_0603 R1502_0603 R1502_0603 R1652_0603 R1623_0603 R1742_0603 R2003_0603 R2003_0603 R2003_0603 R2003_0603 R2003_0603 R2003_0603 R2003_0603 R2003_0603 R2003_0603 R2003_0603 R2003_0603 R2003_0603 R2003_0603 R2003_0603 R2003_0603 R2003_0603 R2003_0603 R2003_0603 R2003_0603 2.38 3.25 3.25 3.25 0.07 0.07 0.07 1.01 1.43 1.43 1.43 0.02 0.02 0.02 0.047 0.009 0.047 0.047 0.047 0.047 0.07 0.07 0.07 0.07 0.07 0.07 0.07 0.07 0.08 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0.009 0.009 0.009 0.009 0.014 0.014 0.014 0.014 0.014 0.014 0.014 0.014 0.02 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top RESISTOR 200K 1/16W 1% RESISTOR 200K 1/16W 1% 311‐196KHRTR‐ND RESISTOR 196K 1/16W 1% RESISTOR 200K 1/16W 1% RESISTOR 200K 1/16W 1% RESISTOR 200K 1/16W 1% RESISTOR 200K 1/16W 1% RESISTOR 200K 1/16W 1% RESISTOR 200K 1/16W 1% RESISTOR 200K 1/16W 1% RESISTOR 200K 1/16W 1% RESISTOR 200K 1/16W 1% RESISTOR 200K 1/16W 1% 541‐220GCT‐ND RESISTOR 220 1/16W 5% 541‐220GCT‐ND RESISTOR 220 1/16W 5% 541‐220GCT‐ND RESISTOR 220 1/16W 5% 541‐220GCT‐ND RESISTOR 220 1/16W 5% 541‐23.2KHCT‐ND RESISTOR 23.2K 1/16W 1% RESISTOR 24.9K 1/16W 1% P27KGCT‐ND RESISTOR 27K ohm 1/16W 1% P27KGCT‐ND RESISTOR 27K ohm 1/16W 1% 541‐422KHCT‐ND RESISTOR 309K 1/16W 1% RESISTOR 31.6K ohm 1/16W 1% RESISTOR 39.2K 1/10W 1% 541‐49.9KHCT‐ND RESISTOR 49.9K 1/16W 1% 541‐49.9KHCT‐ND RESISTOR 49.9K 1/16W 1% 541‐49.9KHCT‐ND RESISTOR 49.9K 1/16W 1% 541‐49.9KHCT‐ND RESISTOR 49.9K 1/16W 1% 541‐49.9KHCT‐ND RESISTOR 49.9K 1/16W 1% 311‐63.4KHRTR‐ND RESISTOR 63.4K 1/16W 1% RESISTOR 75.0K 1/16W 1% RESISTOR 9.09K 1/16W 1% RESISTOR 93.1K 1/16W 1% P97.6KLCT‐ND RESISTOR 95.3K 1/16W 1% MBRM120ET3GOSCT‐ND SCHOTTKY BARRIER RECTIFIER 1A 20V MBRM120ET3GOSCT‐ND SCHOTTKY BARRIER RECTIFIER 1A 20V MBRM120ET3GOSCT‐ND SCHOTTKY BARRIER RECTIFIER 1A 20V MBRM120ET3GOSCT‐ND SCHOTTKY BARRIER RECTIFIER 1A 20V BAT54‐04E6327INCT‐ND SCHOTTKY DUAL SERIES BAT54‐04E6327INCT‐ND SCHOTTKY DUAL SERIES BAT54‐04E6327INCT‐ND SCHOTTKY DUAL SERIES BAT54‐04E6327INCT‐ND SCHOTTKY DUAL SERIES BAT54‐04E6327INCT‐ND SCHOTTKY DUAL SERIES BAT54‐04E6327INCT‐ND SCHOTTKY DUAL SERIES BAT54‐04E6327INCT‐ND SCHOTTKY DUAL SERIES BAT54‐04E6327INCT‐ND SCHOTTKY DUAL SERIES BAT54‐04E6327INCT‐ND SCHOTTKY DUAL SERIES BAT54‐04E6327INCT‐ND SCHOTTKY DUAL SERIES LTM8022EV#PFB‐ND Step Down uModule Regulator LTM8022EV#PFB‐ND Step Down uModule Regulator NC7SZ08M5XCT‐ND TINY AND GATE BC847BVNDICT‐ND TRANSISTOR DUAL DIGITAL PNP/NPN MMBT3904LT1XT1NCT‐ND TRANSISTOR G.P. NPN DALE DALE Yageo DALE DALE DALE DALE DALE DALE DALE DALE DALE DALE Vishay/DALE Vishay/DALE Vishay/DALE Vishay/DALE Vishay/DALE DALE ROHM ROHM Vishay/DALE Vishay/DALe DALE Vishay/DALE Vishay/DALE Vishay/DALE Vishay/DALE Vishay/DALE Yageo DALE DALE Vishay/DALE DALE ON Semi ON Semi ON Semi ON Semi Diodes Inc/Zetex Diodes Inc/Zetex Diodes Inc/Zetex Diodes Inc/Zetex Diodes Inc/Zetex Diodes Inc/Zetex Diodes Inc/Zetex Diodes Inc/Zetex Diodes Inc/Zetex Diodes Inc/Zetex LINEAR LINEAR FAIRCHILD Diodes Inc Infineon CRCW06032003FT CRCW06032003FT RC0603FR‐07196KL CRCW06032003FT CRCW06032003FT CRCW06032003FT CRCW06032003FT CRCW06032003FT CRCW06032003FT CRCW06032003FT CRCW06032003FT CRCW06032003FT CRCW06032003FT CRCW0603220RJNEA CRCW0603220RJNEA CRCW0603220RJNEA CRCW0603220RJNEA CRCW060323K2FKEA CRCW06032492FT ERJ‐3GEYJ273V ERJ‐3GEYJ273V CRCW0603309KFKEA CRCW060331K6FKEA CRCW06033922FT CRCW060349K9FKEA CRCW060349K9FKEA CRCW060349K9FKEA CRCW060349K9FKEA CRCW060349K9FKEA RC0603FR‐0763K4L CRCW06037502FT CRCW06039091FT CRCW060393K1FKEA CRCW06039532FT MBRM120E MBRM120E MBRM120E MBRM120E BAT54‐04 BAT54‐04 BAT54‐04 BAT54‐04 BAT54‐04 BAT54‐04 BAT54‐04 BAT54‐04 BAT54‐04 BAT54‐04 LTM8022 LTM8022 NC7SZ08M5X BC847BVN MMBT3904LT1 R68 R69 R61 R80 R51 R82 R77 R50 R79 R78 R81 R83 R76 R27 R25 R3 R1 R11 R85 R48 R42 R53 R34 R49 R41 R35 R36 R57 R56 R71 R86 R70 R43 R44 CR26 CR7 CR24 CR25 CR9 CR10 CR11 CR12 CR8 CR19 CR20 CR21 CR22 CR23 U25 U40 U36 Q1 Q2 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 CASE457 CASE457 CASE457 CASE457 SOT23 SOT23 SOT23 SOT23 SOT23 SOT23 SOT23 SOT23 SOT23 SOT23 LTM8022 LTM8022 SOT23‐5 SOT563 SOT23 R2003_0603 R2003_0603 R2003_0603 R2003_0603 R2003_0603 R2003_0603 R2003_0603 R2003_0603 R2003_0603 R2003_0603 R2003_0603 R2003_0603 R2003_0603 R220_0603 R220_0603 R220_0603 R220_0603 R2322_0603 R2492_0603 R2702_0603 R2702_0603 R3093_0603 R3162_0603 R3922_0603 R4992_0603 R4992_0603 R4992_0603 R4992_0603 R4992_0603 R7152_0603 R7502_0603 R9091_0603 R9312_0603 R9532_0603 MBRM120E MBRM120E MBRM120E MBRM120E BAT54‐04 BAT54‐04 BAT54‐04 BAT54‐04 BAT54‐04 BAT54‐04 BAT54‐04 BAT54‐04 BAT54‐04 BAT54‐04 LTM8022 LTM8022 NC7SZ08 BC847BVN MMBT3904LT1 0 0 0 0 0 0 0 0 0 0 0 0 0 0.08 0.08 0.08 0.08 0.08 0 0 0 0 0 0 0 0 0 0 0 0 0 0.01 0.01 0.01 0.01 0.02 0.07 0.07 0.08 0.047 0.01 0.01 0 0.009 0.08 0.08 0.08 0.08 0.08 0.02 0.02 0.02 0.02 0.02 0 0 0.047 0.38 0.38 0.38 0.38 0.58 0.58 0.58 0.58 0.58 0.58 0.58 0.58 0.58 0.58 15 15 0.33 0.48 0.13 0 0 0.009 0.13 0.13 0.13 0.13 0.07 0.07 0.07 0.07 0.07 0.07 0.07 0.07 0.07 0.07 10 10 0.07 0.15 0.017 Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top Top