4-Channel, Simultaneous Sampling, High Speed, 12-Bit ADC AD7864 High speed (1.65 μs) 12-bit ADC 4 simultaneously sampled inputs 4 track-and-hold amplifiers 0.35 μs track-and-hold acquisition time 1.65 μs conversion time per channel HW/SW select of channel sequence for conversion Single-supply operation Selection of input ranges ±10 V, ±5 V for AD7864-1 ±2.5 V for AD7864-3 0 V to 2.5 V, 0 V to 5 V for AD7864-2 High speed parallel interface that allows Interfacing to 3 V processors Low power, 90 mW typical Power saving mode, 20 μW typical Overvoltage protection on analog inputs APPLICATIONS AC motor control Uninterrupted power supplies Data acquisition systems Communications GENERAL DESCRIPTION The AD7864 is a high speed, low power, 4-channel, simultaneous sampling 12-bit analog-to-digital converter (ADC) that operates from a single 5 V supply. The part contains a 1.65 μs successive approximation ADC, four track-and-hold amplifiers, a 2.5 V reference, an on-chip clock oscillator, signal conditioning circuitry, and a high speed parallel interface. The input signals on four channels sample simultaneously preserving the relative phase information of the signals on the four analog inputs. The part accepts analog input ranges of ±10 V, ±5 V (AD7864-1), 0 V to +2.5 V, 0 V to +5 V (AD7864-2), and ±2.5 V (AD7864-3). Any subset of the four channels can be converted to maximize the throughput rate on the selected sequence. Select the channels to convert via hardware (channel select input pins) or software (programming the channel select register). A single conversion start signal (CONVST) simultaneously places all the track-and-holds into hold and initiates a conversion sequence for the selected channels. The EOC signal indicates the end of each individual conversion in the selected conversion sequence. The BUSY signal indicates the end of the conversion sequence. FUNCTIONAL BLOCK DIAGRAM AVDD VREF VIN1A VIN1B TRACK-AND-HOLD ×4 SIGNAL SCALING VIN2A VIN2B SIGNAL SCALING VIN3A VIN3B SIGNAL SCALING VIN4A VIN4B SIGNAL SCALING STBY 6kΩ DVDD VDRIVE 2.5V REFERENCE DGND AGND AD7864 RD MUX 12-BIT ADC OUTPUT DATA REGISTERS SOFTWARE LATCH FRSTDATA BUSY EOC VREF GND CONVERSION CONTROL LOGIC DB0 TO DB3 DB11 DB0 CS WR INT/EXT CLOCK SELECT INT CLOCK CONVST SL1 SL2 SL3 SL4 H/S CLKIN INT/EXT AGND AGND SEL CLK 01341-001 FEATURES Figure 1. Data is read from the part by a 12-bit parallel data bus using the standard CS and RD signals. Maximum throughput for a single channel is 500 kSPS. For all four channels, the maximum throughput is 130 kSPS for the read-during-conversion sequence operation. The throughput rate for the read-after-conversion sequence operation depends on the read cycle time of the processor. See the Timing and Control section. The AD7864 is available in a small (0.3 square inch area) 44-lead MQFP. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. Four track-and-hold amplifiers and a fast (1.65 μs) ADC for simultaneous sampling and conversion of any subset of the four channels. A single 5 V supply consuming only 90 mW typical, makes it ideal for low power and portable applications. See the Standby Mode Operation section. High speed parallel interface for easy connection to microprocessors, microcontrollers, and digital signal processors. Available in three versions with different analog input ranges. The AD7864-1 offers the standard industrial input ranges of ±10 V and ±5 V; the AD7864-3 offers the common signal processing input range of ±2.5 V; the AD7864-2 can be used in unipolar, 0 V to 2.5 V and 0 V to 5 V, applications. Features very tight aperture delay matching between the four input sample-and-hold amplifiers. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©1998–2009 Analog Devices, Inc. All rights reserved. AD7864 TABLE OF CONTENTS Features .............................................................................................. 1 Standby Mode Operation .......................................................... 18 Applications ....................................................................................... 1 Accessing the Output Data Registers....................................... 18 General Description ......................................................................... 1 Offset and Full-Scale Adjustment ................................................ 20 Functional Block Diagram .............................................................. 1 Positive Full-Scale Adjust .......................................................... 20 Product Highlights ........................................................................... 1 Negative Full-Scale Adjust......................................................... 20 Revision History ............................................................................... 2 Dynamic Specifications ................................................................. 21 Specifications..................................................................................... 3 Signal-to-Noise Ratio (SNR)..................................................... 21 Timing Characteristics ................................................................ 5 Effective Number of Bits ........................................................... 21 Absolute Maximum Ratings............................................................ 6 Intermodulation Distortion ...................................................... 21 ESD Caution .................................................................................. 6 AC Linearity Plots ...................................................................... 22 Pin Configuration and Function Descriptions ............................. 7 Measuring Aperture Jitter.......................................................... 22 Terminology ...................................................................................... 9 Microprocessor Interfacing ........................................................... 24 Theory of Operation ...................................................................... 11 AD7864 to ADSP-2100/ADSP-2101/ADSP-2102 Interface . 24 Converter Details........................................................................ 11 AD7864 to TMS320C5x Interface............................................ 24 Circuit Description ......................................................................... 13 AD7864 to MC68HC000 Interface .......................................... 24 Analog Input ............................................................................... 13 Vector Motor Control ................................................................ 25 Selecting a Conversion Sequence ................................................. 15 Multiple AD7864s in A System ................................................. 26 Timing and Control ................................................................... 15 Outline Dimensions ....................................................................... 27 Using an External Clock ............................................................ 17 Ordering Guide .......................................................................... 27 REVISION HISTORY 2/09—Rev. C to Rev. D 3/04—Rev. A to Rev. B. Change to t2 Parameter, Table 2 ...................................................... 5 Changes to Specifications and to Footnote 4 .................................2 Changes to Timing Characteristics Footnote 1 .............................4 Addition to Absolute Maximum Ratings .......................................5 Changes to Ordering Guide .............................................................5 Changes to Figure 7 .........................................................................11 Changes to Figure 11 ...................................................................... 13 Updated Outline Dimensions ....................................................... 19 Added Revision History ................................................................ 20 Updated Publication Code ............................................................ 20 2/09—Rev. B to Rev. C Updated Format .................................................................. Universal Changes to t5 Timing Parameter, Table 2....................................... 5 Changes to Figure 15 ...................................................................... 20 Changes to AD7864 to MC68HC000 Interface Section ............ 24 Changes to Figure 25 ...................................................................... 24 Updated Outline Dimensions ....................................................... 29 Changes to Ordering Guide .......................................................... 29 Rev. D | Page 2 of 28 AD7864 SPECIFICATIONS VDD = 5 V ± 5%, AGND = DGND = 0 V, VREF = internal, clock = internal; all specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter SAMPLE AND HOLD −3 dB Full Power Bandwidth Aperture Delay Aperture Jitter Aperture Delay Matching A Version 1 B Version Unit 3 20 50 4 3 20 50 4 MHz typ ns max ps max ns max fIN = 100.0 kHz, fS = 500 kSPS DYNAMIC PERFORMANCE 2 Signal-to-(Noise + Distortion) Ratio 3 @ 25°C TMIN to TMAX Total Harmonic Distortion3 Peak Harmonic or Spurious Noise3 Intermodulation Distortion3 Second-Order Terms Third-Order Terms Channel-to-Channel Isolation3 DC ACCURACY Resolution Relative Accuracy3 Differential Nonlinearity3 AD7864-1 Positive Gain Error3 Positive Gain Error Match3 Negative Gain Error3 Negative Gain Error Match3 Bipolar Zero Error Bipolar Zero Error Match AD7864-3 Positive Gain Error3 Positive Gain Error Match3 Negative Gain Error3 Negative Gain Error Match3 Bipolar Zero Error Bipolar Zero Error Match AD7864-2 Positive Gain Error3 Positive Gain Error Match3 Unipolar Offset Error Unipolar Offset Error Match ANALOG INPUTS AD7864-1 Input Voltage Range Input Resistance AD7864-3 Input Voltage Range Input Resistance Test Conditions/Comments 70 70 −80 −80 72 70 −80 −80 dB min dB min dB max dB max −80 −80 −80 −80 −80 −80 dB typ dB typ dB max 12 ±1 ±0.9 12 ±1/2 ±0.9 Bits LSB max LSB max ±3 +3 ±3 +3 ±4 +2 ±3 ±3 ±3 ±3 ±3 ±2 LSB max LSB max LSB max LSB max LSB max LSB max fa = 49 kHz, fb = 50 kHz ±3 2 ±3 2 ±3 2 LSB max LSB max LSB max LSB max LSB max LSB max ±3 3 ±3 2 LSB max LSB max LSB max LSB max ±5, ±10 9, 18 ±5, ±10 9, 18 V kΩ min ±2.5 4.5 ±2.5 4.5 V kΩ min Rev. D | Page 3 of 28 fIN = 50 kHz sine wave Any channel No missing codes AD7864 Parameter AD7864-2 Input Voltage Range Input Current (0 V to 2.5 V Option) Input Resistance (0 V to 5 V Option) REFERENCE INPUT/OUTPUT VREF In Input Voltage Range VREF In Input Capacitance 4 VREF Out Output Voltage VREF Out Error @ 25°C VREF Out Error TMIN to TMAX VREF Out Temperature Coefficient VREF Out Output Impedance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN4 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL DB11 to DB0 High Impedance Leakage Current Capacitance4 Output Coding AD7864-1, AD7864-3 AD7864-2 CONVERSION RATE Conversion Time Track-And-Hold Acquisition Time2, 3 Throughput Time POWER REQUIREMENTS VDD IDD Normal Mode Standby Mode Power Dissipation Normal Mode Standby Mode A Version 1 B Version Unit 0 to 2.5, 0 to 5 ±100 9 0 to 2.5, 0 to 5 ±100 9 V nA max kΩ min 2.375/2.625 10 2.5 ±10 ±20 25 6 2.375/2.625 10 2.5 ±10 ±20 25 6 VMIN/VMAX pF max V nom mV max mV max ppm/°C typ kΩ typ 2.5 V ± 5% 2.4 0.8 ±10 10 2.4 0.8 ±10 10 V min V max μA max pF max VDD = 5 V ± 5% VDD = 5 V ± 5% 4.0 0.4 4.0 0.4 V min V max ISOURCE = 400 μA ISINK = 1.6 mA ±10 10 ±10 10 μA max pF max Test Conditions/Comments See the Reference section Twos complement Straight (natural) binary 1.65 0.35 130 1.65 0.35 130 μs max μs max kSPS max 5 5 V nom 24 20 24 20 mA max μA max Typically 4 μA 120 100 120 100 mW max μW max Typically 90 mW Typically 20 μW 1 For one channel For all four channels ±5% for specified performance 5 μA typical, logic inputs = 0 V or VDD Temperature ranges are as follows: A, B versions: –40°C to +85°C. The A version is fully specified up to 105°C with a maximum sample rate of 450 kSPS and IDD maximum (normal mode) of 26 mA. 2 Performance is measured through the full channel (SHA and ADC). 3 See the Terminology section. 4 Sample tested at initial release to ensure compliance. Rev. D | Page 4 of 28 AD7864 TIMING CHARACTERISTICS VDRIVE = 5 V± 5%, AGND = DGND = 0 V, VREF = internal, clock = internal; all specifications TMIN to TMAX, unless otherwise noted. 1, 2 Table 2. Parameter tCONV tACQ tBUSY A, B Versions 1.65 13 2.6 0.34 No. of channels × (tCONV + t9) − t9 Unit μs max Clock cycles μs max μs max μs max Test Conditions/Comments Conversion time, internal clock Conversion time, external clock CLKIN = 5 MHz Acquisition time Selected number of channels multiplied by (tCONV + EOC pulse width)—EOC pulse width tWAKE-UP —External VREF 2 μs max STBY rising edge to CONVST rising edge tWAKE-UP —Internal VREF 3 6 ms max STBY rising edge to CONVST rising edge t1 35 ns min CONVST pulse width t2 70 ns max CONVST rising edge to BUSY rising edge READ OPERATION t3 0 ns min CS to RD setup time t4 0 ns min CS to RD hold time t5 35 40 35 ns min ns min ns max Read pulse width, VDRIVE = 5 V Read pulse width, VDRIVE = 3 V Data access time after falling edge of RD, VDRIVE = 5 V 40 ns max Data access time after falling edge of RD, VDRIVE = 3 V t6 4 t7 5 5 ns min Bus relinquish time after rising edge of RD t8 t9 30 10 75 ns max ns min ns min Time between consecutive reads EOC pulse width t10 180 70 ns max ns max RD rising edge to FRSTDATA edge (rising or falling) t11 15 ns max EOC falling edge to FRSTDATA falling delay t12 0 ns min EOC to RD delay 20 ns min WR pulse width t14 0 ns min CS to WR setup time t15 0 ns min WR to CS hold time t16 5 ns min Input data setup time of rising edge of WR t17 5 ns min Input data hold time WRITE OPERATION t13 1 Sample tested at initial release to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. See Figure 9, Figure 10,and Figure 11. 3 Refer to the Standby Mode Operation section. The maximum specification of 6 ms is valid when using a 0.1 μF decoupling capacitor on the VREF pin. 4 Measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.4 V. 5 These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part, and as such, are independent of external bus loading capacitances. 2 1.6mA TO OUTPUT 1.6V 400µA 01341-002 50pF Figure 2. Load Circuit for Access Time and Bus Relinquish Time Rev. D | Page 5 of 28 AD7864 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 3. Parameter AVDD to AGND DVDD to DGND AGND to DGND AVDD to DVDD Analog Input Voltage to AGND AD7864-1 (±10 V Input Range) AD7864-1 (±5 V Input Range) AD7864-3 AD7864-2 Reference Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to DGND VDRIVE to AGND VDRIVE to DGND Operating Temperature Range Commercial (A and B Versions) Storage Temperature Range Junction Temperature MQFP Package, Power Dissipation θJA Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) Rating −0.3 V to +7 V −0.3 V to +7 V −0.3 V to +0.3 V −0.3 V to +0.3 V ±20 V −7 V to +20 V −7 V to +20 V −1 V to +20 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to AVDD + 0.3 V −0.3 V to DVDD + 0.3 V ESD CAUTION −40°C to +85°C −65°C to +150°C 150°C 450 mW 95°C/W 215°C 220°C Rev. D | Page 6 of 28 AD7864 DB6 DVDD VDRIVE DGND DB5 DB4 DB3 DB2 DB1 DB0 EOC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 44 43 42 41 40 39 38 37 36 35 34 33 DB7 BUSY 1 PIN 1 FRSTDATA 2 32 DB8 CONVST 3 31 DB9 CS 4 30 DB10 29 DB11 RD 5 AD7864 WR 6 TOP VIEW (Not to Scale) SL1 7 28 CLKIN 27 INT/EXT CLK SL2 8 26 AGND SL3 9 25 AVDD SL4 10 24 VREF 23 VREF GND H/S SEL 11 01341-003 STBY VIN1A VIN1B VIN2A VIN2B AGND VIN3A VIN3B VIN4A VIN4B AGND 12 13 14 15 16 17 18 19 20 21 22 Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 Mnemonic BUSY Description Busy Output. The busy output is triggered high by the rising edge of CONVST and remains high until conversion is completed on all selected channels. First Data Output. FRSTDATA is a logic output which, when high, indicates that the output data register pointer is addressing Register 1—see the Accessing the Output Data Registers section. Convert Start Input. Logic input. A low-to-high transition on this input puts all track-and-holds into their hold mode and starts conversion on the selected channels. In addition, the state of the channel sequence selection is also latched on the rising edge of CONVST. 2 FRSTDATA 3 CONVST 4 CS Chip Select Input. Active low logic input. The device is selected when this input is active. 5 RD Read Input. Active low logic input that is used in conjunction with CS low to enable the data outputs. Ensure the WR pin is at logic high while performing a read operation. 6 WR 7 to 10 SL1 to SL4 Write Input. A rising edge on the WR input, with CS low and RD high, latches the logic state on DB0 to DB3 into the channel select register. Hardware Channel Select. Conversion sequence selection can also be made via the SL1 to SL4 pins if H/S SEL is Logic 0. The selection is latched on the rising edge of CONVST. See the Selecting a Conversion Sequence section. 11 H/S SEL 12 13 to 16 17 AGND VIN4x, VIN3x AGND 18 to 21 22 VIN2x, VIN1x STBY 23 VREFGND 24 VREF 25 26 AVDD AGND Hardware/Software Select Input. When this pin is at Logic 0, the AD7864 conversion sequence selection is controlled via the SL1 to SL4 input pins. When this pin is at Logic 1, the sequence is controlled via the channel select register. See the Selecting a Conversion Sequence section. Analog Ground. General analog ground. Connect this AGND pin to the AGND plane of the system. Analog Inputs. See the Analog Input section. Analog Ground. Analog ground reference for the attenuator circuitry. Connect this AGND pin to the AGND plane of the system. Analog Inputs. See the Analog Input section. Standby Mode Input. TTL-compatible input that is used to put the device into the power save or standby mode. The STBY input is high for normal operation and low for standby operation. Reference Ground. This is the ground reference for the on-chip reference buffer of the part. Connect the VREFGND pin to the AGND plane of the system. Reference Input/Output. This pin provides access to the internal reference (2.5 V ± 5%) and also allows the internal reference to be overdriven by an external reference source (2.5 V). Connect a 0.1 μF decoupling capacitor between this pin and AGND. Analog Positive Supply Voltage, 5.0 V ± 5%. Analog Ground. Analog ground reference for the DAC circuitry. Rev. D | Page 7 of 28 AD7864 Pin No. 27 INT/EXT CLK Mnemonic 28 CLKIN 29 to 34 DB11 to DB6 35 DVDD 36 VDRIVE 37 DGND 38, 39 40 to 43 DB5, DB4 DB3 to DB0 44 EOC Description Internal/External Clock Select Input. When this pin is at Logic 0, the AD7864 uses its internally generated master clock. When this pin is at Logic 1, the master clock is generated externally to the device. Conversion Clock Input. This is an externally applied clock that allows the user to control the conversion rate of the AD7864. Each conversion needs 14 clock cycles for the conversion to be completed and an EOC pulse to be generated. The clock should have a duty cycle that is no worse than 60/40. See the Using An External Clock section. Data Bit 11 is the MSB, followed by Data Bit 10 to Data Bit 6. Three-state TTL outputs. Output coding is twos complement for the AD7864-1 and AD7864-3. Output coding is straight (natural) binary for the AD7864-2. Positive Supply Voltage for Digital Section, 5.0 V ± 5%. Connect a 0.1 μF decoupling capacitor between this pin and AGND. Both DVDD and AVDD should be externally tied together. This pin provides the positive supply voltage for the output drivers (DB0 to DB11), BUSY, EOC, and FRSTDATA. It is normally tied to DVDD. Decouple VDRIVE with a 0.1 μF capacitor to improve performance when reading during the conversion sequence. To facilitate interfacing to 3 V processors and DSPs, the output data drivers can also be powered by a 3 V ± 10% supply. Digital Ground. This is the ground reference for digital circuitry. Connect this DGND pin to the AGND plane of the system at the AGND pin. Data Bit 5 to Data Bit 4. Three-state TTL outputs. Data Bit 3 to Data Bit 0. Bidirectional data pins. When a read operation takes place, these pins are three-state TTL outputs. The channel select register is programmed with the data on the DB0 to DB3 pins with standard CS and WR signals. DB0 represents Channel 1, and DB3 represents Channel 4. End-of-Conversion. Active low logic output indicating conversion status. The end of each conversion in a conversion sequence is indicated by a low-going pulse on this line. Rev. D | Page 8 of 28 AD7864 TERMINOLOGY Signal-to-(Noise + Distortion) Ratio This is the measured ratio of signal-to-(noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio depends on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB Thus, for a 12-bit converter, this is 74 dB. Channel-to-Channel Isolation Channel-to-channel isolation is a measure of the level of crosstalk between channels. It is measured by applying a fullscale 50 kHz sine wave signal to all nonselected input channels and determining how much that signal is attenuated in the selected channel. The figure given is the worst case across all four channels. Relative Accuracy Relative accuracy, or endpoint nonlinearity, is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of harmonics to the fundamental. For the AD7864, it is defined as V2 2 + V3 2 + V4 2 + V5 2 + V6 2 THD(dB) = 20 log V1 where V1 is the rms amplitude of the fundamental, and V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the fifth harmonics. Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, it is a noise peak. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3, and so on. Intermodulation terms are those for which neither m nor n are equal to zero. For example, second-order terms include (fa + fb) and (fa − fb), whereas third-order terms include (2 fa + fb), (2 fa − fb), (fa + 2 fb), and (fa − 2 fb). The AD7864 is tested using the CCIF standard, where two input frequencies near the top end of the input bandwidth are used. In this case, the second- and third-order terms are of different significance. The second-order terms are usually distanced in frequency from the original sine waves, whereas the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in decibels. Positive Full-Scale Error This is the deviation of the last code transition (01...110 to 01...111) from the ideal, 4 × VREF − 3/2 LSB (AD7864-1, ±10 V), or 2 × VREF − 3/2 LSB (AD7864-1, ±5 V range), or VREF − 3/2 LSB (AD7864-3, ±2.5 V range), after the bipolar offset error has been adjusted out. Positive Full-Scale Error (AD7864-2, 0 V to 2.5 V and 0 V to 5 V) This is the deviation of the last code transition (11...110 to 11...111) from the ideal 2 × VREF − 3/2 LSB (AD7864-2, 0 V to 5 V range) or VREF − 3/2 LSB (AD7864-2, 0 V to 2.5 V range), after the unipolar offset error has been adjusted out. Bipolar Zero Error (AD7864-1, ±10 V/±5 V, AD7864-3, ±2.5 V) This is the deviation of the midscale transition (all 0s to all 1s) from the ideal, AGND − 1/2 LSB. Unipolar Offset Error (AD7864-2, 0 V to 2.5 V and 0 V to 5 V) This is the deviation of the first code transition (00...000 to 00...001) from the ideal, AGND + 1/2 LSB. Negative Full-Scale Error (AD7864-1, ±10 V/±5 V, and AD7864-3, ±2.5 V) This is the deviation of the first code transition (10...000 to 10...001) from the ideal, −4 × VREF + 1/2 LSB (AD7864-1, ±10 V), −2 × VREF + 1/2 LSB (AD7864-1, ±5 V range) or −VREF + 1/2 LSB (AD7864-3, ±2.5 V range), after bipolar zero error has been adjusted out. Track-and-Hold Acquisition Time Track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within ±1/2 LSB, after the end of a conversion (the point at which the track-and-hold returns to track mode). It also applies to situations where there is a step input change on the input voltage applied to the selected VINxA/VINxB input of the AD7864. Rev. D | Page 9 of 28 AD7864 It means that the user must wait for the duration of the trackand-hold acquisition time after the end of conversion or after a step input change to VINxA/VINxB before starting another conversion to ensure that the part operates to specification. Rev. D | Page 10 of 28 AD7864 THEORY OF OPERATION CONVERTER DETAILS The AD7864 is a high speed, low power, 4-channel simultaneous sampling 12-bit ADC that operates from a single 5 V supply. The part contains a 1.65 μs successive approximation ADC, four track-and-hold amplifiers, an internal 2.5 V reference, and a high speed parallel interface. There are four analog inputs that can be simultaneously sampled, thus preserving the relative phase information of the signals on all four analog inputs. Thereafter, conversions are completed on the selected subset of the four channels. The part accepts an analog input range of ±10 V or ±5 V (AD7864-1), ±2.5 V (AD7864-3), and 0 V to +2.5 V or 0 V to +5 V (AD7864-2). Overvoltage protection on the analog inputs of the part allows the input voltage to go to ±20 V, (AD7864-1 ±10 V range), −7 V or +20 V (AD7864-1 ±5 V range), −1 V to +20 V (AD7864-2), and −7 V to +20 V (AD7864-3), without causing damage. The AD7864 has two operating modes: reading-between-conversions and readingafter-the-conversion sequence. These modes are discussed in more detail in the Timing and Control section. A conversion is initiated on the AD7864 by pulsing the CONVST input. On the rising edge of CONVST, all four on-chip trackand-holds are placed into hold simultaneously and the conversion sequence is started on all the selected channels. Channel selection is made via the SL1 to SL4 pins if H/S SEL is Logic 0 or via the channel select register if H/S SEL is Logic 1—see the Selecting a Conversion Sequence section. The channel select register is programmed via the bidirectional data lines (DB0 to DB3) and a standard write operation. The selected conversion sequence is latched on the rising edge of CONVST, therefore, changing a selection only takes effect once a new conversion sequence is initiated. The BUSY output signal is triggered high on the rising edge of CONVST and remains high for the duration of the conversion sequence. The conversion clock for the part is generated internally using a laser trimmed, clock oscillator circuit. There is also the option of using an external clock, by tying the INT/EXT CLK pin logic high, and applying an external clock to the CLKIN pin. However, the optimum throughput is obtained by using the internally generated clock—see the Using an External Clock section. The EOC signal indicates the end of each conversion in the conversion sequence. The BUSY signal indicates the end of the full conversion sequence, and at this time, all four track and holds return to tracking mode. The conversion results can be read either at the end of the full conversion sequence (indicated by BUSY going low), or as each result becomes available (indicated by EOC going low). Data is read from the part via a 12-bit parallel data bus with standard CS and RD signals—see the Timing and Control section. Conversion time for each channel of the AD7864 is 1.65 μs, and the track-and-hold acquisition time is 0.35 μs. To obtain optimum performance from the part, the read operation should not occur during a channel conversion or during the 100 ns prior to the next CONVST rising edge. This allows the part to operate at throughput rates up to 130 kHz for all four channels and achieve data sheet specifications. Track-and-Hold Amplifiers The track-and-hold amplifiers on the AD7864 allow the ADCs to accurately convert an input sine wave of full-scale amplitude to 12-bit accuracy. The input bandwidth of the track-and-hold is greater than the Nyquist rate of the ADC even when the ADC is operated at its maximum throughput rate of 500 kSPS (that is, the track-and-hold can handle input frequencies in excess of 250 kHz). The track-and-hold amplifiers acquire input signals to 12-bit accuracy in less than 350 ns. The operation of the track-andholds are essentially transparent to the user. The four track-andhold amplifiers sample their respective input channels simultaneously, on the rising edge of CONVST. The aperture time for the track-and-holds (that is, the delay time between the external CONVST signal and the track-and-hold actually going into hold) is typically 15 ns and, more importantly, is well matched across the four track-and-holds on one device as well as being well matched from device to device. This allows the relative phase information between different input channels to be accurately preserved. It also allows multiple AD7864s to sample more than four channels simultaneously. At the end of a conversion sequence, the part returns to its tracking mode. The acquisition time of the track-and-hold amplifiers begin at this point. Reference The AD7864 contains a single reference pin, labeled VREF. The VREF pin provides access to the 2.5 V reference within the part, or it serves as the reference source for the part by connecting VREF to an external 2.5 V reference. The part is specified with a 2.5 V reference voltage. Errors in the reference source result in gain errors in the transfer function of the AD7864 and adds to the specified full-scale errors on the part. On the AD7864-1 and AD7864-3, it also results in an offset error injected in the attenuator stage; see Figure 4 and Figure 6. The AD7864 contains an on-chip 2.5 V reference. To use this reference as the reference source for the AD7864, simply connect a 0.1 μF disk ceramic capacitor from the VREF pin to AGND. The voltage that appears at this pin is internally buffered before being applied to the ADC. If this reference is used externally to the AD7864, it should be buffered because the part has a FET switch in series with the reference output resulting in a 6 kΩ Rev. D | Page 11 of 28 AD7864 nominal source impedance for this output. The tolerance on the internal reference is ±10 mV at 25°C with a typical temperature coefficient of 25 ppm/°C and a maximum error overtemperature of ±20 mV. If the application requires a reference with a tighter tolerance or the AD7864 needs to be used with a system reference, the user has the option of connecting an external reference to this VREF pin. The external reference effectively overdrives the internal reference and thus provides the reference source for the ADC. The reference input is buffered before being applied to the ADC with the maximum input current of ±100 μA. Suitable reference sources for the AD7864 include the AD680, AD780, REF192, and REF43 precision 2.5 V references. Rev. D | Page 12 of 28 AD7864 CIRCUIT DESCRIPTION ANALOG INPUT Table 5. Ideal Input/Output Code Table for the AD7864-1 The AD7864 is offered in three models: the AD7864-1, where each input can be configured for ±10 V or a ±5 V input voltage range; the AD7864-3, which handles the input voltage range of ±2.5 V; and the AD7864-2, where each input can be configured to have a 0 V to +2.5 V or 0 V to +5 V input voltage range. Analog Input1 +FSR/2 − 3/2 LSB2 +FSR/2 − 5/2 LSB +FSR/2 − 7/2 LSB AGND + 3/2 LSB AGND + 1/2 LSB AGND − 1/2 LSB AGND − 3/2 LSB −FSR/2 + 5/2 LSB −FSR/2 + 3/2 LSB −FSR/2 + 1/2 LSB AD7864-1 Figure 4 shows the analog input section of the AD7864-1. Each input can be configured for ±5 V or ±10 V operation on the AD7864-1. For ±5 V (AD7864-1) operation, the VINxA and VINxB inputs are tied together and the input voltage is applied to both. For ±10 V (AD7864-1) operation, the VINxB input is tied to AGND and the input voltage is applied to the VINxA input. The VINxA and VINxB inputs are symmetrical and fully interchangeable. Thus for ease of printed circuit board (PCB) layout on the ±10 V range, the input voltage may be applied to the VINxB input while the VINxA input is tied to AGND. 2.5V REFERENCE VREF R1 VIN1A TO ADC REFERENCE CIRCUITRY R2 R3 T/H VIN1B TO INTERNAL COMPARATOR 01341-004 R4 AGND 1 FSR is full-scale range and is 20 V for the ±10 V range and +10 V for the ±5 V range, with VREF = 2.5 V. 2 1 LSB = FSR/4096 = 4.883 mV (±10 V for the AD7864-1) and 2.441 mV (±5 V for the AD7864-1) with VREF = 2.5 V. AD7864-2 Figure 5 shows the analog input section of the AD7864-2. Each input can be configured for 0 V to 5 V operation or 0 V to 2.5 V operation. For 0 V to 5 V operation, the VINxB input is tied to AGND and the input voltage is applied to the VINxA input. For 0 V to 2.5 V operation, the VINxA and VINxB inputs are tied together and the input voltage is applied to both. The VINxA and VINxB inputs are symmetrical and fully interchangeable. Thus for ease of PCB layout on the 0 V to 5 V range, the input voltage may be applied to the VINxB input while the VINxA input is tied to AGND. AD7864-1 6kΩ Digital Output Code Transition 011...110 to 011...111 011...101 to 011...110 011...100 to 011...101 000...001 to 000...010 000...000 to 000...001 111...111 to 000...000 111...110 to 111...111 100...010 to 100...011 100...001 to 100...010 100...000 to 100...001 Figure 4. AD7864-1 Analog Input Structure For the AD7864-2, R1 = 6 kΩ and R2 = 6 kΩ. The designed code transitions occur on successive integer least significant bit values. Output coding is straight (natural) binary with 1 LSB = FSR/4096 = 2.5 V/4096 = 0.61 mV, and 5 V/4096 = 1.22 mV, for the 0 V to 2.5 V and 0 V to 5 V options, respectively. Table 6 shows the ideal input and output transfer function for the AD7864-2. For the AD7864-1, R1 = 6 kΩ, R2 = 24 kΩ, R3 = 24 kΩ, and R4 = 12 kΩ. The resistor input stage is followed by the high input impedance stage of the track-and-hold amplifier. AD7864-2 The designed code transitions take place midway between successive integer least significant bit values (that is, 1/2 LSB, 3/2 LSB, 5/2 LSB, and so forth). Least significant bit size is given by the formula 1 LSB = FSR/4096. For the ±5 V range, 1 LSB = 10 V/4096 = 2.44 mV. For the ±10 V range, 1 LSB = 20 V/4096 = 4.88 mV. Output coding is twos complement binary with 1 LSB = FSR/4096. The ideal input/output transfer function for the AD7864-1 is shown in Table 5. 6kΩ 2.5V REFERENCE VREF TO ADC REFERENCE CIRCUITRY VIN1A R2 T/H TO INTERNAL COMPARATOR 01341-005 VIN1B R1 Figure 5. AD7864-2 Analog Input Structure Rev. D | Page 13 of 28 AD7864 The designed code transitions take place midway between successive integer least significant bit values (that is, 1/2 LSB, 3/2 LSB, 5/2 LSB, and so on). Least significant bit size is given by the formula 1 LSB = FSR/4096. Output coding is twos complement binary with 1 LSB = FSR/4096 = 5 V/4096 = 1.22 mV. The ideal input/ output transfer function for the AD7864-3 is shown in Table 7. Table 6. Ideal Input/Output Code Table for the AD7864-2 Analog Input1 +FSR − 3/2 LSB2 +FSR − 5/2 LSB +FSR − 7/2 LSB AGND + 5/2 LSB AGND + 3/2 LSB AGND + 1/2 LSB Digital Output Code Transition 111...110 to 111...111 111...101 to 111...110 111...100 to 111...101 000...010 to 000...011 000...001 to 000...010 000...000 to 000...001 Table 7. Ideal Input/Output Code Table for the AD7864-3 1 FSR is the full-scale range and is 0 V to 2.5 V and 0 V to 5 V for the AD7864-2 with VREF = 2.5 V. 2 1 LSB = FSR/4096 and is 0.61 mV (0 V to 2.5 V) and 1.22 mV (0 V to 5 V) for the AD7864-2 with VREF = 2.5 V. AD7864-3 Figure 6 shows the analog input section of the AD7864-3. The analog input range is ±2.5 V on the VIN1A input. The VIN1B input can be left unconnected, but if it is connected to a potential, that potential must be AGND. AD7864-3 6kΩ 2.5V REFERENCE Analog Input1 +FSR/2 − 3/2 LSB2 +FSR/2 − 5/2 LSB +FSR/2 − 7/2 LSB AGND + 3/2 LSB AGND + 1/2 LSB AGND − 1/2 LSB AGND − 3/2 LSB −FSR/2 + 5/2 LSB −FSR/2 + 3/2 LSB −FSR/2 + 1/2 LSB 1 2 VREF FSR is the full-scale range and is 5 V, with VREF = 2.5 V. 1 LSB = FSR/4096 = 1.22 mV (±2.5 V − AD7864-3) with VREF = 2.5 V. TO ADC REFERENCE CIRCUITRY R1 VIN1A R2 T/H TO INTERNAL COMPARATOR 01341-006 VIN1B Digital Output Code Transition 011...110 to 011...111 011...101 to 011...110 011...100 to 011...101 000...001 to 000...010 000...000 to 000...001 111...111 to 000...000 111...110 to 111...111 100...010 to 100...011 100...001 to 100...010 100...000 to 100...001 Figure 6. AD7864-3 Analog Input Structure For the AD7864-3, R1 = 6 kΩ and R2 = 6 kΩ. As a result, drive the VIN1A input from a low impedance source. The resistor input stage is followed by the high input impedance stage of the trackand-hold amplifier. Rev. D | Page 14 of 28 AD7864 SELECTING A CONVERSION SEQUENCE Any subset of the four channels, VIN1 to VIN4, can be selected for conversion. The selected channels are converted in ascending order. For example, if the channel selection includes VIN4, VIN1, and VIN3, the conversion sequence is VIN1, VIN3, and then VIN4. The conversion sequence selection can be made either by using the hardware channel select input pins (SL1 through SL4) or by programming the channel select register. A logic high on a hardware channel select pin (or Logic 1 in the channel select register) when CONVST goes logic high marks the associated analog input channel for inclusion in the conversion sequence. Figure 7 shows the arrangement used. The H/S SEL controls a multiplexer that selects the source of the conversion sequence information, that is, from the hardware channel select pins (SL1 to SL4) or from the channel selection register. When a conversion begins, the output from the multiplexer is latched until the end of the conversion sequence. The data bus bits, DB0 to DB3, (DB0 representing Channel 1 through DB3 representing Channel 4) are bidirectional and become inputs to the channel select register when RD is logic high and CS and WR are logic low. The logic state on DB0 to DB3 is latched into the channel select register when WR goes logic high. TIMING AND CONTROL Reading Between Each Conversion in the Conversion Sequence Figure 9 shows the timing and control sequence required to obtain the optimum throughput rate from the AD7864. To obtain the optimum throughput from the AD7864, the user must read the result of each conversion as it becomes available. The timing diagram in Figure 9 shows a read operation each time the EOC signal goes logic low. The timing in Figure 9 shows a conversion on all four analog channels (SL1 to SL4 = 1, see the Selecting a Conversion Sequence section), thus there are four EOC pulses and four read operations to access the result of each of the four conversions. A conversion is initiated on the rising edge of CONVST. This places all four track-and-holds into hold simultaneously. New data from this conversion sequence is available for the first channel selected (VIN1) 1.65 μs later. The conversion on each subsequent channel is completed at 1.65 μs intervals. The end of each conversion is indicated by the falling edge of the EOC signal. The BUSY output signal indicates the end-of-conversion for all selected channels (four in this case). H/S SEL HARDWARE CHANNEL SELECT PINS CHANNEL SELECT REGISTER WR LATCH SEQUENCER TRANSPARENT WHILE WAITING FOR CONVST. LATCHED ON THE RISING EDGE OF CONVST AND DURING A CONVERSION SEQUENCE. CS WR Figure 7. Channel Select Inputs and Registers RD t13 WR t15 t14 CS DATA t17 DATA IN Figure 8. Channel Selection via Software Control 01341-008 t16 01341-007 D3 D2 D1 D0 SL1 SL2 SL3 SL4 MULTIPLEXER DATA BUS SELECT INDIVIDUAL TRACK-AND-HOLDS FOR CONVERSION Data is read from the part via a 12-bit parallel data bus with standard CS and RD signals. The CS and RD inputs are internally gated to enable the conversion result onto the data bus. The data lines (DB0 to DB11) leave their high impedance state when both CS and RD are logic low. Therefore, CS can be permanently tied logic low and the RD signal used to access the conversion result. Because each conversion result is latched into its output data register prior to EOC going logic low, another option is to tie the EOC and RD pins together and use the rising edge of EOC to latch the conversion result. Although the AD7864 has some special features that permit reading during a conversion (such as a separate supply for the output data drivers, VDRIVE) for optimum performance it is recommended that the read operation be completed when EOC is logic low, that is, before the start of the next conversion. Although Figure 10 shows the read operation occurring during the EOC pulse, a read operation can occur at any time. Figure 10 shows a timing specification referred to as the quiet time. Quiet time is the amount of time that should be left after a read operation and before the next conversion is initiated. The quiet time depends heavily on data bus capacitance, but 50 ns to 100 ns is typical. The signal labeled FRSTDATA (first data-word) indicates to the user that the pointer associated with the output data registers is pointing to the first conversion result by going logic high. The pointer is reset to point to the first data location (that is, the first conversion result,) at the end of the first conversion (FRSTDATA Rev. D | Page 15 of 28 AD7864 logic high). The pointer is incremented to point to the next register (next conversion result) when that conversion result is available. Thus, FRSTDATA in Figure 9 is shown as going low just prior to the second EOC pulse. Repeated read operations during a conversion continue to access the data at the current pointer location until the pointer is incremented at the end of that conversion. Note that FRSTDATA has an indeterminate logic state after initial power-up. This means that for the first conversion sequence after power-up, the FRSTDATA logic output may already be logic high before the end of the first conversion (this condition is indicated by the dashed line in Figure 9). Also, the FRSTDATA logic output may already be high as a result of the previous read sequence, as is the case after the fourth read in Figure 9. The fourth read (rising edge of RD) resets the pointer to the first data location. Therefore, FRSTDATA is already high when the next conversion sequence initiates. See the Accessing the Output Data Registers section. Reading After the Conversion Sequence Figure 10 shows the same conversion sequence as Figure 9. In this case, however, the results of the four conversions (on VIN1 to VIN4) are read after all conversions have finished, that is, when BUSY goes logic low. The FRSTDATA signal goes logic high at the end of the first conversion just prior to EOC going logic low. As mentioned previously, FRSTDATA has an indeterminate state after initial power-up, therefore FRSTDATA may already be logic high. Unlike the case when reading between each conversion, the output data register pointer is incremented on the rising edge of RD because the next conversion result is available. This means FRSTDATA goes logic low after the first rising edge on RD. tACQ t1 CONVST BUSY tBUSY QUIET TIME t2 tCONV tCONV tCONV tCONV t8 EOC t11 t 10 FRSTDATA t12 RD t4 t3 t5 CS t7 t6 VIN1 DATA VIN2 VIN3 VIN4 100ns H/S SEL 01341-009 100ns SL1 TO SL4 Figure 9. Timing Diagram for Reading During Conversion t1 CONVST tBUSY QUIET TIME BUSY t2 EOC t8 RD t3 t4 CS t7 VIN1 DATA VIN2 VIN3 t10 VIN4 VIN1 t10 FRSTDATA Figure 10. Timing Diagram, Reading After the Conversion Sequence Rev. D | Page 16 of 28 01341-010 t6 AD7864 Successive read operations access the remaining conversion results in an ascending channel order. Each read operation increments the output data register pointer. The read operation that accesses the last conversion result causes the output data register pointer to be reset so that the next read operation accesses the first conversion result again. This is shown in Figure 10, wherein the fifth read after BUSY goes low accessing the result of the conversion on VIN1. Thus, the output data registers act as a circular buffer in which the conversion results are continually accessible. The FRSTDATA signal goes high when the first conversion result is available. Data is enabled onto the data bus (DB0 to DB11) using CS and RD. Both CS and RD have the same functionality as described in the previous section. There are no restrictions or performance implications associated with the position of the read operations after BUSY goes low. The only restriction is that there is minimum time between read operations. Notice that the quiet time must be allowed before the start of the next conversion. USING AN EXTERNAL CLOCK The logic input INT/EXT CLK allows the user to operate the AD7864 using the internal clock oscillator or an external clock. To achieve optimum performance on the AD7864, use the internal clock. The highest external clock frequency allowed is 5 MHz. This means a conversion time of 2.6 μs compared to 1.65 μs when using the internal clock. In some instances, however, it may be useful to use an external clock when high throughput rates are not required. For example, two or more AD7864s can be synchronized by using the same external clock for all devices. In this way, there is no latency between output logic signals like EOC due to differences in the frequency of the internal clock oscillators. Figure 11 shows how the various logic outputs are synchronized to the CLK signal. Each conversion requires 14 clocks. The output data register pointer is reset to point to the first register location on the falling edge of the 12th clock cycle of the first conversion in the conversion sequence— see the Accessing the Output Data Registers section. At this point, the logic output FRSTDATA goes logic high. The result of the first conversion transfers to the output data registers on the falling edge of the 13th clock cycle. The FRSTDATA signal is reset on the falling edge of the 13th clock cycle of the next conversion, that is, when the result of the second conversion is transferred to its output data register. As mentioned previously, the pointer is incremented by the rising edge of the RD signal if the result of the next conversion is available. The EOC signal goes logic low on the falling edge of the 13th clock cycle and is reset high again on the falling edge of the 14th clock cycle. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 13 14 CLK CONVST FRSTDATA EOC RD FIRST CONVERSION COMPLETE LAST CONVERSION COMPLETE 01341-011 BUSY Figure 11. Using an External Clock Rev. D | Page 17 of 28 AD7864 STANDBY MODE OPERATION 1.0 0.9 POWER-UP TIME (ms) 0.8 0.7 0.6 0.5 +105°C 0.4 +25°C 0.3 0.2 0.1 –40°C 0 0.0001 0.001 0.01 0.1 STANDBY TIME (Seconds) ACCESSING THE OUTPUT DATA REGISTERS There are four output data registers, one for each of the four possible conversion results from a conversion sequence. The result of the first conversion in a conversion sequence is placed in Register 1, the second result is placed in Register 2, and so forth. For example, if the conversion sequence VIN1, VIN3, and VIN4 is selected (see the Selecting a Conversion Sequence section), the results of the conversion on VIN1, VIN3, and VIN4 are placed in Register 1 to Register 3, respectively. The output data register pointer is reset to point to Register 1 at the end of the first conversion in the sequence, immediately prior to EOC going low. At this point, the logic output, FRSTDATA, goes logic high to indicate that the output data register pointer is addressing Register 1. When CS and RD are both logic low, the contents of the addressed register are enabled onto the data bus (DB0 to DB11). 100µs tBUSY tBUSY 7µs BUSY STBY 2µs Figure 13. Power-Down Between Conversion Sequences Rev. D | Page 18 of 28 01341-013 tWAKE-UP IDD = 20µA 10 Figure 12. Power-Up Time vs. Standby Time Using the On-Chip Reference (Decoupled with 0.1 μF Capacitor) Therefore, the average power consumption drops to 125/10 mW or 12.5 mW approximately. CONVST 1 01341-012 The AD7864 has a standby mode whereby the device can be placed in a low current consumption mode (5 μA typical). The AD7864 is placed in standby by bringing the Logic Input STBY low. The AD7864 can be powered up again for normal operation by bringing STBY logic high. The output data buffers remain operational while the AD7864 is in standby. This means the user can continue to access the conversion results while the AD7864 is in standby. This feature can be used to reduce the average power consumption in a system using low throughput rates. To reduce average power consumption, the AD7864 can be placed in standby at the end of each conversion sequence, that is, when BUSY goes low and is taken out of standby again prior to the start of the next conversion sequence. The time it takes the AD7864 to come out of standby is referred to as the wake-up time. The wake-up time limits the maximum throughput rate at which the AD7864 can be operated when powering down between conversion sequences. The AD7864 wakes up in approximately 2 μs when using an external reference. The wake-up time is also 2 μs when the standby time is less than 1 ms while using the internal reference. Figure 12 shows the wake-up time of the AD7864 for standby times greater than 1 ms. Note that when the AD7864 is left in standby for periods of time greater than 1 ms, the part requires more than 2 μs to wake up. For example, after initial power-up using the internal reference, the AD7864 requires 6 ms to power up. The maximum throughput rate that can be achieved when powering down between conversions is 1/(tBUSY + 2 μs) = 100 kSPS, approximately. When operating the AD7864 in a standby mode between conversions, the power savings can be significant. For example, with a throughput rate of 10 kSPS, the AD7864 is powered down (IDD = 5 μA) for 90 μs out of every 100 μs (see Figure 13). AD7864 When reading the output data registers after a conversion sequence, that is, when BUSY goes low, the register pointer is incremented on the rising edge of the RD signal, as shown in Figure 14. However, when reading the conversion results during the conversion sequence, the pointer is not incremented until a valid conversion result is in the register to be addressed. In this case, the pointer is incremented when the conversion has ended and the result has been transferred to the output data register. This happens immediately before EOC goes low, therefore EOC may be used to enable the register contents onto the data bus, as described in the Reading Between Each Conversion in the Conversion Sequence subsection within the Selecting a Conversion Sequence section. The pointer is reset to point to Register 1 on the rising edge of the RD signal when the last conversion result in the sequence is being read. In the example shown, this means that the pointer is set to Register 1 when the contents of Register 3 are read. FRSTDATA 2-BIT COUNTER POINTER* DECODE OUTPUT DATA REGISTERS OE NO. 1 (VIN1) OE NO. 2 (VIN3) OE NO. 3 (VIN4) OE NO. 4 NOT VALID RESET VDRIVE OUTPUT DRIVERS DB0 TO DB11 OE AD7864 RD Figure 14. Output Data Registers Rev. D | Page 19 of 28 01341-014 CS *THE POINTER IS NOT INCREMENTED BY A RISING EDGE ON RD UNTIL THE CONVERSION RESULT IS IN THE OUTPUT DATA REGISTER. THE POINTER IS RESET WHEN THE LAST CONVERSION RESULT IS READ. AD7864 OFFSET AND FULL-SCALE ADJUSTMENT Figure 15 shows a circuit that can be used to adjust the offset and full-scale errors on the AD7864 (VINxA on the AD7864-1 version is shown for example purposes only). Where adjustment is required, offset error must be adjusted before full-scale error. This is achieved by trimming the offset of the op amp driving the analog input of the AD7864 while the input voltage is 1/2 LSB below analog ground. The trim procedure is as follows: apply a voltage of −2.44 mV (−1/2 LSB) at V1 in Figure 15 and adjust the op amp offset voltage until the ADC output code flickers between 1111 1111 1111 and 0000 0000 0000. NEGATIVE FULL-SCALE ADJUST Apply a voltage of −9.9976 V (−FS + 1/2 LSB) at V1 and adjust R2 until the ADC output code flickers between 1000 0000 0000 and 1000 0000 0001. An alternative scheme for adjusting full-scale error in systems that use an external reference is to adjust the voltage at the VREF pin until the full-scale error for any of the channels is adjusted out. Good full-scale matching of the channels ensures small full-scale errors on the other channels. Adjust gain error at either the first code transition (ADC negative full scale) or the last code transition (ADC positive full scale). The trim procedures for both cases are as follows. POSITIVE FULL-SCALE ADJUST INPUT RANGE = ±10V V1 R1 10kΩ R2 500Ω VINxA R4 R3 10kΩ 10kΩ R5 10kΩ AD7864-1* AGND *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 15. Full-Scale Adjust Circuit Apply a voltage of 9.9927 V (FS − 3/2 LSB) at V1 and adjust R2 until the ADC output code flickers between 0111 1111 1110 and 0111 1111 1111. Rev. D | Page 20 of 28 01341-015 In most digital signal processing (DSP) applications, offset and full-scale errors have little or no effect on system performance. Offset error can always be eliminated in the analog domain by ac coupling. Full-scale error effect is linear and does not cause problems as long as the input signal is within the full dynamic range of the ADC. Invariably, some applications require that the input signal spans the full analog input dynamic range. In such applications, offset and full-scale error have to be adjusted to zero. AD7864 DYNAMIC SPECIFICATIONS graph is 72.6 dB. Note that the harmonics are taken into account when calculating the SNR. 0 –20 –30 –40 –60 –80 SNR = (6.02N + 1.76) dB (1) where N is the number of bits. Thus, for an ideal 12-bit converter, SNR = 74 dB. Figure 16 shows a histogram plot for 8192 conversions of a dc input using the AD7864 with a 5 V supply. The analog input was set at the center of a code. The figure shows that all the codes appear in the one output bin, indicating very good noise performance from the ADC. –90 –100 –110 0 50 100 150 200 250 FREQUENCY (kHz) 01341-017 SNR is the measured signal-to-noise ratio at the output of the ADC. The signal is the rms magnitude of the fundamental. Noise is the rms sum of all the nonfundamental signals up to half of the sampling frequency (fS/2) excluding dc. SNR depends on the number of quantization levels used in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-noise ratio for a sine wave input is given by Figure 17. FFT Plot EFFECTIVE NUMBER OF BITS The formula given in Equation 1 relates the SNR to the number of bits. Rewriting the formula, as in Equation 2, it is possible to get a measure of performance expressed in effective number of bits (N). N= SNR − 1.76 6.02 (2) The effective number of bits for a device can be calculated directly from its measured SNR. Figure 18 shows a typical plot of effective number of bits vs. frequency for an AD7864-2. 12 9000 11 EFFECTIVE NUMBERS OF BITS 8000 7000 6000 5000 4000 3000 2000 –40°C 10 +25°C 9 8 +105°C 7 6 5 1000 4 01341-016 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 ADC CODE 0 500 1000 1500 2000 FREQUENCY (kHz) 2500 3000 01341-018 COUNTS –50 –70 SIGNAL-TO-NOISE RATIO (SNR) 0 AD7864-1 @ 25°C 5V SUPPLY SAMPLING AT 499,712Hz INPUT FREQUENCY OF 99,857Hz 8192 SAMPLES TAKEN –10 (dB) The AD7864 is specified and 100% tested for dynamic performance specifications as well as traditional dc specifications, such as integral and differential nonlinearity. These ac specifications are required for signal processing applications such as phased array sonar, adaptive filters, and spectrum analysis. These applications require information on the effect of the ADC on the spectral content of the input signal. Thus, the parameters for which the AD7864 is specified include SNR, harmonic distortion, intermodulation distortion, and peak harmonics. These terms are discussed in more detail in the following sections. Figure 18. Effective Numbers of Bits vs. Frequency Figure 16. Histogram of 8192 Conversions of a DC Input The output spectrum from the ADC is evaluated by applying a sine wave signal of very low distortion to the analog input. A fast fourier transform (FFT) plot is generated from which the SNR data can be obtained. Figure 17 shows a typical 4096 point FFT plot of the AD7864 with an input signal of 99.9 kHz and a sampling frequency of 500 kHz. The SNR obtained from this INTERMODULATION DISTORTION With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3, and so forth. Intermodulation terms are those for which neither m nor n are equal to zero. For example, the second-order Rev. D | Page 21 of 28 AD7864 2.5 terms include (fa + fb) and (fa − fb), whereas the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). 0 AD7864-1 @ 25°C 5V SUPPLY SAMPLING AT 131072Hz INPUT FREQUENCY OF 48,928Hz AND 50,016Hz 4096 SAMPLES TAKEN –10 –20 –30 1.5 1.0 0 –0.5 –1.0 –1.5 –2.5 500 1000 1500 2000 2500 3000 3500 4000 ADC CODE Figure 21. Typical INL Plot MEASURING APERTURE JITTER A convenient way to measure aperture jitter is to use the relationship it is known to have with SNR (signal-to-noise plus distortion) given as follows: ⎛ ⎞ 1 ⎟ SNR JITTER = 20 × log 10 ⎜⎜ ⎟ ( ) × × × 2 π f σ IN ⎝ ⎠ –50 (3) where: SNRJITTER is the signal-to-noise due to the rms time jitter. σ is the rms time jitter. fIN is the sinusoidal input frequency (1 MHz in this case). –60 –70 –80 –90 0 10 20 30 40 FREQUENCY (kHz) 50 Equation 3 demonstrates that the signal-to-noise ratio due to jitter degrades significantly with frequency. At low input frequencies, the measured SNR performance of the AD7864 is indicative of noise performance due to quantization noise and system noise only (72 dB used as a typical figure in this example). 01341-019 –100 60 Figure 19. IMD Plot AC LINEARITY PLOTS The plots shown in Figure 20 and Figure 21 show typical DNL and INL plots for the AD7864. 3 Therefore, by measuring the overall SNR performance (including noise due to jitter, system, and quantization) of the AD7864, a good estimation of the jitter performance of the AD7864 can be calculated. 2 12 11 0 10 ENOB 1 –1 9 8 –2 7 0 500 1000 1500 2000 2500 3000 ADC CODE 3500 4000 6 5 900k Figure 20. Typical DNL Plot 950k 1.00M FREQUENCY (Hz) 1.05M Figure 22. ENOB of the AD7864 at 1 MHz Rev. D | Page 22 of 28 1.10M 01341-022 –3 01341-020 DNL (LSB) 0 01341-021 –2.0 –40 (dB) 0.5 INL (LSB) Using the CCIF standard where two input frequencies near the top end of the input bandwidth are used, the second- and thirdorder terms are of different significance. The second-order terms are usually distanced in frequency from the original sine waves, whereas the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in decibels. In this case, the input consists of two, equal amplitude, low distortion sine waves. Figure 19 shows a typical IMD plot for the AD7864. 2.0 AD7864 From Figure 22, the ENOB of the AD7864 at 1 MHz is approximately 11 bits. This is equivalent to 68 dB SNR. From Equation 3 70.2 dB = 20 × log10[1/(2 × π × 1 MHz × σ)] SNRTOTAL = SNRJITTER + SNRQUANT = 68 dB 68 dB = SNRJITTER + 72 dB (at 100 kHz) σ = 49 ps where σ is the rms jitter of the AD7864. SNRJITTER = 70.2 dB Rev. D | Page 23 of 28 AD7864 MICROPROCESSOR INTERFACING AD7864 TO ADSP-2100/ADSP-2101/ADSP-2102 INTERFACE requirements. The following instruction is used to read the conversion results from the AD7864: IN D,ADC where D is the data memory address and ADC is the AD7864 address. TMS320C5x Figure 23 shows an interface between the AD7864 and the ADSP-210x. The CONVST signal can be generated by the ADSP-210x or from some other external source. Figure 23 shows the CS being generated by a combination of the DMS signal and the address bus of the ADSP-210x. In this way, the AD7864 is mapped into the data memory space of the ADSP-210x. The AD7864 BUSY line provides an interrupt to the ADSP-210x when the conversion sequence is complete on all the selected channels. The conversion results can then be read from the AD7864 using successive read operations. Alternately, one can use the EOC pulse to interrupt the ADSP-210x when the conversion on each channel is complete when reading between each conversion in the conversion sequence (Figure 9). The AD7864 is read using the following instruction: MR0 = DM(ADC) where MR0 is the ADSP-210x MR0 register and ADC is the AD7864 address. ADSP-210x ADDRESS DECODE A0 TO A13 DMS VIN1 CS VIN2 RD RD VIN3 WR WR D0 TO D24 AD7864 CONVST IRQn DT1/F0 01341-023 BUSY A0 TO A13 DS VIN1 CS VIN2 RD RD VIN3 WR WE VIN4 DB0 TO DB11 D0 TO D15 AD7864 BUSY CONVST INTn PA0 Figure 24. AD7864 to TMS320C5x Interface AD7864 TO MC68HC000 INTERFACE An interface between the AD7864 and the MC68HC000 is shown in Figure 25. The conversion can be initiated from the MC68HC000 or from an external source. The AD7864 BUSY line can be used to interrupt the processor or, alternatively, software delays can ensure that the conversion has been completed before a read to the AD7864 is attempted. Because of the nature of its interrupts, the MC68HC000 requires additional logic (not shown in Figure 25) to allow it to be interrupted correctly. For further information on MC68HC000 interrupts, consult the Addendum to MC68000 Users Manual. The MC68HC000 AS and R/W outputs are used to generate a separate RD input signal for the AD7864. RD is used to drive the MC68HC000 DTACK input to allow the processor to execute a normal read operation to the AD7864. The conversion results are read using the following MC68HC000 instruction: VIN4 DB0 TO DB11 ADDRESS DECODE 01341-024 The high speed parallel interface of the AD7864 allows easy interfacing to most DSPs and microprocessors. This interface consists of the data lines (DB0 to DB11), CS, RD, WR, EOC, and BUSY. Figure 23. AD7864 to ADSP-210x Interface MOVE.W ADC,D0 where D0 is the MC68HC000 D0 register and ADC is the AD7864 address. AD7864 TO TMS320C5x INTERFACE Figure 24 shows an interface between the AD7864 and the TMS320C5x. As with the previous interfaces, conversion can be initiated from the TMS320C5x or from an external source, and the processor is interrupted when the conversion sequence is completed. The CS signal to the AD7864 is derived from the DS signal and a decode of the address bus. This maps the AD7864 into external data memory. The RD signal from the TMS320C5x is used to enable the ADC data onto the data bus. The AD7864 has a fast parallel bus, consequently there are no wait state Rev. D | Page 24 of 28 AD7864 Vector control of an ac motor involves controlling phase in addition to drive and current frequency. Controlling the phase of the motor requires feedback information on the position of the rotor relative to the rotating magnetic field in the motor. Using this information, a vector controller mathematically transforms the three-phase drive currents into separate torque and flux components. The AD7864, with its 4-channel simultaneous sampling capability, is ideally suited for use in vector motor control applications. MC68HC000 ADDRESS DECODE CS VIN2 VIN3 VIN4 RD DTACK AS R/W AD7864 D0 TO D15 CONVST A block diagram of a vector motor control application using the AD7864 is shown in Figure 26. The position of the field is derived by determining the current in each phase of the motor. Only two phase currents need to be measured because the third can be calculated if two phases are known. VIN1 and VIN2 of the AD7864 are used to digitize this information. 01341-025 DB0 TO DB11 CLOCK Figure 25. AD7864 to MC68HC000 Interface VECTOR MOTOR CONTROL The current drawn by a motor can be split into two components: one produces torque and the other produces magnetic flux. For optimal performance of the motor, control these two components independently. In conventional methods of controlling a three-phase motor, the current (or voltage) supplied to the motor and the frequency of the drive are the basic control variables. However, both the torque and flux are functions of current (or voltage) and frequency. This coupling effect can reduce the performance of the motor because, for example, if the torque is increased by increasing the frequency, the flux tends to decrease. Simultaneous sampling is critical to maintain the relative phase information between the two channels. A current sensing isolation amplifier, transformer, or Hall effect sensor is used between the motor and the AD7864. Rotor information is obtained by measuring the voltage from two of the inputs to the motor. VIN3 and VIN4 of the AD7864 are used to obtain this information. Once again, the relative phase of the two channels is important. A DSP microprocessor is used to perform the mathematical transformations and control loop calculations on the information fed back by the AD7864. DSP MICROPROCESSOR IC DAC TORQUE AND FLUX CONTROL LOOP CALCULATIONS AND TWO TO THREE PHASE INFORMATION TORQUE SETPOINT FLUX SETPOINT DRIVE CIRCUITRY DAC IB IA VB THREEPHASE VA MOTOR DAC + + ISOLATION AMPLIFIERS – – VIN1 TRANSFORMATION TO TORQUE AND FLUX CURRENT COMPONENTS VIN2 AD7864* VIN3 VIN4 *ADDITIONAL PINS OMITTED FOR CLARITY. VOLTAGE ATTENUATORS Figure 26. Vector Motor Control Using the AD7864 Rev. D | Page 25 of 28 01341-027 VIN1 A0 TO A15 AD7864 the different channels. The AD7864 has a maximum aperture delay matching of 4 ns. MULTIPLE AD7864S IN A SYSTEM Figure 27 shows a system where a number of AD7864s are configured to handle multiple input channels. This type of configuration is common in applications such as sonar and radar. The AD7864 is specified with maximum limits on aperture delay match. This means that the user knows the difference in the sampling instant between all channels. This allows the user to maintain relative phase information between VIN1 All AD7864s use the same external SAR clock (5 MHz). Therefore, the conversion time for all devices is identical; consequently, all devices can be read simultaneously. In the example shown in Figure 27, the data outputs of two AD7864s are enabled onto a 32-bit wide data bus when EOC goes low. EOC VIN2 VIN3 REF193 VIN4 ADSP-2106x 12 32 AD7864 VREF CS CLKIN RD RD VIN1 VIN2 VIN3 VIN4 12 AD7864 CS CLKIN RD ADDRESS DECODE 01341-026 VREF 5MHz Figure 27. Multiple AD7864s in Multichannel System Rev. D | Page 26 of 28 AD7864 OUTLINE DIMENSIONS 1.03 0.88 0.73 14.15 13.90 SQ 13.65 2.45 MAX 34 44 1.95 REF 1 33 PIN 1 SEATING PLANE 10.20 10.00 SQ 9.80 TOP VIEW (PINS DOWN) 2.20 2.00 1.80 0.23 0.11 23 11 0.25 MIN 0.10 COPLANARITY 7° 0° 22 12 VIEW A VIEW A 0.80 BSC LEAD PITCH 0.45 0.30 LEAD WIDTH COMPLIANT TO JEDEC STANDARDS MO-112-AA-1 041807-A ROTATED 90° CCW Figure 28. 44-Lead Metric Quad Flat Package [MQFP] (S-44-2) Dimensions shown in millimeters ORDERING GUIDE Model AD7864ASZ-1 2 AD7864ASZ-1REEL2 AD7864BSZ-12 AD7864BSZ-1REEL2 AD7864ASZ-22 AD7864ASZ-2REEL2 AD7864ASZ-32 AD7864ASZ-3REEL2 EVAL-AD7864-2CB 3 EVAL-AD7864-3CB3 EVAL-CONTROL BRD2 4 Input Ranges ±5 V, ±10 V ±5 V, ±10 V ±5 V, ±10 V ±5 V, ±10 V 0 V to 2.5 V, 0 V to 5 V 0 V to 2.5 V, 0 V to 5 V ±2.5 V ±2.5 V Relative Accuracy ±1 LSB ±1 LSB ±0.5 LSB ±0.5 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB Temperature Range 1 −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C 1 Package Description 44-Lead MQFP 44-Lead MQFP 44-Lead MQFP 44-Lead MQFP 44-Lead MQFP 44-Lead MQFP 44-Lead MQFP 44-Lead MQFP Evaluation Board Evaluation Board Controller Board Package Option S-44-2 S-44-2 S-44-2 S-44-2 S-44-2 S-44-2 S-44-2 S-44-2 The A version is fully specified up to 105°C with a maximum sample rate of 450 kSPS and IDD maximum (normal mode) of 26 mA. Z = RoHS Compliant Part. 3 This can be used as a stand alone evaluation board or in conjunction with the Evaluation Controller Board for evaluation/demonstration purposes. 4 This board is a complete unit, allowing a PC to control and communicate with all Analog Devices, Inc., evaluation boards ending in the CB designators. To order a complete evaluation kit, the particular ADC evaluation board needs to be ordered, for example, EVAL-AD7864-1CB, the EVAL-CONTROL BRD2, and a 12 V ac transformer. See the Evaluation Board application note for more information. 2 Rev. D | Page 27 of 28 AD7864 NOTES ©1998–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01341-0-2/09(D) Rev. D | Page 28 of 28