EVAL-SSM3582Z User Guide UG-934 One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com Evaluating the SSM3582 2×, 31.76 W, Digital Input, Filterless Stereo Class-D Audio Amplifier FEATURES EVALUATION BOARD PHOTOGRAPHS 2×, 31.76 W into 4 Ω at16 V, THD + N = 10% EVALUATION KIT CONTENTS USBi USB interface board USB cable EVAL-SSM3582Z evaluation board ONLINE RESOURCES Documents SSM3582 data sheet EVAL-SSM3582Z user guide Dynamic link library (DLL) for the SigmaStudio software The EVAL-SSM3582Z is the evaluation board for the SSM3582, an integrated stereo, 31.76 W, high efficiency, Class-D, audio amplifier with digital input. The application circuit requires few external components and can operate from a single 4.5 V to 16 V supply. The EVAL-SSM3582Z is capable of delivering 14.67 W of continuous output power to a 4 Ω load from a 12 V power supply, with <1% THD + N, or 31.76 W into a 4 Ω load from 16 V, 10% THD + N. 14262-001 GENERAL DESCRIPTION Figure 1. SSM3582 Evaluation Board, Top View The SSM3582 features a high efficiency, low noise modulation scheme that requires no external reconstruction filter (LC) output filters. This scheme provides high efficiency, even at low output power. This user guide describes how to configure and use the SSM3582 evaluation board. Read this user guide in conjunction with the SSM3582 data sheet, which provides specifications, internal block diagrams, a register map, and application guidance for the amplifier. Figure 1 shows the top view of the evaluation board, and Figure 2 shows the bottom view of the evaluation board. PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS. Rev. 0 | Page 1 of 13 14262-002 The EVAL-SSM3582Z and the SSM3582 operate with 93.8% efficiency at 10 W into an 8 Ω load or 90.6% efficiency at 18 W into 4 Ω load from a 12 V supply. The EVAL-SSM3582Z and the SSM3582 have a typical noise floor of 38.5 μV rms A weighted. Figure 2. SSM3582 Evaluation Board, Bottom View UG-934 EVAL-SSM3582Z User Guide TABLE OF CONTENTS Features .............................................................................................. 1 Power Supply Configuration........................................................3 Evaluation Kit Contents ................................................................... 1 Edge Mode......................................................................................4 Online Resources .............................................................................. 1 Mono Operation ............................................................................4 General Description ......................................................................... 1 Component Selection ...................................................................4 Evaluation Board Top View and Bottom View................................. 1 Getting Started ...................................................................................5 Revision History ............................................................................... 2 Suggested System Level And Audio Tests ..................................5 Setting Up the Hardware ................................................................. 3 Evaluation Board Schematics and Artwork ...................................6 Input Configuration ..................................................................... 3 Ordering Information .................................................................... 12 I C Mode ........................................................................................ 3 Bill of Materials ........................................................................... 12 2 Standalone Mode .......................................................................... 3 Output Configuration .................................................................. 3 REVISION HISTORY 4/16—Revision 0: Initial Version Rev. 0 | Page 2 of 13 EVAL-SSM3582Z User Guide UG-934 SETTING UP THE HARDWARE INPUT CONFIGURATION • There are several ways to source audio to the SSM3582 on the evaluation board. The evaluation board can accept direct digital I2S/time division multiplex (TDM) data or it can convert SPDIF/ optical digital audio data to I2S data using an on-board digital audio receiver (U6). Use the 3-way × 3-way header, J10, to connect either the onboard SPDIF audio receiver circuitry or the external digital audio signals to the SSM3582 device pins. The evaluation board comes set with three jumpers for receiving the SPDIF audio data. To use the external I2S/TDM data, remove the three jumpers on the J10 header and connect the signal sources (FSYNC, BCLK, and SDATA) to the center pins on the J10 header. If the user does not have a direct I2S or TDM source, the on-board digital audio receiver can accept SPDIF data from a digital audio source, such as the digital audio output of a compact disk player. In this case, select either the optical or coaxial option using the S2 switch to properly connect the desired input to the digital audio receiver. I2C MODE The SSM3582 supports I2C control for setting the internal registers. In this mode, Switch S3 must be set to the I2C mode. The 10-way header, J1, connects the external I2C master controlling the board. The board can be set for the desired I2C address using four headers: J18, J21, JP3, and JP4. The JP3 and JP4 headers set the pull-up or pull-down resistors to DVDD or GND, whereas the J18 and J21 headers can bypass either the R8 or R10 47 kΩ resistor. Refer to the data sheet for address selection options. Removing the jumper across Header J18 or Header J21 inserts either the R8 or R10 47 kΩ resistor in the signal path for pull-up or pull-down operation. To properly float the ADDRx pins to a no connect state, do not insert jumpers on the JP3, JP4, J18, and J21 headers. By default, the J18 and J21 headers are inserted and the JP3 and JP4 headers are pulled to GND. This sets the 7-bit device address to 0x10. STANDALONE MODE The SSM3582 also supports standalone (SA) mode operation. In this mode, Switch S3 must be set to SA mode. In SA mode, the ADDRx, SCL, and SDA pins configure the functionality of the SSM3582, including the I2S/TDM configuration and sample rate. Refer to the SSM3582 data sheet for a complete list of options. In SA mode, the duty cycle of FSYNC dictates whether the device is in I2S or TDM mode. If the duty cycle is 50%, use I2S; otherwise, use TDM. The following is an example of the settings that select a 32 kHz to 48 kHz sample rate, utilizing TDM Slot 1 and Slot 2 or the left and right channels of an I2S stream, depending on the FSYNC duty cycle: • • Set Header JP4 to GND and insert Header J21, leaving Header JP3 and Header J18 open. Set Switch S3 to SA mode. OUTPUT CONFIGURATION The binding post output terminals, OUTL−, OUTL+, OUTR−, OUTR+, provide the option to connect the speakers with standard banana connectors. The OUTL± terminals are for the left channel and the OUTR± terminals are for the right channel. In addition, the 2-pin, 0.100 inch headers, J6 and J30, are provided as alternate options. To reduce the system radiated emission, especially if the speaker cable length exceeds 20 cm, it may be necessary to include an output filter. The recommended filter uses L2, L3, L6, and L7 ferrite beads and the C1, C2, C39, and C40 capacitors. Refer to Figure 6 for more details. Note that the addition of ferrite beads other than the type used on the evaluation board may affect the total harmonic distortion (THD) and signal-to-noise ratio (SNR) performance as specified in the SSM3582 data sheet. For best performance, the Murata ferrite bead type in Table 1 and Table 2 is recommended. POWER SUPPLY CONFIGURATION The J5 (PVDD) and J4 (GND) binding posts provide the power supply to the board. Take care when connecting the dc power with correct polarity and voltage; reverse polarity or overvoltage can damage the board permanently. Permissible supply voltages range from 4.5 V to 16 V; higher voltages may damage the amplifier. In addition, use the appropriate current rated power supply to the board. Typically, a 5 A rating supply is recommended if using 4 Ω speakers and 12 V. The board has an option to generate 5 V (AVDD), 3.3 V, and 1.8 V (DVDD) supply voltages from the PVDD supply. These voltages are generated using the linear regulators on the board: U3 for 5 V, U2 for 3.3 V, and U4 for 1.8 V. The 5 V and 3.3 V regulators can be turned off using Header JP11 for 5 V and Header JP10 for 3.3 V. The 3.3 V supply is used for the onboard SPDIF digital audio receiver. The 5 V and 1.8 V supplies can provide AVDD and DVDD to the SSM3582 if required. By default, the evaluation board is set up for generating 5 V and 1.8 V supplies from the SSM3582 internal regulators by removing the jumpers from the J17 and J23 headers. The JP8 and JP9 headers enable or disable the SSM3582 internal regulators. By default, these regulators are enabled. If using the on-board regulators or the external 5 V or 1.8 V sources for the AVDD and DVDD pins, Jumper JP8 and Jumper JP9 must be fitted to the GND position and the J17 and J23 headers must be inserted. Set Switch S1 so that SCL and SDA are pulled to GND. Rev. 0 | Page 3 of 13 UG-934 EVAL-SSM3582Z User Guide EDGE MODE To reduce the radiated emissions from the SSM3582 amplifier, an edge rate control mode is available. Register 0x05, Bit 3, controls the edge rate of the switching. This low electromagnetic interference (EMI) mode is enabled by default. To disable the low EMI mode, set Bit 3 of Register 0x05 to 0. To return to the low EMI mode, set Bit 3 of Register 0x05 to 1. MONO OPERATION The board is configured for stereo operation by default, but can be changed to mono operation. For mono operation, the R27 through R30 resistors must be fitted with 0 Ω or use 16 AWG wires to short the OUTL+ terminal to the OUTR+ pin, and, similarly, to short the OUTL− terminal to the OUTR− pin. Note that the device must be configured to mono operation by setting the MONO bit (Bit 4, Register 0x04) to 0 before turning on the power stage. Set this bit by writing Register 0x04 with the hexadecimal value, 0xB1. This ensures the power stage turns on in mono operation. COMPONENT SELECTION Selecting the proper capacitors and ferrites for the evaluation board is key to achieving the performance required at the cost budgeted. Output Shunting Capacitors There are four output filter capacitors, C1, C2, C39, and C40, that work with the L2, L3, L6, and L7 ferrite beads. Use small size (0603 or 0402), multilayer, ceramic capacitors of dielectric type X7R or COG (NPO) materials. The recommended value of the capacitors is 220 pF. Output Ferrites If ferrite beads are preferred for EMI filtering at the output nodes, Table 1 shows the recommended components to avoid excessive noise induced by the nonlinear behavior of ferrite beads. Table 1. Recommended Output Ferrite Beads 1 Part No. NFZ2MSM101SN10 NFZ2MSM181SN10 NFZ2MSM301SN10 Z (Ω at 100 MHz) 100 180 300 IMAX (mA) 4000 3400 3100 DC Resistance (DCR) (Ω) 0.014 0.020 0.024 Size (mm) 2.0 × 1.6 × 0.9 2.0 × 1.6 × 0.9 2.0 × 1.6 × 0.9 Contact Murata Manufacturing Co. for further options. I2C CONNECTOR FOR USBi I2C PULLUP SELECTOR LEFT OUTPUT 5V LDO ENABLE I2C/STANDALONE SELECT SWITCH PVDD IN OPTICAL IN OPTICAL/COAX SELECTOR SWITCH 5V REG ENABLE/DISABLE 1.8V REGULATOR INT/EXT SELECT COAXIAL IN 5V INT/EXT SELECT 3.3V REG ENABLE/DISABLE SERIAL INPUT SELECT SPDIF/EXT 3.3V REGULATOR INT/EXT SELECT RESET SPDIF RX RIGHT OUTPUT 1.8V LDO ENABLE/DISABLE Figure 3. Board Settings Rev. 0 | Page 4 of 13 DEVICE ADDRESS SETTING JUMPERS 14262-003 1 Manufacturer Murata Manufacturing Co. Murata Manufacturing Co. Murata Manufacturing Co. EVAL-SSM3582Z User Guide UG-934 GETTING STARTED To set up the SSM3582 to work in a simple, single-supply configuration for quick evaluation, follow these steps: 1. 2. 3. 4. 5. 14262-005 6. Download the SigmaStudio™ software and follow the installation steps provided. Connect the USBi board to the USB port on the PC and ensure the USB driver for the USBi board is installed. Copy the provided SigmaStudio software file to the C:\Program files\Analog Devices folder. After the SigmaStudio software is installed, the SigmaStudio icon on the desktop appears. Double-click the icon. This opens up the SigmaStudio graphical user interface. Start a new project by dragging the USBi and SSM3582 icons to the Hardware Configuration tab. Connect the USBi board to the SSM3582 block on the Hardware Configuration tab schematic (see Figure 4). 10. Ensure the jumpers are inserted across all three rows of Header JP10 to establish direct connection of the digital audio signal lines to the inputs of the SSM3582. 11. Connect speakers to the left and right binding posts. 12. If using the on-board SPDIF to I2S circuitry, press the S4 button on the board to synchronize the audio signals by resetting the digital audio receiver device. 13. Click the IC-1SSM3582 tab. When clicking the GetID button, the 3582 with die revision numbers appears in the Capture window (see Figure 4). 14262-004 Figure 5. SSM3582 Device Setup Figure 4. USBi to SSM3582 Configuration 7. 8. 9. Connect the 12 V power supply source to the evaluation board. Connect the USBi board to Header J1 on the evaluation board. Select the digital audio source for the SDATA, FSYNC, and BCLK pins of the SSM3582. By default, the board is set for the SPDIF source. Connect the optical or coaxial cable to the appropriate connector on the board. 14. Click to the Chip/SAI/DAC Control tab. 15. Click the Software Master Powered button. It then turns green and the SSM3582 powers up with audio on the output. SUGGESTED SYSTEM LEVEL AND AUDIO TESTS It is recommended to test the following specifications: • • • • • Rev. 0 | Page 5 of 13 SNR. Output noise. Ensure that an A weighted filter filters the output before reading the measurement meter. Maximum output power. Distortion. Efficiency. UG-934 EVAL-SSM3582Z User Guide EVALUATION BOARD SCHEMATICS AND ARTWORK SSM3 5 8 2 I 2 S_ I 2 C ADDR1 ADDR1 ADDR0 ADDR0 OUTPUTS OUTL+ OUTL+ OUTL– OUTL- OUTR+ SCL_ 3 5 8 2 OUTR+ OUTR– SDA_ 3 5 8 2 OUTR– SCL_ 3 5 8 2 OMCK_ I N FSYNC_ 3 5 8 2 SHEET- 5 SDA_ 3 5 8 2 SDATA_ 3 5 8 2 FSYNC_ 3 5 8 2 BCLK_ 3 5 8 2 SDATA_ 3 5 8 2 8 4 1 6 _ MCLK BCLK_ 3 5 8 2 SHEET-3 SHEET- 2 POWER_SUPPLY E X T S U PPLY PVDD + 5 V_ EXT + 3 V3 _ EXT + 1 V8 _ EXT + 5V TO S S M 3 5 8 2 + 3 V3 T O S PD I F R X + 1 V8 TO S S M 3 5 8 2 14262-006 PV D D I N PU T SHEET- 4 Figure 6. Schematic of the SSM3582 Evaluation Board Block Diagram PVDD OUTL– TP3 2 TP3 4 TP3 8 OUTL+ PVDD + 1 V8 1 C1 5 0 .1 0 µ F C1 4 PV D D 10µF 0 .1 0 µ F U5 40 39 38 37 36 35 34 33 32 31 41 AV D D _ 3 5 8 2 BSTL+ OUTL+ OUTL+ PVDD PVDD PVDD PVDD OUTL– OUTL– BSTL– EPAD 3 B C1 9 2 A J1 7 C1 7 AV D D _ 3 5 8 2 TP3 0 TP2 9 TP2 8 TP2 7 TP2 5 TP2 6 TP2 4 TP2 3 TP2 2 TP2 1 +5V AD D R1 AD D R0 J2 3 1 2 2 - JUMPER 2 3 1 A B JP9 JU M PER2 S I P3 R1 7 C4 5 1 0 pF 3 0 GND 2 9 GND 2 8 DVDD_ 3 5 8 2 2 7 ADDR1 2 6 ADDR0 2 5 GND 2 4 AVDD_ 3 5 8 2 2 3 LDO_ 1 V8 _ EN 2 2 GND 2 1 GND AVDD_ 3 5 8 2 SSM3 5 8 2 11 12 13 14 15 16 17 18 19 20 C3 3 C3 1 0 .2 2 µ F C 26 0 .1 0 µ F PVDD C2 9 10µF OUTR– TP14 0 .2 2 µ F TP18 PVDD C3 2 0 .1 0 µ F C3 7 10µF 14262-007 C4 4 1 0 pF PGND PGND DVDD ADDR1 ADDR0 AGND AVDD DVDD_EN PGND PGND TP12 C4 3 1 0 pF PGND PGND AVDD_EN SCL SDA FSYNC SDATA BCLK PGND PGND BSTR+ OUTR+ OUTR+ PVDD PVDD PVDD PVDD OUTR– OUTR– BSTR– 1 2 3 4 5 6 7 8 9 10 SCL_ 3 5 8 2 S D A_ 3 5 8 2 FS YN C_ 3 5 8 2 S D ATA_ 3 5 8 2 BCLK_ 3 5 8 2 OUTR+ SCL_ 3 5 8 2 SDA_ 3 5 8 2 FSYNC_ 3 5 8 2 SDATA_ 3 5 8 2 BCLK_ 3 5 8 2 TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP1 0 4 7 kΩ 1 JU M PER2 S I P3 JP8 C1 6 0 .2 2 µ F 0 .2 2 µ F LDO_ 5 V_ EN C1 3 10µF 2 Figure 7. Schematic of the SSM3582 Evaluation Board, SSM3582 Section Rev. 0 | Page 6 of 13 J1 3 0 .1 0 µ F RESET SPDIF JP6 S4 CTP- 0 2 1 A- S- YEL COAX IN C4 + 3 V3 U1 3 DVDD L1 2 4 6 8 10 1 3 5 7 9 + 3 V3 TP4 1 J1 R2 2.43kΩ M AS TER_ RES ET R7 750Ω GND TORX 1 4 7 L( FT) 1 OUT 0 . 1 0 µF OPTICAL IN 2 3 4 3 S2 2 + 3 V3 MR RES ET VCC GND U7 AD M 8 1 1 TART Z C3 5 2 2 nF 3.01kΩ R1 4 4 1 + 3 V3 RES ET_ S PD I F + 3 V3 1 0 nF C2 5 1 0 nF C2 3 C1 8 0 .1 0 µF C3 6 1 .0 nF S PD T_ S LI D E_ EG 1 2 1 8 SPDI F_ COAX 1 SPDI F_ OPT 3 2 1 2 S1 + 3 V3 0 .1 0 µF 9 10 11 12 13 3 2 1 8 5 23 VD + 3 V3 RS T 22 AG N D D GN D 7 20 19 18 17 14 15 16 26 SDOUT 2 8 O LRCK 2 7 O S CLK 2 4 RM CK 25 O M CK TX 21 VL U6 CS 8 4 1 6 _ S PD I F_ RX C RX P1 U RX P2 RCBL RX P3 N V / RERR AU D I O 9 6 KH Z RX S EL1 RX S EL0 TX S EL1 TX S EL0 FI LT RX N RX P0 6 VA 0 .1 0 µ F 4 4 SA_ SDA DVDD_ 3 5 8 2 5 DVDD_ 3 5 8 2 6 USB_ SDA DPDT Slide S3 1 2 SA_ SCL 3 USB_ SCL C4 2 0 .1 0 uF 47µF DVDD_ 3 5 8 2 S PS T_ H ALF- PI TCH _ 2 S EC_ S M D R1 2.43kΩ TP3 9 C7 0 .1 0 µF TP3 7 USB_ I O R1 8 10kΩ R5 4 7 kΩ 2 4 R4 4 7 kΩ 1 3 L4 I 2 C / S A M O D E S E LE C T L5 J8 600Ω @100MHz JP4 A B 600Ω @100MHz 600Ω @100MHz C3 8 C3 4 C2 8 C2 7 + DEFAULT 4 7 kΩ R1 2 JP3 A B C3 0 0 .1 0 µ F + 3 V3 R9 Figure 8. Schematic of the SSM3582 Evaluation Board I2C, Digital Input Section 100kΩ Rev. 0 | Page 7 of 13 4 7 kΩ EMPH Off R2 1 ON O M CK_ I N PH DET RATE NORM R2 5 HIGH 1 4 7 kΩ 1 8 4 1 6 _ FYNC J18 8 4 1 6 _ RMCK R1 0 J2 1 2 R8 2 9 6 3 DEFAULT ERRORS NVERR R1 9 RERR 8 4 1 6 _ FYNC 8 4 1 6 _ SDATA 8 4 1 6 _ BCLK R DEFAULT 4 9.9Ω R1 1 R1 3 R1 5 R1 6 0 SFSEL1 R2 0 1 00 01 10 11 = = = = DEFAULT 0 SFSEL0 R2 4 1 LJ 24BIT I2S 24BIT RJ 24BIT DIRECT AES SFSEL [ 1 : 0 ] FSYNC_ 3 5 8 2 SDATA_ 3 5 8 2 BCLK_ 3 5 8 2 8 4 1 6 _ MCLK DEFAULT J1 9 1 2 49.9kΩ 49.9kΩ 49.9kΩ SERIAL PORT CONTROL SERIAL PORT FORMAT SLAVE R2 2 MASTE 8 5 2 7 4 1 PS I A I N J1 0 H EAD ER_ 3 X 3 _ 9 W AY_ U N S H RO U D ADDR0 ADDR1 DEFAULT I 2 C A D D R E S S S E LE C T SDA_ 3 5 8 2 SCL_ 3 5 8 2 RMCK FREQ 2 5 6 xFs R2 3 1 2 8 xFs + 3 V3 VDD OE 1 Y1 2 GND 4 0 .1 0 µF 3 O U TPU T C4 1 + 3 V3 4 7 kΩ R2 6 JP7 USBi or AARDVARK I2C INTERFACE MTH4 MTH3 MTH2 MTH1 EVAL-SSM3582Z User Guide UG-934 14262-008 J4 J7 1 2 1 .0 µF + TP1 6 TP1 5 + 470µF C6 TP1 7 470µF C5 TP3 6 TP3 5 JP1 1 A B TP1 3 5 V_ I N EN/ UVLO VI N 0 .1 0 µ F C8 5 8 PG SENSE VOUT 7 2 1 + 5 V _ EX T 100kΩ R6 + 5 V_ REG J1 2 1 2 1 .0 µ F C1 2 JP2 A B C2 2 10µF + 5V C2 1 1.0µF OUT OUT J2 4 1 2 SD IN 3 2 1 OUT OUT 2 1 C2 4 OUT U4 A3DP3335ARMZ-1.8-RL + 1 V8 _ EX T SD IN OUT U2 ADP3335ARMZ-3.3-RL IN IN C1 0 1 .0 µ F 6 8 7 6 8 7 C1 1 1 +3V3_EXT 2 R3 475Ω 1 . 0 nF C2 0 1 .0 µ F 1 V8 _ REG + 1 V 8 _ EX T 1 .0 µ F C9 1 . 0 nF 3 V3 _ REG J1 4 + 3 V 3 _ EX T JP1 A B JP5 A B + 5 V _ EX T JU M PER2 S I P3 JP1 0 1 A B 3 2 PVDD U3 ADP7 1 0 2 - 5 . 0 V_ LFCSP8 GND 3 C3 TP1 9 GND 6 J5 TP3 3 EP 9 5 NR GND 4 5 NR Rev. 0 | Page 8 of 13 GND Figure 9. Schematic of the SSM3582 Evaluation Board Power Supply Section 4 D1 + 1 V8 + 3 V3 UG-934 EVAL-SSM3582Z User Guide 14262-009 EVAL-SSM3582Z User Guide UG-934 OUTL+ L2 J3 OU TL+ NF 1 2 1 2 1 R2 7 2 C1 C2 J9 LEFT OUTPUT J6 L3 OU TL– J2 2 NF R2 8 1 1 NF R2 9 2 OUTL- OUTR+ L6 J3 1 OU TR+ NF 1 2 1 2 J2 9 C4 0 RIGHT OUTPUT J30 1 R3 0 2 C3 9 L7 J32 OU TR– 14262-010 OUTRR2 THROUGH R30 NOT FITTED FOR STEREO R27 THROUGH R300OHM FOR MONO Figure 10. Schematic of the SSM3582 Evaluation Board Output Section Rev. 0 | Page 9 of 13 EVAL-SSM3582Z User Guide Figure 11. SSM3582 Evaluation Board Top Layer, Copper 14262-013 14262-011 UG-934 Figure 12. SSM3582 Evaluation Board Second Layer, Copper 14262-014 14262-012 Figure 13. SSM3582 Evaluation Board Third Layer, Copper Figure 14. SSM3582 Evaluation Board Bottom Layer, Copper Rev. 0 | Page 10 of 13 Figure 15. SSM3582 Evaluation Board Top Silkscreen 14262-016 UG-934 14262-015 EVAL-SSM3582Z User Guide Figure 16. SSM3582 Evaluation Board Bottom Silkscreen Rev. 0 | Page 11 of 13 UG-934 EVAL-SSM3582Z User Guide ORDERING INFORMATION BILL OF MATERIALS Table 2. Qty Reference Designator Description 1 Board Evaluation Board EVAL-SSM3582Z, 4-layer, 3.8" × 3" 4 C1, C2, C39, C40 Multilayer ceramic capacitors, 220 pF, 50 V, NP0, 0402 1 C3 Multilayer ceramic capacitors, 1 μF, 25 V, X7R, 1206 11 C4, C7, C18, C19, C26 to Multilayer ceramic capacitors, 0.1 μF, 16 V, X7R, 0402 C28, C30, C38, C41 to C42 2 C5, C6 Aluminum electrolytic capacitors, HE, 470 μF, 25 V, 105°C, 5 mm 3 C8, C15, C32 Multilayer ceramic capacitors, 0.1 μF, 35 V, X7R, 0402 5 C9, C10, C12, C20 to C21 Multilayer ceramic capacitors, 1 μF, 16 V, X7R, 0603 3 C11, C24, C36 Multilayer ceramic capacitors, 1 nF, 50 V, NP0, 0402 2 C13, C37 Multilayer ceramic capacitors, 10 μF, 25 V, X7R, 1210 4 C14, C16, C31, C33 Multilayer ceramic capacitors, 0.22 μF, 25 V, X7R, 0603 3 C17, C22, C29 Multilayer ceramic capacitors, 10 μF, 10 V, X7R, 0805 2 C23, C25 Multilayer ceramic capacitors, 10 nF, 25 V, NP0, 0603 1 C34 Aluminum electrolytic capacitor, FC, 47 μF, 16 V, 105°C, SMD_D 1 C35 Multilayer ceramic capacitor, 22 nF, 25 V, NP0, 0805 3 C43 to C45 Multilayer ceramic capacitors, 10 pF, 50 V, NP0, 0402 1 D1 Red, diffused, 6.0 mcd, 635 nm, 1206 1 J1 10-way, shroud polarized header 6 J2 to J5, J31, J32 Binding posts, mini uninsulated base, through-hole 9 J6, J7, J9, J12, J14, J19, 2-pin headers, unshrouded jumper, 0.10", use Tyco J24, J29, J30 shunt 881545-2 1 J8 4-way unshrouded header 1 J10 9-way unshrouded header 1 J13 RCA jack, printed circuit board, through-hole mount, right angle, yellow 3 J17, J18, J21 2-pin headers, unshrouded jumper, 0.10", use Tyco shunt 881545-2 1 J23 2-pin header, unshrouded jumper, 0.10", use Tyco shunt 881545-2 9 JP1 to JP5, JP8 to JP11 Three-position SIP headers 2 JP6, JP7 2-pin headers, unshrouded jumper, 0.10", use Tyco shunt 881545-2 3 L1, L4, L5 Chip ferrite beads, 600 Ω at 100 MHz 4 L2, L3, L6, L7 Chip ferrite beads, 180 Ω at 100 MHz, NFZ2MSM181 4 MTH1 to MTH14 6-32 nylon screws and 1/2" standoff 2 1 7 2 1 4 1 1 R1, R2 R3 R4, R5, R8, R10, R12, R17, R26 R6, R9 R7 R11, R13, R15, R16 R14 R18 Manufacturer Analog Devices, Inc. Part Number EVAL-SSM3582Z Murata ENA Panasonic EC Murata ENA GRM1555C1H221JA01D ECJ-3YB1E105K GRM155R71C104KA88D Nichicon UHE1E471MPD6 TDK Corp Murata ENA Murata ENA Murata ENA CGA2B3X7R1V104K050BB GRM188R71C105KA12D GRM1555C1H102JA01D GCM32ER71E106KA57L Murata ENA Murata ENA TDK Corp Panasonic EC GRM188R71E224KA88D GRM21BR71A106KE51L C1608C0G1E103J EEE-FC1C470P Murata ENA Murata ENA Lumex Opto 3M Johnson Sullins Electronics Corp GRM21B5C1H223JA01L GRM1555C1H100JZ01D SML-LX1206IW-TR N2510-6002RB 111-2223-001 PBC02SAAN; or cut PBC36SAAN PBC02DAAN, or cut PBC36DAAN 103817-2 CTP-021A-S-YEL 3M TE Connectivity Connect-Tech Products Corp. Sullins Electronics Corp PBC02SAAN; or cut PBC36SAAN Sullins Electronics Corp PBC02SAAN; or cut PBC36SAAN Sullins Sullins Electronics Corp PBC03SAAN; or cut PBC36SAAN PBC02SAAN; or cut PBC36SAAN TDK Corp Murata MMZ1005S601C NFZ2MSM181SN10L NY PMS 632 0025 PH and 1903C Chip resistors, 2.43 kΩ ,1%, 63 mW, thick film, 0402 Chip resistors, 475 Ω, 1%, 63 mW, thick film, 0402 Chip resistors, 47 kΩ, 1%, 63 mW, thick film, 0402 Building Fasteners and Keystone Vishay/Dale Vishay/Dale Yageo CRCW04022K43FKED CRCW0402475RFKED RC0402FR-0747K0L Chip resistors, 100 kΩ, 1%, 100 mW, thick film, 0402 Chip resistor, 75 Ω, 1%, 100mW Thick Film 0603 Chip resistors, 49.9 Ω,1%, 63 mW thick film 0402 Chip resistor, 3.01 kΩ, 1%, 100 mW, thick film, 0603 Chip resistor, 10 kΩ, 1%, 63 mW thick film 0402 Panasonic EC Panasonic EC Yageo Rohm Rohm ERJ-2RKF1003X ERJ-3EKF75R0V RC0402FR-0749R9L MCR03EZPFX3011 MCR01MZPF1002 Rev. 0 | Page 12 of 13 EVAL-SSM3582Z User Guide Qty 7 4 1 1 1 1 36 1 1 1 1 1 1 1 1 1 UG-934 Reference Designator R19 to R25 R27 to R30 S1 Description Chip resistors, 47.5 kΩ, 1%, 100 mW, thick film, 0603 Chip resistors, 0 Ω, 5%, 250 mW, thick film, 1206 Switch, dual inline package, 4-poles, sealed SMD (half-pitch) S2 Single-pole double throw, slide switch, PC mount S3 Dual-pole, dual-throw, slide switch, vertical S4 Tact switch, 6 mm, gull wing TP1 to T10, TP12 to T19, Mini test points, white,1", OD TP21 to T30, TP32 to T39 TP41 Gold pad only U1 15 Mb/s, fiber optic receiving module with shutter U2 High accuracy, ultralow IQ, 500 mA, any capacitor, low dropout regulator U3 Fixed 5 V output, 20 V Input, 300 mA, low noise, CMOS LDO U4 High accuracy, ultralow IQ, 500 mA, any capacitor, low dropout regulator U5 IC 2×, 31.76 W, Class-D amplifier SSM3582, 40-lead LFCSP U6 192 kHz digital receiver, 28-TSSOP U7 Microprocessor voltage supervisor, logic low, RESET output Y1 12.288 MHz, fixed SMD oscillator, 3.3 V to 5 V dc Manufacturer Panasonic EC Panasonic EC Omron Part Number ERJ-3EKF4752V ERJ-8GEY0R00V A6H-2102 E-Switch E-Switch Tyco/Alcoswitch Keystone Electronics EG1218 EG2207 FSM6JSMA 5002 Do not install Toshiba Do not install TORX147L(FT) Analog Devices, Inc. Not applicable Analog Devices, Inc. ADP7102ACPZ-5.0 Analog Devices, Inc. Not applicable Analog Devices, Inc. SSM3582 Cirrus Logic Analog Devices, Inc. CS8416-CZZ ADM811TARTZ-REEL7 Cardinal Components CPPFX C 7 L T - A7 BR 12.288MHz TS I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. Legal Terms and Conditions By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc. (“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal, temporary, nonexclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and agrees that the Evaluation Board is provided for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional limitations: Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third Party to access the Evaluation Board. As used herein, the term “Third Party” includes any entity other than ADI, Customer, their employees, affiliates and in-house consultants. The Evaluation Board is NOT sold to Customer; all rights not expressly granted herein, including ownership of the Evaluation Board, are reserved by ADI. CONFIDENTIALITY. This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI. Customer may not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of use of the Evaluation Board or termination of this Agreement, Customer agrees to promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board, including but not limited to soldering or any other activity that affects the material content of the Evaluation Board. Modifications to the Evaluation Board must comply with applicable law, including but not limited to the RoHS Directive. TERMINATION. ADI may terminate this Agreement at any time upon giving written notice to Customer. Customer agrees to return to ADI the Evaluation Board at that time. LIMITATION OF LIABILITY. THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED “AS IS” AND ADI MAKES NO WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT. ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS, ENDORSEMENTS, GUARANTEES, OR WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THE EVALUATION BOARD INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, TITLE, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS. IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER’S POSSESSION OR USE OF THE EVALUATION BOARD, INCLUDING BUT NOT LIMITED TO LOST PROFITS, DELAY COSTS, LABOR COSTS OR LOSS OF GOODWILL. ADI’S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE AMOUNT OF ONE HUNDRED US DOLLARS ($100.00). EXPORT. Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will comply with all applicable United States federal laws and regulations relating to exports. GOVERNING LAW. This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of Massachusetts (excluding conflict of law rules). Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and Customer hereby submits to the personal jurisdiction and venue of such courts. The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed. ©2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. UG14262-0-4/16(0) Rev. 0 | Page 13 of 13