Evaluation Board User Guide UG-040 One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com Evaluating the AD1937/AD1939 Four ADC/Eight DAC with PLL 192 kHz, 24-Bit Codec EVAL-AD1937AZ/EVAL-AD1939AZ PACKAGE CONTENTS through an SPI or I2C interface. A small external interface board, EVAL-ADUSB2EBZ (also called USBi), connects to a PC USB port and provides I2C and SPI access to the evaluation board through a ribbon cable. A graphical user interface (GUI) program is provided for easy programming of the chip in a Microsoft® Windows® PC environment. The evaluation board allows demonstration and performance testing of most AD1937/AD1939 features, including four ADCs and eight DACs, as well as the digital audio ports. AD1937/AD1939 evaluation board USBi control interface board USB cable OTHER SUPPORTING DOCUMENTATION AD1937 data sheet AD1939 data sheet Additional analog circuitry (ADC input filters, DAC output filter/buffer) and digital interfaces such as S/PDIF are provided to ease product evaluation. EVALUATION BOARD OVERVIEW This document explains the design and setup of the evaluation board for the AD1937 and AD1939. The evaluation board must be connected to an external ±12 V dc power supply and ground. On-board regulators derive 5 V and 3.3 V supplies for the AD1937/AD1939. The AD1937/AD1939 can be controlled All analog audio interfaces are accessible with stereo audio, 3.5 mm TRS connectors. FUNCTIONAL BLOCK DIAGRAM POWER SUPPLY CONTROL INTERFACE SPI S/PDIF INTERFACE DAC 1 AND DAC 2 ANALOG AUDIO LRCLK, BCLK, SDATA ANALOG AUDIO AD1939 ADC 1 AND ADC 2 AD1939 VOLT REG SERIAL AUDIO INTERFACES DAC 3 AND DAC 4 CLOCK AND DATA ROUTING MCLK ROUTING a ANALOG AUDIO 08411-001 Pb Figure 1. PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS. Rev. 0 | Page 1 of 32 UG-040 Evaluation Board User Guide TABLE OF CONTENTS EVAL-AD1937AZ/EVAL-AD1939AZ Package Contents ........... 1 Powering the Board.......................................................................4 Other Supporting Documentation ................................................. 1 Setting Up the Master Clock (MCLK)........................................4 Evaluation Board Overview ............................................................ 1 Configuring the PLL Filter ...........................................................5 Functional Block Diagram .............................................................. 1 Connecting Audio Cables ............................................................6 Revision History ............................................................................... 2 Switch and Jumper Settings .........................................................6 Setting Up the Evaluation Board .................................................... 3 Rotary and DIP Switch Settings ......................................................8 Standalone Mode .......................................................................... 3 Schematics and Artwork ............................................................... 10 SPI and I C Control ...................................................................... 3 CPLD Code ..................................................................................... 21 Automated Register Window Builder Software Installation .. 3 Ordering Information .................................................................... 27 Hardware Setup—USBi ............................................................... 3 Bill of Materials ........................................................................... 27 2 REVISION HISTORY 2/10—Revision 0: Initial Version Rev. 0 | Page 2 of 32 Evaluation Board User Guide UG-040 SETTING UP THE EVALUATION BOARD The Automated Register Window Builder controls the AD1937/AD1939 and is available at www.analog.com/AD1937 or www.analog.com/AD1939. 2. Figure 3. Standalone Master Mode At www.analog.com/AD1937 or www.analog.com/AD1939, find the Resources & Tools list. In the list, find Evaluation Boards & Development Kits and click Evaluation Boards/Tools to open the provided ARWBvXX.zip file. Double-click the provided .msi file to extract the files to an empty folder on your PC. Then double-click setup.exe and follow the prompts to install the Automated Register Window Builder. A computer restart is not required. Copy the .xml file for the AD1937/AD1939 from the extraction folder into the C:\Program Files\Analog Devices Inc\AutomatedRegWin folder, if it does not appear in the folder after installation. With the control jumpers set to standalone slave mode, all of S2 and S3 set to off, and both mode switches (S4 and S5) set to 0. The S/PDIF receiver is the LRCLK, BCLK, and SDATA source. The default MCLK jumper setting routes MCLK from the S/PDIF receiver to the AD1937/AD1939. With a valid S/PDIF data stream connected to a selected S/PDIF input port, the board passes audio from the S/PDIF port to all four stereo outputs and from Stereo IN1 to the S/PDIF output ports. IN2 can be selected by changing S3, Position 8, to on. Other serial audio clock and data routing configurations are described in the Switch and Jumper Settings section. HARDWARE SETUP—USBi SPI AND I2C CONTROL To set up the USBi hardware, follow these steps: The evaluation board can be configured for interactive control of the registers in the AD1937/AD1939 by connecting the SPI or I2C port to the USBi. SPI and I2C jumper settings are shown in Figure 4 and Figure 5. All part variations are SPI (for the AD1939). Note that the Automated Register Window Builder software controls the AD1937 (I2C) only when the ADDR jumpers are set to 00 and the correct .xml file is loaded. 1. 2. 3. 3. 4. 5. 08411-004 ADDR1 CLATCH 1 0 J8 CCLK 0 SCL ADDR0 CIN J7 1 0 COUT 0 J6 SDA/1 J5 08411-005 1 CLATCH 0 CCLK 0 SCL 1 CIN COUT ADDR1 Figure 5. I2C Control 1. 08411-003 ADDR1 CLATCH 1 0 J8 CCLK 0 SCL ADDR0 CIN J7 1 0 COUT 0 SDA/1 J6 ADDR0 J8 The Automated Register Window Builder is a program that launches a graphical user interface for direct, live control of the AD1937/AD1939 registers. The GUI content for a part is defined in a part-specific . xml file; these files are included in the software installation. To install the Automated Register Window Builder software, follow these steps: 08411-002 1 ADDR1 Figure 2. Standalone Slave Mode J5 J7 AUTOMATED REGISTER WINDOW BUILDER SOFTWARE INSTALLATION CLATCH 0 J8 CCLK ADDR0 0 SCL 1 J7 CIN 0 COUT 0 J6 SDA/1 J5 0 It is possible to run the board and the AD1937/AD1939 codec in standalone mode, which fixes the functionality of the AD1937/AD1939 into the I2S data format, running at 256 × fS (default register condition). The ADC BCLK and LRCLK ports are flipped between slave and master (input and output) by tying SDA/COUT (Pin 31) to low or high. This is accomplished by moving the J5 jumper to either 0 or SDA/1 (see Figure 2 and Figure 3). J6 SDA/1 J5 0 STANDALONE MODE Figure 4. SPI Control Rev. 0 | Page 3 of 32 Plug the USBi ribbon cable into the J1 header. Connect the USB cable to your computer and to the USBi. When prompted for drivers, follow these steps: a. Choose Install from a list or a specific location. b. Choose Search for the best driver in these locations. c. Check the box Include this location in the search. d. Find the USBi driver in C:\Program Files\Analog Devices Inc\AutomatedRegWin\USB drivers. e. Click Next. f. If prompted to choose a driver, select CyUSB.sys. g. If the PC is running Windows XP and you receive a message that the software has not passed Windows logo testing, click Continue Anyway. UG-040 Evaluation Board User Guide 193X_MCLKI DISABLE JP19 JP20 MCLKO C147 XTAL R160 JP22 OSC Q1 L7 C153 1938_MCLKI R166 JP5 JP6 JP7 R102 C97 J23 U22 JP28 EXT CLK Figure 6. AD1939 Main Regulators Active C96 R172 R174 JP29 8416 R175 C168 EXT CLK IN C170 JP30 HDR2 08411-008 ENABLE DISABLE R169 JP27 193X_MCLKO R178 193X REG R167 OSC DISABLE HDR1 MCLKI BUS JP15 Y1 JP23 CPLD U21 JP25 HDR2 JP24 C122 08411-006 MAIN REGS 193X REG DVDD AVDD1 AVDD2 C158 R117 U18 J22 R156 JP18 C154 R155 C96 Note that, if the HDR connectors are to be driven with MCLK from a source on the evaluation board, SW2 and/or SW3 must be switched from the IN position to the OUT position. R102 C97 The AD1937/AD1939 evaluation board requires power supply input of ±12 V dc and ground to the three binding posts; +12 V draws ~250 mA, and −12 V draws ~100 mA. The on-board regulators provide two 3.3 V rails and one 5.0 V rail. The 3.3 V rails supply AVDD and DVDD for the AD1937/AD1939; DVDD also supplies power for the peripheral active components on the board. The 5.0 V rail provides voltage only to the AD1937/ AD1939 internal regulator, which consists of a PNP pass transistor and a few passive components. The PNP is driven into 3.3 V regulation by the VDRIVE pin of the AD1937/AD1939, with the VSUPPLY and VSENSE pins acting as power and feedback for the regulator. An appropriate sized PNP can supply 3.3 V to the AVDD and DVDD pins of the AD1937/AD1939. The jumper blocks are shown in Figure 6 and Figure 7. The AD1937/AD1939 evaluation board has a series of jumpers that give the user great flexibility in the MCLK clock source of the AD1937/AD1939. MCLK can come from six different sources: passive crystal, active oscillator, external clock in, S/PDIF receiver, and two header connections. Note that the complex programmable logic device (CPLD) on the board must have a valid clock source; the frequency is not critical. These jumper blocks can assign a clock to the CPLD as well. Most applications of the board use MCLK from either the S/PDIF receiver or one of the header (HDR) inputs. Figure 8 to Figure 10 show the onboard active oscillator disabled so that it does not interfere with the selected clock. The clock feed to the CPLD comes directly from the clock source. MCLKO BUS POWERING THE BOARD SETTING UP THE MASTER CLOCK (MCLK) MCLKI XTAL You can now open the Automated Register Window Builder application and load the file for the part onto your evaluation board. JP31 HDR1 Figure 8. S/PDIF Receiver as MCLK Master; the AD1939 and CPLD as Slaves Figure 7. AD1939 Internal Regulator Active Y1 JP23 CPLD U21 JP25 HDR2 R167 R169 JP27 R172 OSC DISABLE HDR1 JP29 8416 JP30 HDR2 JP31 HDR1 193X_MCLKO J23 U22 JP28 EXT CLK MCLKI BUS The first step in using the AD1937/AD1939 internal regulator is to provide power to the regulator circuit by moving the AD1937/ AD1939 REG jumper from DISABLE to ENABLE, as shown in Figure 7. Three discrete jumpers allow the AD1937/AD1939 to be run from either the main AVDD and DVDD regulators or the AD1937/AD1939 internal regulator. These jumpers also allow measurement of current drawn by the individual sections of the AD1937/AD1939. The only components on the AD1937/ AD1939 side of the jumper are the AD1937/AD1939 and the supply decoupling capacitors. U18 R178 JP5 JP6 JP7 C158 R166 ENABLE DISABLE L7 JP24 193X REG OSC R160 JP22 JP15 J22 R174 C168 C170 R175 EXT CLK IN 08411-009 C122 C153 1938_MCLKI R156 C154 R155 JP19 JP20 MCLKO C147 XTAL MCLKO BUS JP18 08411-007 DVDD MCLKI XTAL 193X_MCLKI DISABLE R117 193X REG MAIN REGS AVDD1 AVDD2 Q1 Figure 9. HDR1 as MCLK Master; the AD1939, CPLD, and HDR2 as Slaves Rev. 0 | Page 4 of 32 Evaluation Board User Guide UG-040 J23 R175 EXT CLK IN 08411-010 JP31 HDR1 Figure 10. External Clock In as Master; the AD1939 and CPLD as Slaves R166 J23 C170 R175 EXT CLK IN JP31 HDR1 JP29 8416 JP30 HDR2 R156 C154 R155 C154 R155 R156 193X_MCLKO J23 U22 JP28 MCLKI BUS C168 R172 EXT CLK 08411-011 R178 R174 R169 JP27 OSC DISABLE HDR1 U22 JP28 EXT CLK R167 R174 C168 C170 JP31 HDR1 R175 EXT CLK IN 08411-013 R172 J22 Y1 JP23 CPLD U21 JP25 HDR2 R178 R169 JP27 MCLKI XTAL C158 193X_MCLKO U18 MCLKO BUS L7 C153 R160 JP22 OSC U18 JP20 MCLKO C147 XTAL 1938_MCLKI JP24 R167 OSC DISABLE HDR1 MCLKI BUS JP19 MCLKO BUS R166 JP24 C153 JP31 HDR1 J22 Y1 JP23 CPLD U21 JP25 HDR2 JP30 HDR2 EXT CLK IN C170 JP30 HDR2 Figure 12. Passive Crystal; the AD1939 Is Master and the CPLD Is Slave from the MCLKO Port R156 C154 R155 MCLKI XTAL C158 JP29 8416 R175 C168 JP18 JP20 MCLKO C147 XTAL C153 OSC R160 JP22 J23 193X_MCLKI DISABLE 1938_MCLKI L7 R174 JP29 8416 193X_MCLKI DISABLE JP19 193X_MCLKO U22 JP28 C170 JP18 R172 EXT CLK C168 JP30 HDR2 R169 JP27 MCLKI BUS R178 R174 JP29 8416 R167 OSC DISABLE HDR1 U22 JP28 EXT CLK Y1 JP23 CPLD U21 JP25 HDR2 08411-012 R172 U18 J22 MCLKO BUS R169 JP27 OSC C158 193X_MCLKO R166 R167 OSC DISABLE HDR1 MCLKI BUS R160 JP22 L7 JP24 R166 1938_MCLKI Y1 JP23 CPLD U21 JP25 HDR2 JP24 U18 JP20 MCLKO C147 XTAL R178 C158 JP19 MCLKO BUS OSC R160 JP22 L7 C153 1938_MCLKI J22 R156 JP19 JP18 JP20 MCLKO C147 XTAL C154 R155 MCLKI XTAL JP18 MCLKI XTAL 193X_MCLKI DISABLE 193X_MCLKI DISABLE Figure 13. LRCLK Is the Master Clock Using the PLL; MCLKI Is Disabled, and CPLD Is Slave to the MCLKO Port Figure 11. Active On-Board Oscillator as Master; the AD1939 and CPLD as Slaves The MCLK configurations shown in Figure 12 and Figure 13 use the AD1937/AD1939 MCLKO port to drive the CPLD and, possibly, the HDRs. The passive crystal runs the AD1937/AD1939 at 12.288 MHz. Figure 13 shows the MCLKI shut off; this is the case when the PLL is set to lock to LRCLK instead of to MCLK. CONFIGURING THE PLL FILTER The PLL for the AD1937/AD1939 can run from either MCLK or LRCLK, according to its setting in the PLL and Clock Control 0 register, Bits[6:5]. The matching RC loop filter must be connected to LF (Pin 61) using JP15. See Figure 14 and Figure 15 for the jumper positions. Rev. 0 | Page 5 of 32 Evaluation Board User Guide CM FILTER VREF SELECT IN1R+ IN1R– 08411-016 TP34 R101 R107 GND JP4 C89 C88 U14 C99 C74 TP32 C83 C82 R106 R76 C68 C77 R81 JP12 JP11 R86 C76 S1 IN1L– R90 C80 IN1L+ TP28 JP13 IN1R C75 TP30 R93 R97 C79 MCLK LRCLK JP15 C131 R85 R87 08411-015 C114 C125 R138 C67 U12 C69 R84 PLL SELECT C120 TP26 C65 C64 TP25 Figure 14. MCLK Loop Filter Selected R129 C61 C72 IN1L C105 JP15 C131 C60 R79R77C62 C125 C63 R72 C66 MCLK LRCLK R129 R138 R73 PLL SELECT C120 08411-014 C114 UG-040 Figure 16. VREF Selection and DC Coupling Jumpers Figure 15. LRCLK Loop Filter Selected Digital Audio Normally, the MCLK filter is the default selection; it is also possible to use the register control window to program the PLL to run from the LRCLK. In this case, the jumper must be changed as shown in Figure 15. CONNECTING AUDIO CABLES Analog Audio The analog inputs and outputs use 3.5 mm TRS jacks; they are configured in the standard configuration: tip = left, ring = right, sleeve = ground. The analog inputs to IN1 and IN2 generate 0 dBFS from a 1 V rms analog signal. The on-board buffer circuit creates the differential signal to drive the ADC with 2 V rms at the maximum level. The DAC puts out a 1.8 V rms differential signal; this signal becomes single-ended for the OUT connectors. There are test points that allow direct access to the ADC and DAC pins; note that the ADC and DAC have a common-mode voltage of 1.5 V dc. These test points require proper care so that improper loading does not drag down the common-mode voltage, and the headroom and performance of the part do not suffer. The ADC buffer circuit is designed with a switch (S1) that allows the user to change the voltage reference for all of the amplifiers. GND, CM, and FILTR can be selected as a reference; it is advisable to shut down the power to the board before changing this switch. The CM and FILTR lines are very sensitive and do not react well to a change in load while the AD1937/AD1939 is active. A series of jumpers allows the user to dc-couple the buffer circuit to the ADC analog port when CM and FILTR are selected (see Figure 16). There are two types of digital interfacing, S/PDIF and discrete serial. The input and output S/PDIF ports have both optical and coaxial connectors. The serial audio connectors use 1 × 2 100 mil spaced headers with pins for both signal and ground. The LRCLK, BCLK, and SDATA paths are available for both the ADC and DAC on the HDR1 and HDR2 connectors. Each has a connection for MCLK; each HDR MCLK interface has a switch to set the port as an input or output, depending on the master or slave state of the AD1937/AD1939. SWITCH AND JUMPER SETTINGS Clock and Control The AD1937/AD1939 are designed to run in standalone mode at a sample rate (fS) of 48 kHz, with an MCLK of 12.288 MHz (256 × fS). In standalone slave mode, both ADC and DAC ports must receive valid BCLK and LRCLK. The AD1937/AD1939 can be clocked from either the S/PDIF receiver or the HDR1 connector; the ADC BCLK and LRCK port sources are selected with SW2, Position 2 and Position 3. For S/PDIF master, both switches should be off. For HDR1, SW2, Position 3, should be on (see the detail in Figure 17 and Figure 18). The DAC BCLK and LRCK port sources are selected with SW2, Position 5 and Position 6. For S/PDIF master, both switches should be off. For HDR1, SW2, Position 6, should be on. Note that HDR2 is not implemented in the CPLD routing code. It is also possible to configure the AD1937/AD1939 ADC BCLK and LRCK ports to run in standalone master mode; moving J5 to SDA/1, as shown in Figure 3, changes the state of the AD1937/AD1939. Setting SW2, Position 2 and Position 5, to on selects the proper routing to both the S/PDIF receiver and the HDR1 connector. In this mode, the AD1937/AD1939 ADC port generates BCLK and LRCLK when given a valid MCLK. Rev. 0 | Page 6 of 32 Evaluation Board User Guide UG-040 For the full flexibility of the AD1937/AD1939, the part can be put in SPI/I2C control mode and programmed with the Automated Register Window Builder application (see Figure 4 and Figure 5 for the appropriate jumper settings). Changing the registers and setting the DIP switches allow many possible configurations. In the various master and slave modes, the AD1937/AD1939 take MCLK from a selected source and can be set to generate or receive either BCLK or LRCLK to or from either the ADC or the DAC port, depending on the settings and requirements. As an example, to set the ADC port as master, switch the ADC Control 2 register bits for BCLK and LRCLK to master, and change SW2, Position 2 and Position 5, to on. In this mode, the board is configured so that the ADC BCLK and LRCLK pins are the clock source for both the ADC destination and the DAC data source. For the DAC port to be the master, the DAC Control 1 register bits for BCLK and LRCLK must be changed to master, and SW2, Position 2 and Position 3, and SW2, Position 5 and Position 6, must all be on. On this evaluation board, these settings allow the master port on the AD1937/AD1939 to drive both the S/PDIF and the HDR connections. Many combinations of master and slave are possible (see Figure 17 and Figure 18 for the correct settings). S/PDIF Audio The settings in Figure 17 and Figure 18 show the details of clock routing and control for both the ADC and DAC ports. The board is shipped with the S/PDIF port selected as the default; the hex switches are set to 0, and all DIP switches are set to off. The AD1937/AD1939 are shipped in standalone slave mode (see Figure 2); the BCLK and LRCLK signals run from the S/PDIF receiver to both ADC and DAC ports of the AD1937/AD1939. In this default configuration, the DAC audio path routes the S/PDIF audio signal to all four stereo AD1937/AD1939 DSDATA inputs simultaneously. The rotary switch, S4, allows the user to select individual stereo pairs for transmission of the analog signal. Position 0 is the default; Position 1 to Position 4 allow the S/PDIF input signal to be assigned to Pair 1 to Pair 4, respectively. Also in this default configuration, IN1 analog is routed through the AD1937/AD1939 ADC ASDATA1 path to the S/PDIF output. IN2 is selected by changing the S3 DIP switch, Position 8, from 0 to 1. HDR Connectors—Serial Audio Routing of serial audio to and from the HDR1 connector is controlled by DIP SW3, Position 6 and Position 7, and Rotary S4. For the DAC audio signal path, S4, Position 8, assigns the data signal coming into HDR1 DSDATA1 to all four DSDATA ports on the AD1937/AD1939. S4, Position 9, assigns the HDR1 labeled ports to the associated port on the AD1937/AD1939. Other Options It is possible to mute all data going to the DSDATA ports of the AD1937/AD1939 by selecting S4, Position 7. This shows the SNR of the DACs. To use other fS rates, the USBi must be connected and the AD1937/AD1939 registers must be programmed accordingly. For example, adjusting the fS rate to 96 kHz requires that the ADC and DAC Control 0 registers have sample rates set to 96 kHz (see Figure 17 and Figure 18 for the complete list of options). The CPLD code is presented in the CPLD Code section and is included with the evaluation board; alterations and additions to the functionality of the CPLD are possible by altering the code and reprogramming the CPLD. Rev. 0 | Page 7 of 32 Enable ADC clocks Tristate ADC clocks Enable Disable Position-3 Off* On Off On Off* On Position-2 Off* Off On On Enable DAC clocks Tristate DAC clocks Enable Disable Position-6 Off* On Off On Off* On Position-5 Off* Off On On Figure 17. Settings Chart 1 Rev. 0 | Page 8 of 32 SPDIF TX - CS8406 Jumpers JP18 0 = the V pin input determines the s tate of the v alidity bit in the outgoing AES3 transmitted data 1 = the V pin input determines the s tate of the v alidity bit in the outgoing AES3 transmitted data SPDIF RX - CS8416 Jumpers JP1 0 = Normal update rate phase detector, increased clock jitter 1 = High update rate phase detector, low clock jitter Off* On JP2 0 = NVERR selected 1 = RERR selected Description SPDIF_TX_RX RESETB SPDIF_RX_TX in active mode SPDIF_RX_TX in reset mode Position-8 Off* On Description SPDIF_RX_TX MCLK Rate SPDIF_RX_TX MCLK Rate = 256xfS SPDIF_RX_TX MCLK Rate = 128xfS DLRCLK Source SPDIF_RX_8416 HDR1_DLRCLK ADC-ALRCLK DAC-DLRCLK ALRCLK Source SPDIF_RX_8416 HDR1_ALRCLK ADC-ALRCLK DAC-DLRCLK Position-7 DBCLK Source SPDIF_RX_8416 HDR1_DBCLK ADC-ABCLK DAC-DBCLK Description Position-4 ABCLK Source SPDIF_RX_8416 HDR1_ABCLK ADC-ABCLK DAC-DBCLK Description DIP Switch S2 position: Position-1 SPDIF_Tx Clocks Slave Slave Slave Slave SPDIF_Tx Clocks Slave Slave Slave Slave HDR1 Clocks Slave Master Slave Slave HDR1 Clocks Slave Master Slave Slave ADC Cl ocks N/A N/A Master N/A ADC Cl ocks Slave Slave Master Slave SPDIF_TX CS8406 MCLK Rate Jumper Settings JP10 JP9 0 0 0 1 JP3 0 = Emphasis audio match off 1 = Emphasis audio match on SPDIF_TX MCLK Rate = 256xfS SPDIF_TX MCLK Rate = 128xfS (Note: This position must be toggled after power-up for proper operation.) SPDIF_TX CS8406 MCLK Jumper Settings JP10 JP9 0 0 0 1 SPDIF_Rx Clocks Master Slave Slave Slave SPDIF_Rx Clocks Master Slave Slave Slave 1) DIP Switch S2 controls the AD193x ADC a nd DAC serial clock source selection. One of four clock sources is selected based on the setting. SPDIF Receiver CS8416, Header Connector HDR1, ADC serial clocks, or DAC serial clock can be the clock source. ADC a nd DAC serial clock selection is controlled independently. 2) The AD193x master clock source should be selected using the JP28, JP29, JP30, and JP31 header jumpers such that the MCLK source is in sync with the DAC/ADC serial clock and data source. ADC and DAC Serial Clock (BCLK, LRCLK) Source Selection and Routing (Switch S2) 1) DIP Switch S2 Position-8 (SPDIF_RX_TX reset) must be toggled after power-up for proper operation of the SPDIF receiver and transmitter. 2) The AD193x evalution board defaults the AD193x codec to standalone mode preventing SPI/I2C operation. The J5, J6, J7, and J8 he ader jumpers can be changed for SPI/I2C operation. AD193X/ADAU132X Rev-E Evaluation Board Configuration: (* indicates default setting) DAC Clocks Slave Slave Slave Master DAC Clocks N/A N/A N/A Master UG-040 Evaluation Board User Guide ROTARY AND DIP SWITCH SETTINGS 08411-017 SPDIF_RX_8416 HDR1_DSDATA2 SPDIF_RX_8416 HDR1_DSDATA2 HDR1_DSDATA2 N/A N/A ZERO DATA HDR1_DSDATA1 HDR1_DSDATA2 DAC_TDM_OUT DAC_TDM_OUT Aux ADC1 input TRISTATE SPDIF_RX_8416 SPDIF_RX_8416 HDR1_DSDATA1 HDR1_DSDATA1 HDR1_DSDATA1 N/A N/A ZERO DATA HDR1_DSDATA1 HDR1_DSDATA1 HDR1_DSDATA1 HDR1_DSDATA1 HDR1_DSDATA1 TRISTATE Stereo Stereo Stereo Stereo Stereo N/A N/A Stereo/TDM Stereo Stereo TDM Dual- Line TDM DAC aux mode Stereo/TDM TRISTATE DAC_TDM_OUT Aux DAC2 output HDR1_DSDATA3 Aux ADC2 input TRISTATE SPDIF_RX_8416 HDR1_DSDATA4 HDR1_DSDATA4 HDR1_DSDATA4 SPDIF_RX_8416 N/A N/A ZERO DATA HDR1_DSDATA1 HDR1_DSDATA4 SPDIF_RX_8416 HDR1_DSDATA3 HDR1_DSDATA3 SPDIF_RX_8416 HDR1_DSDATA3 N/A N/A ZERO DATA HDR1_DSDATA1 HDR1_DSDATA3 0* 1 2 3 4 5 6 7 8 9 A B C D E F Figure 18. Settings Chart 2 Rev. 0 | Page 9 of 32 Input Input Input Output Output Input TRISTATE Input Input Input Input Input Input TRISTATE Position-7 Off* On Off On ADC Serial Format Stereo Stereo TDM ADC Aux (see note) HDR1_ ASDATA1 ASDATA1 ASDATA2 ASDATA1 ASDATA1 TRISTATE Output Output Input Input TRISTATE Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input HDR1_ ASDATA1 Output Output Output Output HDR1_ ASDATA2 Output Output Input Input DIP Switch S3 Position: Position-8 Off* ADC1 Data Stream ASDATA1 is sourced to the SPDIF_Tx_8406. On ADC2 Data Stream ASDATA2 is sourced to the SPDIF_Tx_8406. DIP Switch S3 Position: Position-6 Position-7 Off* Off* Off On On Off On On NOTE: ADC A UX mode overrides the DAC data configuration rotary Switch S2 setting. Position-6 Off* Off On On DIP Switch S3 Position: Input Input Input Input Input Input Input Input Input Input ADC1 (ASDATA1) Output Output Output Output HDR1_ ASDATA2 ASDATA2 ASDATA2 ADC TDM input stream ADC TDM input stream Output Input Input Input Input Input N/A N/A Input Input Input ***** Column content indicates the direction of the DAC data pins and corresponding HDR1 connector DAC data pins ******* DAC2 (DSDATA2) DAC3 (DSDATA3) DAC4 (DSDATA4) HDR 1_DSDATA1 S4 Position DAC1 (DSDATA1) 0* 1 2 3 4 5 6 7 8 9 A B C D E F ***** Signal sources to the DAC data lines (DSDATA1/2/3/4) fill the columns, column header is the destination ****** S4 Position DAC Serial Format DAC1 (DSDATA1) DAC2 (DSDATA2) DAC3 (DSDATA3) DAC4 (DSDATA4) Input Input Output Input Input N/A Input Input N/A Input HDR 1_DSDATA3 Output Output Output Input Input N/A Input Input Input N/A HDR 1_DSDATA4 N/A Master Master Master Master Master SPDIF_Rx Data N/A Master Master Master Master Master HDR 1 Data ADC2 (ASDATA2) Output Output Input Input Description (HDR1 ADC Data Source Selection) HDR1 Connector ADC Data Lines ASDATA1 and ASDATA2 receive corresponding ADC data stream HDR1 Connector ADC Data Line ASDATA1 receive ADC2 data line ASDATA2 HDR1 Connector ADC Data Line ASDATA1 receive ADC TDM out data stream HDR1 Connector ADC Data Line ASDATA1 receive ADC TDM out data stream Output Input Input Output Output Input N/A Input N/A Input Input HDR 1_DSDATA2 Tristate all DAC data lines, DSDATA1, DSDATA2, DSDATA3, and DSDATA4 Source zero data to all eight DAC channels HDR1 Connector Signal HDR1_D SDATA1 drives all four DAC pairs HDR1 Connector Data Lines DSDATA1, DSDATA2... so on drive corresponding DAC data lines HDR1 Connector Data Lines DSDATA1, DSDATA2... so on drive/receive corresponding DAC data lines in TDM mode HDR1 Connector Data Lines DSDATA1, DSDATA2... so on drive/receive corresponding DAC data lines in TDM mode HDR1 Connector Data Lines DSDATA1, DSDATA2... so on drive/receive corresponding DAC data lines in TDM mode SPDIF_RX_8416 stereo data to all eight DAC channels SPDIF_RX_8416 stereo data to DAC1 only, rest DACs2/3/4 data from HDR1 connector SPDIF_RX_8416 data to DAC2 only, rest DACs1/3/4 data from HDR1 connector SPDIF_RX_8416 data to DAC3 only, rest DACs1/2/4 data from HDR1 connector SPDIF_RX_8416 data to DAC4 only, rest DACs1/2/3 data from HDR1 connector Description 08411-018 Rotary hex Switch S4 selects the AD193x DAC serial data source. The DAC data source can be either SPDIF Receiver CS8416 or can be provided by the Header Connector HDR1. It is important to note that the DAC data source should be in sync with the DAC serial port clock source (set by DIP Switch S2, Positions [5:6]). DIP Switch S3 routes the ADC serial data among AD193x, SPDIF Transmitter CS8406, and Header Connector HDR1 in stereo, TDM, and aux mode. DAC and ADC Se rial Data (DSDATA/ASDATA) Source Selection and Routing (Switch S4 and S witch S3) Evaluation Board User Guide UG-040 UG-040 Evaluation Board User Guide SCHEMATICS AND ARTWORK 08411-019 Figure 19. Board Schematics, Page 1—ADC Buffer Circuits Rev. 0 | Page 10 of 32 Evaluation Board User Guide UG-040 08411-020 Figure 20. Board Schematics, Page 2—Serial Digital Audio Interface Headers with MCLK Direction Switching Rev. 0 | Page 11 of 32 UG-040 Evaluation Board User Guide 08411-021 Figure 21. Board Schematics, Page 3—S/PDIF Receive and Transmit Interfaces Rev. 0 | Page 12 of 32 Evaluation Board User Guide UG-040 08411-022 Figure 22. Board Schematics, Page 4—Serial Digital Audio Routing and Control CPLD Rev. 0 | Page 13 of 32 UG-040 Evaluation Board User Guide 08411-023 Figure 23. Board Schematics, Page 5—AD1937/AD1939 with MCLK Selection Jumpers Rev. 0 | Page 14 of 32 UG-040 08411-024 Evaluation Board User Guide Figure 24. Board Schematics, Page 6—Daughter Card Interface, Useful as Test Points Rev. 0 | Page 15 of 32 UG-040 Evaluation Board User Guide 08411-025 Figure 25. Board Schematics, Page 7—DAC Buffer Circuits Rev. 0 | Page 16 of 32 UG-040 08411-026 Evaluation Board User Guide Figure 26. Board Schematics, Page 8—SPI and I2C Control Interface Rev. 0 | Page 17 of 32 Evaluation Board User Guide 08411-027 UG-040 Figure 27. Board Schematics, Page 9—Power Supply Rev. 0 | Page 18 of 32 UG-040 08411-028 Evaluation Board User Guide Figure 28. Top Assembly Layer Rev. 0 | Page 19 of 32 Evaluation Board User Guide 08411-029 UG-040 Figure 29. Bottom Assembly Layer Rev. 0 | Page 20 of 32 Evaluation Board User Guide UG-040 CPLD CODE MODULE TITLE IF_Logic 'AD1939 EVB Input Interface Logic' //=================================================================================== // FILE: // REVISION DATE: AD1939_pld_revE.abl // REVISION: // DESCRIPTION: 04-16-09 (rev-E) E //=================================================================================== LIBRARY 'MACH'; "INPUTS ---------------------------------------------------------------------------- // AD1939 CODEC pins DSDATA1,DSDATA2 pin 86, 87 istype 'com'; DSDATA3,DSDATA4 pin 91, 92 istype 'com'; DBCLK,DLRCLK pin 85, 84 istype 'com'; ASDATA1,ASDATA2 pin 80, 81 istype 'com'; ABCLK,ALRCLK pin 78, 79 istype 'com'; // 25-pin header connector HDR1 pins HDR1_DSDATA1 pin 20 istype 'com'; HDR1_DSDATA2 pin 19 istype 'com'; HDR1_DSDATA3 pin 17 istype 'com'; HDR1_DSDATA4 pin 16 istype 'com'; HDR1_DBCLK pin 21 istype 'com'; HDR1_DLRCLK pin 22 istype 'com'; HDR1_ASDATA1 pin 29 istype 'com, buffer'; HDR1_ASDATA2 pin 28 istype 'com, buffer'; HDR1_ABCLK pin 30 istype 'com'; HDR1_ALRCLK pin 31 istype 'com'; // 25-pin header connector HDR2 pins HDR2_DSDATA1 pin HDR2_DSDATA2 pin 36 istype 'com'; 37 istype 'com'; HDR2_DSDATA3 pin 35 istype 'com'; HDR2_DSDATA4 pin 34 istype 'com'; HDR2_DBCLK pin 41 istype 'com'; HDR2_DLRCLK pin 42 istype 'com'; HDR2_ASDATA1 pin 44 istype 'com'; HDR2_ASDATA2 pin 43 istype 'com, buffer'; HDR2_ABCLK pin 47 istype 'com'; HDR2_ALRCLK pin 48 istype 'com'; // S/PDIF Rx CS8414 pins SDATA_8416 pin 61 istype 'com'; Rev. 0 | Page 21 of 32 UG-040 Evaluation Board User Guide BCLK_8416 pin 60 istype 'com'; LRCLK_8416 pin 59 istype 'com'; SOMS_RX,SFSEL1_RX,SFSEL0_RX,RMCKF_RX pin 66,67,64,65 istype 'com'; // S/PDIF Tx CS8404 pins SDATA_8406 'com'; pin 50 istype BCLK_8406,LRCLK_8406 pin 53, 54 istype 'com'; MCLK_8406 'com'; pin 49 istype APMS_TX,SFMT1_TX,SFMT0_TX pin 55,56,58 istype 'com'; CPLD_MCLK 'com'; pin 89 istype // AD1939 SPI port pins //CCLK,CDATA,CLATCH pin 84, 83, 85 istype 'com'; //COUT pin 82 istype 'com'; //CLATCH2,CLATCH3,CLATCH4 pin 86, 56, 4 istype 'com'; //CONTROL_ENB 'com'; pin 81 istype S/PDIF_RESET_OUT 'com'; pin 69 istype // Switch S1, S2, S3 and S4 pins ADC_CLK_OFF 'com'; pin 93 istype // S2-1 ADC_CLK_SRC1 pin 94 istype 'com'; // S2-2 ADC_CLK_SRC0 pin 97 istype 'com'; // S2-3 DAC_CLK_OFF 'com'; pin 98 istype // S2-4 DAC_CLK_SRC1 pin 99 istype 'com'; DAC_CLK_SRC0 pin 100 istype 'com'; S/PDIF_MCLK_RATE pin 3 istype 'com'; // S2-7 S/PDIF_RESET_IN pin 4 istype 'com'; MODE11,MODE12,MODE13,MODE14 STAND_ALONE,MODE22,MODE23,MODE24 // S2-8 pin 5,6,8,9 istype 'com'; // S4 pin 10,11,14,15 istype 'com'; // S5 "NODES I_DSDATA1, I_DSDATA2, I_DSDATA3, I_DSDATA4 node istype 'com'; I_DBCLK, I_DLRCLK node istype 'com'; I_ASDATA1, I_ASDATA2 node istype 'com, buffer'; I_ABCLK, I_ALRCLK node istype 'com'; Qdivide // S2-5 // S2-6 node istype 'reg, buffer'; Rev. 0 | Page 22 of 32 Evaluation Board User Guide UG-040 //================================================================================ "MACROS // Switch S3, DIP POSITIONS 6 AND 7 ADC_HDR_NORMAL = ( MODE22 & MODE23); ADC_HDR_DATA2_DATA1 = ( MODE22 & !MODE23); ADC_HDR_TDM = (!MODE22 & MODE23); ADC_HDR_AUX = (!MODE22 & !MODE23); S/PDIF_OUT_MUX = MODE24; // Hex Switch S4 // S4 position 0, DAC_RX_ALL = ( MODE14 & MODE13 & MODE12 & MODE11); // S4 position 1, DAC_RX_1 = ( MODE14 & MODE13 & MODE12 & !MODE11); // S4 position 2, DAC_RX_2 = ( MODE14 & MODE13 & DAC_RX_3 = ( MODE14 & MODE13 & !MODE12 & MODE11); // S4 position 3, !MODE12 & !MODE11); // S4 position 4, DAC_RX_4 = ( MODE14 & !MODE13 & MODE12 & MODE11); // S4 position 5, NA1 = ( MODE14 & !MODE13 & NA2 = ( MODE14 & !MODE13 & MODE12 & !MODE11); // S4 position 6, !MODE12 & MODE11); // S4 position 7, DAC_DATA_ZERO = ( MODE14 & !MODE13 & !MODE12 & !MODE11); // S4 position 8, DAC_HDR1_ALL = ( !MODE14 & MODE13 & DAC_HDR1_IND = ( !MODE14 & MODE13 & MODE12 & MODE11); // S4 position 9, MODE12 & !MODE11); // S4 position A, DAC_HDR1_TDM = ( !MODE14 & MODE13 & !MODE12 & MODE11); Rev. 0 | Page 23 of 32 UG-040 Evaluation Board User Guide // S4 position B, DAC_DUAL_TDM = ( !MODE14 & MODE13 & DAC_HDR1_AUX = ( !MODE14 & !MODE13 & !MODE12 & !MODE11); // S4 position C, MODE12 & MODE11); // S4 position D, NA3 = ( !MODE14 & !MODE13 & MODE12 & !MODE11); // S4 position E, NA4 = ( !MODE14 & !MODE13 & !MODE12 & MODE11); // S4 position F, DAC_DATA_HIZ = ( !MODE14 & !MODE13 & !MODE12 & !MODE11); // Switch S2 DAC_S/PDIF = (DAC_CLK_SRC1 & DAC_CLK_SRC0); DAC_HDR1 = (DAC_CLK_SRC1 & !DAC_CLK_SRC0); DAC_ADC = (!DAC_CLK_SRC1 & DAC_CLK_SRC0); DAC_DAC = (!DAC_CLK_SRC1 & !DAC_CLK_SRC0); ADC_S/PDIF = (ADC_CLK_SRC1 & ADC_CLK_SRC0); ADC_HDR1 = (ADC_CLK_SRC1 & !ADC_CLK_SRC0); ADC_ADC = (!ADC_CLK_SRC1 & ADC_CLK_SRC0); ADC_DAC = (!ADC_CLK_SRC1 & !ADC_CLK_SRC0); "==================================================================================== EQUATIONS S/PDIF_RESET_OUT = S/PDIF_RESET_IN; // Configuration of the CS8416, changes active on reset, BCLK_8416 and LRCLK_8416 are bidirectional signals. SOMS_RX = DAC_S/PDIF; // SOMS = Serial Output Master/Slave Select SFSEL1_RX = 0; //DIR_RJ # DIR_RJ16; // SFSEL1 = Serial Format Select 1 SFSEL0_RX = 1; //DIR_I2S # DIR_DSP; // SFSEL0 = Serial Format Select 0 RMCKF_RX = !S/PDIF_MCLK_RATE; // RMCKF = Receive Master Clock Frequency // M0_8414 = (0 # !DAC_S/PDIF); // M1_8414 = 1; // M2_8414 = 0; Rev. 0 | Page 24 of 32 Evaluation Board User Guide // UG-040 M3_8414 = 0; // CS8404 Tx interface mode select APMS_TX = 0; // Tx serial port is always slave in this application SFMT1_TX = 0; // Tx data format is I2S always SFMT0_TX = 1; // M0_8404 = 0; // M1_8404 = 0; // M2_8404 = 1; // I2S format only // divide 256Fs clock by 2 for 128Fs clock to the S/PDIF Tx // Qdivide.clk = CPLD_MCLK; // Qdivide.d = !Qdivide; // MCLK_8406 = Qdivide; MCLK_8406 = CPLD_MCLK; BCLK_8406 = I_ABCLK; LRCLK_8406 = I_ALRCLK; SDATA_8406 = (ASDATA1 & S/PDIF_OUT_MUX) # (ASDATA2 & !S/PDIF_OUT_MUX); // For SPI mode, let external port drive the SPI port DBCLK.oe = (DAC_S/PDIF # DAC_HDR1 # DAC_ADC # !DAC_DAC) & (DAC_CLK_OFF); DLRCLK.oe = (DAC_S/PDIF # DAC_HDR1 # DAC_ADC # !DAC_DAC) & (DAC_CLK_OFF); ABCLK.oe = (ADC_S/PDIF # ADC_HDR1 # !ADC_ADC # ADC_DAC) & (ADC_CLK_OFF); ALRCLK.oe = (ADC_S/PDIF # ADC_HDR1 # !ADC_ADC # ADC_DAC) & (ADC_CLK_OFF); HDR1_DBCLK.oe = (DAC_S/PDIF # !DAC_HDR1 # DAC_ADC # DAC_DAC); HDR1_DLRCLK.oe = (DAC_S/PDIF # !DAC_HDR1 # DAC_ADC # DAC_DAC); HDR1_ABCLK.oe = (ADC_S/PDIF # !ADC_HDR1 # ADC_ADC # ADC_DAC); HDR1_ALRCLK.oe = (ADC_S/PDIF # !ADC_HDR1 # ADC_ADC # ADC_DAC); BCLK_8416.oe = (!DAC_S/PDIF); LRCLK_8416.oe = (!DAC_S/PDIF); BCLK_8416 = I_DBCLK; LRCLK_8416 = I_DLRCLK; DSDATA1.oe = (!DAC_DATA_HIZ); DSDATA2.oe = (!(DAC_HDR1_TDM # DAC_DUAL_TDM # DAC_DATA_HIZ)); TDM-daisy chain mode DSDATA3.oe //DSDATA2 is output in DAC = (!DAC_DATA_HIZ); DSDATA4.oe = (!(DAC_DUAL_TDM # ADC_HDR_AUX # DAC_HDR1_AUX # DAC_DATA_HIZ)); TDM-OUT IN DUAL LINE DAC TDM MODE ASDATA2.oe = (ADC_HDR_TDM); //ASDATA2 is input in ADC TDM mode HDR1_DSDATA2.oe = (DAC_HDR1_TDM # DAC_DUAL_TDM); Rev. 0 | Page 25 of 32 // SECOND UG-040 Evaluation Board User Guide HDR1_DSDATA4.oe = (DAC_DUAL_TDM # ADC_HDR_AUX # DAC_HDR1_AUX); HDR1_ASDATA2.oe = (!ADC_HDR_TDM); DBCLK = I_DBCLK; DLRCLK = I_DLRCLK; ABCLK = I_ABCLK; ALRCLK = I_ALRCLK; DSDATA1 = (HDR1_DSDATA1 & (DAC_HDR1_ALL # DAC_HDR1_IND # DAC_RX_2 # DAC_RX_3 # DAC_RX_4 # DAC_HDR1_TDM # DAC_DUAL_TDM # ADC_HDR_AUX)) # (SDATA_8416 & (DAC_RX_ALL # DAC_RX_1)) # (0 & DAC_DATA_ZERO); DSDATA2 = (HDR1_DSDATA1 & DAC_HDR1_ALL) # (HDR1_DSDATA2 & (DAC_HDR1_IND # ADC_HDR_AUX # DAC_HDR1_AUX # DAC_RX_1 # DAC_RX_3 # DAC_RX_4)) # (SDATA_8416 & (DAC_RX_ALL # DAC_RX_2)) # (0 & DAC_DATA_ZERO); DSDATA3 = (HDR1_DSDATA1 & (DAC_HDR1_ALL)) # (HDR1_DSDATA3 & (DAC_HDR1_IND # DAC_DUAL_TDM # ADC_HDR_AUX # DAC_HDR1_AUX # DAC_RX_1 # DAC_RX_2 # DAC_RX_4)) # (SDATA_8416 & (DAC_RX_ALL # DAC_RX_3)) # (0 & DAC_DATA_ZERO); DSDATA4 = (HDR1_DSDATA1 & (DAC_HDR1_ALL)) # (HDR1_DSDATA4 & (DAC_HDR1_IND # DAC_RX_1 # DAC_RX_2 # DAC_RX_3)) # (SDATA_8416 & (DAC_RX_ALL # DAC_RX_4)) # (0 & DAC_DATA_ZERO); HDR1_DBCLK = I_DBCLK; HDR1_DLRCLK = I_DLRCLK; HDR1_ABCLK = I_ABCLK; HDR1_ALRCLK = I_ALRCLK; HDR1_ASDATA1 = (ASDATA1 & (ADC_HDR_NORMAL # ADC_HDR_TDM # ADC_HDR_AUX # DAC_HDR1_AUX )) # (ASDATA2 & ADC_HDR_DATA2_DATA1); HDR1_ASDATA2 = ASDATA2; ASDATA2 = HDR1_ASDATA2; HDR1_DSDATA2 = DSDATA2; HDR1_DSDATA4 = DSDATA4; // Internal node signals I_DBCLK = (BCLK_8416 & DAC_S/PDIF) # (HDR1_DBCLK & DAC_HDR1) # (DBCLK & DAC_DAC) # (I_ABCLK & DAC_ADC); I_DLRCLK = (LRCLK_8416 & DAC_S/PDIF) # (HDR1_DLRCLK & DAC_HDR1) # (DLRCLK & DAC_DAC) # (I_ALRCLK & DAC_ADC); I_ABCLK = (BCLK_8416 & ADC_S/PDIF) # (HDR1_ABCLK & ADC_HDR1) # (ABCLK & ADC_ADC) # (I_DBCLK & ADC_DAC); I_ALRCLK = (LRCLK_8416 & ADC_S/PDIF) # (HDR1_ALRCLK & ADC_HDR1) # (ALRCLK & ADC_ADC) # (I_DLRCLK & ADC_DAC); "==================================================================================== END IF_Logic Rev. 0 | Page 26 of 32 Evaluation Board User Guide UG-040 ORDERING INFORMATION BILL OF MATERIALS Table 1. Qty 18 50 9 12 8 16 1 32 3 12 Designator C85, C90 to C94, C101 to C103, C107, C108, C110, C115, C116, C121, C127, C132, C134 C1, C2, C5, C7 to C10, C20, C21, C28, C29, C38, C42, C48 to C51, C58 to C60, C62, C64, C69, C73, C76, C79, C82, C97, C99, C112, C118, C122, C128, C135, C146, C147, C149, C151, C155, C156, C158, C162, C168, C174, C176, C177, C193, C194, C197, C203 C37, C65, C67, C83, C88, C124, C129, C157, C160 R28, R30, R51, R59, R166, R167, R169, R172, R185, R189, R212, R214 C68, C71, C87, C89, C130, C138, C159, C161 R24, R31, R44, R60, R77, R84, R93, R106, R136, R149, R159, R170, R180, R191, R207, R217 C84 R6, R7, R13, R14, R18, R20, R40, R43, R47 to R49, R54, R55, R63, R64, R74, R78, R80, R82, R158, R164, R186, R224 to R227, R232 to R237 C6, C39, C40 5 C15 to C17, C81, C86, C95, C98, C170, C175, C178, C180, C183 C104, C106, C109, C111, C117, C123, C140 to C145 C3, C4, C74, C96, C126 4 C61, C77, C113, C150 1 R117 3 9 1 D1, D3, D4 C23, C33, C43, C55, C114, C166, C184, C188, C200 C36 2 C153, C154 8 R76, R81, R90, R101, R134, R141, R157, R168 R1, R4 12 2 10 R91, R94, R98, R99, R108, R109, R114, R115, R118, R123 Description Multilayer ceramic capacitor,16 V, X7R (0402) Manufacturer Panasonic EC Part Number ECJ-0EX1C104K Multilayer ceramic capacitor, 50 V, X7R (0603) Panasonic EC ECJ-1VB1H104K Multilayer ceramic capacitor, 50 V, NP0 (0603) Chip resistor, 100 kΩ, 1%, 125 mW, thick film (0603) Panasonic EC ECJ-1VC1H102J Panasonic EC ERJ-3EKF1003V Panasonic EC ECJ-1VC1H101J Panasonic EC ERJ-3EKF1000V Panasonic EC EEE-FC1C101P Panasonic EC ERJ-3EKF1002V TDK Corp C1608C0G1E103J Panasonic EC ECJ-1VC2A100D Kemet C0402C100J5GACTU Panasonic EC EEE-FC1C100R Panasonic EC ECJ-1VC1H121J Panasonic EC ERJ-3EKF1001V ON Semiconductor Murata Electronics 1SMB15AT3G GRM1885C1H222JA01D Murata ENA GRM21B5C1H223JA01L Panasonic EC ECJ-1VC1H220J Panasonic EC ERJ-3EKF2370V Panasonic EC ERJ-3EKF2430V Rohm MCR01MZPF24R9 Multilayer ceramic capacitor, 50 V, NP0 (0603) Chip resistor, 100 kΩ, 1%, 100 mW, thick film (0603) Aluminum electrolytic capacitor, 100 μF, 16 V, FC 105 deg, SMD_E Chip resistor, 10 kΩ, 1%, 125 mW, thick film (0603) Multilayer ceramic capacitor, 25 V, NP0 (0603) Multilayer ceramic capacitor, 100 V, NP0 (0603) Multilayer ceramic capacitor, 50 V, NP0 (0402) Aluminum electrolytic capacitor, 16 V, FC 105 deg, SMD_B Multilayer ceramic capacitor, 50 V NP0 (0603) Chip resistor, 1 kΩ, 1% 125 mW thick film (0603) TVS Zener, 15 V, 600 W, SMB Multilayer ceramic capacitor, 50 V, NP0 (0603) Multilayer ceramic capacitor, 50 V, NP0 (0805) Multilayer ceramic capacitor, 50 V, NP0 (0603) Chip resistor, 237 Ω, 1%, 125 mW, thick film (0603) Chip resistor, 243 Ω, 1%, 100 mW, thick film (0603) Chip resistor, 24.9 Ω, 1%, 63 mW, thick film (0402) Rev. 0 | Page 27 of 32 UG-040 Qty 16 3 Designator R56, R57, R65, R66, R88, R89, R140, R154, R179, R183, R213, R216, R228 to R231 C24, C25, C31, C34, C44, C45, C53, C56, C167, C169, C181, C185, C189, C190, C198, C201 R3, R11, R58 1 C125 4 R5, R52, R53, R75 1 C120 33 R21, R22, R26, R27, R33 to R35, R37 to R39, R41, R46, R50, R62, R68, R69, R71, R173, R176, R182, R184, R193, R195, R197, R199, R202, R204, R209, R211, R219 to R221, R223 R23, R25, R32, R36, R42, R45, R61, R70, R177, R181, R192, R198, R205, R208, R218, R222 R129 16 16 1 23 3 C11, C13, C14, C26, C30, C46, C52, C63, C66, C72, C75, C80, C105, C119, C133, C139, C148, C152, C164, C172, C179, C191, C196 C12, C18, C19 1 R12 4 R83, R96, R148, R163 20 1 R103, R104, R110 to R112, R116, R119, R124, R126 to R128, R130 to R132, R142 to R147 R8 to R10, R15 to R17, R19, R92, R95, R100, R105, R113, R120, R125, R133, R135, R139, R153, R155, R156, R160, R174, R175, R178, R187, R188, R190, R194, R196, R200, R201, R203, R206, R210, R215 C131 1 R138 16 4 R72, R73, R79, R85 to R87, R97, R107, R121, R122, R137, R150 to R152, R165, R171 C78, C137, C171, C195 1 R2 1 2 1 U11 U19, U26 R29 35 Evaluation Board User Guide Description Chip resistor, 24.9 Ω, 1%, 100 mW, thick film (0603) Manufacturer Rohm Part Number MCR03EZPFX24R9 Multilayer ceramic capacitor, 100 V, NP0 (0603) Murata ENA GRM1885C2A301JA01D Chip resistor, 374 Ω, 1%, 100 mW, thick film (0603) Multilayer ceramic capacitor, 50 V, NP0 (0603) Chip resistor, 392 Ω, 1%, 100 mW, thick film (0603) Multilayer ceramic capacitor, 16 V, ECH-U (1206) Chip resistor, 3.01 kΩ, 1%, 100 mW, thick film (0603) Rohm MCR03EZPFX3740 Panasonic EC ECJ-1VC1H391J Rohm MCR03EZPFX3920 Panasonic EC ECH-U1C393JB5 Rohm MCR03EZPFX3011 Chip resistor, 3.09 kΩ, 1%, 100 mW, thick film (0603) Rohm MCR03EZPFX3091 Chip resistor, 3.32 kΩ, 1%, 100 mW, thick film (0603) Aluminum electrolytic capacitor, 16 V, FC 105 deg, SMD_D Rohm MCR03EZPFX3321 Panasonic EC EEE-FC1C470P Panasonic EC EEE-FC1E470P Rohm MCR03EZPFX4990 Panasonic EC ERJ-3EKF4992V Rohm MCR01MZPF49R9 Chip resistor, 49.9 Ω, 1%, 100 mW, thick film (0603) Panasonic EC ERJ-3EKF49R9V Multilayer ceramic capacitor, 25 V, NP0 (0603) Chip resistor, 562 Ω, 1%, 125 mW, thick film (0603) Chip resistor, 5.76 kΩ, 1%, 125 mW, thick film (0603) TDK Corp C1608C0G1E562J Panasonic EC ERJ-3EKF5620V Panasonic EC ERJ-3EKF5761V Panasonic EC ECJ-1VC2A680J Rohm MCR03EZPFX7150 NXP Semi Texas Instruments Panasonic EC 74HC04D-T SN74LV125AD ERJ-3EKF75R0V Aluminum electrolytic capacitor FC 105 deg SMD_E Chip resistor, 499 Ω, 1%, 100 mW, thick film (0603) Chip resistor, 49.9 Ω, 1%, 100 mW, thick film (0603) Chip resistor, 49.9 Ω, 1%, 63 mW, thick film (0402) Multilayer ceramic capacitor, 100 V, NP0 (0603) Chip resistor, 715 Ω, 1%, 100 mW, thick film (0603) IC inverter hex, TTL/LSTTL, 14 SOIC IC buffer, quad three-state, 14 SOIC Chip resistor, 75 Ω, 1%, 100 mW, thick film Rev. 0 | Page 28 of 32 Evaluation Board User Guide Qty Designator 1 R67 16 1 C22, C27, C32, C35, C41, C47, C54, C57, C165, C173, C182, C186, C187, C192, C199, C202 Y1 1 1 1 1 U15 U23 U1 J2 1 J3 1 J4 2 1 1 2 1 1 6 1 2 4 1 UG-040 Manufacturer Part Number Rohm MCR03EZPFX90R9 Murata ENA GRM1885C1H911JA01D Crystal, 12.288 MHz, SMT, 10 pF Abracon Corp J22, J23 U8 U13 D2, D5 S1 SW1 L2 to L7 L1 J1, J14 J15 to J18 J19 Four ADC/eight DAC with PLL, 192 kHz Microprocessor voltage supervisor Voltage regulator, low dropout 5-way binding post, black, uninsulated base TH 5-way binding post, mini, green, uninsulated base TH 5-way binding post, mini, red, uninsulated base TH SMA receptacle straight PCB mount 192 kHz digital audio receiver, 28-TSSOP 192 kHz digital audio, S/PDIF transmitter Passivated rectifier, 1 A 50 V MELF Switch slide, DP3T, PC MNT, L = 4 mm DPDT slide switch, vertical Chip ferrite bead, 600 Ω at 100 MHz Chip ferrite bead, 600 Ω at 100 MHz 10-way shrouded polarized header 16-way unshrouded, not populated Connector header, 0.100 dual STR, 72 POS Analog Devices Analog Devices Analog Devices Deltron Components Deltron Components Deltron Components Amp-RF Division Cirrus Logic Cirrus Logic Micro Commercial E-Switch E-Switch TDK Steward 3M 3M Sullins ABM3B-12.288MHZ-101-U-T AD1939YSTZ ADM811RARTZ ADP3303ARZ-3.3 552-0100 BLK 2 J20, J26 Connector header, 0.100 dual STR, 72 POS Sullins 4 J5 to J8 Connector header, 0.100 dual STR, 72 POS Sullins 2 16 16-position rotary switch hex 2-pin header, unshrouded jumper, 0.10"; use shunt Tyco 881545-2 3-position SIP header APEM Sullins 1 S4, S5 JP4, JP11 to JP14, JP17, JP18, JP20 to JP22, JP24, JP26, JP28 to JP31 JP1 to JP3, JP5 to JP10, JP15, JP16, JP19, JP23, JP25, JP27 U16 2 D8, D11 2 D6, D9 2 D7, D10 2 U2, U3 6 2 8 1 1 J10, J11, J13, J21, J27, J28 R161, R162 U6, U9, U12, U14, U17, U20, U24, U25 R102 U21 2 J9, J12 15 Description (0603) Chip resistor, 90.9 Ω, 1%, 100 mW, thick film (0603) Multilayer ceramic capacitor, 50 V, NP0 (0603) Complex programmable logic device (CPLD), HI PERF E2CMOS PLD Green, diffused, 10 millicandela, 565 nm (1206) Red, diffused, 6.0 millicandela, 635 nm (1206) Yellow, diffused, 4.0 millicandela, 585 nm (1206) 3-terminal adjustable voltage regulator, DPak Stereo mini jack SMT Resistor network, bussed 8 res, 9 pin Dual bipolar/JFET audio op amp Not populated 12.288 MHz fixed SMD oscillator, 1.8 V dc to 3.3 V dc RCA jack PCB TH mount R/A yellow Rev. 0 | Page 29 of 32 Sullins 552-0400 GRN 552-0500 RED 901-144-8RFX CS8416-CZZ CS8406-CZZ DL4001-TP EG2305 EG2207 MPZ1608S601A HZ0805E601R-10 N2510-6002RB N/A PBC10DAAN; or cut PBC36DAAN PBC13DAAN; or cut PBC36DAAN PBC06DAAN; or cut PBC36DAAN PT65503 PBC02SAAN; or cut PBC36SAAN PBC03SAAN; or cut PBC36SAAN LC4128V-75TN100C Lattice Semiconductor Lumex Opto SML-LX1206GW-TR Lumex Opto SML-LX1206IW-TR CML Innovative Tech STMicroelectronics CMD15-21VYD/TR8 CUI CTS Analog Devices SJ-3523-SMT 773091103 OP275GSZ N/A Abracon Corp N/A AP3S-12.288MHz-F-J-B Connect-Tech Products CTP-021A-S-YEL LM317MDT-TR UG-040 Evaluation Board User Guide Qty 1 Designator U10 Description 110 Ω AES/EBU transformer 2 1 2 2 U18, U22 U4 SW2, SW3 S2, S3 1 1 S6 U5 1 69 U7 TP1 to TP69 Buffer, three-state single gate Octal, three-state buffer/driver SPDT slide switch, PC mount 8-position, SPST SMD switch, flush, actuated Tact switch, 6 mm, gull wing 15 Mb/sec fiber optic receiving module with shutter 15 Mb/sec fiber optic transmit module, Mini test point, white, 0.1 inch, OD 1 Q1 100 V, medium power, low saturation transistor, SOT223, NPN Rev. 0 | Page 30 of 32 Manufacturer Scientific Conversion Texas Instruments Texas Instruments E-Switch CTS Part Number SC937-02 SN74LVC1G125DRLR SN74LVC541ADBR EG1218 219-8LPST Tyco/Alcoswitch Toshiba FSM6JSMA TORX147L(F,T) Toshiba Keystone Electronics Zetex TOTX147L(F,T) 5002 ZX5T953GTA Evaluation Board User Guide UG-040 NOTES Rev. 0 | Page 31 of 32 UG-040 Evaluation Board User Guide NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. Legal Terms and Conditions By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. 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Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and Customer hereby submits to the personal jurisdiction and venue of such courts. The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed. ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. UG08411-0-2/10(0) Rev. 0 | Page 32 of 32