165 MHz, High Performance HDMI Transmitter ADV7513 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM APPLICATIONS Gaming consoles PCs DVD players and recorders Digital set-top boxes A/V receivers CEC CONTROLLER/ BUFFER ADV7513 HDCP KEYS SPDIF I2S[3:0] MCLK CEC CEC_CLK AUDIO DATA CAPTURE LRCLK HDCP ENCRYPTION 4:2:2 SCLK D[23:0] VSYNC HSYNC DE CLK VIDEO DATA CAPTURE SCL TX0+/TX0– TX1+/TX1– TMDS OUTPUTS TX2+/TX2– HPD INT SDA 4:4:4 AND COLOR SPACE CONVERTER REGISTERS AND CONFIGURATION LOGIC TXC+/TXC– I2C SLAVE HDCP AND EDID MICROCONTROLLER I2C MASTER DDCSDA DDCSCL 10225-001 General Incorporates HDMI v1.4 features, including 3D video support 165 MHz supports all video formats up to 1080p and UXGA Supports gamut metadata packet transmission Integrated CEC buffer/controller Compatible with DVI v1.0 and HDCP v1.4 Video/audio inputs accept logic levels from 1.8 V to 3.3 V Digital video 3D video ready Programmable, 2-way color space converter Supports RGB, YCbCr, and DDR Supports ITU-656-based embedded syncs Automatic input video format timing detection (CEA-861-E) Digital audio Supports standard S/PDIF for stereo linear pulse code modulation (LPCM) or compressed audio up to 192 kHz High bit rate (HBR) audio 8-channel uncompressed LPCM I2S audio up to 192 kHz Special features for easy system design 5 V tolerant I2C and Hot Plug™ detect (HPD) I/Os, no extra device needed No audio master clock needed for supporting S/PDIF and I2S On-chip MPU with I2C master performs HDCP operations and EDID reading operations On-chip MPU reports HDMI events through interrupts and registers Figure 1. GENERAL DESCRIPTION The ADV7513 is a 165 MHz, High-Definition Multimedia Interface (HDMI®) transmitter that is ideal for DVD players/ recorders, digital set-top boxes, A/V receivers, gaming consoles, and PCs. The digital video interface contains an HDMI v1.4/DVI v1.0compatible transmitter and supports all HDTV formats. The ADV7513 supports HDMI v1.4-specific features, including 3D video. The ADV7513 also supports x.v.Color™, high bit rate (HBR) audio, and the programmable auxiliary video information (AVI) InfoFrame features. With the inclusion of HDCP, the ADV7513 allows the secure transmission of protected content as specified by the HDCP v1.4 protocol. The ADV7513 supports both S/PDIF and 8-channel I2S audio. Its high fidelity 8-channel I2S interface can transmit either stereo or 7.1 surround audio up to 768 kHz. The S/PDIF interface can carry compressed audio, including Dolby® Digital, DTS®, and THX®. Fabricated in an advanced CMOS process, the ADV7513 is provided in a 64-lead LQFP surface-mount plastic package with exposed pad and is specified over the −25°C to +85°C temperature range. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2011–2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADV7513 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ............................................................5 Applications ....................................................................................... 1 Explanation of Test Levels ............................................................5 Functional Block Diagram .............................................................. 1 ESD Caution...................................................................................5 General Description ......................................................................... 1 Pin Configuration and Function Descriptions..............................6 Revision History ............................................................................... 2 Applications Information .................................................................8 Specifications..................................................................................... 3 Design Resources ..........................................................................8 Electrical Specifications ............................................................... 3 Outline Dimensions ..........................................................................9 Ordering Guide .............................................................................9 REVISION HISTORY 5/14—Rev. A to Rev. B Change to Design Resources Section ............................................. 8 Changes to Ordering Guide ............................................................ 9 1/13—Rev. 0 to Rev. A Updated Outline Dimensions ......................................................... 9 Changes to Ordering Guide ............................................................ 9 11/11—Revision 0: Initial Version Rev. B | Page 2 of 12 Data Sheet ADV7513 SPECIFICATIONS ELECTRICAL SPECIFICATIONS Table 1. Parameter DIGITAL INPUTS Data Inputs, Video and Audio, CEC_CLK Input Voltage, High Input Voltage, Low Input Capacitance CEC_CLK Frequency 2 CEC_CLK Accuracy DDC I2C Lines (DDCSDA, DDCSCL) Input Voltage, High Input Voltage, Low I2C Lines (SDA, SCL) Input Voltage, High Input Voltage, Low CEC Pin Input Voltage, High Input Voltage, Low Output Voltage, High Output Voltage, Low HPD Pin Input Voltage, High Input Voltage, Low THERMAL CHARACTERISTICS Thermal Resistance Junction-to-Case Junction-to-Ambient Ambient Temperature DC SPECIFICATIONS Input Leakage Current POWER SUPPLY 1.8 V Supply Voltage (DVDD, AVDD, PVDD, BGVDD) 3.3 V Supply Voltage (DVDD_3V) Power-Down Current Transmitter Total Power 3 At 1.8 V At 3.3 V AC SPECIFICATIONS TMDS Output Clock Frequency TMDS Output Clock Duty Cycle Input Video Clock Frequency Input Video Data Setup Time 4 Input Video Data Hold Time4 TMDS Differential Swing Differential Output Timing Low-to-High Transition Time High-to-Low Transition Time VSYNC and HSYNC Delay From DE Falling Edge Symbol Temp Test Level 1 VIH VIL Full Full 25°C Full Full VI VI VIII VIII VIII 3 −2 VIH VIL Full Full IV IV VIH VIL Full Full VIH VIL VOH VOL Max Unit 3.5 +0.7 1.5 100 +2 V V pF MHz % 1.4 −0.3 5.5 +0.7 V V VI VI 1.4 −0.3 5.5 +0.7 V V Full Full Full Full VI VI VI VI 2.0 −0.3 2.5 −0.3 5.5 +0.8 3.63 +0.6 V V V V VIH VIL Full Full VI VI 1.3 −0.3 5.5 +0.8 V V θJC θJA Full Full Full V V V −25 +85 °C/W °C/W °C 25°C VI −1 +1 µA Full IV 1.71 1.8 1.90 V Full 25°C IV IV 3.15 3.3 3.45 300 V µA Full Full VI VI 256 1 mW mW 25°C 25°C Full Full Full 25°C IV IV IV IV IV VII 165 52 165 1.8 1.3 800 1100 MHz % MHz ns ns mV 25°C 25°C VII VII 75 75 95 95 ps ps 25°C IV 1 UI 5 IIL tVSU tVHLD Rev. B | Page 3 of 12 Min Typ 1.35 −0.3 1.0 12 20 43 +25 20 48 1200 ADV7513 Parameter To DE Rising Edge AUDIO AC TIMING SCLK Duty Cycle N/2 Is an Even Number N/2 Is an Odd Number I2S[3:0], S/PDIF Setup Time I2S[3:0], S/PDIF Hold Time LRCLK Setup Time LRCLK Hold Time I2C INTERFACE SCL Clock Frequency SDA Setup Time SDA Hold Time Setup Time for Start Condition Hold Time for Start Condition Setup Time for Stop Condition Data Sheet Temp 25°C Test Level 1 IV Min Typ 1 Max Unit UI5 IV IV IV IV IV IV 40 49 2 2 2 2 50 50 60 51 tASU tAHLD tASU tAHLD Full Full Full Full Full Full % % ns ns ns ns Full Full Full Full Full Full 400 tDSU tDHO tSTASU tSTAH tSTOSU kHz ns ns µs µs µs Symbol 100 100 0.6 0.6 0.6 See the Explanation of Test Levels section. 12 MHz crystal oscillator for default register settings. 3 1080p, 24-bit typical random pattern. 4 The video data setup and hold times are measured at 0.9 V. The relationship between the clock and data is programmable in 400 ps steps. 5 UI is the unit interval. 1 2 Rev. B | Page 4 of 12 Data Sheet ADV7513 ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS Table 2. Parameter Digital Inputs (SDA, SCL, DDCSDA, DDCSCL, HPD, PD) Audio/Video Digital Inputs (D[23:0], MCLK, CLK, LRCLK, CEC, CEC_CLK, SPDIF, I2S[3:0], SCLK, HSYNC, DE, VSYNC) Digital Output Current Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Maximum Case Temperature Rating −0.3 V to +5.5 V I. 100% production tested. II. 100% production tested at 25°C and sample tested at specified temperatures. III. Sample tested only. IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only. VI. 100% production tested at 25°C; guaranteed by design and characterization testing. VII. Limits defined by HDMI specification; guaranteed by design and characterization testing. VIII. Parameter is guaranteed by design. −0.3 V to +3.63 V 20 mA −40°C to +100°C −65°C to +150°C 150°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. B | Page 5 of 12 ADV7513 Data Sheet D11 D10 D9 DVDD D8 CLK D7 D5 D6 D4 D2 D3 D1 D0 HSYNC DE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DVDD 1 48 D12 47 D13 SPDIF 3 46 D14 MCLK 4 45 D15 I2S0 5 44 D16 I2S1 6 43 D17 I2S2 7 42 D18 41 D19 40 D20 LRCLK 10 39 D21 DVDD 11 38 D22 PVDD 12 37 D23 BGVDD 13 36 SDA R_EXT 14 35 SCL AVDD 15 34 DDCSDA HPD 16 33 DDCSCL VSYNC PIN 1 2 ADV7513 I2S3 8 TOP VIEW (Not to Scale) SCLK 9 NOTES 1. THE EXPOSED PAD IS THE ELECTRICAL GROUND FOR THE PART AND MUST BE SOLDERED TO THE PCB. 10225-002 DVDD CEC_CLK CEC DVDD_3V INT TX2– TX2+ AVDD TX1– TX1+ PD TX0+ TX0– AVDD TXC– TXC+ 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1, 11, 31, 51 2 3 4 5 6 7 8 9 10 12 13 14 15, 19, 25 16 17, 18 Mnemonic DVDD VSYNC SPDIF MCLK I2S0 I2S1 I2S2 I2S3 SCLK LRCLK PVDD BGVDD R_EXT AVDD HPD TXC−, TXC+ 20, 21 TX0−, TX0+ 22 23, 24 PD TX1−, TX1+ 26, 27 TX2−, TX2+ Type Power Input Input Input Input Input Input Input Input Input Power Power Input Power Input Differential output Differential output Input Differential output Differential output Description 1.8 V Power Supply. These pins should be filtered and as quiet as possible. Vertical Synchronization Input. S/PDIF (Sony/Philips Digital Interface) Audio Input. Audio Reference Clock Input. I2S Channel 0 Audio Data Input. I2S Channel 1 Audio Data Input. I2S Channel 2 Audio Data Input. I2S Channel 3 Audio Data Input. I2S Audio Clock Input. Left/Right Channel Signal Input. 1.8 V PLL Power Supply. 1.8 V Band Gap Power Supply. This pin sets the internal reference currents. 1.8 V Power Supply for TMDS Outputs. Hot Plug Detect Signal Input. Differential TMDS Clock Output. Differential TMDS Output Channel 0. Power-Down Control and I2C Address Selection. Differential TMDS Output Channel 1. Differential TMDS Output Channel 2. Rev. B | Page 6 of 12 Data Sheet Pin No. 28 29 30 32 33 34 35 36 37 to 50, 52, 54 to 62 53 63 64 ADV7513 Mnemonic INT DVDD_3V CEC CEC_CLK DDCSCL DDCSDA SCL SDA D[23:0] Type Output Power Input/output Input Control Control Control Control Input Description Interrupt Signal Output. 3.3 V Power Supply. CEC Data Signal. CEC Clock (Oscillator from 3 MHz to 100 MHz). Serial Port Data Clock to Sink. Serial Port Data Input/Output to Sink. Serial Port Data Clock Input. Serial Port Data Input/Output. Video Data Inputs. CLK DE HSYNC EPAD Input Input Input Power Video Input Clock. Data Enable Signal for Digital Video. Horizontal Synchronization Input. The exposed pad is the electrical ground for the part and must be soldered to the PCB. Rev. B | Page 7 of 12 ADV7513 Data Sheet APPLICATIONS INFORMATION DESIGN RESOURCES • Evaluation kits, reference design schematics, hardware and software guides, and other support documentation are available under a nondisclosure agreement (NDA). For more information, contact your local Analog Devices, Inc., sales office at www.analog.com/sales. • Other references include the following: • EIA/CEA-861-E—this technical specification document describes audio and video InfoFrames, as well as the E-EDID structure for HDMI. It is available from the Consumer Electronics Association (CEA). Rev. B | Page 8 of 12 High-Definition Multimedia Interface Specification Version 1.4, a defining document for HDMI v1.4, and the HDMI Compliance Test Specification (CTS) Version 1.3a are available from HDMI Licensing, LLC. High-Bandwidth Digital Content Protection System Revision 1.4, the defining technical specification document for HDCP Revision 1.4, is available from Digital Content Protection, LLC. Data Sheet ADV7513 OUTLINE DIMENSIONS 1.60 MAX 49 64 64 49 48 1 1.00 REF SEATING PLANE 10.20 10.00 SQ 9.80 48 1 PIN 1 EXPOSED PAD 5.30 5.20 SQ 5.10 7.50 REF SQ BOTTOM VIEW TOP VIEW 1.45 1.40 1.35 0.15 0.10 0.05 0.20 0.15 0.09 (PINS UP) (PINS DOWN) 16 33 32 17 16 33 17 32 VIEW A 0.08 COPLANARITY 7° 0° 0.50 LEAD PITCH 0.27 0.22 0.17 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BCD-HD 06-27-2012-B 0.75 0.60 0.45 12.20 12.00 SQ 11.80 Figure 3. 64-Lead Low Profile Quad Flat Package [LQFP_EP] (SW-64-2) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADV7513BSWZ 1 Temperature Range −25°C to +85°C Package Description 64-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP] Z = RoHS Compliant Part. Rev. B | Page 9 of 12 Package Option SW-64-2 ADV7513 Data Sheet NOTES Rev. B | Page 10 of 12 Data Sheet ADV7513 NOTES Rev. B | Page 11 of 12 ADV7513 Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). HDMI, the HDMI Logo, and High-Definition Multimedia Interface are trademarks or registered trademarks of HDMI Licensing LLC in the United States and other countries. ©2011–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10225-0-5/14(B) Rev. B | Page 12 of 12