CT2553PCB/CT2554PCB/CT2555PCB/CT2556PCB (7/06)

Standard Products
CT2553-PCB / 2554-PCB / 2555-PCB / 2556-PCB
Advanced Integrated MUX (AIM) Hybrid
for MIL-STD-1553 / SAE-AS15531 in PCB Style
July 14, 2006
FEATURES
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CT2553-PCB replaces DDC BUS-61553
CT2554-PCB replaces DDC BUS-61554
CT2555-PCB replaces DDC BUS-61555
CT2556-PCB replaces DDC BUS-61556
Complete integrated MUX including:
- Low power dual transceiver
- BC/RTU/MT protocol
- 8K x 16 shared RAM
- Interrupt logic
Compatible with MIL-STD-1750 and other standard CPUs
DIP or flatpack
Minimizes CPU overhead
Provides memory mapped 1553 / SAE-AS15531 interface
On-line & off-line self-test
Advanced low power VLSI technology
COTs PCB construction
Designed for commercial, industrial and aerospace applications
APPLICATIONS
Aeroflex’s CT2553-PCB Advanced Integrated Mux (AIM) PCB is a complete MIL-STD-1553 / SAE-AS15531 Bus
Controller (BC), Remote Terminal Unit (RTU), and Bus Monitor (MT) device. Packaged using COTs PCB
Construction, the CT2553 contains dual low-power transceivers, complete BC/RTU/MT protocol logic, a
MIL-STD-1553-to-host interface unit and an 8K x 16 RAM.
Using an industry standard dual transceiver and standard status and control signals, the CT2553-PCB simplifies
system integration at both the MIL-STD-1553 and host processor interface levels.
All 1553 operations are controlled through the CPU access to the shared 8K x 16 RAM. To ensure maximum design
flexibility, memory control lines are provided for attaching external RAM to the CT2553-PCB Address and Data
Buses and for disabling internal memory; the total combined memory space can be expanded to 64K x16. All 1553
transfers are entirely memory-mapped; thus the CPU interface requires minimal hardware and/or software support.
The CT2553-PCB operates over the military -55°C to +95°C temperature range. See "Ordering Information" (last
sheet) for CT2554-PCB, CT2555-PCB & CT2556-PCB.
SCDCT2553PCB Rev A
SCDCT2553PCB Rev A Preliminary 7/13/06
2
Aeroflex Plainview
4
3
2
1
4
3
2
1
TRANSFORMER B
DATA
BUS B
8
Q1553-2
TRANSFORMER A
DATA
BUS A
8
Q1553-2
INH
768µs
TIMEOUT
INH
RAM
8K X 16
SHARED RAM
PROTOCOL
CONTROLLER
MEMORY
TIMING
PARITY
CHECKER
CONTENTION
RESOLVER
Note: The Watch-Dog Time Out (768µs TYP) is built in.
DECODER
CHANNEL B
ENCODER/
DECODER
CHANNEL A
ENCODER/
FIGURE 1 – CT2553/4/5/6-PCB BLOCK DIAGRAM
TRANSCEIVER B
RX
RX
TX
TX
RX
RX
TX
TX
TRANSCEIVER A
CT2556-PCB
CT2553/4/5-PCB
RT ADDR
D15 - D00
A15 - A00
INTERRUPT
GENERATOR
CPU
TIMING
RTPARERR
RTADR4
RTADRP
RTADR3
RTADR2
RTADR1
RTADR0
INT
EXTLD
EXTEN
MEM/REG
RD/WR
READYD
STRBD
SELECT
MSTRCLR
CLOCK IN
Values at nominal Power Supply Voltages unless otherwise specified
PARAMETER
VALUE
UNITS
40 max
Vp-p
7 min
40 min
KΩ
db
6.0 min, 9.0 max
100 min, 300 max
±90 max
Vp-p
nsec
mV
Logic*
VIH
VIL
2.2 min
0.8 max
V
V
Clock
16
MHZ
+5±10%
V
-15±10%
-12±10%
Not Used
Not Used
V
V
+5±5%
Not Used
(85) / 170
V
mA
(45) / 80
(45) / 80
mA
mA
(85) / 170
(85) / 170
mA
mA
(80) / 130
mA
(80) / 130
mA
−55 to +125
−65 to +150
°C
°C
2.1 x 1.87 x 0.3
(53 x 47.5 x 7.62)
2.19 x 1.6 x 0.3
(55.6 x 40.6 x 7.62)
in
(mm)
in
(mm)
Receiver
Differential Input Voltage
Differential Input Impedance
CMRR
Transmitter (Direct Coupled)
Differential Output Voltage
Output Rise and Fall Times
Output Offset Voltage
Power Requirements
+5V (Logic)
-VEEA (Channel A Transceiver) & -VEEB (Channel B Transceiver)
CT2553-PCB
CT2554-PCB
CT2555-PCB
CT2556-PCB
+5VA (Channel A) & +5VB (Channel B)
CT2553/4/5-PCB
CT2556-PCB
+5V (Idle)
-VEEA / -VEEB (Idle)
CT2553-PCB
CT2554-PCB
+5V (25% Duty Cycle)
CT2553/4/5-PCB
CT2556-PCB
-VEEA / -VEEB (25% Duty Cycle)
CT2553-PCB
CT2554-PCB
Temperature Range
Operating transceiver case
Storage
Physical Characteristics
Size
78 pin DDIP
82 pin flatpack
* See Table 7 for pin loading characteristics.
TABLE 1 – CT2553-PCB SPECIFICATIONS
SCDCT2553PCB Rev A Preliminary 7/13/06
Aeroflex Plainview
3
GENERAL
MEMORY MANAGEMENT
The CT2553-PCB is a complete MIL-STD-1553 bus
interface unit containing dual low-power transceivers;
Bus Controller (BC), Remote Terminal (RTU), and Bus
Monitor (MT) protocol logic; 8K x 16-bit pseudo dual
port RAM; and memory management arbitration control
circuitry. The host processor interface consists of
standard control and interrupt signals, memory expansion
capability and non-multiplexed address and data buses.
Control of the CT2553-PCB is accomplished entirely
through the use of three internal registers and the shared
RAM. Transfers to and from the CT2553-PCB are
executed on a word-by-word basis ensuring minimal wait
time if contention occurs.
The specific mods of operation (1553 BC/RT/MT) is
software programmable. Memory is configured into
unique control and data block areas based on the 1553
mode of operation. External registers are also supported
by the CT2553-PCB for manipulation of user data. In
addition, the CT2553-PCB provides dynamic, online and
software initiated self-test capabilities.
Memory can be configured to support two AREAs (A
and B), each with an independent sequential stack and
pointers for manipulating 1553 message and control data.
The CPU can access the shared RAM while 1553
message transfers are taking place. Arbitration of the
RAM is automatically implemented in a manner
transparent to the subsystem (See Figures 28-31).
Variable Length DATA BLOCKS are also stored in the
shared RAM and can be addressed by setting pointers
residing in Area A, Area B or both.
For BC/RTU operation, each area contains a Descriptor
Stack and Stack Pointer (See Figures 6 and 7). BC
operation further maintains a Message Count for each
area (number of 1553 messages per frame). RTU
operation maintains a data block address Look-Up Table
for each area. MT operation utilizes a single Stack
Pointer to indicate the starting address for storage of
received words and associated identification Words.
CURRENT AREA ASSIGNMENT/SWAING
Current area status (currently available to the 1553
terminal) is Software programmable by the host; the
unassigned area automatically assumes non-current area
status. Both areas are always addressable by the host.
Swapping of the Current Area can be done following
message transfers for user operations such as exception
handling or multiple buffering of 1553 data.
The host selects the Current Area by writing to the
CT2553-PCB’s Configuration Register with bit 13 set to
the appropriate logic level (0 for area A or 1 for area B).
Internal circuitry ensures that the swapping of Current
Area Status does not occur during an ongoing message
transfer (See Configuration Register).
INTERFACING
The CT2553-PCB is compatible with most common
microprocessors including, but not limited to, the
Motorola 680 x 0, the Intel 808x, Zilog Z800x and
MIL-STD-1750 processors.
Interfacing the CT2553-PCB to the MIL-STD-1553 Data
Bus requires two Q1553-2 pulse transformers and an
external 16 MHz clock (See Figure 2). Tri-state buffers
are used to isolate the CPU's data and address lines.
External RAM can be used instead of or in conjunction
with the CT2553-PCB's internal 8K x 16 bits. The
external RAM used by the CT2553-PCB can be any
standard static memory with an access time of < 55ns.
The external RAM can be expanded to 64K x 16.
Two control signals, MEMENA-IN (pin 69) and
MEMENMA-OUT (pin 31) are provided in addition to the
standard memory I/O signals for internal/external
memory access control (See Figures 3 - 5). MEMEN-OUT
and MEMEN-IN should be tied together for Internal
Memory Only configuration. Memory CS signals can be
generated for configurations using external memory.
DESCRIPTOR STACK (BC/RTU)
The DESCRIPTOR STACK (DS) is divided into 64
entries. Each stack entry contains four words which refer
to one 1553 message. The Block Status Word (BSW)
indicates the physical bus on which the message was
received (RTU mode), reports whether or not an error
was detected during message transfer and indicates
message completion (See Figure 8).
The user-supplied Time Tag word is loaded at the start of
a message transfer and is updated at the end of the
transfer (See Time Tagging).
SCDCT2553PCB Rev A Preliminary 7/13/06
Aeroflex Plainview
4
RD/WR
RD/WR
(DIR)
DATA
D0 - D15
36
16
RTADP
51
RTADDRESS
(OE) (54LS245)
IOEN
ROM
RAM
I/O
MEMENA-OUT
MEMENA-IN
(OE) (54LS244)
TX/RX-A
1
7
+
6
2
TX/RX-A
5
3
–
4
69
*T1
ADDRESS
A0 - A12
13
CT2553-PCB
8
POR
(SEE NOTE 2)
ADDRESS
DECODER
40
31
78
(SEE NOTE 1)
CPU
8
73
MSTRCLR
SELECT
MEM/REG
20
71
READYD
INT
59
TX/RX-B
5
3
72
52
54
32
3
+5V
2
-15V
ILLCMD
12
15
30
–
4
*T2
34
75
+
6
33
HOST PROCESSOR
16MHz
CLOCK
7
74
13
MEMOE
1
2
(54LS04)
STRBD
TX/RX-B
53
57
XX
17
+5V
SA/MC-0
SA/MC-1
SA/MC-2
SA/MC-3
SA/MC-4
ILLEGALIZATION
PROM
(OPTIONAL)
T/R
BCSTRCV
LMC
1553 INTERFACE
* T1 / T2
CT2553-PCB Q1553-2 (Technitrol)
CT2554-PCB BUS-29854
CT2555-PCB Q1553-45 (Technitrol)
or equivalent low leakage Inductance Transformer
FIGURE 2 – CT2553-PCB EXAMPLE INTERCONNECTION
SCDCT2553PCB Rev A Preliminary 7/13/06
Aeroflex Plainview
5
ADDRESS BUS
ADDRESS BUS
CPU
16
CPU
CT2553-PCB
CS
MEMENA OUT
31
31
MEMENA OUT
MEMENA IN
69
64K x 16
STATIC RAM
CT2553-PCB
E
ADDRESS
DECODER
69
MEMENA IN
10K
+5V
FIGURE 3 – INTERNAL MEMORY ONLY
69
FIGURE 4 – EXTERNAL MEMORY ONLY
MEMENA IN
ADDRESS BUS
0
CT2553-PCB
A13
A
1
A14
B
2
A15
C
3
CPU
13
4
31
MEMENA OUT
E
5
6
7
ADDRESS
DECODER
8K
x
16
8K
x
16
8K
x
16
8K
x
16
8K
x
16
8K
x
16
8K
x
16
56 x 16K STATIC RAM MAX
FIGURE 5 – CONFIGURATION USING BOTH INTERNAL AND EXTERNAL MEMORY
SCDCT2553PCB Rev A Preliminary 7/13/06
Aeroflex Plainview
6
CONFIGURATION
REGISTER
15
13
STACK
POINTERS
0
DESCRIPTOR
STACKS
**
DATA **
BLOCKS
*
CURRENT
AREA B/A
BLOCK STATUS WORD
TIME TAG WORD
RESERVED
MESSAGE
BLOCK ADDR
DATA BLOCK
MESSAGE
COUNTER
*
DATA BLOCK
*
Note:
STACK POINTERS and MESSAGE COUNTERS are switched via the
CONFIGURATION REGISTER under external CPU control.
** Note:
DESCRIPTOR STACKS and DATA BLOCKS have 256 word boundries which
should be observed.
FIGURE 6 – USE OF DESCRIPTOR STACK – BC MODE
CONFIGURATION
REGISTER
15
13
STACK
POINTERS
0
DESCRIPTOR
STACKS
**
LOOK-UP TABLE
(DATA BLOCK ADDR)
*
DATA **
BLOCKS
*
CURRENT
AREA B/A
BLOCK STATUS WORD
TIME TAG WORD
LOOK-UP
TABLE ADDR
RESERVED
DATA BLOCK
RECEIVED COMMAND
WORD
DATA BLOCK
*
Note:
STACK POINTERS and LOOK-UP TABLE are switched via the
CONFIGURATION REGISTER under external CPU control.
** Note:
DESCRIPTOR STACKS and DATA BLOCKS have 256 word boundries which
should be observed.
FIGURE 7 – USE OF DESCRIPTOR STACK – RTU MODE
SCDCT2553PCB Rev A Preliminary 7/13/06
Aeroflex Plainview
7
15
EOM
SOM
CHB/CHA
(RTU ONLY)
ERROR FLAG
STACK POINTER. A STACK POINTER (SP) is
maintained
at a specified location in shared RAM for each
1 1 1 1 1 1 1 1
Descriptor Stack (SP-A: 0100H; SP-B: 0104H). Each
Stack Pointer must be initialized by the CPU to point to
LOOP TEST FAIL
the Descriptor Stack Entry to be used for the first
RESPONSE TIME OUT (BC ONLY) MIL-STD-1553 transmission. The current area SP is
FORMAT ERROR
automatically incremented by four following each
STATUS SET (BC ONLY)
message transfer thereby always pointing to the next
Block Status Word.
8 7
0
Note: In BC operation, the CT2553-PCB always writes the BSW to RAM
with Bit-13. CHB/CHA toggles as per the message control word setting.
BIT NAME
DEFINITION
Note: The Stack Pointer is maintained internally using an 8-BIT
REGISTER for the HIGH BYTE and an 8-BIT COUNTER for the
LOW BYTE. The high byte remains constant (user value) while
the low byte will wrap around from FF(H) to 00(H). For example:
a current Stack Pointer value of 00 FF(H) will increment to 00
00(H) and not 01 00 (H).
EOM
Set at the completion of a message
transfer regardless of whether any errors
were detected.
SOM
Set at the beginning of a message transfer LOOK-UP TABLE (RTU). A data block address
and Reset upon completion of the
Look-Up Table is used to indicate the data blocks to be
transfer.
used for individual commands. Look-Up is based upon the
Set in RTU mode to indicate whether the T/R (transmit/receive) and Subaddress bits of the received
message was received on 1553 bus A or 1553 Command Word. See RTU Operation for detailed
bus B. Toggles to indicate channel, in BC operation; two tables are provided for double buffering in
mode.
the RTU mode.
CHB/CHA
ERROR
FLAG
Indicates that an error was detected within
the message transfer. The specific error
condition(s) are identified in bits 8-11.
STATUS
SET
Set in BC mode to indicate that a status
flag bit was set within the received RTU
Status Word or that the RTU address did
not match the associated Command. Set
in BC mode when the message error bit is
set within the received RTU Status Word.
FORMAT
ERROR
Also set in RTU mode (RT-RT transfer;
CT2553-PCB is acting as the receiving
RT) when the transmitting RTU Status
Word contains an incorrect address. Also,
set in BC or RTU mode if the message
violates MIL-STD-1553 (parity,
Manchester, sync bit count,
non-contiguous data or word count
errors).
RESPONSE
TIMEOUT
Set in BC mode if the addressed RTU did
not respond within 14µs. Also set when
acting as a receiving RT (RT-RT transfer)
if the transmitting RT does not respond in
the specified 1553 response time.
MULTIPLE BUFFERING (BC/RTU).
Unused
areas of shared RAM can be used to store additional
stacks, tables, data blocks and/or user (non 1553-related)
data. In this way, multiple data blocks (RTU) or messages
(BC) can be stored for later use: simply update respective
pointers and initiate the appropriate start conditions. (BC
mode requires SP, message block address and message
count updating while in RTU mode, the SP and Look-Up
Table entry must be updated).
Set when the CT2553-PCB does not pass
LOOP
TEST FAIL the Loop Test. See Self Test paragraph.
FIGURE 8 – DESCRIPTOR STACK - BLOCK
STATUS WORD
CT2553-PCB REGISTERS
The contents of the fourth word of the stack entry depends
upon the 1553 operating mode selected. In BC mode, It
contains the address of the associated 1553 message (Data
Block). In RTU mode, it contains the complete (received)
1553 Command Word.
SCDCT2553PCB Rev A Preliminary 7/13/06
The CT2553-PCB is controlled through the use of three
internal registers: Interrupt Mask Register, Configuration
Register and a Start/Reset Register. In addition, the
CT2553-PCB can access up to four external, user supplied
registers (See Table 2). Possible external register
applications include: CPU Time Tag storage and RTU
Address assignment (See Figures 9 and 10).
Aeroflex Plainview
8
ADDRESS
DECODER
A
A01
B
EXTEN
E
A00
A
A01
B
{
{
A00
READ
WRITE
E
EXTLD
Note:
A02 of the CT2553-PCB must be set to logic 1 to operate with external registers.
FIGURE 9 – USE OF EXTERNAL REGISTERS
EXTLD
1
6
REGISTER
RTADP
5
RT ADDR
CPU
DATA BUS
16
D15 - D00
OE
CT2553-PCB
IOENBL
FIGURE 10 – EXAMPLE CONFIGURATION USING EXTERNAL REGISTERS
SCDCT2553PCB Rev A Preliminary 7/13/06
Aeroflex Plainview
9
CPU TO REGISTER OPERATIONS. The CPU
selects a register by asserting MEM/REG low and A2 to a
logic 0 (for internal registers) or logic 1 (for external
registers) with A0 and A1 indicating the appropriate
register address (See Figures 28-32). The signals EXTEN
and EXTLD are used to access the external registers.
15
8 7
0
1 1 1 1 1 1 1 1
RTU/BC
MT
CURRENT AREA B/A
STOP ON ERROR
SUBSYSTEM FLAG
SERVICE REQUEST
BUSY
DB ACCEPT
BIT NAME
DEFINITION
SUBYSTEM FLAG
SERVICE REQUEST
BUSY
DB ACCEPT
STOP ON ERROR
Sets/resets 1553 Status Word flag.
Sets/resets 1553 Status Word flag.
Sets/resets 1553 Status Word flag.
Sets/resets 1553 Status Word flag.
BC will halt message transfer after
completing current EOM cycle.
CURRENT AREA B/A Selects Current Area Pointers.
RTU/BC
RTU or BC-MT Operation Select.
CONFIGURATION REGISTER. The Configuration
Register is a 16-bit read/write register used to define the
1553 operating mode (BC, RTU, or MT); define selectable
1553 Status Word bits (RTU only); select stop-on-error
option; and support the double buffering scheme (See
Figure 11).
BIT15
0
0
1
1
BIT 14
0
1
0
1
Operation
BC
MT
RTU
Illegal
Note: A logic 0 causes the corresponding bit within the RTU’s status
word to be set to a logic 1.
FIGURE 11 – CONFIGURATION REGISTER
INTERRUPT MASK REGISTER (BC/RTU). This START/RESET REGISTER. This write-only register
register is a 16-bit read/write register used to enable/mask is used to reset the CT2553-PCB and to start the BC and
interrupt conditions. If an interrupt condition occurs and MT operations, as illustrated in Figure 13.
the corresponding Interrupt Register bit has been enabled
(set to logic 1) pin 72, INT will be pulsed low during the
respective End of Message (EOM) cycle (See Figure 12).
Not Used bit locations can optionally be used for storing
user flags.
15
9 8 7
1 1 1 1 1 1 1
15
4 3 2 1 0
9 8 7
NOT
USED
NOT USED
BC EOM
FORMAT ERROR/STATUS SET
NOT USED
EOM
INTERRUPT
EOM
FORMAT
ERROR/
STATUS SET
BC EOM
4 3 2 1 0
CONTROLLER START
RESET
DEFINITION
End of message. Set by CT2553-PCB in
BC or RTU mode following each 1553
transfer (regardless of validity).
Set if one of the following occurs:.
Loop Test Failure: Received word does
not match last word transmitted.
Message Error: Received message
contained a violation of any of the 1553
message validation criteria (parity, sync,
manchester encoding, bit/word count, etc.)
Time-Out: Expected transmission was
not received during the allotted time.
Status Set: Received Status Word
contained status bit(s) set or address error.
Bus Controller End of Message. Set by the
CT2553-PCB following transmission of all
messages within the current Message Block
(Current area message count = FFFF).
FIGURE 12 – INTERRUPT MASK REGISTER
START
RESET
BIT NAME
CONTROLLER
START
RESET
BIT 1
1
0
BIT 0
0
1
DEFINITION
Issued by the CPU to start
message block transmission (BC
Operation) or to begin reception of
1553 messages (MT Operation).
Issued by the CPU to place the
CT2553-PCB in the power-on
condition; (1) aborts 1553 transfers
currently in progress, and (2)
resets Configuration and Interrupt
Mask Register bits (logic 0).
FIGURE 13 – START/RESET REGISTER
SCDCT2553PCB Rev A Preliminary 7/13/06
Aeroflex Plainview
10
TABLE 2 – CT2553-PCB REGISTER ADDRESS
DEFINITION
Address Bits
A2
A1
A0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Definition
R/W
R/W
–
W
R/W
R/W
R/W
R/W
initiates the standard wrap-around test (i.e., internal 1553
encoder output is fed back into the decoder - the word is
then written into memory). See BC Operation and Figure
14, BC Control Word for more details.
Interrupt Mask Register
Configuration Register
Not Used
Start/Reset Register
* External Register
* External Register
* External Register
* External Register
15
8
7
6
5
4
3
2
1
0
NOT USED
BUS CHANNEL A/B
OFF-LINE SELF TEST
MASK BROADCAST
NOT USED
MODE CODE
BROADCAST
* Note: R/W (read/write) capability is dependent on the user's
decoding implementation (See Figure 9).
RT-RT
CONTENTION HANDLING
The CT2553-PCB arbitrates shared RAM (and control
register) accesses between the host CPU and the internal
1553 protocol logic.
If the host attempts to access the RAM while an internal
1553 memory cycle is in progress, the CT1553 will delay
the CPU's memory cycle by inserting wait states via the
READYD control signal until the cycle has been
completed. The maximum delay is 1.8µs.
If the internal 1553 protocol logic attempts to access the
RAM while the host CPU has control of the memory, the
internal 1553 logic will wait until the host CPU cycle has
been completed. To ensure the integrity of 1553 data
transfers, the host CPU must complete its memory cycle
within 1.5µs (See Figures 28-32).
BIT NAME
BUS CHANNEL
A/B
Determines whether message will be
transmitted on 1553 Bus A or Bus B.
Logic 1 = A, logic 0 = B.
INITIATE
Logic 1 performs internal off-line
OFF-LINE SELF transmit/receive test. The last word
TEST
of the message is looped back
through the decoder and placed in
RAM. See Self Test paragraph.
MASK
When logic 1, prevents Broadcast
BROADCAST (1) RCVD bit of the 1553 Status Word
response from signalling a status
error as a result of a Broadcast
command. (A FORMAT error will be
generated if the BROADCAST bit is
not set on the RTU’s Status Word.)
MODE CODE
When logic 1, the message is treated
as a Mode Code. (The Command
Word - Word Count field indicates
Mode Code type.)
BROADCAST
When logic 1, indicates that the
message is a Broadcast Command.
(No Status Word is expected.)
RT-RT
When logic 1, the message is treated
as an RT-RT transfer. (The next two
words are Command Words.) Both
Status Word responses are
validated.
SELF TEST
The CT2553-PCB has two self-test modes: the automatic,
continuous On-Line test and the software-initiated
Off-Line test. In both tests the Loop Test Fail bit within
the Block Status Word will be set to a logic 1 if a failure is
detected.
ON-LINE TEST. The On-Line test occurs in BC and
RTU modes during transmission of each message onto the
1553 bus. This test wraps around the last word
transmitted, exercising the 1553 protocol logic through the
1553 transceivers.
While operating as a BC, the last word transmitted is
received, decoded, and written back into memory location
immediately following the last word within the message
block. The host CPU can read and compare this Loop
Back Word with the last word of the message Data Block;
these two words should be identical. This insures data
integrity between the CPU and the CT2553-PCB.
While in the RTU mode, the internal 1553 Status Word
will be updated to reflect the result of the self test. The
Status Word's Terminal Flag bit will be set to a logic 1 if a
fault was indicated by the wrap-around, self-test.
OFF-LINE TEST. The software-initiated Off-Line test
can be executed only when the CT2553-PCB is configured
as a BC. Set the Wrap-Around Test bit within the BC
Control Word to a logic 1 and initiate any standard
message transfer. This inhibits the 1553 transceivers and
DEFINITION
Note:
1. MASK BROADCAST XOR BROADCAST BIT in Status Word =
STATUS SET ERROR.
2. When the BC expects the BROADCAST bit set in the Status Word,
a logic 1 will mask the Status Interrupt Error flag.
FIGURE 14 – BC CONTROL WORD
RESET
The CT2553-PCB can be reset by pulsing the MSTRCLR
(pin 71) low or by writing to the Start/Reset register. After
a reset condition has occurred, the Configuration,
Interrupt, and (internal) Block Status word register outputs
are forced to a logic 0.
SCDCT2553PCB Rev A Preliminary 7/13/06
Aeroflex Plainview
11
TIME TAGGING (OPTIONAL)
The CT2553-PCB will automatically access an external,
3-state device (i.e., counter) at the start and end of each
message in BC or RTU modes. The CT2553-PCB output,
TAGEN (pin 76), enables the device's output onto the
common, 16-bit data highway while executing a
memory-write cycle. The device's value is written into the
second location of the Descriptor Stack Entry. If a counter is
used its clock, enable, and reset control lines are connected
per system requirement (See Figure 15). If no external
device is attached to the data bus, an expected value of
FFFF (H) will be written into the Time Tag location within
the Descriptor Stack.
Note that the 8-bit Time Tag value generated in the 1553
MT mode of operation is implemented using an 8-bit
counter internal to the CT2553-PCB (See MT operation).
THREE-STATE
COUNTER
OE
CPU
DATA BUS
DATA
BUS
D15 - D00
D15 - D00
OE
TAGEN
CT2553-PCB
IOEN
FIGURE 15 – BC/RT TAGGING (OPTIONAL)
CONTROL
WORD
CONTROL
WORD
CONTROL
WORD
CONTROL
WORD
CONTROL
WORD
CONTROL
WORD
CONTROL
WORD
CONTROL
WORD
BROADCAST
COMMAND
(NO DATA)
RECEIVE
COMMAND
TRANSMIT
COMMAND
RECEIVE
COMMAND
MODE
COMMAND
MODE
COMMAND
MODE
COMMAND
BROADCAST
COMMAND
BROADCAST
COMMAND
LOOPED
BACK
DATA WORD
1
TRANSMIT
COMMAND
LOOPED
BACK
TRANSMIT
COMMAND
DATA WORD
MODE
COMMAND
LOOPED
BACK
MODE
COMMAND
LOOPED
BACK
DATA WORD
1
DATA WORD
2
STATUS
RECEIVED
TRANSMIT
COMMAND
LOOPED
BACK
DATA WORD
LOOPED
BACK
STATUS
WORD
STATUS
WORD
DATA WORD
2
DATA WORD
LAST
DATA WORD
1
STATUS
WORD 1
FROM XMTR
STATUS
WORD
DATA WORD
RECEIVED
MODE CODE
WITHOUT
DATA
DATA
WORD LAST
DATA WORD
LAST
LOOPED
BACK
DATA WORD
2
DATA WORD
1 RECEIVED
MODE CODE
WITH DATA
RECEIVE
DATA BLOCK
FORMAT
MODE CODE
WITH DATA
TRANSMIT
DATA BLOCK
FORMAT
STATUS
RECEIVE
DATA WORD
LAST
DATA WORD
2 RECEIVED
TRANSMIT
DATA BLOCK
LAST DATA
WORD
RECEIVED
BROADCAST
COMMAND
(NO DATA)
RECEIVE
DATA BLOCK
DATA WORD
LOOPED
BACK
BROADCAST
COMMAND
WITH DATA
STATUS
WORD 2
FROM
RECEIVER
REMOTE
TERMINAL TO
REMOTE
TERMINAL
DATA BLOCK
FIGURE 16 – BC MESSAGE FORMATS
SCDCT2553PCB Rev A Preliminary 7/13/06
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12
BC OPERATION
ADDITIONAL FEATURES.
The Configuration
Register – STOP ON ERROR bit can be set. This causes
the CT2553-PCB to halt operation at the end of the
current message transfer if an error is detected. In
addition, setting the Interrupt Mask Register bits will
result in a low pulse on the Interrupt (INT) pin with each
BC MEMORY CONFIGURATION. The user occurrence of the respective error, end of message or end
configures the memory by: (1) writing the start address of of message frame condition (See Configuration Register
the Descriptor Stack into the Current Area Stack Point and Interrupt Register sections).
location; (2) loading the fourth word of each Descriptor
Stack Entry (DSE) with the start location of each
message block; and (3) loading the Message Counter BC TRANSFER-START SEQUENCE
with the total number of messages to be transmitted. Note After setting the CONTROLLER START bit in the
that the Message Count must be written in 1's Start/Reset Register, the CT2553-PCB takes the
compliment. For example, to transmit one message, load following actions:
00FE(H) (See Table 3, BC Memory Map).
1. Reads the Current Area Stack Pointer for the
If both map areas A and B are utilized, this procedure
address of the Descriptor Stack Entry (DSE).
must be performed for each area. Note that the Stack
Pointer and Message Counter locations are fixed;
2. Stores an SOM (Start of Message) flag in the
Message Block locations are user-defined.
Block Status word to indicate a transfer
Each message block must be proceeded by a BC Control
operation in progress.
Word (See Figure 14). This word informs the
CT2553-PCB as to the format of the message transfer. Bit
3. Writes the Time Tag value into the Descriptor
1 of the Control Word defines whether the following
Stack (See Time Tag).
message to RT 31 is to be issued in Broadcast Mode or
whether RT 31 is a unique terminal. Memory locations
4. Reads the Data Block Address from the fourth
must be reserved at the end of each message for: (1) a
location of the DSE.
Loop Back Word; (2) RTU Status Word(s); and (3)
received Data words. See Figure 16, BC Message
5. Starts the MIL-STD-1553 message transfer.
Formats.
Message blocks may be loaded anywhere in the non-fixed
area of the shared RAM. However, each data block may Upon completion of the MIL-STD-1553 message
not cross a 256 word boundary (i.e., bit 8 of the starting transfer, the CT2553-PCB:
address of the message block must match bit 8 of the
address of the last word of the message block).
1. Generates an End Of Message (EOM) or Error
(if applicable) interrupt if enabled.
Initialization of the CT2553-PCB via a Reset or by
setting the appropriate Configuration Register bits will
result in placing the CT2553-PCB in the BC operating
mode.
2. Reads the Stack Pointer for the address of the
DSE.
TABLE 3 - TYPICAL BC MEMORY MAP
HEX ADDRESS
FUNCTION
3. Updates the Block Status Word; resets SOM,
sets EOM, and sets any applicable Error bits.
Fixed Areas
0100
0101
0104
0105
Stack Pointer A
Message Count A
Stack Pointer B
Message Count B
4. Writes the Time Tag value into the Descriptor
Stack (See Time Tag).
5. Increment Pointers: Stack Pointer incremented
by 4 and Message Count incremented by 1.
User Defined Areas
0108-013F
0140-017F
0180-01BF
01C0-01FF
•
•
0F00-0FFF
Not Used
Data Block 1
Data Block 2
Data Block 3
•
•
Descriptor Stack A
0000-00FF
Descriptor Stack B
6. If more messages remain to be sent, a BC End
Of Message (BCEOM) interrupt occurs (if
enabled).
If an error occurs and Stop On Error has been enabled,
the CT2553-PCB stops initiating BC Transfer-Start
sequences. The Stack Pointer will point to the next
message to be transferred (See Figure 17).
SCDCT2553PCB Rev A Preliminary 7/13/06
Aeroflex Plainview
13
CONTROLLER START
COMMAND RECEIVED
READS STACK POINTER
LOAD BLOCK STATUS WORD
INTO FIRST WORD OF
DESCRIPTOR STACK ENTRY
(SET SOM BIT IN BLOCK
STATUS WORD)
LOAD TIME TAG INTO
SECOND WORD OF
DESCRIPTOR
STACK ENTRY
DATA BLOCK
TRANSFERRED OK
?
YES
NO
OBTAIN DATA BLOCK
ADDRESS FROM FOURTH WORD
STOP ON
ERROR SET
?
YES
READ CONTROL WORD TO
DETERMINE TYPE OF TRANSFER
TRANSFER DATA TO/FROM
1553 BUS
NO
MORE MESSAGES
TO SEND
?
NO
YES
ISSUE BC EOM
UPDATE BLOCK STATUS WORD
STOP
UPDATE TIME TAG
INCREMENT STACK
POINTER BY FOUR.
DECREMENT
MESSAGE COUNT
FIGURE 17 – BC SEQUENCE OF OPERATION
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14
BC SETUP IMPLEMENTATION EXAMPLE
Figure 18a-c shows the BC mode examples for two
message transfers, BASIC setup, and BC memory setup.
START
0000
LOAD CONFIGURATION
REGISTER (BC MODE)
GIVEN:
1. All values are in hex.
01
40
0003
01
80
0007
Descriptor
Stack Entries
2. Map Area "A" is used and located from Address 0000 to Address
00FF.
LOAD STACK POINTER
LOAD STARTING ADDRESS OF
FIRST MESSAGE INTO STACK
LOAD STARTING ADDRESS OF
SECOND MESSAGE INTO STACK
LOAD FIRST MESSAGE
INTO MEMORY
LOAD SECOND MESSAGE
INTO MEMORY
3. Message 1 located at Address 0140, is a TRANSMIT Command
to RT# 1, Subaddress #1, Word Count = 1, transmitted on
BUS A.
4. Message 2 located at Address 0180, is a RECEIVE Command to
RT#3, Subaddress #1, Word Count = 3, transmitted on BUS B.
0000
0100
5. Configuration Register is assumed to be memory mapped at
location 2001. START/RESET Register is memory mapped at
location 2003.
00FD
0101
00
80
0C
21
MOV
MOV
2003,
2001,
0001
0FFF
;
;
Issue Reset
Initialize Configuration Register
MOV
MOV
0100,
0101,
0000
00FD
;
;
Initialize Stack Pointer
Initialize Message Count
**
MOV
0003,
0140
;
Load Start Address Of Message #1
*
MOV
0007,
0180
;
Load Start Address Of Message #2
*
MOV
MOV
0140,
0141,
0080
0C21
;
;
Load BC Control Word Message #1
Load Command Word Message #1
MOV
MOV
MOV
MOV
MOV
0180,
0181,
0182,
0183,
0184,
0000
1823
1111
2222
3333
;
;
;
;
;
Load BC Control Word Message #2
Load Command Word Message #2
Load Data Word #1 Message #2
Load Data Word #2 Message #2
Load Data Word #3 Message #2
MOV
2003,
0002
;
Issue "Start"
LOAD MESSAGE COUNTER WITH
1's COMPLEMENT OF MESSAGE
COUNT = FD (HEX)
FIGURE 18B – SAMPLE
BC SET-UP INSTRUCTIONS
LOAD START REGISTER
WITH THE VALUE 02
0140
Message #1
00
00
18
23
11
11
22
22
33
33
0180
Message #2
**
*
* Left empty for RTU’s status response.
** Loop Back word.
FIGURE 18C – BC SET-UP
MEMORY MAP
FIGURE 18A – BC SET-UP
EXAMPLE FOR TWO
MESSAGE TRANSFER
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15
RTU OPERATION
RTU LOOK-UP TABLE. The RTU mode uses a
Look-Up
Table in order to map the Data Blocks based
The RTU mode is selected by resetting the CT2553-PCB
upon
incoming
1553 Command Words. The
and setting the appropriate bits in the Configuration
CT2553-PCB
uses
the
T/R and Subaddress fields to
Register.
address the Look-Up Table. Each Look-Up Table (A and
B) location contains a user-defined Data Block Pointer to
an associated Data Block (See Figures 20 and 21).
RTU MEMORY CONFIGURATION. The user
Note: The Data Block and Stack Pointers are
maintained internally using an 8-BIT-REGISTER
for the HIGH BYTE and an 8-BIT COUNTER for
the LOW BYTE; the high byte remains constant
(user value) while the low byte will wrap around
from FF(H) to 00(H). For example: a current Pointer
value of 10 FF(H) will increment to 10 00(H) and
not 11 00(H).
configures the memory by:
1. Writing the start address of the Descriptor
Stack into the Stack Pointer location and
2. Setting up the Look-Up Table as described
below.
The first 32 words of the Look-Up Table are reserved for
Data Blocks associated with Receive Commands (T/R bit
= 0). The remaining 32 words are reserved for Data
Blocks associated with Transmit Commands (T/R bit
= 1).
Mode Commands with data are mapped in the same
manner as non-mode commands. A Synchronize With
Data command maps to the first or thirty-second Table
entry (depending upon subaddress: all 0's or all 1's),
while a Transmit Vector Word command points to the
thirty-third or sixty-fourth entry.
If both map areas (A and B) are utilized, this procedure
must be performed for each area. Note that the Stack
Pointer and Look-Up Table locations are fixed; Data
Block(s) locations are user-defined. Message blocks may
be loaded anywhere in the non-fixed areas of the shared
RAM. However, each data block may not cross a 256
word boundary (i.e., bit 8 of the starting address of the
message block must match bit 8 of the address of the last
word of the message block). An example of a typical
RTU Memory Map is given in Table 4. Figure 19 shows
the RTU Initialization steps.
START
ISSUE RESET COMMAND
TABLE 4 – TYPICAL RTU MEMORY MAP
HEX ADDRESS
FUNCTION
INITIALIZE STACK POINTER
Fixed Areas
0100
0101
0104
0105
0108-013F
0140-017F
01C0-01FF
SET UP LOOK-UP TABLE(S)
DATA BLOCK ASSIGNMENTS
Descriptor Stack Pointer A
Reserved
Descriptor Stack Pointer B
Reserved
Spare
Look-Up Table A
Look-Up Table B
SET UP DATA BLOCKS
INITIALIZE INTERRUPT
MASK REGISTER
User Defined Areas
0180-019F
01A0-01BF
0200-021F
•
•
0EE0-0EFF
0000-00FF
0F00-0FFF
SET CONFIGURATION
REGISTER TO RTU MODE
Data Block 1
Data Block 2
Data Block 3
•
•
Data Block 107
Descriptor Stack A
Descriptor Stack B
START REGISTER
WAIT FOR 1553 COMMAND
FIGURE 19 – RTU INITIALIZATION
SCDCT2553PCB Rev A Preliminary 7/13/06
Aeroflex Plainview
16
15
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 1
RECEIVED COMMAND WORDS
1
LOOK-UP
TABLE (A)
T/R SUBADD
ADDRESS
0
00000
0140
0
00001
0141
0
00010
0142
*
64 LOCATIONS
*
*
1
11110
XXXXX
017E
1
11111
XXXXX
017F
WORD
COUNT
XXXXX
XXXXX
XXXXX
CURRENT AREA B/A
T/R (from command word)
SUB-ADDRESS (command word)
FIGURE 20 – RTU LOOK-UP ADDRESS
RTU MESSAGE BLOCK TRANSFER
SEQUENCE
DATA BLOCK
DATA BLOCK
USER DEFINED
USER DEFINED
USER DEFINED
USER DEFINED
USER DEFINED
FIGURE 21 – LOOK-UP TABLE EXAMPLE
RTU message transfer operations begin automatically upon
receipt of a valid command word from the 1553 bus. A
message transfer takes the form of an RTU Start Of
Message (SOM) cycle followed by the 1553 Message
Transfer Cycle and an RTU End Of Message (EOM) cycle
(See Figure 22).
During the RTU SOM cycle, the CT2553-PCB executes the
following actions:
1. Loads the 1553 command word.
1553 COMMAND WORD
RECEIVED
READ STACK POINTER
UPDATE DESCRIPTOR STACK
BLOCK STATUS WORD, TIME
TAG AND COMMAND WORD
2. Reads the current area Stack Pointer to get the
address of the current Descriptor Stack Entry
(DSE).
READ LOOK-UP TABLE USING
T/R SUBADDRESS CURRENT
AREA BIT B/A
3. Stores an SOM flag into the Block Status Word
to indicate a transfer in progress.
4. Writes the Time Tag value into the the
Descriptor Stack.
TRANSFER DATA TO/FROM
1553 INTERFACE DEVICE
5. Stores the Command Word received.
6. Reads the associated Data Block Address from
the (current area) Look-Up Table.
NO
MESSAGE COMPLETE
?
The MESSAGE TRANSFER CYCLE refers to the actual
transfer of the 1553 message under control of the
CT2553-PCB. The CT2553-PCB transfers data to and from
the memory on a word-by-word basis.
Upon completion of the message transfer, the CT2553-PCB
executes an RTU End Of Message (EOM) cycle during
which the CT2553-PCB:
YES
UPDATE BLOCK STATUS WORD
AND TIME TAG
INCREMENT STACK POINTER
BY FOUR
GENERATE EOM INTERRUPT AND
ERROR INTERRUPT IF ERROR
CONDITION DETECTED
1. Generates an EOM or Error interrupt (if
enabled).
2. Updates the Block Status Word: clears SOM, sets
EOM, and any appropriate error bits.
WAIT FOR NEXT
1553 COMMAND
3. Writes the Time Tag value into the Descriptor
Stack.
FIGURE 22 – RTU MESSAGE TRANSFER
OPERATION
4. Increments the Stack Pointer by 4.
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17
ADDITIONAL FEATURES. Four 1553 Status Upon receipt of a valid mode command, the
CT2553-PCB will output the Command Word-Word
Count field and set the Latched Mode Command (LMC)
output to a logic 1. Upon receipt of a valid non-mode
command, the CT2553-PCB will output the Command
Word-Subaddress field and set the Latched Mode
Command (LMC) output to a logic 0.
An external PROM can be used for command
illegalization by decoding the word count/subaddress,
LMC and Broadcast Received (BCSTRCV) bits and
driving ILLCMD low where appropriate (See Figure 23).
Word flags can be programmed via the appropriate
Configuration Register bits. In addition, setting Interrupt
Mask Register bits will result in a low pulse on the
Interrupt (INT) pin with each occurrence of the
respective error or end of message condition. (See
Configuration Register and Interrupt Register sections.)
THIS RT: Each command appearing on either 1553 Bus
is decoded and tested for Manchester/protocol errors. If
the CT2553-PCB receives a valid command word
containing a RTU address equivalent to the
RTAD0-RTAD4 inputs (pins 10, 9, 50, 49, and 11,
respectively), THIS-RT (pin 55) will be pulsed low. This
signal can be used to identify specific 1553 commands.
This signal is also active in the BC mode.
Command Illegalization (Optional). The CT2553-PCB
has the capability to illegalize MIL-STD-1553 mode
commands. In addition, valid non-mode commands can
be illegalized based upon the Command Word
subaddress field. An illegal command is identified by
driving the Illegal Command, ILLCMD (pin 12) input
low. The CT2553-PCB multiplexes the Word Count and
Subaddress fields (pins SA/MC0 - SA/MC4).
The CT2553-PCB responds to illegalized commands by
transmitting its Status Word with the Message Error bit
set. No data words are transmitted; received words,
however, are placed in the shared RAM locations
indicated by the current area Look-Up Table.
BUSY BIT. If the user asserts the BUSY bit low in the
Configuration Register, the CT2553-PCB will respond
with a Status Word with the BUSY bit set. In addition,
no data words will be transferred from the shared RAM
as indicated by the corresponding value in the current
area Look-Up Table. The CT2553-PCB will transfer
data associated with a Receive Command into memory
but will not transmit data out onto the MIL-STD-1553
bus when busy upon receipt of a Transmit Command.
LMC
SA/MC0-4, T/R
VALID UNTIL NEXT VALID COMMAND WORD RECEIVED
t1
ILLCMD
LATCHED UNTIL NEXT VALID COMMAND WORD RECEIVED
MODE COMMAND ILLEGALIZATION TIMING
SYMBOL
t1
DESCRIPTION
LMC to ILLCMD latch
MIN
MAX
UNITS
250
-
ns
FIGURE 23 – MODE COMMAND/SUB-ADDRESS ILLEGALIZATION TIMING
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Aeroflex Plainview
18
MT OPERATION
START
Initiate a Reset in order to initialize the CT2553-PCB.
Configure the CT2553-PCB as a Bus Monitor (MT) by
setting the appropriate Configuration Register Bits. See
Figure 24 for MT initialization Steps.
ISSUE RESET COMMAND
MT MEMORY CONFIGURATION.
The user
configures the memory by writing the start address for
1553 data storage into the Stack Pointer location. The
Monitor Stack will automatically wrap around once the
RAM has been filled (i.e., location FFF(H) is followed by
location 0000). An example of a typical MT Memory
Map 4 given in Table 5.
CLEAR RAM
INITIALIZE STACK POINTER
SET CONFIGURATION
REGISTER TO MT MODE
TABLE 5 – TYPICAL MT MEMORY MAP
HEX ADDRESS
0000
0001
0002
0003
0004
0005
0006
•
•
0100
•
•
FFFF
FUNCTION
ISSUE START COMMAND
First Received 1553 Word
First Identification Word
Second Received 1553 Word
Second Identification Word
FIGURE 24 – MT INITIALIZATION
LSB
8 7 6 5 4 3 2 1 0
1
MSB
15
•
•
•
•
•
GAP TIME
WORD FLAG
Stack Pointer (Fixed location)
THIS RT
•
•
•
BROADCAST
ERROR
COMMAND SYNC
1553 CHANNEL A/B
MT START SEQUENCE.
After
setting
the
CONTROLLER START bit in the Start/Reset Register,
the CT2553-PCB takes the following actions:
1. Reads the start address for 1553 data storage
from the Stack Pointer location. The Stack
Pointer location(s) will be overwritten with
1553 data once the MT mode has begun and
1553 data is written into locations 0100(H) and
0101(H)].
2. Stores the received 1553 word into memory.
3. Increments the Stack Pointer by 1.
4. Generates an Identification Word and stores
this value into memory.
5. Repeats steps 2-4 until a Reset condition
occurs.
MT IDENTIFICATION WORD. The Identification
word provides the CPU with information pertaining to the
received 1553 word. Its format is shown in Figure 25,
This information allows the user to analyze the 1553 data.
CONTIGUOUS DATA
MODE CODE
BIT NAME
GAP TIME
WORD FLAG
THIS RT
BROADCAST
ERROR
COMMAND SYNC
THIS-RT: Each command appearing on either 1553 Bus
is decoded and tested for Manchester/protocol errors. If
the CT2553-PCB receives a valid command word
containing a Command Sync and a RTU address
equivalent to the RTAD0-RTAD4 inputs (pins 10, 9, 50,
49, and 11, respectively), THIS-RT (pin 55) will be pulsed
low. This signal can be used to identify specific 1553
commands or for switching to RTU mode upon receipt of
a command to this address.
1553 CHANNEL
A/B
CONTIGUOUS
DATA
MODE CODE
DEFINITION
Indicates the time between receipt of the
previous and current words.Time is
indicated in 0.5µs increments for a
maximum of 128 µs and goes to FF over
128µs. (See Word Gap bit.)
Always logic 1.
Logic 0 indicates RT address field of the
associated command or Status Word
matches the RT address field of the
CT2553-PCB.
Logic 0 indicates the RTU address field of
the command or Status Word
corresponds to address 31 (decimal).
Logic 1 indicates Manchester, Parity,
Sync and/or low bit counter.
Logic 1 indicates 1553 Command or
Status Word sync field. (Logic 0 indicates
a Data Word sync field in received word.)
Indicates word received on 1553 Bus A
(1) or Bus B (0).
Logic 1 indicates the word was received
within 2µs of the previous word. If logic 0,
bits 8-15 contain the measured gap
between the words.
When logic 1, the data transferred is a
mode code command.
FIGURE 25 – MT IDENTIFICATION WORD
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19
MT DATA STORAGE. Figure 26 shows the steps
in a MT data Storage operation.
START COMMAND ISSUED
GET STACK POINTER FROM
WORD 100 IN RAM AND
STORE IN INTERNAL REGISTER
WORD TRANSFERRED
ACROSS 1553 BUS
?
YES
NO
STORE RETREIVED 1553 WORD
IN RAM, INCREMENTS INTERNAL
ADDRESS REGISTER
STORE IDENTIFICATION WORD
IN RAM, INCREMENT INTERNAL
ADDRESS REGISTER
INTERRUPTS: SA/MC - 0 (pin 13), SA/MC - 1 (pin
52) and SA/MC - 2 (on 52) represents B6, B7, and B8
counter outputs in the MT mode. B6 counts every 32
words transferred, B7 every 64 words, and B8 every 128
words. These counter outputs can be used to generate
interrupts to the subsystem to insure proper servicing of
Memory. The Data Word and Identification Word
transfers increment the counter by two.
BUILT-IN-TEST WORD (RTU MODE)
The CT2553-PCB contains a 14 bit Built-In-Test (BIT)
word register which stores information about the
condition of the RTU. When a Mode Command is
received to transmit BIT word, the contents of this
register are transmitted over the 1553 data bus. Figure 27
shows the meaning of each bit in the BIT register.
Information is included regarding transmitter timeouts,
loop test failures, transmitter shutdown, subsystem
handshake failure, and the results of individual message
validations.
MODE CODES
FIGURE 26 – MT DATA STORAGE
OPERATION
The CT2553-PCB implements all mode codes applicable
to dual redundant systems. Mode codes can also be
illegalized using the appropriate I/O signals. Mode
command illegalization and handling are detailed in the
RTU Operation section and listed in Table 6.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0
CHAN B XMITTER TIMEOUT
CHAN A XMITTER TIMEOUT
CHAN B LOOP TEST FAILURE
CHAN A LOOP TEST FAILURE
CHAN B XMITTER SHUTDOWN
CHAN A XMITTER SHUTDOWN
NON-MODE BROADCAST CMD TO XMIT
MESSAGE HIGH WORD COUNT
MESSAGE LOW WORD COUNT
ILLEGAL MODE CODE OR ILLEGAL
BROADCAST WITH MODE CODE
MODE CODE OR T/R ERROR
CHAN A/B LOOP TEST FAILURE
HANDSHAKE FAILURE
CHAN A/B XMITTER TIMEOUT
Notes:
(1) Bits 0-2 and 10-13 are latched and only cleared by a mode reset command or a master RESET.
(2) Bits 3-7 are cleared at the start of each new message and updated at the end of the message. They
reflect the present command word.
(3) Bits 8-9 are set by the mode command for Transmitter Shutdown and are cleared by the mode
command for Override Transmitter Shutdown, Reset RT or a master RESET.
FIGURE 27 – BUILT-IN-TEST WORD (RTU MODE)
SCDCT2553PCB Rev A Preliminary 7/13/06
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20
DYNAMIC BUS CONTROL (00000)
MESSAGE SEQUENCE = DBC * STATUS
The CT2553-PCB responds with status. If the subsystem wants control of the bus, it must set DBACC within 2.5us after NBGRT.
ERROR CONDITIONS
1. Invalid Command. No response, command ignored.
2. Command Followed by Data Word. No status response. Bits set: message error (SW), High word Count (BIT Word).
3. T/R bit Set to Zero. No status response. Bits set: message error (SW), T/R Error (Bit Word).
4. Zero T/R bit and Broadcast Address. No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code, T/R
Error (BIT Word).
5. Broadcast Address. No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code (BIT Word).
SYNCHRONIZE WITHOUT DATA WORD (00001)
MESSAGE SEQUENCE = SYNC * STATUS
The CT2553-PCB responds with status. If sent as a broadcast, the broadcast receive bit will be set and status response suppressed.
ERROR CONDITIONS
1. Invalid Command. No response, command ignored.
2. Command Followed by Data Word. No status response. Bits set: message error (SW), High Word Count (BIT Word).
3. T/R bit Set to Zero. No status response. Bits set: message error (SW), T/R Error (BIT Word).
4. Zero T/R bit and Broadcast Address. No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code, T/R
Error (BIT Word).
TRANSMIT STATUS WORD (00010)
MESSAGE SEQUENCE = TRANSMIT STATUS * STATUS
The status and BIT word registers are not altered by this command and contain the resulting status from the previous command.
ERROR CONDITIONS
1. Invalid Command. No response, command ignored.
2. Command Followed by Data Word. No status response. Bits set: message error (SW), High Word Count (BIT Word).
3. T/R bit Set to Zero. No status response. Bits set: message error (SW), T/R Error (BIT Word).
4. Zero T/R bit and Broadcast Address. No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code, T/R
Error (BIT Word).
5. Broadcast Address. No status response. Bits set: message error, broadcast received (S/W), Illegal Mode code, T/R Error (BIT Word).
INITIATE SELF-TEST (00011)
MESSAGE SEQUENCE = SELF TEST * STATUS
The CT2553-PCB responds with a status word. If the command was broadcast, the broadcast received bit is set and status transmission
suppressed. Short-loop test is initiated on the status word transmitted. If the test fails, an RT fail flag is generated.
ERROR CONDITIONS
1. Invalid Command. No response, command ignored.
2. Command Followed by Data Word. No status response. Bits set: message error (SW), High Word Count (BIT Word).
3. T/R bit Set to Zero. No status response. Bits set: message error (SW), T/R Error (BIT Word).
4. Zero T/R bit and Broadcast Address. No status response. Bits set: message error, broadcast received (SW), T/R Error (BIT Word).
5. Faulty Test. Bits set: terminal flag (SW), A/B Loop Test Fail, Current 1553 Bus (A or B) Loop Test Fail (BIT Word).
TRANSMITTER SHUTDOWN (00100)
MESSAGE SEQUENCE - SHUTDOWN * STATUS
This command is only used with dual redundant bus systems. The CT2553-PCB responds
with status. At the end of the status transmission, the CT2553-PCB inhibits any further transmission from the dual redundant channel.
Once shutdown, the transmitter can only be re-activated by Override Transmitter Shutdown or RESET RT commands.
ERROR CONDITIONS
1. Invalid Command. No response, command ignored.
2. Command Followed by Data Word. No status response. Bits set: message error (SW), High Word Count (BIT Word).
3. T/R bit Set to Zero. No status response. Bits set: message error (SW), T/R Error BIT Word).
4. Zero T/R bit and Broadcast Address. No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code, T/R
Error (BIT Word).
TABLE 6 – MODE CODES
SCDCT2553PCB Rev A Preliminary 7/13/06
Aeroflex Plainview
21
OVERRIDE TRANSMITTER SHUTDOWN (00101)
MESSAGE SEQUENCE - OVERRIDE SHUTDOWN - STATUS
This command is only used with dual redundant bus systems. The CT2553-PCB responds with status. At the end of the status
transmission, the CT2553-PCB re-enables the transmitter of the redundant bus. If the command was broadcast, the broadcast received
bit is set and status transmission is suppressed.
ERROR CONDITIONS
1. Invalid Command. No response, command ignored.
2. Command Followed by Data Word. No status response. Bits set: message error (SW), High Word Count (BIT Word).
3. T/R bit Set to Zero. No status response. Bits set: message error (SW), T/R Error (BIT Word).
4. Zero T/R bit and Broadcast Address. No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code, T/R
Error (BIT Word).
INHIBIT TERMINAL FLAG BIT (00110)
MESSAGE SEQUENCE - INHIBIT TERMINAL FLAG * STATUS
The CT2553-PCB responds with status and inhibits further internal or external setting of the terminal flag bit in the status register. Once
the terminal flag has been inhibited, it can only be reactivated by an Override Inhibit Terminal Flag or Reset RT command. If the
command was broadcast, the broadcast received bit is set and status transmission is suppressed.
ERROR CONDITIONS
1. Invalid Command. No response, command ignored.
2. Command Followed by Data Word. No status response. Bits set: message error (SW), High Word Count (BIT Word).
3. T/R bit Set to Zero. No status response. Bits set: message error (SW), T/R Error (BIT Word).
4. Zero T/R bit and Broadcast Address. No status response. Bits set: message error, broadcast received (SW), T/R Error (BIT Word).
OVERRIDE INHIBIT TERMINAL FLAG BIT (00111)
MESSAGE SEQUENCE - OVERRIDE INHIBIT TERMINAL FLAG * STATUS
The RTU responds with status and reactivates the terminal flag bit in the status register. If the command was broadcast, the broadcast
received bit is set and status transmission is suppressed.
ERROR CONDITIONS
1. Invalid Command. No response, command ignored.
2. Command Followed by Data Word. No status response. Bits set: message error (SW), High Word Count (BIT Word).
3. T/R bit Set to Zero. No status response. Bits set: message error (SW), T/R Error (BIT Word).
4. Zero T/R bit and Broadcast Address. No status response. Bits set: message error, broadcast received (SW), T/R Error (BIT Word).
RESET REMOTE TERMINAL (01000)
MESSAGE SEQUENCE - RESET REMOTE TERMINAL * STATUS
The CT2553-PCB responds with status and internally resets. Transmitter shutdown, mode commands, and inhibit terminal flag
commands will be reset. If the command was broadcast, the broadcast received bit is set and the status word is suppressed.
ERROR CONDITIONS
1. Invalid Command. No response, command ignored.
2. Command Followed by Data Word. No status response. Bits set: message error (SW), High Word Count (BIT Word).
3. T/R bit Set to Zero. No status response. Bits set: message error (SW), T/R Error (BIT Word).
4. Zero T/R bit and Broadcast Address. No status response. Bits set: message error, broadcast received (SW), T/R Error (BIT Word).
RESERVED MODE CODES (01001-01111)
MESSAGE SEQUENCE = RESERVED MODE CODES * STATUS
The CT2553-PCB responds with status. If the command is illegalized through an optional PROM, the message error bit is set and only
the status word is transmitted.
ERROR CONDITIONS
1. Invalid Command. No response, command ignored.
2. Command Followed by Data Word. No status response. Bits set: message error (SW), High Word Count (BIT Word).
3. T/R bit Set to Zero. No status response. Bits set: message error (SW), Illegal Mode Code (BIT Word).
4. Zero T/R bit and Broadcast Address. No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code (BIT
Word).
TABLE 6 – MODE CODES (con’t)
SCDCT2553PCB Rev A Preliminary 7/13/06
Aeroflex Plainview
22
TRANSMIT VECTOR WORD (10000)
MESSAGE SEQUENCE - TRANSMIT VECTOR WORD * STATUS VECTOR WORD
The CT2553-PCB transmits a status word followed by a vector word. The contents of the vector word (from the subsystem) are enabled
onto DBO-DB15 with BUSREQ after the command transfer (same as data word in a normal transmit command).
ERROR CONDITIONS
1. Invalid Command. No response, command ignored.
2. Command Followed by Data Word. No status response. Bits set: message error (SW) High Word Count (BIT Word).
3. T/R bit Set to Zero. No status response. Bits set: message error (SW), T/R Error, Low Word Count (BIT Word).
4. Zero T/R bit and Broadcast Address. No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code, T/R
Error, Low Word Count (BIT Word).
5. Broadcast Address. No status response. Bits set: message error, broadcast received (SW), Illegal Mode code, (BIT Word).
SYNCHRONIZE WITH DATA WORD (10001)
MESSAGE SEQUENCE - SYNCHRONIZE DATA WORD * STATUS
The data word received following the command word is transferred to the subsystem. The status register is then enabled and its contents
transferred onto the data bus and transmitted. If the command was broadcast, the broadcast received bit is set and status transmission
is suppressed.
ERROR CONDITIONS
1. Invalid Command. No response, command ignored.
2. Command Not Followed by Data Word. No status response. Bits set: message error (SW), Low Word Count (BIT Word).
3. Command followed by too many Data Words. No status response. Bits set: message error (SW), High Word Count (BIT word).
4. Command T/R bit Set to One. No status response. Bits set: message error (SW), T/R Error, High Word Count (BIT Word).
5. Command, T/R bit Set to One and Broadcast Address. No status response. Bits set: message error, broadcast received (SW), High
Word Count, T/R Error (BIT Word).
TRANSMIT LAST COMMAND (10010)
MESSAGE SEQUENCE = TRANSMIT LAST COMMAND * STATUS LAST COMMAND
The status and BIT word registers are not altered by this command. The SW contains the status from the previous command. The data
word transmitted contains the previous valid command (providing it was not another TRANSMIT LAST COMMAND).
ERROR CONDITIONS
1. Invalid Command. No response, command ignored.
2. Command Followed by Data Word. No status response. Bits set: message error (SW).
3. T/R bit Set to Zero. No status response. Bits set: message error (SW), T/R Error, Low Word Count (BIT Word).
4. Zero T/R bit and Broadcast Address. No status response. Bits set: message error, (SW), Illegal Mode Code T/R Error (BIT Word).
5. Broadcast Address. No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code (BIT Word).
TRANSMIT BIT WORD (10011)
MESSAGE SEQUENCE - TRANSMIT BIT WORD * STATUS BIT WORD
The CT2553-PCB transmits a status word followed by the BIT word . When activated, BITEN allows the subsystem to latch the BIT word
on the parallel data bus. The BIT word is not altered by this command; however, the next SW will reflect errors in this transmission.
ERROR CONDITIONS
1. Invalid Command. No response, command ignored.
2. Command Followed by Data Word. No status response. Bits set: message error (SW).
3. T/R bit Set to Zero. No status response. Bits set: message error (SW), T/R Error, Low Word Count (BIT Word).
4. Zero T/R bit and Broadcast Address. No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code, T/R
Error, Low Word Count (BIT Word).
5. Broadcast Address. No status response. Bits set: message error, broadcast received (SW), Illegal Mode code, (BIT Word).
TABLE 6 – MODE CODES (con’t)
SCDCT2553PCB Rev A Preliminary 7/13/06
Aeroflex Plainview
23
SELECTED TRANSMITTER SHUTDOWN (10100)
MESSAGE SEQUENCE - TRANSMITTER SHUTDOWN DATA * STATUS
The data word received is transferred to the subsystem and status is transmitted. If the
command was broadcast, the broadcast received bit is set and status transmission suppressed. Intended for use with RTs with more
than one dual redundant channel.
ERROR CONDITIONS
1. Invalid Command. No response, command ignored.
2. Command Not Followed by Data Word. No status response. Bits set: message error (SW), High Word Count, Illegal Mode Code (BIT
Word).
3. Command Followed by too many Data Words. No status response. Bits set: message error (SW), Low Word Count, Illegal Mode
Code (BIT Word).
4. Command T/R bit Set to One. No status response. Bits set: message error (SW), Illegal Mode Code, High word count (BIT Word).
5. Command T/R bit Set to One and Broadcast Address. No status response. Bits set: message error, broadcast received (SW),
Illegal Mode Code, High Word Count (BIT Word).
OVERRIDE SELECTED TRANSMITTER SHUTDOWN (10101)
MESSAGE SEQUENCE - TRANSMITTER SHUTDOWN DATA * STATUS
The data word received after the command word is transferred to the subsystem. If the
command was broadcast, the broadcast received bit is set and status transmission suppressed.
ERROR CONDITIONS
1. Invalid Command. No response, command ignored.
2. Command Not Followed by Data Word. No status response. Bits set: message error (SW), Low Word Count, Illegal Mode Code (BIT
Word).
3. Command Followed by too many Data Words. No status response. Bits set: message error (SW), High Word Count, Illegal Mode
Code (BIT Word).
4. Command T/R bit Set to One. No status response. Bits set: message error (SW), Illegal Mode Code, High Word Count (Bit Word).
5. Command T/R bit Set to One and Broadcast Address. No status response. Bits set: message error, broadcast received (SW),
Illegal Mode Code, High Word Count, T/R (BIT Word).
RESERVED MODE CODES
MESSAGE SEQUENCE = RESERVED MODE CODE (T/R = 1) * STATUS
RESERVED MODE CODE (T/R = 0) * STATUS
The CT2553-PCB responds with status. If the command was broadcast, the broadcast received bit is set and status transmission
suppressed.
ERROR CONDITIONS (T/R = 1)
1. Invalid Command. No response, command ignored.
2. Command Followed by Data Word. No status response. Bits set: message error (SW), High Word Count, Illegal Mode Code (BIT
Word).
ERROR CONDITIONS (T/R = 0)
1. Invalid Command. No response, command ignored.
2. Command not Followed by Contiguous Data Word. No status response. Bits set: message error (SW), High word Count, Illegal
Mode Code (BIT Word).
3. Command Followed by too many Data Words. No status response. Bits set: message error (SW), High Word Count, Illegal Mode
Code (BIT Word).
TABLE 6 – MODE CODES (con’t)
SCDCT2553PCB Rev A Preliminary 7/13/06
Aeroflex Plainview
24
tr
16MHz Clock
(Internal)
See Note 1
STRBD
SELECT
IOEN
tz
td1
See Note 2
td8
td2
tpw1
READYD
MEM/REG
RD/WR
A02
A01
A00
td7
SSFLAG, SSBUSY, SVCRQST
DBAC, RTU/BC, MT, CTLOUT B/A
DATA LATCHED
Configuration Register Only
D15-D00
DATA VALID
td9
NOTE:
1. STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two clock cycles following release of bus.
2. CPU must release STRBD within 1.5µs of IOEN going active. READYD will go away within one clock cycle maximum.
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
td1
READYD low delay (CPU Handshake)
-
150
ns
td2
IOEN high delay (CPU Handshake)
-
20
ns
50
-
ns
tpw1
READYD pulse width (CPU Handshake)
td7
Internal Register delay (write)
-
60
ns
td8
Register Data/Address set-up time
-
30
ns
td9
Register Data/Address hold time
-
0
ns
tr
READYD to STRBD release
-
1.37
µs
tz
(SELECT • STRBD) to IOEN
-
1.8
µs
FIGURE 28 – CPU WRITES TO INTERNAL REGISTER
SCDCT2553PCB Rev A Preliminary 7/13/06
Aeroflex Plainview
25
tr
16MHz Clock
(Internal)
See Note 1
STRBD)
SELECT
td2
td1
See Note 2
IOEN
tz
td9
td8
tpw1
READYD
MEM/REG
RD/WR
A02
VALID
A01
VALID
A00
td5
EXTLD
tpw6
D15-D00
CPU DATA
NOTE:
1. STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two clock cycles following release of bus.
2. CPU must release STRBD within 1.5µs of IOEN going active. READYD will go away within one clock cycle maximum.
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
td1
READYD low delay (CPU Handshake)
-
150
ns
td2
IOEN high delay (CPU Handshake)
-
20
ns
READYD pulse width (CPU Handshake)
50
-
ns
td5
EXTLD low delay
50
-
ns
td8
Register Data/Address set-up time
-
30
ns
td9
Register Data/Address set-up time
-
0
ns
56
-
ns
tpw1
tpw6
EXTLD low pulse width
tr
READYD to STRBD release
-
1.37
µs
tz
(SELECT • STRBD) to IOEN
-
1.8
µs
FIGURE 29 – CPU WRITES TO EXTERNAL REGISTER
SCDCT2553PCB Rev A Preliminary 7/13/06
Aeroflex Plainview
26
tr
16MHz Clock
(Internal)
See Note 1
STRBD
SELECT
IOEN
See Note 2
td1
tz
READYD
td2
tpw1
MEM/REG
RD/WR
MEMCS
(Internal)
MEMOE
td4
A15-A00
RAM ADDRESS VALID
RAM DATA VALID
D15-D00
NOTE:
1. STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two clock cycles following release of bus.
2. CPU must release STRBD within 1.5µs of IOEN going active. READYD will go away within one clock cycle maximum.
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
td1
READYD low delay (CPU Handshake)
-
150
ns
td2
IOEN high delay (CPU Handshake)
-
20
ns
50
-
ns
CPU MEMOE low delay
-
100
ns
tr
READYD to STRBD release
-
1.37
µs
tz
(SELECT • STRBD) to IOEN
-
1.8
µs
tpw1
td4
READYD pulse width (CPU Handshake)
FIGURE 30 – CPU READS FROM RAM TIMING
SCDCT2553PCB Rev A Preliminary 7/13/06
Aeroflex Plainview
27
tr
16MHz Clock
(Internal)
See Note 1
STRBD
SELECT
IOEN
tz
See Note 2
td1
td2
tpw1
READYD
MEM/REG
RD/WR
MEMENA-OUT
td3
MEMWR
tpw2
A15-A00
RAM ADDRESS VALID
D15-D00
RAM DATA VALID
NOTE:
1. STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two clock cycles following release of bus.
2. CPU must release STRBD within 1.5µs of IOEN going active. READYD will go away within one clock cycle maximum.
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
td1
READYD low delay (CPU Handshake)
-
150
ns
td2
IOEN high delay (CPU Handshake)
-
20
ns
50
-
ns
-
120
ns
70
-
ns
tpw1
td3
tpw2
READYD pulse width (CPU Handshake)
CPU MEMWR low delay
CPU MEMWR low pulse width
tr
READYD to STRBD release
-
1.37
µs
tz
(SELECT • STRBD) to IOEN
-
1.8
µs
FIGURE 31 – CPU WRITES TO RAM TIMING
SCDCT2553PCB Rev A Preliminary 7/13/06
Aeroflex Plainview
28
tr
16MHz Clock
(Internal)
See Note
STRBD
SELECT
td1
IOEN
tz
td2
td8
tpw1
READYD
MEM/REG
RD/WR
A02 (38)
A01
A00
EXTEN
D15-D00
DATA FROM EXTERNAL REGISTER
NOTE: STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two clock cycles following release of bus.
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
td1
READYD low delay (CPU Handshake)
-
150
ns
td2
IOEN high delay (CPU Handshake)
-
20
ns
50
-
ns
Register Data/Address set-up time
-
40
ns
tr
READYD to STRBD release
-
1.37
µs
tz
(SELECT • STRBD) to IOEN
-
1.8
µs
tpw1
td8
READYD pulse width (CPU Handshake)
FIGURE 32 – CPU READS FROM EXTERNAL REGISTER TIMING
SCDCT2553PCB Rev A Preliminary 7/13/06
Aeroflex Plainview
29
tr
16MHz Clock
(Internal)
See Note 1
STRBD
SELECT
IOEN
td1
See Note 2
td6
tz
td2
READYD
tpw1
MEM/REG
RD/WR
A02
A01
A00
SSFLAG, SSBUSY, SVCRQST
DBAC, RTU/BC, MT, CTLIN B/A
DATA VALID
D15-D00
NOTE:
1. STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two clock cycles following release of bus.
2. CPU must release STRBD within 1.5µs of IOEN going active. READYD will go away within one clock cycle maximum.
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
td1
READYD low delay (CPU Handshake)
-
200
ns
td2
IOEN high delay (CPU Handshake)
-
20
ns
70
-
ns
tpw1
READYD pulse width (CPU Handshake)
td6
Internal Register delay (read)
-
60
ns
tr
READYD to STRBD release
-
1.37
µs
tz
(SELECT • STRBD) to IOEN
-
1.8
µs
FIGURE 33 – CPU READS FROM INTERNAL REGISTER TIMING
SCDCT2553PCB Rev A Preliminary 7/13/06
Aeroflex Plainview
30
Pin
Name
IIH (µA)
IIL (mA) IOH (µA) IOL (mA)
Description
1
D00
(5)
-0.4
-400
3.6
I/O Data Bus Bit 0 (LSB).
2
D02
(5)
-0.4
-400
3.6
I/O Data Bus Bit 2.
3
D04
(5)
-0.4
-400
3.6
I/O Data Bus Bit 4.
4
D06
(5)
-0.4
-400
3.6
I/O Data Bus Bit 6.
5
D08
(5)
-0.4
-400
3.6
I/O Data Bus Bit 8.
6
D10
(5)
-0.4
-400
3.6
I/O Data Bus Bit 10.
7
D12
(5)
-0.4
-400
3.6
I/O Data Bus Bit 12.
8
D14
(5)
-0.4
-400
3.6
I/O Data Bus Bit 14.
9
RTAD1
(5)
-0.4
-
-
Remote Terminal Address Bit 1.
10
RTAD0
(5)
-0.4
-
-
Remote Terminal Address Bit 0 (LSB)
11
RTAD4
(5)
-0.4
-
-
Remote Terminal Address Bit 4 (MSB)
12
ILLCMD
+10
±0.01
-
-
Legal Command. Defines the received command as illegal.
13
SA/MC-0 (6)
-
-
-400
2.0
14
Logic +5V
-
-
-
-
15
SA/MC-1 (6)
-
-
-400
2.0
Subaddress/Mode Command Bit 1. In MT mode, pulses every time 32
words have been stored. B7 counter.
16
BCSTRCV
-
-
-400
2.0
Broadcast Received. Indicates current command is a 1553 Broadcast
Command.
17
LMC
-
-
-400
2.0
Latched Mode Command. Logic 1 indicates current command word is a
mode code and selects MC0-MC4. Logic 0 indicates non-mode
comrnand and selects SA0-SA4.
18
-VEEB
-
-
-
-
18
TX DATA B
19
GNDB
19
TX DATA B
20
TX/RX-B
20
RXDATAB
21
Logic GND
22
23
Subaddress/Mode Command Bit 0. Multiplexed output bit-0 of
subaddress/word count field of the current command word. SA/MC
determined by the state of LMC.
+5V supply input for digital logic section. B6 counter.
-15V input power supply connection for the B channel transceiver.
CT2553-PCB VEEB -15V
CT2554-PCB VEEB -12V
CT2555-PCB VEEB No Connect
XXXXXXXXXXX
CT2556-PCB only
-
-
-
-
Ground B. Power supply return connection for the B channel
transceiver.
CT2553/4/5-PCB only
XXXXXXXXXXX
CT2556-PCB only
-
-
-
-
Transmit/Receive Transceiver-B. Input/output to the coupling
transformer that connects to the B channel of the 1553 Bus.
CT2553/4/5-PCB only
XXXXXXXXXXX
CT2556-PCB only
-
-
-
-
Logic Ground. Power supply return for the digital logic section.
A01
(5)
-0.4
-400
3.6
Address Bit 1
A03
(5)
-0.4
-400
3.6
Address Bit 3
24
A05
(5)
-0.4
-400
3.6
Address Bit 5
25
A07
(5)
-0.4
-400
3.6
Address Bit 7
26
A09
(5)
-0.4
-400
3.6
Address Bit 9
27
A11
(5)
-0.4
-400
3.6
Address Bit 11
28
A13
(5)
-0.4
-400
3.6
Address Bit 13
29
A15
(5)
-0.4
-400
3.6
Address Bit 15 (MSB)
TABLE 7 – PIN vs FUNCTION & LOADING (78 PIN DIP)
SCDCT2553PCB Rev A Preliminary 7/13/06
Aeroflex Plainview
31
Pin
Name
30
MEMOE
31
MEMENA-OUT
32
IIH (µA)
IIL (mA) IOH (µA) IOL (mA)
Description
-400
4.0
Memory Output Enable. A Logic 0 used to enable data output from
memory when the 1553 or CPU reads from memory.
Memory Enable Out. Low level output to enable external RAM. Used
with MEMOE to read data or with MEMWR to write data into external
RAM.
-
-
-400
4.0
CLOCK IN
±20
±0.02
-
-
Clock Input. 16 MHz TTL clock.
33
MEM/REG
(5)
-0.7
-
-
Memory/Register. Input from CPU to select memory or register data
transfer.
34
STRBD
(5)
-0.7
-
-
Strobe Data. Used in conjunction with SELECT to initiate a data
transfer cycle to/from CPU.
35
EXTEN
-
-
36
RD/WR
(5)
-0.7
External Enable. Used to load data into external devices.
-
-
Read/Write. Input from the CPU which defines the Data Bus transfer as
a read or write operation.
-
-
Ground A. Power supply return connection for the A channel
transceiver.
CT2553/4/5-PCB only
37
EXTLD
-
-
38
GNDA
-
-
38
TX DATA A
39
-VEEA
39
TX DATA A
40
TX/RX-A
40
RXDATAA
41
D01
(5)
-0.4
-400
3.6
I/O Data Bus Bit 1.
42
D03
(5)
-0.4
-400
3.6
I/O Data Bus Bit 3.
43
D05
(5)
-0.4
-400
3.6
I/O Data Bus Bit 5.
44
D07
(5)
-0.4
-400
3.6
I/O Data Bus Bit 7.
45
D09
(5)
-0.4
-400
3.6
I/O Data Bus Bit 9.
46
D11
(5)
-0.4
-400
3.6
I/O Data Bus Bit 11.
47
D13
(5)
-0.4
-400
3.6
I/O Data Bus Bit 13.
48
D15
(5)
-0.4
-400
3.6
I/O Data Bus Bit 15 (MSB).
49
RTAD3
(5)
-0.4
-
-
Remote Terminal Address Bit 3.
50
RTAD2
(5)
-0.4
-
-
Remote Terminal Address Bit 2.
51
RTADP
(5)
-0.4
-
-
Remote Terminal Address Parity input.
52
SA/MC-2 (6)
-
-
-400
2.0
Subaddress/Mode Command Bit 2. B8 (MSB) counter.
53
SA/MC-4
-
-
-400
2.0
Subaddress/Mode Command Bit 4.
54
SA/MC-3
-
-
-400
2.0
Subaddress/Mode Command Bit 3.
55
THIS-RT
-
-
-400
2.0
Logic 0 pulse indicates receipt of a valid command word which
contains the Remote Terminal address equivalent to the
RTADO-RTAD4 inputs.
56
RTPARERR
-
-
-400
2.0
RTU (address) Parity Error. Logic 0 indicates RTU address parity (odd
parity: RTADO-RTAD4, RTADP) has been violated.
External load. Used to load data into external devices.
XXXXXXXXXXX
CT2556-PCB only
-
-
-
-
-I5V input power supply connection for the A channel transceiver.
CT2553-PCB VEEA -15V
CT2554-PCB VEEA -12V
CT2555-PCB VEEA No Connect
XXXXXXXXXXX
CT2556-PCB only
-
-
-
-
Transmit/Receive Transceiver-A. Input/Output to the coupling
transformer that connects to the A channel of the 1553 Bus.
CT2553/4/5-PCB only
XXXXXXXXXXX
CT2556-PCB only
TABLE 7 – PIN vs FUNCTION & LOADING (78 PIN DIP) (con’t)
SCDCT2553PCB Rev A Preliminary 7/13/06
Aeroflex Plainview
32
IIH (µA)
IIL (mA) IOH (µA) IOL (mA)
Description
Pin
Name
57
T/R
-
-
-400
2.0
58
+5VB
-
-
-
-
58
TXINHB
59
TX/RX-B
59
RXDATAB
60
A00
(5)
-0.4
-400
3.6
Address Bit 0 (LSB).
61
A02
(5)
-0.4
-400
3.6
Address Bit 2.
62
A04
(5)
-0.4
-400
3.6
Address Bit 4.
63
A06
(5)
-0.4
-400
3.6
Address Bit 6.
64
A08
(5)
-0.4
-400
3.6
Address Bit 8.
65
A10
(5)
-0.4
-400
3.6
Address Bit 10.
66
A12
(5)
-0.4
-400
3.6
Address Bit 12.
67
A14
(5)
-0.4
-400
3.6
Address Bit 14.
68
MEMWR
-
-
-400
4.0
Memory Write. Output pulse to write data into memory.
69
MEMENA-IN
±20
±0.02
-
-
Memory Enable In. Enables internal RAM only; connect directly to
MEMENA-OUT.
70
INCMD
-
-
-400
2.0
In Command. Indicates BC or RTU currently in message transfer
sequence.
71
MSTRCLR
(5)
-0.7
-
-
72
INT
-
-
-400
4.0
Interrupt. Interrupt pulse line to CPU.
73
IOEN
-
-
-400
4.0
Input/Output Enable. Output to enable external hybrid to the
address/data bus.
74
SELECT
(5)
-0.7
-
-
Select. Input from the CPU. When active, selects CT2553 for
operation.
75
READYD
-
-
-400
4.0
Ready Data. When active indicates data has been received from, or is
available to, the CPU.
76
TAGEN
-
-
-400
4.0
Tag Enable. Enables an external time to counter for transferring the
time tag word into memory.
77
+5VA
-
-
-
-
77
TXINHA
78
TX/RX-A
78
RXDATAA
1.
2.
3.
4.
5.
6.
Transmit/Receive 1553 data. Latched T/R bit from current command
word.
+5V power supply connection for the B channel transceiver.
CT2553/4/5-PCB only
XXXXXXXXXXX
CT2556-PCB only
-
-
-
-
Transmit/Receive transceiver-B. Inverted I/O to coupling transformer
that connects to channel B of the 1553 Bus.
XXXXXXXXXXX
CT2556-PCB
Master Clear. Power-on reset from CPU.
+5V input/power supply for channel A transceiver.
CT2553/4/5-PCB only
XXXXXXXXX
CT2556-PCB only
-
-
-
-
Transmit/Receive transceiver-A. Inverted I/O to the coupling
transformer that connects to the A channel of the 1553 Bus.
CT2553/4/5-PCB only
XXXXXXXXX
CT2556-PCB only
IIH is specified at: VCC = 5.5V, VIH = 2.7V.
IIL is specified at: VCC = 5.5V, VIL = 0.4V.
IOH is specified at: VCC = 4.5V, VIH = 2.4V.
IOL is specified at: VCC = 4.5V, VIH = 0.4V.
Internal Pull-up Resistor = 33K Ohms, Typ.
Pin 13 = B6, Pin 15 = B7 and Pin 52 = B8 (MSB). B6, B7 and B8 are the MSB lines of an 8 BIT Counter used in the BC and MT mode to count
32 WORD TRANSFERS to memory (16 words received off the bus) for a total of 128 DATA and Tag words (in MT mode). (See pages 19 &
20 for discussion.)
TABLE 7 – PIN vs FUNCTION & LOADING (78 PIN DIP) (con’t)
SCDCT2553PCB Rev A Preliminary 7/13/06
Aeroflex Plainview
33
Table 8A – CT2553/4/5-PCB Pin Out
Description (DIP)
Pin
#
1
41
2
42
3
43
4
44
5
45
6
46
7
47
8
48
9
49
10
50
11
51
12
52
13
53
14
54
15
55
16
56
17
57
18
58
19
59
20
D00
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15
RTAD1
RTAD3
RTAD0
RTAD2
RTAD4
RTADP
ILLCMD
SA/MC-2
SA/MC-0
SA/MC-4
LOGIC +5V
SA/MC-3
SA/MC-1
THIS-RT
BCSTRCV
RTPARERR
LMC
T/R
-VEEB
+5VB
GNDB
TX/RX-B
TX/RX-B
LOGIC GND
A00
A01
A02
MIL-STD-1553
A03
BUS Controller,
A04
Remote Terminal and
A05
A06
BUS Monitor
A07
A08
A09
A10
A11
A12
A13
A14
A15
MEMWR
MEMOE
MEMENA-IN
MEMENA-OUT
INCMD
CLOCK IN
MSTRCLR
MEM/REG
INT
STRBD
IOEN
EXTEN
SELECT
RD/WR
READYD
EXTLD
TAGEN
GNDA
+5VA
-VEEA
TX/RX-A
TX/RX-A
CT2553 / 4 / 5-PCB
21
60
22
61
23
62
24
63
25
64
26
65
27
66
28
67
29
68
30
69
31
70
32
71
33
72
34
73
35
74
36
75
37
76
38
77
39
78
40
Function
Pin
#
Function
1
D00
40
TX/RX-A
2
D02
41
D01
3
D04
42
D03
4
D06
43
D05
5
D08
44
D07
6
D10
45
D09
7
D12
46
D11
8
D14
47
D13
9
RTAD1
48
D15
10
RTAD0
49
RTAD3
11
RTAD4
50
RTAD2
12
ILLCMD
51
RTADP
13
SA/MC-0
52
SA/MC-2
14
LOGIC +5V
53
SA/MC-4
15
SA/MC-1
54
SA/MC-3
16
BCSTRCV
55
THIS-RT
17
LMC
56
RTPARERR
18
-VEEB
57
T/R
19
GNDB
58
+5VB
20
TX/RX-B
59
TX/RX-B
21
LOGIC GND
60
A00
22
A01
61
A02
23
A03
62
A04
24
A05
63
A06
25
A07
64
A08
26
A09
65
A10
27
A11
66
A12
28
A13
67
A14
29
A15
68
MEMWR
30
MEMOE
69
MEMENA-IN
31
MEMENA-OUT
70
INCMD
32
CLOCK IN
71
MSTRCLR
33
MEM/REG
72
INT
34
STRBD
73
IOEN
35
EXTEN
74
SELECT
36
RD/WR
75
READYD
37
EXTLD
76
TAGEN
38
GNDA
77
+5VA
39
-VEEA
78
TX/RX-A
NOTE:
1. For VEEA & VEEB conditions see Table 1 or 7. VEEA & VEEB are no connect for CT2555-PCB.
DIP PIN CONNECTION DIAGRAM, CT2553/4/5-PCB AND PINOUT
SCDCT2553PCB Rev A Preliminary 7/13/06
Aeroflex Plainview
34
Table 8B – CT2553/4/5-PCB Pin Out
Description (FP)
Pin
#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
N/C
D00
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15
RTAD1
RTAD3
RTAD0
RTAD2
RTAD4
RTADP
ILLCMD
SA/MC-2
SA/MC-0
SA/MC-4
LOGIC +5V
SA/MC-3
SA/MC-1
THIS-RT
BCSTRCV
RTPARERR
LMC
T/R
-VEEB
+5VB
GNDB
TX/RX-B
TX/RX-B
N/C
N/C
LOGIC GND
A00
A01
A02
MIL-STD-1553
A03
BUS Controller,
A04
A05
Remote Terminal and
A06
BUS Monitor
A07
A08
A09
A10
A11
A12
A13
A14
A15
MEMWR
MEMOE
MEMENA-IN
MEMENA-OUT
INCMD
CLOCK IN
MSTRCLR
MEM/REG
INT
STRBD
IOEN
EXTEN
SELECT
RD/WR
READYD
EXTLD
TAGEN
GND A
+5VA
-VEEA
TX/RX-A
TX/RX-A
CT2553 / 4 / 5 FP-PCB
N/C
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
Function
Pin
#
Function
1
N/C
42
N/C
2
D00
43
TX/RX-A
3
D01
44
TX/RX-A
4
D02
45
-VEEA
5
D03
46
+5VA
6
D04
47
GND A
7
D05
48
TAGEN
8
D06
49
EXTLD
9
D07
50
READYD
10
D08
51
RD/WR
11
D09
52
SELECT
12
D10
53
EXTEN
13
D11
54
IOEN
14
D12
55
STRBD
15
D13
56
INT
16
D14
57
MEM/REG
17
D15
58
MSTRCLR
18
RTAD1
59
CLOCK IN
19
RTAD3
60
INCMD
20
RTAD0
61
MEMENA-OUT
21
RTAD2
62
MEMENA-IN
22
RTAD4
63
MEMOE
23
RTADP
64
MEMWR
24
ILLCMD
65
A15
25
SA/MC-2
66
A14
26
SA/MC-0
67
A13
27
SA/MC-4
68
A12
28
LOGIC +5V
69
A11
29
SA/MC-3
70
A10
30
SA/MC-1
71
A09
31
THIS-RT
72
A08
32
BCSTRCV
73
A07
33
RTPARERR
74
A06
34
LMC
75
A05
35
T/R
76
A04
36
-VEEB
77
A03
37
+5VB
78
A02
38
GNDB
79
A01
39
TX/RX-B
80
A00
40
TX/RX-B
81
LOGIC GND
41
N/C
82
N/C
NOTE:
1. For VEEA & VEEB conditions see Table 1 or 7. VEEA & VEEB are no connect for CT2555-PCB.
FLAT PACKAGE PIN CONNECTION DIAGRAM, CT2553/4/5-PCB AND PINOUT
SCDCT2553PCB Rev A Preliminary 7/13/06
Aeroflex Plainview
35
Table 9A – CT2556-PCB Pin Out
Description (DIP)
Pin
#
1
41
2
42
3
43
4
44
5
45
6
46
7
47
8
48
9
49
10
50
11
51
12
52
13
53
14
54
15
55
16
56
17
57
18
58
19
59
20
D00
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15
RTAD1
RTAD3
RTAD0
RTAD2
RTAD4
RTADP
ILLCMD
SA/MC-2
SA/MC-0
SA/MC-4
LOGIC +5V
SA/MC-3
SA/MC-1
THIS-RT
BCSTRCV
RTPARERR
LMC
T/R
TX DATA B
TX INH B
TX DATA B
RX DATA B
RX DATA B
LOGIC GND
A00
A01
A02
MIL-STD-1553
A03
BUS Controller,
A04
Remote Terminal and
A05
A06
BUS Monitor
A07
A08
A09
A10
A11
A12
A13
A14
A15
MEMWR
MEMOE
MEMENA-IN
MEMENA-OUT
INCMD
CLOCK IN
MSTRCLR
MEM/REG
INT
STRBD
IOEN
EXTEN
SELECT
RD/WR
READYD
EXTLD
TAGEN
TX DATA A
TX INH A
TX DATA A
RX DATA A
RX DATA A
CT2556-PCB
21
60
22
61
23
62
24
63
25
64
26
65
27
66
28
67
29
68
30
69
31
70
32
71
33
72
34
73
35
74
36
75
37
76
38
77
39
78
40
Function
Pin
#
Function
1
D00
40
RX DATA A
2
D02
41
D01
3
D04
42
D03
4
D06
43
D05
5
D08
44
D07
6
D10
45
D09
7
D12
46
D11
8
D14
47
D13
9
RTAD1
48
D15
10
RTAD0
49
RTAD3
11
RTAD4
50
RTAD2
12
ILLCMD
51
RTADP
13
SA/MC-0
52
SA/MC-2
14
LOGIC +5V
53
SA/MC-4
15
SA/MC-1
54
SA/MC-3
16
BCSTRCV
55
THIS-RT
17
LMC
56
RTPARERR
18
TX DATA B
57
T/R
19
TX DATA B
58
TX INH B
20
RX DATA B
59
RX DATA B
21
LOGIC GND
60
A00
22
A01
61
A02
23
A03
62
A04
24
A05
63
A06
25
A07
64
A08
26
A09
65
A10
27
A11
66
A12
28
A13
67
A14
29
A15
68
MEMWR
30
MEMOE
69
MEMENA-IN
31
MEMENA-OUT
70
INCMD
32
CLOCK IN
71
MSTRCLR
33
MEM/REG
72
INT
34
STRBD
73
IOEN
35
EXTEN
74
SELECT
36
RD/WR
75
READYD
37
EXTLD
76
TAGEN
38
TX DATA A
77
TX INH A
39
TX DATA A
78
RX DATA A
DIP PIN CONNECTION DIAGRAM, CT2556-PCB AND PINOUT
SCDCT2553PCB Rev A Preliminary 7/13/06
Aeroflex Plainview
36
Table 9B – CT2556-PCB Pin Out
Description (FP)
Pin
#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
N/C
D00
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15
RTAD1
RTAD3
RTAD0
RTAD2
RTAD4
RTADP
ILLCMD
SA/MC-2
SA/MC-0
SA/MC-4
LOGIC +5V
SA/MC-3
SA/MC-1
THIS-RT
BCSTRCV
RTPARERR
LMC
T/R
TX DATA B
TX INH B
TX DATA B
RX DATA B
RX DATA B
N/C
N/C
LOGIC GND
A00
A01
MIL-STD-1553
A02
A03
BUS Controller,
A04
Remote Terminal and
A05
BUS Monitor
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
MEMWR
MEMOE
MEMENA-IN
MEMENA-OUT
INCMD
CLOCK IN
MSTRCLR
MEM/REG
INT
STRBD
IOEN
EXTEN
SELECT
RD/WR
READYD
EXTLD
TAGEN
TX DATA A
TX INH A
TX DATA A
RX DATA A
RX DATA A
CT2556FP-PCB
N/C
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
Function
Pin
#
Function
1
N/C
42
N/C
2
D00
43
RX DATA A
3
D01
44
RX DATA A
4
D02
45
TX DATA A
5
D03
46
TX INH A
6
D04
47
TX DATA A
7
D05
48
TAGEN
8
D06
49
EXTLD
9
D07
50
READYD
10
D08
51
RD/WR
11
D09
52
SELECT
12
D10
53
EXTEN
13
D11
54
IOEN
14
D12
55
STRBD
15
D13
56
INT
16
D14
57
MEM/REG
17
D15
58
MSTRCLR
18
RTAD1
59
CLOCK IN
19
RTAD3
60
INCMD
20
RTAD0
61
MEMENA-OUT
21
RTAD2
62
MEMENA-IN
22
RTAD4
63
MEMOE
23
RTADP
64
MEMWR
24
ILLCMD
65
A15
25
SA/MC-2
66
A14
26
SA/MC-0
67
A13
27
SA/MC-4
68
A12
28
LOGIC +5V
69
A11
29
SA/MC-3
70
A10
30
SA/MC-1
71
A09
31
THIS-RT
72
A08
32
BCSTRCV
73
A07
33
RTPARERR
74
A06
34
LMC
75
A05
35
T/R
76
A04
36
TX DATA B
77
A03
37
TX INH B
78
A02
38
TX DATA B
79
A01
39
RX DATA B
80
A00
40
RX DATA B
81
LOGIC GND
41
N/C
82
N/C
FLAT PACKAGE PIN CONNECTION DIAGRAM, CT2556-PCB AND PINOUT
SCDCT2553PCB Rev A Preliminary 7/13/06
Aeroflex Plainview
37
PLUG-IN PCB TYPICAL OUTLINE
TOP VIEW
1.870
1.650
Lead 1 & ESD
Designator
1.500
Pin 60
Pin 41
Pin 1
Pin 21
.100
TYP
FPGA
PROTOCOL
.050
TYP
1.900
2.100
1.800
.018 DIA
TYP
DUAL
TRANSCEIVER
Pin 59
Pin 20
Pin 78
Pin 40
PLUG-IN SIDE VIEW
(Components on both sides of PCB)
TOP
BOTTOM
.300 MAX
from highest
component
.190 MIN
SCDCT2553PCB Rev A Preliminary 7/13/06
Aeroflex Plainview
38
FLAT PCB TYPICAL OUTLINE
1.610
.400
MIN
Lead 1 & ESD
Designator
Pin 82
2.000
.050
Lead
Centers
41
Leads/Side
.050
TYP
2.200
.018
TYP
DUAL
TRANSCEIVER
Pin 41
Pin 42
FLAT PCB SIDE VIEW
(Components on both sides of PCB)
TOP
.110 MAX
from bottom highest
component
.300 MAX
from highest
component
.010
±.002
BOTTOM
SCDCT2553PCB Rev A Preliminary 7/13/06
Aeroflex Plainview
39
ORDERING INFORMATION
Model Number
CT2553-PCB
* CT2553-FP-PCB
Screening
Power Supply
Package
In accordance with Pending MIL-PRF-38534,
Appendix D, Class B.
-55°C to +95°C
+5V, -15V
Plug in
Flat Package
CT2554-PCB
+5V, -12V
* CT2554-FP-PCB
Plug in
Flat Package
CT2555-PCB
+5V only
* CT2555-FP-PCB
Plug in
Flat Package
** CT2556-PCB
Plug in
** CT2556-FP-PCB
Flat Package
* Contact factory for LOWER profile option
** Contact Factory for Availability
PLAINVIEW, NEW YORK
Toll Free: 800-THE-1553
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www.aeroflex.com
[email protected]
Aeroflex Microelectronic Solutions reserves the right to
change at any time without notice the specifications, design,
function, or form of its products described herein. All
parameters must be validated for each customer's application
by engineering. No liability is assumed as a result of use of
this product. No patent licenses are implied.
Our passion for performance is defined by three
attributes represented by these three icons:
solution-minded, performance-driven and customer-focused
SCDCT2553PCB Rev A 7/13/06
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