CT2561 Bus Controller, Remote Terminal and BUS Monitor FOR MIL-STD-1553B Features ■ ■ ■ ■ ■ ■ ■ ■ C F LE X LA ISO 9001 E I NC . ■ www.aeroflex.com S ■ CIRCUIT TECHNOLOGY B ■ Second Source Compatible to the BUS-65610 16MHz CT2565 Replacement RTU implements all dual redundant mode codes Selective mode code illegalization available 16 bit microprocessor compatibility BC checks status word for correct address and set flags RTU illegal mode codes externally selectable 16 bit µProcessor compatibility DMA handshaking for subsystem message transfers Continuous On-Line and Initiated Built-In-Test MIL-PRF-38534 compliant circuits available Packaging – Hermetic Metal • 78 Pin, 2.1" x 1.87" x .25" Plug-In type package • 82 Lead, 2.2" x 1.61" x .18" Flat package A E RO ■ RTIFIED General Description The CT2561 is a 16 MHz single chip dual redundant MIL-STD-1553 Bus Controller (BC), Remote Terminal Unit (RTU) and Bus Monitor (MT). Packaged in a hybrid plug-in or flatpack, the CT2561 performs all the functions required to interface a MIL-STD-1553 dual redundant serial data bus such as ACT4487 and a subsystem parallel three-state data bus. Using a single Aeroflex custom monolithic ASIC design, the CT2561 features pin-for-pin and functional CT2565 compatibility, user initiated self-test, and low power consumption. Compatible with most microprocessors the CT2561 provides a 16bit three-state parallel data bus and uses direct memory access (DMA type) handshaking for subsystem transfers. All message transfer timing, DMA and control lines are provided internally, thereby reducing the subsystem overhead associated with message transfers. The CT2561 implements all dual redundant MIL-STD-1553 mode codes. In addition, any mode code may (Optionally) be legalized through the use of an external PROM. Complete error detection is provided by the CT2561 for BC and RTU operation. Error detection includes: response time-out, inter-message gaps, sync, parity, Manchester, word count and bit count. The CT2561 is fully compliant with MIL-STD-1553, is available screened in accordance with the requirements of MIL-STD-883 and operates over the full military temperature range of -55°C to +125°C. eroflex Circuit Technology – Data Bus Modules For The Future © SCDCT2561 REV A 8/16/99 Aeroflex Circuit Technology 2 SCDCT2561 REV A 8/16/99 Plainview NY (516) 694-6700 B B B B B 16MHz RTADR0 RTADR1 RTADR2 RTADR3 RTADR4 RTADRP TXINH TXDATA TXDATA RXDATA RXDATA TXINH A TXDATA A TXDATA A RXDATA A RXDATA A RTADDR RTADDR CH B ENCODE/ DECODE CH A ENCODE/ DECODE RTADDR PARITY CHECKER CONTROL BUS BUS CONTROLLER LOGIC DATA BUS REMOTE TERMINAL LOGIC Figure 1 – CT2561 Block Diagram CH B CONTROL CH A CONTROL I/O BUS EN I/O LOGIC BUFFERS R/W DATA BUFFERS MODE CODE CONTROL STATUS INPUTS BUSREQ BUSGRNT BUSACK TIMEOUT SOM EOM INCMD CS OE WR TESTIN TESTOUT RT/BC MT BCSTART CHA/CHB LOOPERR MSGERR STATERR LWORD HSFAIL STATEN BITEN NBGRNT ADRINC NODT BSCTRCV BUFENA I/O0 - I/O16 WC0-WC4 T/R LMC ILLCMD DBACCEPT SSFLAG SERREQ SSERR SSBUSY Table 1A – Pin Function Table (78 Pin Plug-In) Pin # Symbol I/O 1 RT/BC I Mode Select input - logic "1" for RT mode, logic “0” for BC mode. 2 MT I Monitor mode enable. When unit is operating as a BC, a logic “0” will select monitor mode. 3 STATEN O Output signal in RT mode that indicates status word is being transferred on the internal bus. 4 TIMEOUT O Indicates No Response Timeout has occurred during BC and RTU (RT to RT transfer). 5 HSFAIL O Output in RT mode indicating the DMA transfer did not occur in time to allow proper operation on the 1553 bus. 6 DBACCEPT I Input signal used to set DBACCEPT bit in status register for response to a valid mode command on the 1553 bus. 7 SSFLAG I Input which controls the SSFLAG bit in the status register. 8 SVCREQ I Input which controls the service request bit in the status word. 9 INCMD O Output signal indicating the RT is currently in a message transfer sequence. 10 SSER I Input which controls the subsystem error bit in the status register. 11 TESTOUT - Factory test point. Do not connect. 12 WC1 O WC bit 1 - latched output of command word. 13 WC3 O WC bit 3 - latched output of command word. 14 TXINH B O Transmitter inhibit output for channel B. 15 T/R O Output indicating T/R bit of current command word in RT mode. 16 CHA/CHB O Output indicating current selected channel (0 = Channel A). 17 CS O Chip Select output for subsystem memory control. 18 OE O Output Enable output for subsystem memory control. 19 BUSREQ O Output signal used to initiate transfer to/from subsystem. 20 +5V I +5 Volt DC input. 21 DB0(LSB) I/O Least significant bit - 16 bit parallel data bus. 22 DB2 I/O Bit 2 of data bus. 23 DB4 I/O Bit 4 of data bus. 24 DB6 I/O Bit 6 of data bus. 25 DB8 I/O Bit 8 of data bus. 26 DB10 I/O Bit 10 of data bus. 27 DB12 I/O Bit 12 of data bus. 28 DB14 I/O Bit 14 of data bus. Aeroflex Circuit Technology Description 3 SCDCT2561 REV A 8/16/99 Plainview NY (516) 694-6700 Table 1A – Pin Function Table (78 Pin Plug-In) (continued) Pin # Symbol I/O 29 LWORD - Last word output during BC mode indicates last data word of the current message transfer has been transferred on the parallel bus. 30 MSGERR O Output signal which indicates an error occurred during the current message sequence. 31 TXDATA A O Bipolar serial data output to positive input of bus transceiver. 32 RXDATA A I Bipolar serial input from negative output of bus transceiver. 33 RTADP I Parity bit input for RT address. 34 RTAD1 I Bit 1 of RT address input. 35 RTAD3 I Bit 3 of RT address input. 36 RESET I System reset input - resets all inputs in module. 37 TXDATA B O Bipolar serial data output to negative input bus transceiver. 38 RXDATA B I Bipolar serial data input from positive output of bus transceiver. 39 16MHz I 16MHz TTL clock input. 40 GROUND - Signal ground. 41 BCSTART I Cycle enable input Logic "0" initiates bus controller message transfer operation. 42 NBGRNT O New bus grant output from RT indicates beginning of message transfer sequence. 43 BITEN O Built in Test enable output indicates RT is transferring BlT word on internal 16 bit bus. 44 WR O Write enable output for control of subsystem memory. 45 BUSGRNT I Bus request input in response to DTREQ. Allows BC/RT to transfer data to subsystem. 46 LOOPERR O Loop error output. Logic "0" indicates failure of loop back transmitted data. 47 SSBUSY I Subsystem busy input for RT status word. 48 ILLCMD I Illegal command input to RT, used to block RT response to an illegal command. 49 ADRINC O Increment output pulse. Goes LOW at the completion of each word transfer to/from subsystem. Can increment external address counter. 50 CHASSIS - Frame ground electricity isolated from signal ground 51 WC0 O LSB of current command word count field. 52 WC2 O Bit 2 of word count field. 53 WC4 O Bit 4 of word count field. 54 TXINH A O Transmitter inhibit output signal for Channel A. 55 LMC O Latched Mode Command. Logic "1" indicates current word command is a mode code word, WC0-WC4. 56 TESTIN - Factory test point. Do not connect. Aeroflex Circuit Technology Description 4 SCDCT2561 REV A 8/16/99 Plainview NY (516) 694-6700 Table 1A – Pin Function Table (78 Pin Plug-In) (continued) Pin # Symbol I/O 57 EOM O End of message output. Logic "0" occurs when BC/RT message is completed. 58 BUFENA I Buffer enable input, may be driven LOW by STATEN or BITEN if subsystem must read bit or Status words. Enables internal 16 bit bus onto subsystem bus. 59 BUSACK O Bus acknowledge output. LOW during DMA Handshake, in response to BUSGRNT. 60 DB1 I/O Bit 1 of 16 bit parallel bus. 61 DB3 I/O Bit 3 of 16 bit parallel bus. 62 DB5 I/O Bit 5 of 16 bit parallel bus. 63 DB7 I/O Bit 7 of 16 bit parallel bus. 64 DB9 I/O Bit 9 of 16 bit parallel bus. 65 DB11 I/O Bit 11 of 16 bit parallel bus. 66 DB13 I/O Bit 13 of 16 bit parallel bus. 67 DB15(MSB) I/O Bit 15 of 16 bit parallel bus. 68 STATERR O BC output indicates one or more bits set or address mismatch in a received status word. 69 TXDATA A O Bipolar serial data output to negative input of bus transceiver. 70 RXDATA A I Bipolar serial data input from positive output of bus transceiver. 71 NODT O No data input. Logic "0" indicates the 1553 bus is idle; HIGH means device front end is active. 72 RTAD0 I LSB of 5 bit RT address. 73 RTAD2 I Bit 2 of RT address. 74 RTAD4 I Bit 4 of RT address. 75 BCSTRCV O Broadcast receive. Logic "0" means the current command was a broadcast command. 76 TXDATA B O Bipolar serial output to positive input of bus transceiver. 77 RXDATA B I Bipolar serial input from negative output of bus transceiver. 78 SOM O Start of message output indicates beginning of RT/BC message transfer sequence. Aeroflex Circuit Technology Description 5 SCDCT2561 REV A 8/16/99 Plainview NY (516) 694-6700 Table 1B – CT2561 Pin Out Description (Plug-In) Pin # 1 41 2 42 3 43 4 44 5 45 6 46 7 47 8 48 9 49 10 50 11 51 12 52 13 53 14 54 15 55 16 56 17 57 18 58 19 59 20 RT/BC BCSTART MT NBGRNT STATEN BITEN TIMEOUT WR HSFAIL BUSGRNT DBACCEPT LOOPERR SSFLAG SSBUSY SVCREQ ILLCMD INCMD ADRINC SSER CASE GND TESTOUT WC0 WC1 WC2 WC3 WC4 TXINH B TXINH A T/R LMC CHB/CHA TESTIN CS EOM OE BUFENA BUSREQ BUSACK +5 Volt CT2561 MIL-STD-1553 BUS Controller, Remote Terminal and BUS MONITOR DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 (MSB) LWORD STATERR MSGERR TXDATA A TXDATA A RXDATA A RXDATA A NODT RTADP RTAD0 RTAD1 RTAD2 RTAD3 RTAD4 RESET BCSTRCV TXDATA B TXDATA B RXDATA B RXDATA B 16MHz SOM GND 21 60 22 61 23 62 24 63 25 64 26 65 27 66 28 67 29 68 30 69 31 70 32 71 33 72 34 73 35 74 36 75 37 76 38 77 39 78 40 Function Pin # Function 1 RT/BC 40 GND 2 MT 41 BCSTART 3 STATEN 42 NBGRNT 4 TIMEOUT 43 BITEN 5 HSFAIL 44 WR 6 DBACCEPT 45 BUSGRNT 7 SSFLAG 46 LOOPERR 8 SVCREQ 47 SSBUSY 9 INCMD 48 ILLCMD 10 SSER 49 ADRINC 11 TESTOUT 50 CASE GND 12 WC1 51 WC0 13 WC3 52 WC2 14 TXINH B 53 WC4 15 T/R 54 TXINH A 16 CHB/CHA 55 LMC 17 CS 56 TESTIN 18 OE 57 EOM 19 BUSREQ 58 BUFENA 20 + 5 Volt 59 BUSACK 21 DB0 (LSB) 60 DB1 22 DB2 61 DB3 23 DB4 62 DB5 24 DB6 63 DB7 25 DB8 64 DB9 26 DB10 65 DB11 27 DB12 66 DB13 28 DB14 67 DB15 (MSB) 29 LWORD 68 STATERR 30 MSGERR 69 TXDATA A 31 TXDATA A 70 RXDATA A 32 RXDATA A 71 NODT 33 RTADP 72 RTAD0 34 RTAD1 73 RTAD2 35 RTAD3 74 RTAD4 36 RESET 75 BCSTRCV 37 TXDATA B 76 TXDATA B 38 RXDATA B 77 RXDATA B 39 16MHz 78 SOM Plug-In Pin Connection Diagram, CT2561 and Pinout Aeroflex Circuit Technology 6 SCDCT2561 REV A 8/16/99 Plainview NY (516) 694-6700 Table 2 – CT2561 Pin Out Description (FP) Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 N/C RT/BC BCSTART MT NBGRNT STATEN BITEN TIMEOUT WR HSFAIL BUSGRNT DBACCEPT LOOPERR SSFLAG SSBUSY SVCREQ ILLCMD INCMD ADRINC SSER CASE GND TESTOUT WC0 WC1 WC2 WC3 WC4 TXINH B TXINH A T/R LMC CHB/CHA TESTIN CS EOM OE BUFENA BUSREQ BUSACK +5V N/C N/C CT2561FP MIL-STD-1553 BUS Controller, Remote Terminal and BUS MONITOR DB0 (LSB) DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 (MSB) LWORD STATERR MSGERR TXDATA A TXDATA A RXDATA A RXDATA A NODT RTADP RTAD0 RTAD1 RTAD2 RTAD3 RTAD4 RESET BCSTRCV TXDATA B TXDATA B RXDATA B RXDATA B 16MHz SOM GROUND N/C 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 Function Pin # Function 1 N/C 42 N/C 2 RT/BC 43 GROUND 3 BCSTART 44 SOM 4 MT 45 16MHz 5 NBGRNT 46 RXDATA B 6 STATEN 47 RXDATA B 7 BITEN 48 TXDATA B 8 TIMEOUT 49 TXDATA B 9 WR 50 BCSTRCV 10 HSFAIL 51 RESET 11 BUSGRNT 52 RTAD4 12 DBACCEPT 53 RTAD3 13 LOOPERR 54 RTAD2 14 SSFLAG 55 RTAD1 15 SSBUSY 56 RTAD0 16 SVCREQ 57 RTADP 17 ILLCMD 58 NODT 18 INCMD 59 RXDATA A 19 ADRINC 60 RXDATA A 20 SSER 61 TXDATA A 21 CASE GND 62 TXDATA A 22 TESTOUT 63 MSGERR 23 WC0 64 STATERR 24 WC1 65 LWORD 25 WC2 66 DB15 (MSB) 26 WC2 67 DB14 27 WC4 68 DB13 28 TXINH B 69 DB12 29 TXINH A 70 DB11 30 T/R 71 DB10 31 LMC 72 DB9 32 CHB/CHA 73 DB8 33 TESTIN 74 DB7 34 CS 75 DB6 35 EOM 76 DB5 36 OE 77 DB4 37 BUFENA 78 DB3 38 BUSREQ 79 DB2 39 BUSACK 80 DB1 40 +5V 81 DB0 (LSB) 41 N/C 82 N/C Flat Package Pin Connection Diagram, CT2561 and Pinout Aeroflex Circuit Technology 7 SCDCT2561 REV A 8/16/99 Plainview NY (516) 694-6700 2.100 1.870 Lead 1 & ESD Designator 1.900 .100 .110 Pin 2 Pin 1 .050 Pin 19 TYP Pin 20 .250 MAX Pin 59 Pin 41 .018 DIA TYP 1.650 1.500 Pin 60 Pin 78 Pin 21 Pin 22 .100 TYP Pin 40 Pin 39 .250 1.800 Figure 2 – Plug In Package Outline .050 2.200 MAX .010 ±.002 .015 Pin 42 Pin 82 .180 MAX 1.610 MAX Lead 1 & ESD Designator .400 MIN .095 (4 Places) Pin 41 2.000 .050 Lead Centers 41 Leads/Side .080 Figure 3 – Flat Package Outline Aeroflex Circuit Technology 8 SCDCT2561 REV A 8/16/99 Plainview NY (516) 694-6700 CIRCUIT TECHNOLOGY Ordering Information Model Number CT2561 CT2561-FP Screening Package Military Temperature, -55°C to +125°C, Screened to the individual test methods of MIL-STD-883 Plug in Flat Package Specifications subject to change without notice Aeroflex Circuit Technology 35 South Service Road Plainview New York 11803 www.aeroflex.com/act1.htm Aeroflex Circuit Technology Telephone: (516) 694-6700 FAX: (516) 694-6715 Toll Free Inquiries: (800) THE-1553 E-Mail: [email protected] 9 SCDCT2561 REV A 8/16/99 Plainview NY (516) 694-6700