AEROFLEX DATA EXCHANGE PROGRAM TRANSMITTAL PROBLEM ADVISORY 1. TITLE 2. DOCUMENT NUMBER MICROCIRUIT, MEMORY, DIGITAL, CMOS, 512K X 32-BIT (16M) WITH EMBEDDED EDAC, RADIATION-HARDENED LOW VOLTAGE SRAM, MONOLITHIC SILICON SPO-2012-PA-0001 3. DATE (Year, Month, Date) 2012, October, 04 4. MANUFACTURER NAME AND ADDRESS 5. MANUFACTURER POINT OF CONTACT NAME AEROFLEX COLORADO SPRINGS, INC. Mike Leslie 4350 CENTENNIAL BOULEVARD COLORADO SPRINGS, COLORADO 80907-3486 6. MANUFACTURER POINT OF CONTACT TELEPHONE (719) 594-8148 7. MANUFACTURER POINT OF CONTACT EMAIL [email protected] 8. CAGE CODE 9. LDC START 10. LDC END 11. PRODUCT IDENTIFICATION CODE 12. BASE PART 65342 ALL ALL WC04 / WC05 UT8ER512K32M/S 13. BLANK 14. SMD NUMBER 15. DEVICE TYPE DESIGNATOR 5962-06261 TYPE (01-06) 16. RHA LEVELS 17. QML LEVEL R Q, V 18. NON QML LEVEL 19. BLANK HiRel, Protos 20. PROBLEM DESCRIPTION / DISCUSSION / EFFECT The EDAC control register electrical performance characteristic parameter tAVCL (Table 1A, sheet 10 of SMD: 5962-06261) min of 200ns is insufficient for reliable accesses to the EDAC control register settings. An incorrect test method resulted in inaccurate initial characterization data. 21. ACTION TAKEN / PLANNED Aeroflex’s test methodology has been corrected. Device Characterization has been performed to verify compliance with the increased 400ns minimum specification. Additionally, parameters tCHAV and tCLAX specifications of 0ns minimum were added to clarify the EDAC control register sequence. Aeroflex is working in coordination with DLA Land and Maritime to effect the changes referenced in this ADEPT to the SMD, which is currently at revision level B. The proposed list of SMD changes related to parameters tCHAV, tCLAX, and tAVCL are appended to this GIDEP. Fielded units are guaranteed by design to meet these parameters, no field returns are planned. 22. DISPOSITIONARY RECOMMENDATION: 23. ADEPT REPRESENTATIVE Timothy L. Meade ADEPT FORM F##### REV - USE AS IS 24. ☐ SIGNATURE CONTACT MANUFACTURER ☐ REMOVE & REPLACE ☐ CHECK & ☒ USE AS IS 25. DATE 04, October, 2012 RELEASE DATE: 11/11/11 TABLE IA. Electrical performance characteristics (sheet 10) Previous: Test Address valid to control low Symbol Test condition tAVCL Group A subgroups 9,10,11 Device Type All Limits min 200 Units max ns Corrected: Test Address valid to control low Symbol Test condition tAVCL Group A subgroups 9,10,11 Device Type All Limits min 400 Units max ns Added parameter to TABLE IA. Electrical performance characteristics (sheet 10) Test MBE high to address valid MBE low to address invalid Symbol tCHAV tCLAX Test condition Group A subgroups 9,10,11 9,10,11 Device Type All All Limits min 0 0 Units max ns ns FIGURE 5. Timing waveforms - Continued (sheet 22) Previous: Notes: 1. MBE is driven high by the user. 2. Lower 9 bits of the last address are used to read or configure the control register (see vendor data sheet) 3. SCRUB ≥ VOH before the start of the configuration cycle. Ignore SCRUB during configuration cycle. EDAC Control register cycle ADEPT FORM F##### REV - RELEASE DATE: 11/11/11 Corrected: SEE NOTE 1 SEE NOTE 4 Notes: 1. MBE is driven high by the user. 2. Lower 10 bits of the last address are used to read or configure the control register (see vendor data sheet) 3. SCRUB ≥ VOH before the start of the configuration cycle. Ignore SCRUB during configuration cycle. 4. Device must see a transition to address 70000h coincident with or subsequent to MBE assertion. EDAC Control register cycle ADEPT FORM F##### REV - RELEASE DATE: 11/11/11