FEATURES APPLICATIONS AV receivers LCD HDTVs PDP HDTVs CRT HDTVs HDTV STBs with PVR DVD recorders with progressive scan input support Projectors DATA (16) ADV7800 CLK ADDRESS (14) CONTROL (9) ANALOG INPUT INTERFACE YPrPb SCART CVBS S-VIDEO CLAMP ADC CLAMP ADC CLAMP ADC DAC CORE_CLK CP SDP PLL VBI DATA PROCESSOR (VDP) SYNC ANA DIG ADC, CORE, MEMORY CLK GENERATION DDS FOR SDP LINE-LOCKED CLK GENERATION DAC CP SDP Y 10 Cb STANDARD DEFINITION PROCESSOR (SDP) ADC_CLK DIGITAL INPUT INTERFACE HS_IN1 VS_IN1 SOG XTAL 10 DDR/SDR SDRAM INTERFACE ADC CLAMP MUX GR RGB INPUT MUX 10 Cr HS VS CORE_CLK FLD COMPONENT PROCESSOR (CP) DE LLC I2C CONFIGURATION ANALOG DIGITAL 06760-001 Four 10-bit ADCs 10-bit high dynamic range processing 12-channel analog input mux 10-bit deep color processing Analog monitor output NTSC/PAL/SECAM color standards support NTSC/PAL 3D comb filter 3D digital noise reduction (DNR) Advanced time base correction (TBC) with frame synchronization Interlaced-to-progressive conversion for 525i and 625i Advanced VBI data slicer, including Teletext, CC, and V-chip IF compensation filter SCART fast blank support including slow switch detect Programmable internal antialias filters Weak, poor time base, and nonstandard signal support Vertical peaking, horizontal peaking, CTI, LTI Simultaneous interlaced and progressive parallel output for 525i/525p and 625i/625p 525p/625p component progressive scan support 720p/1080i/1080p component HDTV support Digitizes RGB graphics with maximum pixel clock rate of 150 MHz (150 MHz speed grade only) 24-bit digital input port supports data from DVI/HDMI Rx IC Any-to-any, advanced 3 × 3 color space conversion matrix Flexible output pixel interface supporting 8-/10-/16-/ 20-/24-/30-bit SDR/DDR 4:2:2/4:4:4 data formats Programmable interrupt request output pin DDR/SDR SDRAM INTERFACE OUTPUT FORMATTING Data Sheet 10-Bit, SDTV/HDTV 3D Comb Filter, Video Decoder, and Graphics Digitizer ADV7800 Figure 1. Simplified Functional Block Diagram GENERAL DESCRIPTION The ADV78001 is a high quality, single-chip, multiformat 3D comb filter, video decoder, and graphics digitizer. This multiformat 3D comb filter decoder supports the conversion of PAL, NTSC, and SECAM standards in the form of a composite or an S-Video into a digital ITU-R BT.656 format. The ADV7800 also supports the decoding of a component RGB/YPrPb video signal into a digital YCrCb or RGB pixel output stream. The support for component video includes standards such as 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and many other HD and SMPTE standards. Graphics digitization is supported by the ADV7800; it is capable of digitizing RGB graphics signals from VGA to SXGA rates and converting them into a digital RGB or YCrCb pixel output stream. SCART and overlay functionality are enabled by the ability of the ADV7800 to simultaneously process CVBS and standard definition RGB signals. The ADV7800 contains two main processing sections. The first section is the standard definition processor (SDP), which processes all PAL, NTSC, SECAM, and component (up to 525p/625p) signal types. The second section is the component processor (CP), which processes YPrPb and RGB component formats, including RGB graphics. 1 Protected by U.S. Patent Number 4,907,093 and other intellectual property rights. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. ADV7800 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Key Features ................................................................................ 13 Applications ....................................................................................... 1 Analog Front End ....................................................................... 13 General Description ......................................................................... 1 Standard Definition Processor ................................................. 13 Revision History ............................................................................... 2 VBI Data Processor .................................................................... 14 Functional Block Diagram .............................................................. 3 Component Processor ............................................................... 14 Specifications..................................................................................... 4 Additional Features .................................................................... 15 Electrical Characteristics ............................................................. 4 External Memory Requirements .................................................. 16 Video Specifications ..................................................................... 5 Single Data Rate (SDR).............................................................. 16 Timing Characteristics ................................................................ 6 Double Data Rate (DDR) .......................................................... 16 Timing Diagrams.......................................................................... 7 Recommended External Loop Filter Components .................... 17 Analog Specifications ................................................................... 8 Typical Connection Diagrams ...................................................... 18 Absolute Maximum Ratings............................................................ 9 Pixel Input/Output Formatting .................................................... 20 Package Thermal Performance ................................................... 9 Pixel Data Output Modes Highlights ...................................... 20 Thermal Resistance ...................................................................... 9 Digital Video Input Port Highlights ........................................ 20 ESD Caution .................................................................................. 9 Outline Dimensions ....................................................................... 26 Pin Configuration and Function Descriptions ........................... 10 Ordering Guide .......................................................................... 26 Theory of Operation ...................................................................... 13 REVISION HISTORY 8/11—Revision C: Initial Version Rev. C | Page 2 of 28 Figure 2. Rev. C | Page 3 of 28 SCLK1 SCLK2 SDA1 SDA2 ALSB SOY SOG VS_IN1 HS_IN1 P30 TO P53 HS_IN2 VS_IN2 CLK_IN DE_IN CVBS OUT FUNCT1 FB CVBS S-VIDEO YPrPb SCART (CBVS + RGB) GRAPHICS RGB AIN1 TO AIN12 12 24 INPUT MUX ADC ANTIALIAS FILTER CLAMP STDI SERIAL INTERFACE CONTROL AND VBI DATA SSPD SYNC PROCESSING AND CLOCK GENERATION DIGITAL INPUT PORT DVI OR HDMI DAC ADC ADC ANTIALIAS FILTER ANTIALIAS FILTER ADC ANTIALIAS FILTER CLAMP CLAMP CLAMP 10 10 10 10 MUX CORE CLK COLORSPACE CONVERSION 10 10 10 10 FASTBLANK OVERLAY CONTROL AV CODE INSERTION DIGITAL FINE CLAMP GAIN CONTROL MACROVISION DETECTION I TO P COLORSPACE CONVERSION STANDARD AUTODECTION OFFSET CONTROL AV CODE INSERTION ACTIVE PEAK AND AGC VBI DATA PROCESSOR (VDP) LTI CTI HORIZONTAL PEAKING VERTICAL PEAKING MACROVISION DETECTION COMPONENT PROCESSOR (CP) TBC 3D COMB 2D COMB 525p/625p SUPPORT DDR/SDR-SDRAM INTERFACE STANDARD DEFINITION PROCESSOR (SDP) 54 INT LLC SFL/SYNC_OUT FLD_DE_OUT VS_OUT CS/HS_OUT PIXEL DATA P0 TO P53 06760-002 ADV7800 Data Sheet ADV7800 FUNCTIONAL BLOCK DIAGRAM OUTPUT FIFO AND FORMATTER ADV7800 Data Sheet SPECIFICATIONS ELECTRICAL CHARACTERISTICS AVDD = 3.15 V to 3.45 V, DVDD = 1.75 V to 1.85 V, DVDDIO = 3.0 V to 3.6 V, DVDDIO_SDRAM = 2.35 V to 2.65 V (DDR), DVDDIO_SDRAM = 3.2 V to 3.4 V (SDR), PVDD = 1.71 V to 1.89 V, nominal input range 1.6 V. TA = 0°C to 85°C, unless otherwise noted. Table 1. Parameter 1 STATIC PERFORMANCE 2, 3 Resolution (Each ADC) Integral Nonlinearity 4 Differential Nonlinearity4 POWER REQUIREMENTS 5 Digital Core Power Supply Digital I/O Power Supply PLL Power Supply Analog Power Supply Memory Interface Power Supply Symbol N INL DNL DVDD DVDDIO PVDD AVDD DVDDIO_SDRAM Digital Core Supply Current IDVDD Digital I/O Supply Current IDVDDIO PLL Supply Current IPVDD Analog Supply Current IAVDD Memory Interface Supply Current Power-Down Current Power-Up Time DIGITAL INPUTS Input High Voltage Input Low Voltage Input Current Input Capacitance DIGITAL OUTPUTS Output High Voltage 6 Output Low Voltage6 High Impedance Leakage Current Output Capacitance IVDDRAM IPWRDN TPWRUP Test Conditions BSL at 27 MHz (at a 10-bit level) BSL at 54 MHz (at a 10-bit level) BSL at 74 MHz (at a 10-bit level) BSL at 110 MHz (at a 10-bit level) BSL at 150 MHz (at an 8-bit level) At 27 MHz (at a 10-bit level) At 54 MHz (at a 10-bit level) At 74 MHz (at a 10-bit level) At 110 MHz (at a 10-bit level) At 150 MHz (at an 8-bit level) DDR SDR CVBS input sampling at 54 MHz Graphics RGB sampling at 78 MHz SCART RGB FB sampling at 54 MHz 525p input sampling at 54 MHz CVBS input sampling at 54 MHz Graphics RGB sampling at 78 MHz CVBS input sampling at 54 MHz Graphics RGB sampling at 78 MHz CVBS input sampling at 54 MHz Graphics RGB sampling at 78 MHz SCART RGB FB sampling at 54 MHz CVBS input sampling at 54 MHz VIH VIL IIN CIN VOH VOL Min ISOURCE = 0.4 mA ISINK = 3.2 mA ILEAK COUT Temperature range TMIN to TMAX. All ADC linearity tests performed with part configured for component video input. 3 All ADC linearity tests performed at input range of full scale − 12.5% and at zero scale + 12.5%. 4 Maximum INL and DNL specifications obtained with part configured for component video input. 5 Guaranteed by characterization. 6 VOH and VOL levels obtained using default drive strength. 1 2 Rev. C | Page 4 of 28 Typ Max Unit 10 Bits LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB 1.85 3.6 1.89 3.45 2.65 3.4 V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA mA ms −0.3/+0.4 −0.4/+0.5 −0.3/+0.2 −0.3/+0.6 −0.6/+0.6 −0.2/+0.3 −0.2/+0.3 −0.5/+0.4 −0.2/+0.3 −0.2/+0.4 1.75 3.0 1.71 3.15 2.35 3.2 1.8 3.3 1.8 3.3 2.5 3.3 236 103 236 319 6 15 13 10 99 263 269 17 8 20 2 0.8 ±10 15 V V µA pF 2.4 0.4 V V 10 20 μA pF Data Sheet ADV7800 VIDEO SPECIFICATIONS AVDD = 3.15 V to 3.45 V, DVDD = 1.75 V to 1.85 V, DVDDIO = 3.0 V to 3.6 V, DVDDIO_SDRAM = 2.35 V to 2.65 V (DDR), DVDDIO_SDRAM = 3.2 V to 3.4 V (SDR), PVDD = 1.71 V to 1.89 V. TA = 0°C to 85°C, unless otherwise noted. Table 2. Parameter 1 NONLINEAR SPECIFICATIONS Differential Phase Differential Gain Luma Nonlinearity NOISE SPECIFICATIONS SNR Unweighted Symbol Test Conditions DP DG LNL CVBS input (modulated 5-step) CVBS input (modulated 5-step) CVBS input (modulated 5-step) 0.47 0.47 0.8 Degrees % % Luma ramp Luma flat field 61 62 60 dB dB dB Analog Front-End Crosstalk LOCK TIME SPECIFICATIONS (SDP) Horizontal Lock Range Vertical Lock Range Subcarrier Lock Range, fSC Color Lock-In Time Sync Depth Range 2 Color Burst Range Vertical Lock Time Horizontal Lock Time CHROMA SPECIFICATIONS (SDP) Chroma Amplitude Error Chroma Phase Error Chroma Luma Intermodulation 1 2 Min Typ Max ±5 300 100 % Hz kHz Lines % % ms Lines 0.4 0.3 0.2 % Degrees % 40 70 ±0.8 60 20 1 Guaranteed by characterization. Nominal sync depth is 300 mV at 100% sync depth range. Rev. C | Page 5 of 28 Unit 200 200 ADV7800 Data Sheet TIMING CHARACTERISTICS AVDD = 3.15 V to 3.45 V, DVDD = 1.75 V to 1.85 V, DVDDIO = 3.0 V to 3.6 V, DVDDIO_SDRAM = 2.35 V to 2.65 V (DDR), DVDDIO_SDRAM = 3.2 V to 3.4 V (SDR), PVDD = 1.71 V to 1.89 V. TA = 0°C to 85°C, unless otherwise noted. Table 3. Parameter 1 SYSTEM CLOCK AND CRYSTAL Crystal Nominal Frequency Crystal Frequency Stability Horizontal Sync Input Frequency LLC Frequency Range I2C PORT SCLK Frequency SCLK Minimum Pulse Width High SCLK Minimum Pulse Width Low Hold Time (Start Condition) Setup Time (Start Condition) SDA Setup Time SCLK and SDA Rise Time SCLK and SDA Fall Time Setup Time (Stop Condition) FAST I2C PORT 2 SCLK Frequency SCLK Minimum Pulse Width High SCLK Minimum Pulse Width Low Hold Time (Start Condition) Setup Time (Start Condition) SDA Setup Time SCLK and SDA Rise Time SCLK and SDA Fall Time Setup Time (Stop Condition) RESET FEATURE Reset Pulse Width CLOCK OUTPUTS LLC Mark Space Ratio DATA AND CONTROL OUTPUTS 3 Data Output Transition Time, SDR (SD Core) Symbol t11 Data Output Transition Time, SDR (SD Core) t12 Data Output Transition Time, SDR (CP Core) t13 Data Output Transition Time, SDR (CP Core) t14 Test Conditions Min Typ Max Unit ±50 90 150 MHz ppm kHz MHz 28.63636 14.8 12.825 400 t1 t2 t3 t4 t5 t6 t7 t8 0.6 1.3 0.6 0.6 100 t1 t2 t3 t4 t5 t6 t7 t8 60 160 160 160 10 10 10 160 300 300 0.6 3.4 80 80 5 t9, t10 DATA AND CONTROL INPUTS 4 Input Setup Time (Digital Input Port) t17 Input Hold Time (Digital Input Port) t18 45:55 Negative clock edge to start of valid data End of valid data to negative clock edge Negative clock edge to start of valid data End of valid data to negative clock edge HS_IN1, VS_IN1 HS_IN2, VS_IN2 DE_IN, data inputs HS_IN1, VS_IN1 HS_IN2, VS_IN2 DE_IN, data inputs Guaranteed by characterization. With a bus line load less than 100 pF. 3 Timing figures obtained using default drive strength value. 4 TTL input values are 0 V to 3 V, with rise/fall times ≥ 3 ns, measured between the 10% and 90% points. 1 2 Rev. C | Page 6 of 28 kHz µs µs µs µs ns ns ns µs MHz ns ns ns ns ns ns ns ns ms 55:45 % duty cycle 4.5 ns 0 ns 2.5 ns 0.2 ns 9.5 ns 2 −4 ns ns 0.8 ns Data Sheet ADV7800 TIMING DIAGRAMS t3 t5 t3 SDA1/SDA2 t1 SCLK1/SCLK2 t2 t7 t4 t8 06760-004 t6 2 Figure 3. I C Timing t9 t10 LLC t11 06760-005 t12 P0 TO P53, VS_OUT, HS_OUT, FLD_DE_OUT Figure 4. Pixel Port and Control SDR Output Timing (SD Core) t9 t10 LLC t13 06760-011 t14 P0 TO P53, VS_OUT, HS_OUT, FLD_DE_OUT Figure 5. Pixel Port and Control SDR Output Timing (CP Core) DCLK_IN t18 P30 TO P39, P40 TO P43, P44 TO P53 t17 Figure 6. Digital Input Port and Control Input Timing Rev. C | Page 7 of 28 06760-007 CONTROL INPUTS HS_IN1, VS_IN1, HS_IN2, VS_IN2, DE_IN ADV7800 Data Sheet ANALOG SPECIFICATIONS AVDD = 3.15 V to 3.45 V, DVDD = 1.75 V to 1.85 V, DVDDIO = 3.0 V to 3.6 V, DVDDIO_SDRAM = 2.35 V to 2.65 V (DDR), DVDDIO_SDRAM = 3.2 V to 3.4 V (SDR), PVDD = 1.71 V to 1.89 V. TA = 0°C to 85°C, unless otherwise noted. Recommended analog input video signal range is 0.5 V to 1.6 V, typically 1 V p-p. Recommended external clamp capacitor value is 0.1 μF. Table 4. Parameter 1, 2 CLAMP CIRCUITRY Input Impedance 3 Input Impedance of Pin 90 (FB) CML ADC Full-Scale Level ADC Zero-Scale Level ADC Dynamic Range Clamp Level (When Locked) Large Clamp Source Current Large Clamp Sink Current Fine Clamp Source Current Fine Clamp Sink Current 1 2 3 Test Conditions Min Clamps switched off CVBS input SCART RGB input (R, G, B signals) S-Video input (Y signal) S-Video input (C signal) Component input (Y signal) Component input (Pr, Pb signals) PC RGB input (R, G, B signals) SDP only SDP only SDP only SDP only The minimum/maximum specifications are guaranteed over 0°C to 85°C. Guaranteed by characterization. Except Pin 90 (FB). Rev. C | Page 8 of 28 Typ 10 20 2.0 CML + 0.8 CML − 0.8 1.6 CML − 0.292 CML − 0.3 CML − 0.292 CML − 0 CML − 0.3 CML − 0 CML − 0.3 0.75 0.9 17 17 Max Unit MΩ kΩ V V V V V V V V V V V mA mA µA µA Data Sheet ADV7800 ABSOLUTE MAXIMUM RATINGS PACKAGE THERMAL PERFORMANCE Table 5. Parameter Rating AVDD to AGND DVDD to DGND PVDD to AGND DVDDIO to DGND DVDDIO_SDRAM to DGND_SDRAM (DDR) DVDDIO_SDRAM to DGND_SDRAM (SDR) DVDDIO to AVDD DVDDIO to DVDD DVDDIO_SDRAM to DVDD (DDR) DVDDIO_SDRAM to DVDD (SDR) AVDD to PVDD AVDD to DVDD DVDDIO to DVDDIO_SDRAM (DDR) DVDDIO to DVDDIO_SDRAM (SDR) AVDD to DVDDIO_SDRAM (DDR) AVDD to DVDDIO_SDRAM (SDR) Digital Inputs Voltage to DGND DVDDIO_SDRAM Inputs to DGND_SDRAM Analog Inputs to AGND SCLK/SDA Data Pins to DVDDIO Maximum Junction Temperature (TJ MAX) Storage Temperature Range Infrared Reflow Soldering (20 sec) 4.0 V 2.2 V 2.2 V 4.0 V 2.7 V To reduce power consumption when using the part, the user is advised to turn off any unused ADCs. The junction temperature must always stay below the maximum junction temperature (TJ MAX) of 125°C. This equation shows how to calculate the junction temperature: TJ = TA MAX + (θJA × WMAX) 4.0 V −0.3 V to +0.3 V −0.3 V to +2 V −0.3 V to +2.5 V −0.3 V to +3.3 V −0.3 V to +2 V −0.3 V to +2 V −0.3 V to +2 V −0.3 V to +3.3 V −0.3 V to +2.5 V −0.3 V to +1.8 V DGND − 0.3 V to DVDDIO + 0.3 V DGND_SDRAM − 0.3 V to DVDDIO_SDRAM + 0.3 V AGND − 0.3 V to AVDD + 0.3 V DVDDIO − 0.3 V to DVDDIO + 3.6 V 125°C where: TA MAX = 85°C θJA = 21.0330°C/W WMAX = ((AVDD × IAVDD) + (DVDD × IDVDD) + (DVDDIO × IDVDDIO) + (PVDD × IPVDD)+(DVDD_SDRAM × IDVDD_SDRAM )). THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 6. Thermal Resistance Package Type 176-Lead LQFP 1 2 4-layer PCB with solid ground plane. 4-layer PCB with solid ground plane (still air). ESD CAUTION −65°C to +150°C 260°C θJA1 21 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. C | Page 9 of 28 θJC2 7 Unit °C/W ADV7800 Data Sheet PIN 1 2 131 3 130 4 129 5 128 6 127 7 126 8 125 9 124 10 123 11 122 12 121 13 120 14 119 15 118 16 117 17 116 18 115 19 114 20 ADV7800 113 21 TOP VIEW (Not to Scale) 111 22 112 110 23 24 109 25 108 26 107 27 106 28 105 29 104 30 103 31 102 88 87 86 85 83 84 81 82 80 79 78 77 76 75 73 74 72 71 70 69 68 67 66 65 64 63 62 61 60 59 89 58 90 44 56 91 43 57 92 42 55 93 41 54 94 40 53 95 39 52 96 38 51 97 37 50 98 36 49 99 35 48 34 47 100 46 101 33 45 32 Figure 7. Pin Configuration Rev. C | Page 10 of 28 P48 P49 P50 P51 P52 P53 DE_IN VS_IN1 VS_IN2 INT SCLK SDA ALSB HS_IN2 HS_IN1 FUNCT1 AOUT AIN6 AIN12 AIN5 AIN11 AIN4 AIN10 CAPC2 CAPC1 CAPY1 BIAS AVDD AGND CML REFOUT AVDD AGND AGND AIN3 AIN9 AIN2 AIN8 AIN1 AIN7 SOG SOY FB AGND 06760-003 134 133 135 137 136 138 140 139 142 141 144 143 145 146 148 147 151 149 152 150 153 155 154 157 156 158 160 159 161 162 163 165 164 168 166 169 167 170 171 173 172 174 176 132 1 SDRAM_WE SDRAM_LDM DVDDIO_SDRAM DGND_SDRAM SDRAM_LDQS SDRAM_DQ7 SDRAM_DQ6 SDRAM_DQ5 SDRAM_DQ4 SDRAM_DQ3 SDRAM_DQ2 SDRAM_DQ1 SDRAM_DQ0 SDRAM_VREF DGND DVDD DVDDIO_SDRAM DGND_SDRAM SDRAM_DQ15 SDRAM_DQ14 SDRAM_DQ13 SDRAM_DQ12 SDRAM_DQ11 SDRAM_DQ10 SDRAM_DQ9 SDRAM_DQ8 SDRAM_UDQS SDRAM_UDM SDRAM_CK SDRAM_CK SDRAM_CKE DVDD DGND CLKIN DVDDIO XTAL XTAL1 DGND RESET PVDD AGND ELPF1 PVDD ELPF2 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 DVDDIO DGND LLC CS/HS_OUT SFL/SYNC_OUT FLD_DE_OUT VS_OUT DGND DVDD SDRAM_A11 SDRAM_A9 SDRAM_A8 SDRAM_A7 SDRAM_A6 SDRAM_A5 SDRAM_A4 SDRAM_A3 SDRAM_A2 SDRAM_A1 SDRAM_A0 DGND DVDD DVDDIO_SDRAM DGND_SDRAM SDRAM_A10 SDRAM_BA1 SDRAM_BA0 SDRAM_CS SDRAM_RAS SDRAM_CAS 175 DGND DVDD P14 P15 P16 DGND DVDDIO P17 P18 P19 P20 P21 P22 P23 P24 P25 DGND DVDD P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 DGND DVDDIO P40 P41 P42 P43 DGND DVDD P44 P45 P46 P47 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Data Sheet ADV7800 Table 7. Pin Function Descriptions Pin No. 1 to 14, 155 to 158, 161 to 169, 172 to 174 15, 79, 143, 170 16, 22, 35, 59, 77, 82, 138, 144, 160, 171, 176 17 18 Mnemonic P0 to P29 Type 1 O Description Video Pixel Output Port. See Figure 7 for details on pin mapping. DVDDIO DGND P GND Digital Input/Output Supply Voltage (3.3 V). Digital Ground. LLC CS/HS_OUT O O 19 SFL/SYNC_OUT O 20 FLD_DE_OUT O 21 23, 36, 60, 76, 137, 159, 175 24 to 34, 39 VS_OUT DVDD SDRAM_A0 to SDRAM_A11 DVDDIO_SDRAM O P O GND O 42 DGND_SDRAM SDRAM_BA1, SDRAM_BA0 SDRAM_CS Line-Locked Output Clock for the Pixel Data. Horizontal Synchronization or Composite Synchronization Signal. This signal can be selected while in SDP mode. Subcarrier Frequency Lock. This pin contains a serial output stream, which can be used to lock the subcarrier frequency when this decoder is connected to any digital video encoder from Analog Devices, Inc. SYNC_OUT is the sliced synchronization output signal available only in CP mode. Field Synchronization Output Signal (All Interlaced Video Modes). This pin can also be enabled as a data enable signal (DE) to allow direct connection to a HDMI™/DVI Tx IC. Vertical Synchronization Output Signal (SDP and CP modes). Digital Core Supply Voltage (1.8 V). Address Outputs. Interface to external RAM address lines. See Figure 7 for details on pin mapping. External Memory Interface Digital Input/Output Supply (2.5 V for DDR, or 3.3 V for SDR). External Memory Interface Digital GND. Bank Address Outputs. Interface to external RAM bank address lines. 43 SDRAM_RAS O 44 SDRAM_CAS O 45 SDRAM_WE O 46, 72 SDRAM_LDM, SDRAM_UDM O 49 SDRAM_LDQS I/O 50 to 57, 63 to 70 SDRAM_DQ0 to SDRAM_DQ15 SDRAM_VREF SDRAM_UDQS I/O 37, 47, 61 38, 48, 62 40, 41 58 71 P O P I/O 73, 74 SDRAM_CK, SDRAM_CK O 75 78 SDRAM_CKE CLKIN O I SDRAM_CS is a chip select function that enables and disables the command decoder on the RAM. Row Address Select Command Signal. SDRAM_RAS, SDRAM_CAS, SDRAM_WE, and SDRAM_CS define the command to the RAM. Column Address Select Command Signal. SDRAM_RAS, SDRAM_CAS, SDRAM_WE, and SDRAM_CS define the command to the RAM. Write Enable Output Command Signal. SDRAM_RAS, SDRAM_CAS, SDRAM_WE, and SDRAM_CS define the command to the RAM. Data Mask Output. Data is masked when DM is high, for write data to the external RAM. LDM corresponds to the data on SDRAM_DQ0 to SDRAM_DQ7, and UDM corresponds to the data on SDRAM_DQ8 to SDRAM_DQ15. Lower Data Strobe Pin. Data strobe pins are used for the RAM interface. This is an output with read data and an input with write data. It is edge aligned with write data and centered in read data. SDRAM_ LDQS corresponds to the data on SDRAM_DQ0 to SDRAM_DQ7. Data Bus. Interface to external RAM 16-bit data bus. See Figure 7 for details on pin mapping. 1.25 V reference for DDR SDRAM interface or 1.65 V for SDR SDRAM interface. Upper Data Strobe Pin. Data strobe pins for the RAM interface. This is an output with read data and an input with write data. It is edge aligned with write data and centered in read data. SDRAM_UDQS corresponds to the data on SDRAM_DQ8 to SDRAM_DQ16. Differential Clock Output. All address and control output signals to the RAM should be sampled on the positive edge of SDRAM_CK and on the negative edge of SDRAM_CK. Clock Enable. This pin is used to enable the clock signals of the external RAM. Clock Input Signal. Used in 24-bit digital input mode (for example, processing 24-bit RGB data from a DVI/HDMI Rx IC) and also in digital CVBS input mode. Rev. C | Page 11 of 28 ADV7800 Data Sheet Pin No. 80 81 83 Mnemonic XTAL XTAL1 RESET Type 1 I O I 84, 87 85, 89, 99, 100, 104 86, 88 PVDD AGND ELPF1, ELPF2 P GND I 90 91 92 93 to 98, 110 to 115 101, 105 102 103 106 FB SOY SOG AIN1 to AIN12 AVDD REFOUT CML BIAS I I I I P O O O 107 108, 109 116 117 118 CAPY1 CAPC1, CAPC2 AOUT FUNCT1 HS_IN1 I I O I I 119 HS_IN2 I/O 120 ALSB I 121 122 123 SDA SCLK INT I/O I O 124 VS_IN2 I/O 125 126 VS_IN1 DE_IN I I 127 to 136, 139 to 142, 145 to 154 P30 to P53 I/O 1 Description Crystal Input. Input pin for 28.63636 MHz crystal. Crystal Output. This pin should be connected to the 28.63636 MHz crystal. System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset the ADV7800 circuitry. PLL Supply Voltage (1.8 V). Analog Ground. External Loop Filter. The recommend external loop filter must be connected to each ELPF pin (see Figure 8). SCART Fast Blank Input. Sync On Luma Input. Used in embedded synchronization mode. Sync On Green Input. Used in embedded synchronization mode. Analog Video Input Channels. See Figure 7 for details on pin mapping. Analog Supply Voltage (3.3 V). Internal Voltage Reference Output. Common-Mode Level Pin Used for the Internal ADCs. External Bias Setting Pin. Connect the recommended resistor (1.35 kΩ) between the pin and ground. ADC Capacitor Network. ADC Capacitor Network. Analog Monitor Output. SCART Function Select Input. Horizontal Synchronization Input Signal. Used in CP mode for 5-wire timing mode. Horizontal Synchronization Input Signal. Used in 24-bit digital input mode port mode (for example, processing 24-bit RGB data from an HDMI Rx IC). HS_IN2 in conjunction with VS_IN2 can be configured as a fast I2C interface for teletext data extraction. HS_IN2 is used as the I2C port serial clock input. ALSB selects the I2C address for the ADV7800 control. ALSB set to Logic 0 configures the address for a write to the input/output port of 0x40. ALSB set to Logic 1 configures the address for a write to the input/output port of 0x42. I2C Port Serial Data Input/Output Pin. I2C Port Serial Clock Input (Maximum Clock Rate of 400 kHz). Interrupt Output. This pin can be active low or active high. When SDP/CP status bits change, this pin triggers. The set of events that triggers an interrupt is under user control. Vertical Synchronization Input Signal. Used in 24-bit digital input mode (for example, processing 24-bit RGB data from an DVI/HDMI Rx IC). VS_IN2 in conjunction with HS_IN2 can be configured as a fast I2C interface for teletext data extraction. VS_IN2 is used as the I2C port serial data input/output pins. Vertical Synchronization Input Signal. Data Enable Input Signal. Used in 24-bit digital input port mode (for example, processing 24-bit RGB data from an DVI/HDMI Rx IC). Video Pixel Input/Output Port. See Figure 7 for details on pin mapping. GND = ground, I = input, I/O = input/output, O = output, P = power. Rev. C | Page 12 of 28 Data Sheet ADV7800 THEORY OF OPERATION KEY FEATURES Analog front-end features include The ADV7800 is a high quality, single-chip, multiformat 3D comb filter video decoder, and graphics digitizer. Key features of the device include • Four 150 MHz, 10-bit ADCs that enable true 10-bit video decoding • 12-channel analog input mux that enables multiple source connections without the requirement of an external mux • Four current and voltage clamp control loops that ensure any dc offsets are removed from the video signal • SCART functionality and SD RGB overlay on CVBS controlled by fast blank input • Four 10-bit ADCs • NTSC/PAL/SECAM video decoder • Adaptive 3D comb filtering • 3D digital noise reduction • Advanced frame time-base correction (TBC) • SCART source switching detection through FUNCT1 input • Composite, S-Video, YPrPb/RGB SCART support • • YPrPb component HD and RGB graphics input support Four programmable antialias filters on standard definition video signals and enhance definition • CVBS monitor output • 30-bit digital YPrPb/RGB output supporting 10-bit deep color ANALOG FRONT END The ADV7800 analog front end comprises four 10-bit ADCs that digitize the analog video signal before applying it to the SDP or CP. The front end includes a 12-channel input mux that enables multiple video signals to be applied to the ADV7800 without the requirement of an external mux. Current and voltage clamps are positioned in front of each ADC to ensure the video signal remains within the range of the converter. The ADCs are configured to run up to 4× oversampling mode when decoding composite and S-Video inputs or components up to 525i and 625i. 2× oversampling is available for 525p and 625p. All other video standards are 1× oversampled. In oversampling the video signals, a reduction in the cost and complexity of external antialiasing filters can be obtained with the benefit of an increased signal-to-noise ratio (SNR). Optional internal antialiasing filters with programmable bandwidth are positioned in front of each ADC. These filters can be used to band-limit standard definition video signals, removing spurious, out-of-band noise. The ADV7800 can support simultaneous processing of CVBS and RGB standard definition signals to enable SCART compatibility and overlay functionality. A combination of CVBS and RGB inputs can be mixed and can be output under the control of I2C registers and the fast blank pin. STANDARD DEFINITION PROCESSOR The standard definition processor (SDP) is capable of decoding a large selection of baseband video signals in composite, S-Video, and YUV formats. The video standards supported by the SDP include PAL, PAL 60, PAL M, PAL N, PAL NC, NTSC M/J, NTSC 4.43, and SECAM. The ADV7800 can automatically detect the video standard and process it accordingly. The ADV7800 can process video up to 525p/625p formats. The SDP has a 3D temporal comb filter and a 5-line adaptive 2D comb filter that gives superior chrominance and luminance separation when decoding a composite video signal. This highly adaptive filter automatically adjusts its processing mode according to the video standard and signal quality with no user intervention required. The SDP has an IF filter block that compensates for attenuation in the high frequency chroma spectrum due to a tuner SAW filter. The SDP has specific luminance and chrominance parameter controls for brightness, contrast, saturation, and hue. The ADV7800 implements a patented adaptive digital line length tracking (ADLLT) algorithm to track varying video line lengths from sources such as a VCR. ADLLT enables the ADV7800 to track and decode poor quality video sources (such as VCRs) and noisy sources (such as tuner outputs, VCRs, and camcorders). Frame TBC ensures stable clock synchronization between the decoder and the downstream devices to prevent disruptions. The SDP also contains both a luma transient improvement (LTI) and a chroma transient improvement (CTI) processor. This processor increases the edge rate on the luma and chroma transitions, resulting in a sharper video image. Rev. C | Page 13 of 28 ADV7800 Data Sheet The SDP has a Macrovision® detection circuit, which allows Type I, Type II, and Type III Macrovision protection levels. The decoder is also fully robust to all Macrovision signal inputs. SDP features include • Full automatic detection and autoswitching of all worldwide standards (PAL, NTSC, and SECAM) • Advanced adaptive 3D comb with concurrent 3D noise reduction (using either external DDR or SDR memory) • Adaptive 2D 5-line comb filters for NTSC and PAL that give superior chrominance and luminance separation for composite video VBI DATA PROCESSOR The VBI data processor (VDP) of the ADV7800 is capable of slicing multiple vertical blanking interval data standards on SD video and component video. The VDP decodes the VBI data on the incoming CVBS/YC or YUV data processed by the SDP core. It can also decode VBI data on the luma channel of YUV data processed through the CP core. The VDP can process a variety of VBI data services, such as • Teletext • Video programming system (VPS) • Vertical interval time codes (VITC) Automatic gain control with white peak mode that ensures the video is always processed without loss of the video processing range • Closed captioning (CC) and extended data service (EDS) • Wide screen signaling (WSS) • Proprietary architecture for locking to weak, noisy, and unstable sources from VCRs and tuners • Copy generation management system (CGMS, CGMS Type B) • IF filter block that compensates for high frequency luma attenuation due to a tuner SAW filter • Gemstar® 1×/2× electronic program guide compatible • Extended data service (SDS); the data extracted can be read back over a fast I2C interface • • LTI and CTI • Vertical and horizontal programmable luma peaking filters COMPONENT PROCESSOR • 10-bit deep color processing path from front to back end in RGB/YCrCb formats • Macrovision copy protection detection on composite and S-Video for all worldwide formats (PAL, NTSC, and SECAM) • 4× oversampling (54 MHz) for CVBS, S-Video, and YUV modes The component processor (CP) is capable of decoding and digitizing a wide range of component video formats in any color space. The CP can accept video data from the analog front end or from the HDMI receiver. Component video standards supported by the CP include 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and VGA (up to SXGA at 75 Hz), and many other standards. • 2× oversampling (54 MHz) for 525p and 625p modes • Line-locked clock output (LLC) • Free run output mode that provides stable timing when no video input is present • Internal color bar test pattern • Advanced TBC with frame synchronization, which ensures nominal clock and data for nonstandard input • Interlace-to-progressive conversion for 525i and 625i formats, enabling direct drive of HDMI Tx devices • Color controls that include hue, brightness, saturation, and contrast • Differential gain (DG), typically 0.45% • Differential phase (DP), typically 0.45° • Video SNR, typically 61 dB A fully programmable any-to-any, 3 × 3 color space conversion (CSC) matrix is placed before the CP. This enables YPrPb-toRGB and RGB-to-YCrCb conversions of video data coming from the analog front end or from the HDMI receiver. Many other standards of color space can be implemented using the color space converter. The CP of the ADV7800 contains an automatic gain control (AGC) block. The AGC is followed by a clamp circuit that ensures the video signal is clamped to the correct blanking level. Automatic adjustments within the CP include gain (contrast) and offset (brightness). Manual adjustment controls are also supported. In cases where no embedded synchronization is preset, the video gain can be set manually. Rev. C | Page 14 of 28 Data Sheet ADV7800 The CP contains circuitry to enable the detection of Macrovision encoded YPrPb signals for 525i, 625i, 525p, and 625p. It is designed to be fully robust to these types of signals. CP features include • 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and many other HDTV formats supported • Automatic adjustments including gain (contrast) and offset (brightness); manual adjustment controls also supported • Support for analog component YPrPb and RGB video formats with embedded synchronization or with separate HS, VS, or CS • Any-to-any, 3 × 3 color space conversion matrix that supports YCrCb-to-RGB and RGB-to-YCrCb, fully programmable or preprogrammable configurations • Macrovision copy protection detection on component formats (525i, 625i, 525p, and 625p) • Free run output mode that provides stable timing when no video input is present • Arbitrary pixel sampling support for nonstandard video sources • Automatic or manual clamp-and-gain controls for graphics modes • 32-phase DLL that allows optimum pixel clock sampling • Automatic detection of synchronization source and polarity by SSPD block • Standard identification enabled by STDI block • RGB that can be color space converted to YCrCb and decimated to a 4:2:2 format for videocentric back-end IC interfacing • DE output signal that is supplied for direct connection to HDMI/DVI Tx IC • Arbitrary pixel sampling support for nonstandard video sources The ADV7800 also includes Synchronization source polarity detector (SSPD) that determines the source and polarity of the synchronization signals that accompany the input video 150 MHz conversion rate, which supports RGB input resolutions up to 1280 × 1024 at 75 Hz Contrast, brightness, hue, and saturation controls ADDITIONAL FEATURES • • • • HS, VS, FIELD, and DE output signals with programmable position, polarity, and width • Programmable interrupt request output pin (INT)that signals SDP/CP status changes • Two I2C host port interface (control and VBI) support • Integrated programmable antialiasing filters • 176-lead, 26 mm × 26 mm, RoHS-compliant LQFP For more detailed product information about the ADV7800, email [email protected] or contact a local Analog Devices sales representative. Rev. C | Page 15 of 28 ADV7800 Data Sheet EXTERNAL MEMORY REQUIREMENTS SINGLE DATA RATE (SDR) DOUBLE DATA RATE (DDR) The ADV7800 uses SDR external memory for 3D comb, frame synchronizer operation, or 3D-DNR nonconcurrent operation. The ADV7800 uses DDR external memory for simultaneous 3D comb, frame synchronizer, and 3D-DNR operation. • 64 Mb SDR SDRAM minimum memory requirement • 128 Mb DDR SDRAM minimum memory requirement • The memory architecture required is four banks of 1 Mb × 16 (4M16) • The memory architecture required is four banks of 2 Mb × 16 (8M16) • Speed grade of 133 MHz at CAS latency (CL) 3 is required • • 22 Ω series termination resistors are recommended for this configuration Speed grade of 133 MHz at CAS latency (CL) 2.5 is required • • Recommended memory that is compatible with the ADV7800 includes the MT48LC4M16A2 from Micron Termination resistors not recommended for this configuration • Recommended memory that is compatible with the ADV7800 includes K4H281638B-TCB0 from Samsung, the MT46V8M16-TGP-75 from Micron, and the HYB25D128160CE-6 from Infineon Rev. C | Page 16 of 28 Data Sheet ADV7800 RECOMMENDED EXTERNAL LOOP FILTER COMPONENTS The external loop filter components for the ELPF pins should be placed as close as possible to the respective pins. Figure 8 shows the recommended component values. PIN 88 (ELPF2) PIN 86 (ELPF1) 10nF 160Ω 39nF 820nF 82nF PVDD = 1.8V PVDD = 1.8V Figure 8. ELPF Components Rev. C | Page 17 of 28 06760-008 1.69kΩ ADV7800 Data Sheet TYPICAL CONNECTION DIAGRAMS 06760-009 ADV7800 Figure 9. Typical Connection Diagram (External DDR Memory) Rev. C | Page 18 of 28 Data Sheet ADV7800 06760-010 ADV7800 Figure 10. Typical Connection Diagram (External SDR Memory) Rev. C | Page 19 of 28 ADV7800 Data Sheet PIXEL INPUT/OUTPUT FORMATTING There are several modes in which the ADV7800 pixel port can be configured. These modes are under the I2C control of OP_FORMAT_SEL[5:0]. PIXEL DATA OUTPUT MODES HIGHLIGHTS The ADV7800 has a flexible pixel port, which can be configured in a variety of formats to accommodate downstream ICs. See Table 8 and Table 9 for more information on each mode. The output pixel port features include • 8-/10-bit ITU-R BT.656 4:2:2 YCrCb with embedded time codes and/or HS_OUT, VS_OUT, and FLD_DE_OUT pin timing • 16-/20-/24-bit YCrCb with embedded time codes and/or HS_OUT, VS_OUT, and FLD_DE_OUT pin timing • 24-/30-bit YCrCb/RGB with embedded time codes and/or HS_OUT, VS_OUT, and FLD_DE_OUT pin timing • DDR 8-/10-bit 4:2:2 YCrCb for all standards • DDR 24-/30-bit 4:4:4 RGB for all standards • Simultaneous output modes 16-/20-bit YCrCb and 8-/10-bit 4:2:2 YCrCb up to 525i/525p and 625i/625p DIGITAL VIDEO INPUT PORT HIGHLIGHTS The ADV7800 contains a 24-bit digital input port. Main features are as follows: • Support for 24-bit RGB input data from the DVI/HDMI Rx IC, pass-through, or output converted to 4:2:2 YCrCb • Support for 24-bit 4:4:4, 16-/20-bit 4:2:2 525i, 625i, 525p, 625p, 1080i, 720p, 1080p, and VGA to SXGA at 75 Hz input data from the DVI/HDMI Rx IC chip, pass-through, or output converted to 4:2:2 YCrCb • Dedicated synchronization and pixel port inputs Rev. C | Page 20 of 28 Data Sheet ADV7800 Table 8. SDR Pixel Port Output Modes 1 OP_FORMAT_SEL [5:0] Pixel Output P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 1 0x00 8-Bit SDR ITU-656 Mode 1 Y7, Cb7, Cr7 Y6, Cb6, Cr6 Y5, Cb5, Cr5 Y4, Cb4, Cr4 Y3, Cb3, Cr3 Y2, Cb2, Cr2 Y1, Cb1, Cr1 Y0, Cb0, Cr0 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z 0x01 10-Bit SDR ITU-656 Mode 1 Y9, Cb9, Cr9 Y8, Cb8, Cr8 Y7, Cb7, Cr7 Y6, Cb6, Cr6 Y5, Cb5, Cr5 Y4, Cb4, Cr4 Y3, Cb3, Cr3 Y2, Cb2, Cr2 Y1, Cb1, Cr1 Y0, Cb0, Cr0 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z 0x05 16-Bit SDR ITU-656 4:2:2 Mode 1 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Z Z Cb7, Cr7 Cb6, Cr6 Cb5, Cr5 Cb4, Cr4 Cb3, Cr3 Cb2, Cr2 Cb1, Cr1 Cb0, Cr0 Z Z Z Z Z Z Z Z Z Z Z Z 0x06 20-Bit SDR ITU-656 4:2:2 Mode 1 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb9, Cr9 Cb8, Cr8 Cb7, Cr7 Cb6, Cr6 Cb5, Cr5 Cb4, Cr4 Cb3, Cr3 Cb2, Cr2 Cb1, Cr1 Cb0, Cr0 Z Z Z Z Z Z Z Z Z Z 0x0A 24-Bit SDR 4:4:4 Mode 1 G7 G6 G5 G4 G3 G2 G1 G0 Z Z B7 B6 B5 B4 B3 B2 B1 B0 Z Z R7 R6 R5 R4 R3 R2 R1 R0 Z Z It is recommended to print this table (located on this page and the following page) and read as one horizontal expanded table. Rev. C | Page 21 of 28 0x2C 24-Bit SDR 4:4:4 Mode 2 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 R7 R6 R5 R4 R3 R2 R1 R0 Z Z Z Z Z Z ADV7800 OP_FORMAT_SEL [5:0] Pixel Output P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 Data Sheet 0x2D 24-Bit SDR 4:4:4 Mode 1 R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 Z Z Z Z Z Z 0x2E 24-Bit SDR 4:4:4 Mode 1 B7 B6 B5 B4 B3 B2 B1 B0 R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 Z Z Z Z Z Z 0x0B 30-Bit SDR 4:4:4 Mode 1 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 Rev. C | Page 22 of 28 0x28 16-Bit and 8-Bit SDR 4:2:2 Mode 1 Parallel Output Main Y7 Main Y6 Main Y5 Main Y4 Main Y3 Main Y2 Main Y1 Main Y0 Z Z Main Cb7, Cr7 Main Cb6, Cr6 Main Cb5, Cr5 Main Cb4, Cr4 Main Cb3, Cr3 Main Cb2, Cr2 Main Cb1, Cr1 Main Cb0, Cr0 Z Z Aux Y7, Cb7, Cr7 Aux Y6, Cb6, Cr6 Aux Y5, Cb5, Cr5 Aux Y4, Cb4, Cr4 Aux Y3, Cb3, Cr3 Aux Y2, Cb2, Cr2 Aux Y1, Cb1, Cr1 Aux Y0, Cb0, Cr0 Z Z 0x29 20-Bit and 10-Bit SDR 4:2:2 Mode 1 Parallel Output Main Y9 Main Y8 Main Y7 Main Y6 Main Y5 Main Y4 Main Y3 Main Y2 Main Y1 Main Y0 Main Cb9, Cr9 Main Cb8, Cr8 Main Cb7, Cr7 Main Cb6, Cr6 Main Cb5, Cr5 Main Cb4, Cr4 Main Cb3, Cr3 Main Cb2, Cr2 Main Cb1, Cr1 Main Cb0, Cr0 Aux Y9, Cb9, Cr9 Aux Y8, Cb8, Cr8 Aux Y7, Cb7, Cr7 Aux Y6, Cb6, Cr6 Aux Y5, Cb5, Cr5 Aux Y4, Cb4, Cr4 Aux Y3, Cb3, Cr3 Aux Y2, Cb2, Cr2 Aux Y1, Cb1, Cr1 Aux Y0, Cb0, Cr0 Data Sheet ADV7800 Table 9. DDR Pixel Port Output Modes 1 OP_FORMAT_SEL [5:0] Pixel Output P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 1 0x10 8-Bit DDR ITU-656 Clock Rise Clock Fall Cb7, Cr7 Y7 Cb6, Cr6 Y6 Cb5, Cr5 Y5 Cb4, Cr4 Y4 Cb3, Cr3 Y3 Cb2, Cr2 Y2 Cb1, Cr1 Y1 Cb0, Cr0 Y0 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z 0x11 10-Bit DDR ITU-656 Clock Rise Clock Fall Cb9, Cr9 Y9 Cb8, Cr8 Y8 Cb7, Cr7 Y7 Cb6, Cr6 Y6 Cb5, Cr5 Y5 Cb4, Cr4 Y4 Cb3, Cr3 Y3 Cb2, Cr2 Y2 Cb1, Cr1 Y1 Cb0, Cr0 Y0 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z 0x3D 24-Bit DDR 4:2:2 RGB (CLK/2) Mode 1 Clock Rise Clock Fall B7-0 B7-1 B6-0 B6-1 B5-0 B5-1 B4-0 B4-1 B3-0 B3-1 B2-0 B2-1 B1-0 B1-1 B0-0 B0-1 R7-0 R7-1 R6-0 R6-1 R5-0 R5-1 R4-0 R4-1 R3-0 R3-1 R2-0 R2-1 R1-0 R1-1 R7-0 R7-1 G7-0 G7-1 G6-0 G6-1 G5-0 G5-1 G4-0 G4-1 G3-0 G3-1 G2-0 G2-1 G1-0 G1-1 G0-0 G0-1 Z Z Z Z Z Z Z Z Z Z Z Z 0x3E 24-Bit DDR 4:2:2 RGB (CLK/2) mode 2 Clock Rise Clock Fall R7-0 R7-1 R6-0 R6-1 R5-0 R5-1 R4-0 R4-1 R3-0 R3-1 R2-0 R2-1 R1-0 R1-1 R0-0 R0-1 G7-0 G7-1 G6-0 G6-1 G5-0 G5-1 G4-0 G4-1 G3-0 G3-1 G2-0 G2-1 G1-0 G1-1 G0-0 G0-1 B7-0 B7-1 B6-0 B6-1 B5-0 B5-1 B4-0 B4-1 B3-0 B3-1 B2-0 B2-1 B1-0 B1-1 B0-0 B0-1 Z Z Z Z Z Z Z Z Z Z Z Z It is recommended to print this table (located on this page and the following page) and read as one horizontal expanded table. Rev. C | Page 23 of 28 ADV7800 OP_FORMAT_SEL [5:0] Pixel Output P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 Data Sheet 0x38 16-Bit and 8-Bit DDR 4:2:2 Mode 1 Parallel Output (CLK/2) Clock Rise Clock Fall Main Y7 Main Y7 Main Y6 Main Y6 Main Y5 Main Y5 Main Y4 Main Y4 Main Y3 Main Y3 Main Y2 Main Y2 Main Y1 Main Y1 Main Y0 Main Y0 Z Z Z Z Main Cb7 Main Cr7 Main Cb6 Main Cr6 Main Cb5 Main Cr5 Main Cb4 Main Cr4 Main Cb3 Main Cr3 Main Cb2 Main Cr2 Main Cb1 Main Cr1 Main Cb0 Main Cr0 Z Z Z Z Aux Cb7, Cr7 Aux Y7 Aux Cb6, Cr6 Aux Y6 Aux Cb5, Cr5 Aux Y5 Aux Cb4, Cr4 Aux Y4 Aux Cb3, Cr3 Aux Y3 Aux Cb2, Cr2 Aux Y2 Aux Cb1, Cr1 Aux Y1 Aux Cb0, Cr0 Aux Y0 Z Z Z Z 0x39 20-Bit and 10-Bit DDR 4:2:2 Mode 1 Parallel Output (CLK/2) Clock Rise Clock Fall Main Y9 Main Y9 Main Y8 Main Y8 Main Y7 Main Y7 Main Y6 Main Y6 Main Y5 Main Y5 Main Y4 Main Y4 Main Y3 Main Y3 Main Y2 Main Y2 Main Y1 Main Y1 Main Y0 Main Y0 Main Cb9 Main Cr9 Main Cb8 Main Cr8 Main Cb7 Main Cr7 Main Cb6 Main Cr6 Main Cb5 Main Cr5 Main Cb4 Main Cr4 Main Cb3 Main Cr3 Main Cb2 Main Cr2 Main Cb1 Main Cr1 Main Cb0 Main Cr0 Aux Cb9, Cr9 Aux Y9 Aux Cb8, Cr8 Aux Y8 Aux Cb7, Cr7 Aux Y7 Aux Cb6, Cr6 Aux Y6 Aux Cb5, Cr5 Aux Y5 Aux Cb4, Cr4 Aux Y4 Aux Cb3, Cr3 Aux Y3 Aux Cb2, Cr2 Aux Y2 Aux Cb1, Cr1 Aux Y1 Aux Cb0, Cr0 Aux Y0 Rev. C | Page 24 of 28 0x3C 24-Bit DDR 4:2:2RGB (CLK/2) Clock Rise Clock Fall G7-0 G7-1 G6-0 G6-1 G5-0 G5-1 G4-0 G4-1 G3-0 G3-1 G2-0 G2-1 G1-0 G1-1 G0-0 G0-1 B7-0 B7-1 B6-0 B6-1 B5-0 B5-1 B4-0 B4-1 B3-0 B3-1 B2-0 B2-1 B1-0 B1-1 B0-0 B0-1 R7-0 R7-1 R6-0 R6-1 R5-0 R5-1 R4-0 R4-1 R3-0 R3-1 R2-0 R2-1 R1-0 R1-1 R0-0 R0-1 Z Z Z Z Z Z Z Z Z Z Z Z Data Sheet ADV7800 Table 10. Pixel Port Input Modes IP_DATA_SEL[5:0] Pixel Input P53 P52 P51 P50 P49 P48 P47 P46 P45 P44 P43 P42 P41 P40 P39 P38 P37 P36 P35 P34 P33 P32 P31 P30 0x00 24-Bit 4:4:4 Input G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 R7 R6 R5 R4 R3 R2 R1 R0 0x01 20-Bit 4:2:2 Input Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Cb9, Cr9 Cb8, Cr8 Cb7, Cr7 Cb6, Cr6 Cb5, Cr5 Cb4, Cr4 Cb3, Cr3 Cb2, Cr2 Y1 Y0 Z Z Cb1, Cr1 Cb0, Cr0 Z Z 0x04 16-Bit 4:2:2 Input Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb7, Cr7 Cb6, Cr6 Cb5, Cr5 Cb4, Cr4 Cb3, Cr3 Cb2, Cr2 Cb1, Cr1 Cb0, Cr0 Z Z Z Z Z Z Z Z Rev. C | Page 25 of 28 0x06 10-Bit 4:2:2 Input Y9, Cb9, Cr9 Y8, Cb8, Cr8 Y7, Cb7, Cr7 Y6, Cb6, Cr6 Y5, Cb5, Cr5 Y4, Cb4, Cr4 Y3, Cb3, Cr3 Y2, Cb2, Cr2 Y1, Cb1, Cr1 Y0, Cb0, Cr0 Z Z Z Z Z Z Z Z Z Z Z Z Z Z 0x07 8-Bit 4:2:2 Input Y7, Cb7, Cr7 Y6, Cb6, Cr6 Y5, Cb5, Cr5 Y4, Cb4, Cr4 Y3, Cb3, Cr3 Y2, Cb2, Cr2 Y1, Cb1, Cr1 Y0, Cb0, Cr0 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z ADV7800 Data Sheet OUTLINE DIMENSIONS 0.75 0.60 0.45 26.20 26.00 SQ 25.80 1.60 MAX 133 132 176 1 PIN 1 24.20 24.00 SQ 23.80 TOP VIEW (PINS DOWN) 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 MAX COPLANARITY VIEW A VIEW A ROTATED 90° CCW 89 44 45 88 0.50 BSC LEAD PITCH 0.27 0.22 0.17 COMPLIANT TO JEDEC STANDARDS MS-026-BG A 051706-A 1.45 1.40 1.35 Figure 11. 176-Lead Low Profile Quad Flat Package [LQFP] (ST-176) Dimensions shown in millimeters ORDERING GUIDE Model1 ADV7800BSTZ-80 ADV7800BSTZ-150 EVAL-ADV7800EB1Z 1 Temperature Range 0°C to +85°C 0°C to +85°C Package Description 176-Lead Low Profile Quad Flat Package (LQFP) 176-Lead Low Profile Quad Flat Package (LQFP) Evaluation Board (External DDR SD Memory) Z = RoHS Compliant Part. Rev. C | Page 26 of 28 Package Option ST-176 ST-176 Data Sheet ADV7800 NOTES Rev. C | Page 27 of 28 ADV7800 Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06760-0-8/11(C) Rev. C | Page 28 of 28