REVISIONS LTR DESCRIPTION DATE Prepared in accordance with ASME Y14.24 APPROVED Vendor item drawing REV PAGE REV PAGE 18 19 REV STATUS OF PAGES 20 21 22 23 REV PAGE PMIC N/A 1 2 3 4 5 6 7 8 9 PREPARED BY CHECKED BY 12 13 14 15 16 17 TITLE Phu H. Nguyen 13-01-17 11 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http://www.landandmaritime.dla.mil/ Phu H. Nguyen Original date of drawing YY MM DD 10 APPROVED BY MICROCIRCUIT, LINEAR, 1.2 GHz CLOCK DISTRIBUTION IC, 1.6 GHz INPUTS, DIVIDERS, FIVE OUTPUTS, MONOLITHIC SILICON Thomas M. Hess SIZE A REV AMSC N/A CODE IDENT. NO. DWG NO. V62/12656 16236 PAGE 1 OF 23 5962-V041-13 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 1.2 GHz clock distribution IC, 1.6 GHz inputs, dividers, five outputs microcircuit, with an operating temperature range of -55°C to +85°C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/12656 - Drawing number 01 X E Device type (See 1.2.1) Case outline (See 1.2.2) Lead finish (See 1.2.3) 1.2.1 Device type(s). Device type Generic 01 AD9512-EP Circuit function 1.2 GHz clock distribution IC, 1.6 GHz inputs, dividers, five outputs 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins X 48 JEDEC PUB 95 Package style JEDEC MO-220-VKKD-2 Lead Frame Chip Scale Package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator A B C D E Z DLA LAND AND MARITIME COLUMBUS, OHIO Material Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium Other SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12656 PAGE 2 1.3 Absolute maximum ratings. 1/ VS with respect to GND .......................................................................... DSYNC/DSYNCB with respect to GND ................................................... RSET with respect to GND ..................................................................... CLK1, CLK1B, CLK2, CLK2B with respect to GND ................................. CLK1 with respect to CLK1B ................................................................... CLK2 with respect to CLK2B ................................................................... SCLK, SDIO, SDO, CSB with respect to GND ........................................ OUT0, OUT1, OUT2, OUT3, OUT4 with respect to GND ....................... FUNCTION with respect to GND ............................................................. SYNC STATUS with respect to GND ...................................................... Storage temperature range ..................................................................... Junction temperature .............................................................................. Lead temperature (10 sec) ...................................................................... -0.3 V to +3.6 V -0.3 V to VS + 0.3 V -0.3 V to VS + 0.3 V -0.3 V to VS + 0.3 V -1.2 V to +1.2 V -1.2 V to +1.2 V -0.3 V to VS + 0.3 V -0.3 V to VS + 0.3 V -0.3 V to VS + 0.3 V -0.3 V to VS + 0.3 V -65°C to 150°C 150°C 300°C 1.4 Thermal characteristics. Thermal resistance 2/ Case outline Case X θJA 28.5 Unit °C/W 2. APPLICABLE DOCUMENTS JEDEC – SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 JESD51-7 – – Registered and Standard Outlines for Semiconductor Devices High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Copies of these documents are available online at http:/www.jedec.org or from JEDEC – Solid State Technology Association, 3103 North 10th Street, Suite 240–S, Arlington, VA 22201.) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as follows: A. B. C. 1/ 2/ Manufacturer’s name, CAGE code, or logo Pin 1 identifier ESDS identification (optional) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Thermal impedance measurements were taken on a 4-layer board in still air, in accordance with EIA/JESD51-7. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12656 PAGE 3 3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Terminal function. The terminal function shall be as shown in figure 3. 3.5.4 Functional block diagram. The functional block diagram shall be as shown in figure 4. 3.5.5 LVPECL differential output swing vs frequency. The LVPECL differential output swing vs frequency shall be as shown in figure 5. 3.5.6 LVDS differential output swing vs frequency. The LVDS differential output swing vs frequency shall be as shown in figure 6. 3.5.7 CMOS single ended output swing vs frequency and load. The CMOS single ended output swing vs frequency and load shall be as shown in figure 7. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12656 PAGE 4 TABLE I. Electrical performance characteristics. 1/ Test Symbol Limits Test conditions 2/ Min Typ Unit Max CLOCK INPUTS Clock inputs (CLK1, CLK2) Input frequency Input sensitivity Input level 3/ 0 Input common mode voltage VCM Input common mode range Input sensitivity, single ended VCMR Input resistance Input capacitance 4/ 5/ 6/ At -40°C to +85°C With 200 mV p-p signal applied, dc-coupled CLK2 ac-coupled; CLK2B ac bypassed to RF ground Self-biased CLOCK OUTPUTS LVPECL clock outputs (Termination = 50 Ω to VS – 2 V) OUT0, OUT1, OUT2; Differential Output level 0x3D (0x3E) (0x3F)[3:2] = 10b Output frequency See FIGURE 5 Output high voltage VOH Output low voltage VOL Output differential voltage VOD LVDS clock outputs (Termination = 100 Ω differential; default) OUT3, OUT4; Differential Output level 0x40 (0x41)[2:1] = 01b Output frequency Differential output voltage Delta VOD Output offset voltage Delta VOS Short Circuit current CMOS clock outputs OUT3, OUT4 Output frequency Output voltage high Output voltage low 1.6 150 7/ 1.45 1.5 1.6 1.6 1.3 VOS ISA, ISB VOH VOL At full temperature range At -40°C to +85°C 4.0 4.8 2 VS – 1.22 VS – 2.10 660 VS – 0.98 VS – 1.80 810 250 360 1.05 1.125 1.23 1.23 Output shorted to GND 14 Single ended measurements; B outputs: inverted, termination open With 5 pF load each outputs, see FIGURE 7 @ 1 mA load @ 1 mA load 1.8 V mV p-p 5.6 kΩ pF 1200 VS – 0.93 VS – 1.67 965 MHz V V mV 800 450 25 1.375 1.375 25 24 MHz mV mV V V mV mA 250 MHz V V 150 3.5 mA termination current See FIGURE 6 VOD 2 8/ 1.7 1.7 GHz mV p-p V p-p V V VS – 0.1 0.1 See footnote at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12656 PAGE 5 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test conditions 2/ Limits Min Unit Typ Max 130 130 180 180 ps 320 335 490 490 635 635 ps 360 375 545 545 695 695 TIMING CHARACTERISTICS LVPECL (Termination = 50 Ω to VS – 2V, Output level 0x3D (0x3E)(0x3F)[3:2] =10b) Output rise time tRP Output fall time tFP Propagation delay, tPELC, CLK-TO-LVPECL OUT 9/ 20% to 80%, measured differentially 80% to 20%, measured differentially Divide = Bypass At full temperature range Divide = 2 to 32 At -40°C to +85°C At full temperature range At -40°C to +85°C Variation with temperature Output skew, LVPECL outputs 0.5 OUT1 to OUT0 on same part 10/ tSKP 70 OUT1 to OUT2 on same part 10/ tSKP 15 OUT0 to OUT2 on same part 10/ tSKP 45 All LVPECL OUT across multiple parts 11/ tSKP_AB Same LVPECL OUT across multiple parts 11/ tSKP_AB LVDS (Termination = 100 Ω differential, Output level 0x40 (0x41)[2:1] = 01b, 3.5 mA termination current) 100 45 65 140 80 90 275 130 ps Output rise time Output fall time Propagation delay, tLVDS, CLK-to-LVDS OUT 9/ OUT3 to OUT4 200 210 350 350 ps 0.97 0.99 1.33 1.33 1.59 1.59 ns 1.02 1.04 1.38 1.38 0.9 1.64 1.64 tRL tFL 20% to 80%, measured differentially 80% to 20%, measured differentially Divide = Bypass At full temperature range Divide = 2 to 32 At -40°C to +85°C At full temperature range At -40°C to +85°C Variation with temperature Output skew, LVDS outputs OUT3 to OUT4 on same part, 10/ All LVDS OUTs across multiple parts 11/ Same LVDS OUT across multiple parts 11/ tSKV tSKV_AB tSKV_AB -85 ps/°C ps/°C +270 450 325 ps See footnote at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12656 PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test conditions 2/ TIMING CHARACTERISTICS-Continued. CMOS (B outputs are inverted; termination = open) Output rise time tRC 20% to 80%, CLOAD = 3 pF Output fall time tFC 80% to 20%, CLOAD = 3 pF Propagation delay, tCMOS, CLK to CMOS OUT 9/ At full temperature range Divide = Bypass Divide = 2 to 32 At -40°C to +85°C At full temperature range At -40°C to +85°C Variation with temperature Output skew, CMOS outputs OUT3 to OUT4 on same part, 10/ tSKC All CMOS OUT across multiple parts 11/ tSKC_AB Same CMOS OUT across multiple parts 11/ tSKC_AB LVPECL to LVDS OUT (Everything the same; different logic type LVPECL to LVDS on same part) Output skew tSKP_V LVPECL to CMOS OUT (Everything the same; different logic type LVPECL to CMOS on same part) Output skew tSKP_C LVDS to CMOS OUT (Everything the same; different logic type LVDS to CMOS on same part) Output skew tSKV_C Limits Min Unit Typ Max 681 646 865 992 ps 1.0 1.02 1.39 1.39 1.71 1.71 ns 1.05 1.07 1.44 1.44 1.76 1.76 1 ps/°C -140 +145 +300 650 500 ps 0.73 0.92 1.14 ns 0.87 1.14 1.43 ns 158 353 506 ps See footnote at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12656 PAGE 7 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test conditions 2/ Limits Min Typ Unit Max CLOCK OUTPUT PHASE NOISE CLK1 to LVPECL and additive phase noise CLK1 = 622.08 MHz, OUT = 622.08 MHz Divide Ratio = 1 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 KHz Offset @100 kHz Offset > 1 MHz Offset CLK1 = 622.08 MHz, OUT = 155.52 MHz Divide Ratio = 4 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 KHz Offset @100 kHz Offset > 1 MHz Offset CLK1 = 622.08 MHz, OUT = 38.88 MHz Divide Ratio = 16 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 KHz Offset @100 kHz Offset > 1 MHz Offset CLK1 = 491.52 MHz, OUT = 61.44 MHz Divide Ratio = 8 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 KHz Offset @100 kHz Offset > 1 MHz Offset CLK1 = 491.52 MHz, OUT = 245.76 MHz Divide Ratio = 2 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 KHz Offset @100 kHz Offset > 1 MHz Offset Input slew rate > 1 V/ns -125 -132 -140 -148 -153 -154 dBc/Hz -128 -140 -148 -155 -161 -161 dBc/Hz -135 -145 -158 -165 -165 -166 dBc/Hz -131 -142 -153 -160 -165 -165 dBc/Hz -125 -132 -140 -151 -157 -158 dBc/Hz See footnote at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12656 PAGE 8 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test conditions 2/ CLOCK OUTPUT PHASE NOISE- Continued. CLK1 to LVPECL and additive phase noise – Continued. CLK1 = 245.76 MHz, OUT = 61.44 MHz Divide Ratio = 4 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 KHz Offset @100 kHz Offset > 1 MHz Offset CLK1 to LVDS additive phase noise CLK1 = 622.08 MHz, OUT = 622.08 MHz Divide Ratio = 1 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 KHz Offset @100 kHz Offset @1 MHz Offset > 10 MHz Offset CLK1 = 622.08 MHz, OUT = 155.52 MHz Divide Ratio = 4 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 KHz Offset @100 kHz Offset @1 MHz Offset > 10 MHz Offset CLK1 = 491.52 MHz, OUT = 245.76 MHz Divide Ratio = 2 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 KHz Offset @100 kHz Offset @1 MHz Offset > 10 MHz Offset Limits Min Typ Unit Max -138 -144 -154 -163 -164 -165 dBC/Hz -100 -110 -118 -129 -135 -140 -148 dBC/Hz -112 -122 -132 -142 -148 -152 -155 dBC/Hz -108 -118 -128 -138 -145 -148 -154 dBC/Hz See footnote at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12656 PAGE 9 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Limits Test conditions 2/ Min CLOCK OUTPUT PHASE NOISE- Continued. CLK1 to LVDS additive phase noise – Continued. CLK1 = 491.52 MHz, OUT = 122.88 MHz Divide Ratio = 4 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 KHz Offset @100 kHz Offset @1 MHz Offset > 10 MHz Offset CLK1 = 245.76 MHz, OUT = 245.76 MHz Divide Ratio = 1 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 KHz Offset @100 kHz Offset @1 MHz Offset > 10 MHz Offset CLK1 = 245.76 MHz, OUT = 122.88 MHz Divide Ratio = 2 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 KHz Offset @100 kHz Offset @1 MHz Offset > 10 MHz Offset Typ Unit Max -118 -129 -136 -147 -153 -156 -158 dBC/Hz -108 -118 -128 -138 -145 -148 -155 dBC/Hz -118 -127 -137 -147 -154 -156 -158 dBC/Hz See footnote at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12656 PAGE 10 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test conditions 2/ Limits Min Typ Unit Max CLOCK OUTPUT PHASE NOISE- Continued. CLK1 to CMOS additive phase noise CLK1 = 245.76 MHz, OUT = 245.76 MHz Divide Ratio = 1 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 KHz Offset @100 kHz Offset @1 MHz Offset > 10 MHz Offset CLK1 = 245.76 MHz, OUT = 61.44 MHz Divide Ratio = 4 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 KHz Offset @100 kHz Offset @1 MHz Offset > 10 MHz Offset CLK1 = 78.6432 MHz, OUT = 78.6432 MHz Divide Ratio = 1 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 KHz Offset @100 kHz Offset @1 MHz Offset > 10 MHz Offset CLK1 = 78.6432 MHz, OUT = 39.3216 MHz Divide Ratio = 2 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 KHz Offset @100 kHz Offset > 1 MHz Offset -110 -121 -130 -140 -145 -149 -156 dBC/Hz -122 -132 -143 -152 -158 -160 -162 dBC/Hz -122 -132 -140 -150 -155 -158 -160 dBC/Hz -128 -136 -146 -155 -161 -162 dBC/Hz See footnote at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12656 PAGE 11 TABLE I. Electrical performance characteristics - Continued. 1/ Test Test conditions 2/ Limits Min Typ Unit Max CLOCK OUTPUT PHASE NOISE- Continued. LVPECL output additive time jitter CLK1 = 622.08 MHz Any LVPECL (OUT0 to OUT2) = 622.08 MHz, Divide ratio = 1 CLK1 = 622.08 MHz Any LVPECL (OUT0 to OUT2) = 155.52 MHz, Divide ratio = 4 CLK1 = 400 MHz Any LVPECL (OUT0 to OUT2) = 100 MHz, Divide ratio = 4 CLK1 = 400 MHz Any LVPECL (OUT0 to OUT2) = 100 MHz, Divide ratio = 4 Other LVPECL = 100 MHz Both LVDS (OUT3, OUT4) = 100 MHz CLK1 = 400 MHz Any LVPECL (OUT0 to OUT2) = 100 MHz, Divide ratio = 4 Other LVPECL = 50 MHz Both LVDS (OUT3, OUT4) = 50 MHz CLK1 = 400 MHz Any LVPECL (OUT0 to OUT2) = 100 MHz, Divide ratio = 4 Other LVPECL = 50 MHz Both CMOS (OUT3, OUT4) = 50 MHz (B outputs Off) CLK1 = 400 MHz Any LVPECL (OUT0 to OUT2) = 100 MHz, Divide ratio = 4 Other LVPECL = 50 MHz Both CMOS (OUT3, OUT4) = 50 MHz (B outputs On) 40 fs rms 55 fs rms Calculated from SNR of ADC method; fc = 100 MHz with AIN = 170 MHz 215 fs rms Calculated from SNR of ADC method; fc = 100 MHz with AIN = 170 MHz 215 fs rms 222 fs rms 225 fs rms 225 fs rms BW = 12 kHz to 20 MHz (OC-12) BW = 12 kHz to 20 MHz (OC-3) Interferer(s) Interferer(s) Calculated from SNR of ADC method; fc = 100 MHz with AIN = 170 MHz Interferer(s) Interferer(s) Calculated from SNR of ADC method; fc = 100 MHz with AIN = 170 MHz Interferer(s) Interferer(s) Calculated from SNR of ADC method; fc = 100 MHz with AIN = 170 MHz Interferer(s) Interferer(s) See footnote at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12656 PAGE 12 TABLE I. Electrical performance characteristics - Continued. 1/ Test Test conditions 2/ Limits Min Typ Unit Max CLOCK OUTPUT PHASE NOISE- Continued. LVDS output additive time jitter CLK1 = 400 MHz LVDS (OUT3) = 100 MHz Divide ratio = 4 CLK1 = 400 MHz LVDS (OUT4) = 100 MHz Divide ratio = 4 CLK1 = 400 MHz LVDS (OUT3) = 100 MHz Divide ratio = 4 LVDS (OUT4) = 50 MHz All LVPECL = 50 MHz CLK1 = 400 MHz LVDS (OUT4) = 100 MHz Divide ratio = 4 LVDS (OUT3) = 50 MHz All LVPECL = 50 MHz CLK1 = 400 MHz LVDS (OUT3) = 100 MHz Divide ratio = 4 CMOS (OUT4) = 50 MHz (B Outputs Off) All LVPECL = 50 MHz CLK1 = 400 MHz LVDS (OUT4) = 100 MHz Divide ratio = 4 CMOS (OUT3) = 50 MHz (B Outputs Off) All LVPECL = 50 MHz CLK1 = 400 MHz LVDS (OUT3) = 100 MHz Divide ratio = 4 CMOS (OUT4) = 50 MHz (B Outputs On) All LVPECL = 50 MHz Calculated from SNR of ADC method; fc = 100 MHz with AIN = 170 MHz 264 fs rms Calculated from SNR of ADC method; fc = 100 MHz with AIN = 170 MHz 319 fs rms Calculated from SNR of ADC method; fc = 100 MHz with AIN = 170 MHz 395 fs rms 395 fs rms 367 fs rms 367 fs rms 548 fs rms Interferer(s) Interferer(s) Calculated from SNR of ADC method; fc = 100 MHz with AIN = 170 MHz Interferer(s) Interferer(s) Calculated from SNR of ADC method; fc = 100 MHz with AIN = 170 MHz Interferer(s) Interferer(s) Calculated from SNR of ADC method; fc = 100 MHz with AIN = 170 MHz Interferer(s) Interferer(s) Calculated from SNR of ADC method; fc = 100 MHz with AIN = 170 MHz Interferer(s) Interferer(s) See footnote at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12656 PAGE 13 TABLE I. Electrical performance characteristics - Continued. 1/ Test Test conditions 2/ Limits Min CLOCK OUTPUT PHASE NOISE- Continued. LVDS output additive time jitter – Continued. CLK1 = 400 MHz Calculated from SNR of ADC method; fc = 100 MHz with AIN = 170 MHz LVDS (OUT4) = 100 MHz Divide ratio = 4 CMOS (OUT3) = 50 MHz (B Outputs On) Interferer(s) All LVPECL = 50 MHz Interferer(s) CMOS output additive time jitter CLK1 = 400 MHz Calculated from SNR of ADC method; fc = 100 MHz with AIN = 170 MHz Both CMOS (OUT3, OUT4) = 100 MHz (B output On) Divide ratio = 4 CLK1 = 400 MHz Calculated from SNR of ADC method; fc = 100 MHz with AIN = 170 MHz CMOS (OUT3) = 100 MHz (B output On) Divide ratio = 4 All LVPECL = 50 MHz Interferer(s) LVDS (OUT4) = 50 MHz Interferer(s) CLK1 = 400 MHz Calculated from SNR of ADC method; fc = 100 MHz with AIN = 170 MHz CMOS (OUT3) = 100 MHz (B output On) Divide ratio = 4 All LVPECL = 50 MHz Interferer(s) CMOS (OUT4) = 50 MHz (B output Off) Interferer(s) CLK1 = 400 MHz Calculated from SNR of ADC method; fc = 100 MHz with AIN = 170 MHz CMOS (OUT3) = 100 MHz (B output On) Divide ratio = 4 All LVPECL = 50 MHz Interferer(s) CMOS (OUT4) = 50 MHz (B output On) Interferer(s) Typ Unit Max 548 fs rms 275 400 374 555 See footnote at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12656 PAGE 14 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Limits Test conditions 2/ Min Typ Unit Max SERIAL CONTROL PORT CSB, SCLK (Inputs) 12/ Input logic 1 voltage Input logic 0 voltage Input logic 1 current Input logic 0 current Input capacitance SDIO (when input) Input logic 1 voltage Input logic 0 voltage Input logic 1 current Input logic 0 current Input capacitance SDIO, SDO (Outputs) Input logic 1 voltage Input logic 0 voltage Timing Clock rate (SCLK, 1/tSCLK) Pulse width high Pulse width low SDIO to SCLK setup SCLK to SDIO hold SCLK to valid SDIO and SDO CSB to SCLK setup and hold CSB minimum pulse width high 2.0 V 0.8 110 µA 1 2 pF 2.0 V 0.8 10 10 2 nA pF 2.7 V 0.4 25 tPWH tPWL tDS tDH tDV tS, tH tPWH MHz ns 16 16 2 1 6 2 3 FUNCTION PIN Input characteristics 13/ Input logic 1 voltage Input logic 0 voltage Input logic 1 current Input logic 0 current Capacitance Reset timing Pulse width low SYNC timing Pulse width low 2.0 V 0.8 110 µA 1 2 14/ pF 50 ns 1.5 High speed clock cycles See footnote at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12656 PAGE 15 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test conditions 2/ Limits Min Typ Unit Max SYNC STATUS PIN Output characteristics Output voltage high Output voltage low VOH VOL 2.7 V 0.4 POWER Power up default mode power dissipation Power dissipation Full sleep power down Power down (PDB) Power delta CLK1, CLK2 power down Divider, DIV 2 to 32 bypass LVPELL output power down (PD2, PD3) LVDS Output power down CMOS output power down (Static) CMOS output power down (Dynamic) CMOS output power down (Dynamic) 15/ 550 600 mW mW 35 60 800 850 60 80 10 23 50 15 27 65 25 33 75 mW 80 56 115 92 70 150 110 85 190 125 165 210 16/ 17/ 18/ 19/ For each divider. For each output. Does not include dissipation in termination (PD2 only) For each output For each output. Static (no clock) For each CMOS output, single ended. Clocking at 62 MHz with 5 pF load. For each CMOS output, single ended. Clocking at 125 MHz with 5 pF load. See footnote at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12656 PAGE 16 TABLE I. Electrical performance characteristics - Continued. 1/ 1/ 2/ 3/ 4/ 5/ 6/ 7/ 8/ 9/ 10/ 11/ 12/ 13/ 14/ 15/ 16/ 17/ 18/ 19/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. Typical (Typ) is given for VS = 3.3 V ±5%; TA = 25°C, RSET = 4.12 kΩ, unless otherwise noted. Minimum (Min) and Maximum (Max) values are given over full VS and TA (-55°C to +85°C) variation. CLK1 and CLK2 are electrically identical; each can be used as either differential or single ended input. Jitter performance can be improved with high slew rates (greater swing). Larger swing turn on protection diodes and can degrade jitter performance. Self biased; enables ac coupling; at full temperature range. With a 50 Ω termination, this is -12.5 dBm. With a 50 Ω termination, this is +10 dBm. The measurements are for CLK1. For CLK2, add approximately 25 ps. This is the difference between any two similar delay paths within a single device operating at the same voltage and temperature. This is the difference between any two similar delay paths across multiple devices operating at the same voltage and temperature CSB and SCLK have 30 kΩ internal pull down resistor. The FUNCTION pin has a 30 kΩ internal pull down resistor. This pin should normally be held high. Do not let input float. High speed clock is CLK1 or CLK2, whichever is being used for distribution. Power up default state; does not include power dissipated in output load resistors. No clock. All outputs on. Three LVPECL outputs @ 800 MHz, two CMOS out @ 62 MHz (5 pF load). Does not include power dissipated in external resistors. All outputs on. Three LVPECL outputs @ 800 MHz, two CMOS out @ 125 MHz (5 pF load). Does not include power dissipated in external resistors. Maximum sleep is entered by setting 0x0A[1:0] = 01b and 0x58[4] = 1b. This power off all band gap references. Does not include power dissipated in terminations. Set FUNCTION pin for PDB operation by setting 0x58[6:5] = 11b. Pull PDB low. Does not include power dissipated in terminations. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12656 PAGE 17 Case X D/E D1/E1 PIN 1 IDENTIFIER TOP VIEW 12° MAX SEATING PLANE A1 A A3 A2 e b 48 PLS L1 13 12 24 25 L1 EXPOSED PAD PIN 1 IDENTIFIER D2/E2 L 1 36 37 48 L2 e1 BOTTOM VIEW FIGURE 1. Case outline. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12656 PAGE 18 Dimensions Millimeters Symbol Min Max Symbol A A1 A2 A3 b D/E D1/E1 0.80 1.00 0.80 0.20 REF 0.05 0.18 0.30 7.00 BSC 6.75 BSC D2/E2 e e1 L L1 L2 Millimeters Min Max 4.95 5.25 0.50 BSC 5.50 REF 0.30 0.50 0.60 0.25 NOTES: 1. All linear dimensions are in millimeters. 2. Falls within JEDEC MO-220-VKKD-2. FIGURE 1. Case outline - Continued. Terminal number Terminal symbol Terminal number 1 2 3 4 5 6 7 8 9 10 11 12 DSYNC DSYNCB VS VS DNC VS CLK2 CLK2B VS CLK1 CLK1B FUNCTION 13 14 15 16 17 18 19 20 21 22 23 24 Case outline X Terminal symbol Terminal number Terminal symbol Terminal number Terminal symbol SYNC STATUS SCLK SDIO SDO CSB VS GND OUT2B OUT2 VS VS GND VS OUT1B OUT1 VS VS OUT4B OUT4 VS VS OUT3B OUT3 VS 37 38 39 40 41 42 43 44 45 46 47 48 GND GND VS VS OUT0B OUT0 GND VS RSET GND VS VS 25 26 27 28 29 30 31 32 33 34 35 36 FIGURE 2. Terminal connections. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12656 PAGE 19 Case outline X Terminal number Mnemonic 1 2 3, 4, 6, 9, 18, 22, 23, 25, 28, 29, 32, 33, 36, 39, 40 44, 47, 48 5 7 8 10 11 12 DSYNC DSYNCB 13 14 15 16 17 19, 24, 37, 38, 43, 46 20 21 26 27 30 31 34 35 41 42 45 VS DNC CLK2 CLK2B CLK1 CLK1B FUNCTION SYNC STATUS SCLK SDIO SDO CSB GND OUT2B OUT2 OUT1B OUT1 OUT4B OUT4 OUT3B OUT3 OUT0B OUT0 RSET EPAD Description Detect Sync. Use for multichip synchronization. Detect Sync. Complement. Used for multichip synchronization. Power supply (3.3 V). Do Not Connect. Do not connect to this pin. Clock input. Complementary Clock input. Used in conjunction with CLK2. Clock input. Complementary Clock input. Used in conjunction with CLK1. Multipurpose Input. Can be programmed as a reset (RESETB), sync (SYNCB), or power down (PDB) pin. Output Used to Monitor the Status of Multichip Synchronization. Serial Data Clock. Serial Data I/O. Serial Data Output. Serial Port Chip Select. Ground. Complementary LVPECL Output. LVPECL Output. Complementary LVPECL Output. LVPECL Output. Complementary LVDS/Inverted CMOS Output. LVDS/CMOS Output. Complementary LVDS/Inverted CMOS Output. LVDS/CMOS Output. Complementary LVPECL Output. LVPECL Output. Current Set Resistor to Ground. Nominal value = 4.12 kΩ. Exposed paddle. The exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to function properly, the paddle must be attached to ground, GND. FIGURE 3. Terminal function. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12656 PAGE 20 VS DSYNC SYNC STATUS PROGRAMMABLE DIVIDERS AND PHASE ADJUST DETECT SYNC DSYNCB RSET VREF SYNCB, RESETB PDB FUNCTION GND SYNC STATUS LVPECL OUT0 /1,/2,/3.../31,/32 OUT0B LVPECL OUT1 /1,/2,/3.../31,/32 OUT1B CLK1 LVPECL CLK1B OUT2 /1,/2,/3.../31,/32 OUT2B CLK2 LVDS/CMOS CLK2B OUT3 /1,/2,/3.../31,/32 SCLK SDIO SDO CSB OUT3B LVDS/CMOS SERIAL CONTROL PORT OUT4 /1,/2,/3.../31,/32 OUT5B FIGURE 4. Functional block diagram. 1.8 DIFFERENTIAL SWING (V P-P ) 1.7 1.6 1.5 1.4 1.3 1.2 100 600 1100 1600 OUTPUT FREQUENCY (MHz) FIGURE 5. LVPECL differential output swing vs frequency. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12656 PAGE 21 DIFFERENTIAL SWING (mV P-P ) 750 700 650 600 550 500 100 300 500 700 900 OUTPUT FREQUENCY (MHz) FIGURE 6. LVDS differential output swing vs frequency. 3.5 2 pF 3.0 OUTPUT(V PK ) 2.5 10 pF 2.0 1.5 100 20 pF 0.5 0 0 100 200 300 400 500 600 OUTPUT FREQUENCY(MHz) FIGURE 7. CMOS single ended output swing vs frequency and load. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12656 PAGE 22 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number V62/12656-01XE 24355 AD9512UCPZ-EP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code 24355 DLA LAND AND MARITIME COLUMBUS, OHIO Source of supply Analog Devices 1 Technology Way P.O. Box 9106 Norwood, MA 02062-9106 SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12656 PAGE 23