PDF Data Sheet Rev. C

FEATURES
FUNCTIONAL BLOCK DIAGRAM
Output frequency: <1 MHz to 1 GHz
Start-up frequency accuracy: <±100 ppm (determined by
VCXO reference accuracy)
Zero delay operation
Input-to-output edge timing: <150 ps
Dual VCO dividers
14 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS
14 dedicated output dividers with jitter-free adjustable delay
Adjustable delay: 63 resolution steps of ½ period of VCO
output divider
Output-to-output skew: <50 ps
Duty cycle correction for odd divider settings
Automatic synchronization of all outputs on power-up
Absolute output jitter: <150 fs at 122.88 MHz
Integration range: 12 kHz to 20 MHz
Broadband timing jitter: 124 fs
Digital lock detect
Nonvolatile EEPROM stores configuration settings
SPI- and I²C-compatible serial control port
Dual PLL architecture
PLL1
Low bandwidth for reference input clock cleanup with
external VCXO
Phase detector rate up to 130 MHz
Redundant reference inputs
Automatic and manual reference switchover modes
Revertive and nonrevertive switching
Loss of reference detection with holdover mode
Low noise LVCMOS output from VCXO used for RF/IF
synthesizers
PLL2
Phase detector rate up to 259 MHz
Integrated low noise VCO
APPLICATIONS
LTE and multicarrier GSM base stations
Wireless and broadband infrastructure
Medical instrumentation
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
Low jitter, low phase noise clock distribution
Clock generation and translation for SONET, 10Ge, 10G FC,
and other 10 Gbps protocols
Forward error correction (G.710)
High performance wireless transceivers
ATE and high performance instrumentation
Rev. C
OSC_IN, OSC_IN
OUT0,
OUT0
AD9523-1
REFA,
REFA
REFB,
REFB
PLL1
PLL2
DIVIDE-BY3, 4, 5
OUT3,
OUT3
8 OUTPUTS
REF_TEST
OUT10,
OUT10
OUT13,
OUT13
SCLK/SCL
SDIO/SDA
SDO
OUT4,
OUT4
CONTROL
INTERFACE
(SPI AND I 2C)
DIVIDE-BY3, 4, 5
6 OUTPUTS
OUT9,
OUT9
ZERO
DELAY
14-CLOCK
DISTRIBUTION
EEPROM
ZD_IN, ZD_IN
09278-001
Data Sheet
Low Jitter Clock Generator with
14 LVPECL/LVDS/HSTL/29 LVCMOS Outputs
AD9523-1
Figure 1.
GENERAL DESCRIPTION
The AD9523-1 provides a low power, multi-output, clock
distribution function with low jitter performance, along with an
on-chip PLL and VCO with two VCO dividers. The on-chip VCO
tunes from 2.94 GHz to 3.1 GHz.
The AD9523-1 is designed to support the clock requirements
for long term evolution (LTE) and multicarrier GSM base
station designs. It relies on an external VCXO to provide the
reference jitter cleanup to achieve the restrictive low phase noise
requirements necessary for acceptable data converter SNR
performance.
The input receivers, oscillator, and zero delay receiver provide
both single-ended and differential operation. When connected
to a recovered system reference clock and a VCXO, the device
generates 14 low noise outputs with a range of 1 MHz to 1 GHz,
and one dedicated buffered output from the input PLL (PLL1).
The frequency and phase of one clock output relative to another
clock output can be varied by means of a divider phase select
function that serves as a jitter-free, coarse timing adjustment
in increments that are equal to half the period of the signal
coming out of the VCO.
An in-package EEPROM can be programmed through the serial
interface to store user-defined register settings for power-up
and chip reset.
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AD9523-1
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 22
Applications ....................................................................................... 1
Detailed Block Diagram ............................................................ 22
Functional Block Diagram .............................................................. 1
Overview ..................................................................................... 22
General Description ......................................................................... 1
Component Blocks—Input PLL (PLL1).................................. 23
Revision History ............................................................................... 3
Component Blocks—Output PLL (PLL2) .............................. 24
Specifications..................................................................................... 4
Clock Distribution ..................................................................... 26
Conditions ..................................................................................... 4
Zero Delay Operation ................................................................ 28
Supply Current .............................................................................. 4
Lock Detect ................................................................................. 28
Power Dissipation ......................................................................... 6
Reset Modes ................................................................................ 28
REFA, REFA, REFB, REFB, OSC_IN, OSC_IN, and ZD_IN,
ZD_IN Input Characteristics ...................................................... 7
Power-Down Mode .................................................................... 29
OSC_CTRL Output Characteristics .......................................... 7
Serial Control Port ......................................................................... 30
REF_TEST Input Characteristics ............................................... 7
SPI/I²C Port Selection................................................................ 30
PLL1 Output Characteristics ...................................................... 8
I²C Serial Port Operation .......................................................... 30
OUT0, OUT0 to OUT13, OUT13 Distribution Output
Characteristics .............................................................................. 8
SPI Serial Port Operation .......................................................... 33
Timing Alignment Characteristics ............................................ 9
Jitter and Noise Characteristics ................................................ 10
PLL2 Characteristics .................................................................. 10
Logic Input Pins—PD, SYNC, RESET, EEPROM_SEL,
REF_SEL ...................................................................................... 10
Status Output Pins—STATUS1, STATUS0 ............................. 11
Serial Control Port—SPI Mode ................................................ 11
Serial Control Port—I²C Mode ................................................ 12
Absolute Maximum Ratings .......................................................... 13
Thermal Resistance .................................................................... 13
ESD Caution ................................................................................ 13
Pin Configuration and Function Descriptions ........................... 14
Typical Performance Characteristics ........................................... 17
Input/Output Termination Recommendations .......................... 20
Terminology .................................................................................... 21
Power Supply Sequencing ......................................................... 29
SPI Instruction Word (16 Bits) ................................................. 34
SPI MSB/LSB First Transfers .................................................... 34
EEPROM Operations ..................................................................... 37
Writing to the EEPROM ........................................................... 37
Reading from the EEPROM ..................................................... 37
Programming the EEPROM Buffer Segment ......................... 38
Device Initialization Flowcharts ................................................... 40
Power Dissipation and Thermal Considerations ....................... 43
Clock Speed and Driver Mode ................................................. 43
Evaluation of Operating Conditions........................................ 43
Thermally Enhanced Package Mounting Guidelines ............ 44
Control Registers ............................................................................ 45
Control Register Map ................................................................ 45
Control Register Map Bit Descriptions ................................... 50
Outline Dimensions ....................................................................... 63
Ordering Guide .......................................................................... 63
Rev. C | Page 2 of 63
Data Sheet
AD9523-1
REVISION HISTORY
9/15—Rev. B to Rev. C
Changes to Features Section ............................................................ 1
Added Junction Temperature, TJ Parameter, Table 1 ................... 4
Changes to Table 7 ............................................................................ 8
Changes to Table 11 ........................................................................10
Changes to Figure 23 ......................................................................20
Changes to Overview Section ........................................................22
Added OSC_IN Input Section .......................................................23
Changes to PLL1 Loop Filter Section ...........................................23
Changed VCXO to OSC_IN, VCO Calibration Section ............25
Changes to Clock Distribution Synchronization Section ..........27
Changes to Zero Delay Operation Section ..................................28
Added Lock Detect Section and Reset Modes Section ..............28
Added Power-Down Mode Section and Power Supply
Sequencing Section .........................................................................29
Changes to Read Section ................................................................33
Changes to Writing to the EEPROM Section ..............................37
Changes to Reading from the EEPROM Section and
Programming the EEPROM Buffer Segment Section ................38
Added Device Initialization Flowcharts Section, Figure 46, and
Figure 47; Renumbered Sequentially ............................................40
Changes to Power Dissipation and Thermal Considerations
Section and Evaluation of Operating Conditions Section .........43
Changes to Example 2 Section.......................................................44
Changes to Table 39 ........................................................................51
Changes to Table 46 ........................................................................54
Updated Outline Dimensions ........................................................63
3/11—Rev. A to Rev. B
Added Table Summary, Table 8 ....................................................... 7
Changes to Figure 24 ...................................................................... 21
Changes to EEPROM Operations Section and Writing to the
EEPROM Section ............................................................................ 35
Changes to Addr (Hex) 0x01A, Bits[4:3], Table 30 .................... 40
Changes to Bits[4:3], Table 40 ....................................................... 47
12/10—Rev. 0 to Rev. A
Changes to General Description Section ....................................... 1
Changes to Frequency Range, Table 11 .......................................... 9
Changes to PLL2 General Description Section ........................... 23
Changes to Table 47, Address 0x0F3, Bit 1 .................................. 48
10/10—Revision 0: Initial Version
Rev. C | Page 3 of 63
AD9523-1
Data Sheet
SPECIFICATIONS
fVCXO = 122.88 MHz single-ended, REFA and REFB on differential at 30.72 MHz, fVCO = 2949.12 MHz, doubler is on, unless otherwise noted.
Typical is given for VDD = 3.3 V ± 5%, and TA = 25°C, unless otherwise noted. Minimum and maximum values are given over the full VDD and
TA (−40°C to +85°C) variation, as listed in Table 1.
CONDITIONS
Table 1.
Parameter
SUPPLY VOLTAGE
VDD3_PLL, Supply Voltage for PLL1 and PLL2
VDD3_VCO, Supply Voltage for VCO
VDD3_REF, Supply Voltage Clock Output Drivers Reference
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
VDD1.8_OUT[x:y],1 Supply Voltage Clock Dividers
AMBIENT TEMPERATURE RANGE, TA
JUNCTION TEMPERATURE, TJ
1
Min
Typ
Max
Unit
Test Conditions/Comments
3.135
3.135
3.135
3.135
1.768
−40
3.3
3.3
3.3
3.3
1.8
+25
3.465
3.465
3.465
3.465
1.832
+85
+115
V
V
V
V
V
°C
°C
3.3 V ± 5%
3.3 V ± 5%
3.3 V ± 5%
3.3 V ± 5%
1.8 V ± 5%
x and y are the pair of differential outputs that share the same power supply. For example, VDD3_OUT[0:1] is Supply Voltage Clock Output OUT0, OUT0 (Pin 68 and Pin 67,
respectively) and Supply Voltage Clock Output OUT1, OUT1 (Pin 65 and Pin 64, respectively).
SUPPLY CURRENT
Table 2.
Parameter
SUPPLIES OTHER THAN CLOCK OUTPUT DRIVERS
VDD3_PLL, Supply Voltage for PLL1 and PLL2
VDD3_VCO, Supply Voltage for VCO and VCO Divider M1
VDD3_REF, Supply Voltage Clock Output Drivers Reference
VCO Divider M1 Enabled
LVPECL Mode, LVDS Mode
Typ
Max
Unit
Test Conditions/Comments
37
70
41.9
75.8
mA
mA
Decreases by 9 mA typical if REFB is turned off
All outputs use VCO Divider M1
4
5.1
mA
HSTL Mode, CMOS Mode
3
3.6
mA
Use VCO Divider M1; only one output driver
is turned on; for each additional output that
is turned on, the current increments by 1.2 mA
maximum
Use VCO Divider M1; values are independent
of the number of outputs turned on
VCO Divider M2 Enabled
LVPECL Mode, LVDS Mode
26
30.1
mA
24.5
28.6
mA
3.2
6.4
5.8
12
mA
mA
11.5
40
13.2
45
mA
mA
f = 122.88 MHz
f = 983.04 MHz
6.5
23
7.5
26.3
mA
mA
f = 122.88 MHz
f = 983.04 MHz
13
41
14.4
46.5
mA
mA
f = 122.88 MHz
f = 983.04 MHz
HSTL Mode, CMOS Mode
VDD1.8_OUT[x:y],1 Supply Voltage Clock Dividers
VDD1.8_OUT[x:y],1 Supply Voltage Clock Dividers
CLOCK OUTPUT DRIVERS—LOWER POWER MODE OFF
LVDS Mode, 7 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
LVDS Mode, 3.5 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
LVPECL Mode
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
Min
Rev. C | Page 4 of 63
Use VCO Divider M2; only one output driver
is turned on; for each additional output that
is turned on, the current increments by 1.2 mA
maximum
Use VCO Divider M2; values are independent
of the number of outputs turned on
Current for each divider: f = 122.88 MHz
Current for each divider: f = 983.04 MHz
Channel x control register, Bit 4 = 0
Data Sheet
Parameter
HSTL Mode, 16 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
HSTL Mode, 8 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
CMOS Mode (Single-Ended)
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
CLOCK OUTPUT DRIVERS—LOWER POWER MODE ON
LVDS Mode, 7 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
LVDS Mode, 3.5 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
LVPECL Mode
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
HSTL Mode, 16 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
HSTL Mode, 8 mA
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers
1
AD9523-1
Min
Typ
Max
Unit
Test Conditions/Comments
20
50
24.2
59.1
mA
mA
f = 122.88 MHz
f = 983.04 MHz
14
42.5
16.7
49
mA
mA
f = 122.88 MHz
f = 983.04 MHz
2
2.4
mA
f = 15.36 MHz, 10 pF Load
Channel x control register, Bit 4 = 1
10
27
10.8
29.8
mA
mA
f = 122.88 MHz
f = 983.04 MHz
6.5
23
7.5
26.3
mA
mA
f = 122.88 MHz
f = 983.04 MHz
11
28
12.4
31.2
mA
mA
f = 122.88 MHz
f = 983.04 MHz
20
50
24.3
59.1
mA
mA
f = 122.88 MHz
f = 983.04 MHz
11
27
12.7
31.8
mA
mA
f = 122.88 MHz
f = 983.04 MHz
x and y are the pair of differential outputs that share the same power supply. For example, VDD3_OUT[0:1] is Supply Voltage Clock Output OUT0, OUT0 (Pin 68 and Pin 67,
respectively) and Supply Voltage Clock Output OUT1, OUT1 (Pin 65 and Pin 64, respectively).
Rev. C | Page 5 of 63
AD9523-1
Data Sheet
POWER DISSIPATION
Table 3.
Parameter
POWER DISSIPATION
Typical Configuration
PD, Power-Down
INCREMENTAL POWER DISSIPATION
Base Typical Configuration
Switched to One Input,
Reference Single-Ended Mode
Switched to Two Inputs,
Reference Differential Mode
Switched to Two Inputs,
Reference Single-Ended Mode
VCO Divider M2
Output Distribution, Driver On
LVDS Mode
3.5 mA
7 mA
LVPECL Mode
HSTL Mode
8 mA
16 mA
CMOS Mode
Output Distribution, Driver On
LVDS Mode
3.5 mA
7 mA
LVPECL Mode
HSTL Mode
8 mA
16 mA
Min
Typ
Max
Unit
Test Conditions/Comments
Does not include power dissipated in termination resistors
Clock distribution outputs running as follows: 7 LVPECL at 122.88 MHz,
3 LVDS (3.5 mA) at 61.44 MHz, 3 LVDS (3.5 mA) at 245.76 MHz, 1 singleended CMOS 10 pF load at 122.88 MHz, 1 differential input reference
at 30.72 MHz; fVCXO = 122.88 MHz, fVCO = 2949.12 MHz, VCO Divider M1
at 3, and VCO Divider M2 is off; PLL2 BW = 530 kHz
PD pin pulled low, with typical configuration conditions
898
984.7
mW
74
98.2
mW
393
434.7
mW
−28.5
−8
mW
Absolute total power with clock distribution; 1 LVPECL output (OUT0)
running at 122.88 MHz; 1 differential input reference at 30.72 MHz;
fVCXO = 122.88 MHz, fVCO = 2949.12 MHz, VCO Divider M1 at 3; VCO
Divider M2 is off
Running at 30.72 MHz
26
44.6
mW
Running at 30.72 MHz
−27.5
−5.1
mW
Running at 30.72 MHz
76
88.3
mW
Incremental power increase VCO Divider M2 (OUT4) from base typical
Incremental power increase (OUT1) from base typical
29
88
43
141
46
144
34.8
105.6
50
164
51
159
mW
mW
mW
mW
mW
mW
Single 3.5 mA LVDS output at 122.88 MHz
Single 3.5 mA LVDS output at 983.04 MHz
Single 7 mA LVDS output at 122.88 MHz
Single 7 mA LVDS output at 983.04 MHz
Single LVPECL output at 122.88 MHz
Single LVPECL output at 983.04 MHz
44
143
48
153
6.6
9.9
9.9
51
165
55
176
7.9
11.9
11.9
mW
mW
mW
mW
mW
mW
mW
Single 8 mA HSTL output at 122.88 MHz
Single 8 mA HSTL output at 983.04 MHz
Single 16 mA HSTL output at 122.88 MHz
Single 16 mA HSTL output at 983.04 MHz
Single 3.3 V CMOS output at 15.36 MHz
Dual complementary 3.3 V CMOS output at 15.36 MHz
Dual in-phase 3.3 V CMOS output at 15.36 MHz
Lower power mode on, (Channel x control register, Bit 4 = 1)
28.5
88
37
98
40.5
100
33.6
105.6
42.9
113.7
46
110
mW
mW
mW
mW
mW
mW
Single 3.5 mA LVDS output at 122.88 MHz
Single 3.5 mA LVDS output at 983.04 MHz
Single 7 mA LVDS output at 122.88 MHz
Single 7 mA LVDS output at 983.04 MHz
Single LVPECL output at 122.88 MHz
Single LVPECL output at 983.04 MHz
34
94
48
153
39.1
108.1
55.2
176
mW
mW
mW
mW
Single 8 mA HSTL output at 122.88 MHz
Single 8 mA HSTL output at 983.04 MHz
Single 16 mA HSTL output at 122.88 MHz
Single 16 mA HSTL output at 983.04 MHz
Rev. C | Page 6 of 63
Data Sheet
AD9523-1
REFA, REFA, REFB, REFB, OSC_IN, OSC_IN, AND ZD_IN, ZD_IN INPUT CHARACTERISTICS
Table 4.
Parameter
DIFFERENTIAL MODE
Input Frequency Range
Input Slew Rate (OSC_IN)
Common-Mode Internally
Generated Input Voltage
Input Common-Mode Range
Differential Input Voltage,
Sensitivity Frequency < 250 MHz
Differential Input Voltage,
Sensitivity Frequency > 250 MHz
Min
Pulse Width Low
Pulse Width High
Max
Unit
400
MHz
V/µs
400
0.6
0.7
1.025
100
0.8
V
1.475
V
mV p-p
200
Differential Input Resistance
Differential Input Capacitance
Duty Cycle
Pulse Width Low
Pulse Width High
CMOS MODE, SINGLE-ENDED INPUT
Input Frequency Range
Input High Voltage
Input Low Voltage
Input Capacitance
Duty Cycle
Typ
mV p-p
4.8
1
Test Conditions/Comments
Minimum limit imposed for jitter
performance
For dc-coupled LVDS (maximum swing)
Capacitive coupling required; can
accommodate single-ended input
by ac grounding of unused input;
instantaneous voltage on either pin
must not exceed the 1.8 V dc supply rails
Capacitive coupling required; can
accommodate single-ended input
by ac grounding of unused input;
instantaneous voltage on either pin
must not exceed the 1.8 V dc supply rails
kΩ
pF
Duty cycle limits are set by pulse width
high and pulse width low
1
1
ns
ns
250
2.0
0.8
1
MHz
V
V
pF
Duty cycle limits are set by pulse width
high and pulse width low
1.6
1.6
ns
ns
OSC_CTRL OUTPUT CHARACTERISTICS
Table 5.
Parameter
OUTPUT VOLTAGE
High
Low
Min
Typ
Max
Unit
Test Conditions/Comments
V
mV
RLOAD > 20 kΩ
150
Max
Unit
Test Conditions/Comments
250
MHz
V
V
VDD3_PLL − 0.15
REF_TEST INPUT CHARACTERISTICS
Table 6.
Parameter
REF_TEST INPUT
Input Frequency Range
Input High Voltage
Input Low Voltage
Min
Typ
2.0
0.8
Rev. C | Page 7 of 63
AD9523-1
Data Sheet
PLL1 OUTPUT CHARACTERISTICS
Table 7.
Parameter1
MAXIMUM OUTPUT FREQUENCY
Rise Time/Fall Time (20% to 80%)
Duty Cycle
OUTPUT VOLTAGE HIGH
Min
45
Typ
250
387
50
Max
665
55
VDD3_PLL − 0.25
VDD3_PLL − 0.1
Unit
MHz
ps
%
V
V
OUTPUT VOLTAGE LOW
0.2
0.1
V
V
MAXIMUM PFD FREQUENCY
Antibacklash Pulse Width
15 pF load
f = 250 MHz
Output driver static
Load current = 10 mA
Load current = 1 mA
Output driver static
Load current = 10 mA
Load current = 1 mA
High is the initial PLL1 antibacklash pulse
width setting. The user must program
Register 0x019[4] = 1b to enable SPI
control of the antibacklash pulse width to
the setting defined in Register 0x019[3:2]
and Table 39.
Minimum
Low
High
Maximum
1
Test Conditions/Comments
130
90
65
45
MHz
MHz
MHz
MHz
CMOS driver strength: strong (see Table 52).
OUT0, OUT0 TO OUT13, OUT13 DISTRIBUTION OUTPUT CHARACTERISTICS
Duty cycle performance is specified with the invert divider bit set to 1, and the divider phase bits set to 0.5. (For example, for Channel 0,
0x190[7] = 1 and 0x192[7:2] = 1.)
Table 8.
Parameter
LVPECL MODE
Maximum Output Frequency
Rise Time/Fall Time (20% to 80%)
Duty Cycle
Differential Output Voltage Swing
Common-Mode Output Voltage
SCALED HSTL MODE, 16 mA
Maximum Output Frequency
Rise Time/Fall Time (20% to 80%)
Duty Cycle
Differential Output Voltage Swing
Supply Sensitivity
Common-Mode Output Voltage
Min
Typ
Max
Unit
Test Conditions/Comments
47
43
40
643
1
117
50
48
49
775
147
52
52
54
924
GHz
ps
%
%
%
mV
VDD – 1.5
VDD − 1.4
VDD − 1.25
V
Minimum VCO/maximum dividers
100 Ω termination across output pair
f < 500 MHz
f = 500 MHz to 800 MHz
f = 800 MHz to 1 GHz
Magnitude of voltage across pins; output
driver static
Output driver static
1
112
50
48
49
1.6
0.6
141
52
51
54
1.7
VDD − 1.6
VDD − 1.42
47
44
40
1.3
VDD − 1.76
Rev. C | Page 8 of 63
GHz
ps
%
%
%
mV
mV/
mV
V
Minimum VCO/maximum dividers
100 Ω termination across output pair
f < 500 MHz
f = 500 MHz to 800 MHz
f = 800 MHz to 1 GHz
Nominal supply
Change in output swing vs.
VDD3_OUT[x:y] (ΔVOD/ΔVDD3)
Data Sheet
Parameter
LVDS MODE, 3.5 mA
Maximum Output Frequency
Rise Time/Fall Time (20% to 80%)
Duty Cycle
Differential Output Voltage Swing
Balanced
AD9523-1
Min
Typ
Max
Unit
Test Conditions/Comments
48
43
41
1
138
51
49
49
161
53
53
55
GHz
ps
%
%
%
100 Ω termination across output pair
f < 500 MHz
f = 500 MHz to 800 MHz
f = 800 MHz to 1 GHz
454
mV
50
mV
1.375
50
V
mV
3.5
24
mA
250
387
50
665
55
MHz
ps
%
247
Unbalanced
Common-Mode Output Voltage
Common-Mode Difference
Short-Circuit Output Current
CMOS MODE
Maximum Output Frequency
Rise Time/Fall Time (20% to 80%)
Duty Cycle
Output Voltage High
1.125
45
VDD − 0.25
VDD − 0.1
V
V
Output Voltage Low
Voltage swing between output pins;
output driver static
Absolute difference between voltage
swing of normal pin and inverted pin
Output driver static
Voltage difference between output pins;
output driver static
Output driver static
15 pF load
f = 250 MHz
Output driver static
Load current = 10 mA
Load current = 1 mA
Output driver static
Load current = 10 mA
Load current = 1 mA
0.2
0.1
V
V
Typ
Max
Unit
30
183
ps
100
50
300
ps
Single-ended, true phase, high-Z mode
63
Steps
ps
Resolution step; for example, 8 × 0.5/1 GHz
½ period of 1 GHz
500
ps
PLL1 settings: PFD = 7.68 MHz, ICP = 63.5 µA,
RZERO = 10 kΩ, antibacklash pulse width is
at maximum, BW = 40 Hz, REFA and
ZD_IN are set to differential mode
TIMING ALIGNMENT CHARACTERISTICS
Table 9.
Parameter
OUTPUT TIMING SKEW
Between Outputs in Same Group1
LVPECL, HSTL, and LVDS
Between LVPECL, HSTL, and
LVDS Outputs
CMOS
Between CMOS Outputs
Mean Delta Between Groups1
Adjustable Delay
Resolution Step
Zero Delay
Between Input Clock Edge on
REFA or REFB to ZD_IN Input
Clock Edge, External Zero
Delay Mode
1
Min
0
500
150
Test Conditions/Comments
Delay off on all outputs; maximum
deviation between rising edges of outputs;
all outputs are on, unless otherwise noted
There are three groups of outputs. They are as follows: the top outputs group, consisting of OUT0, OUT1, OUT2, and OUT3; the right outputs group, consisting of
OUT4, OUT5, OUT6, OUT7, OUT8, and OUT9; and the bottom outputs group, consisting of OUT10, OUT11, OUT12, and OUT13.
Rev. C | Page 9 of 63
AD9523-1
Data Sheet
JITTER AND NOISE CHARACTERISTICS
Table 10.
Parameter
OUTPUT ABSOLUTE RMS TIME JITTER
Min
Typ
Max
Unit
Test Conditions/Comments
Application example based on a typical setup (see Table 3);
f = 122.88 MHz
fs
fs
fs
fs
fs
fs
Integrated BW = 200 kHz to 5 MHz
Integrated BW = 200 kHz to 10 MHz
Integrated BW = 12 kHz to 20 MHz
Integrated BW = 10 kHz to 61 MHz
Integrated BW = 1 kHz to 61 MHz
Integrated BW = 1 MHz to 61 MHz
Max
Unit
Test Conditions/Comments
3100
MHz
MHz/V
dBc/Hz
LVPECL Mode, HSTL Mode, LVDS Mode
109
115
150
177
187
124
PLL2 CHARACTERISTICS
Table 11.
Parameter
VCO (ON CHIP)
Frequency Range
Gain
PLL2 FIGURE OF MERIT (FOM)
MAXIMUM PFD FREQUENCY
Antibacklash Pulse Width
Min
Typ
2940
45
−226
High is the initial PLL2 antibacklash pulse width setting.
The user must program Register 0x019[4] = 1b to enable SPI
control of the antibacklash pulse width to the setting defined
in Register 0x00F2[3:2] and Table 46.
Minimum
Low
High
Maximum
259
200
135
80
MHz
MHz
MHz
MHz
LOGIC INPUT PINS—PD, SYNC, RESET, EEPROM_SEL, REF_SEL
Table 12.
Parameter
VOLTAGE
Input High
Input Low
INPUT LOW CURRENT
CAPACITANCE
RESET TIMING
Pulse Width Low
Inactive to Start of Register
Programming
SYNC TIMING
Pulse Width Low
Min
Typ
Max
Unit
±80
0.8
±250
V
V
µA
2.0
3
Test Conditions/Comments
The minus sign indicates that, due to the internal pull-up
resistor, current is flowing out of the AD9523-1
pF
50
100
ns
ns
1.5
ns
High speed clock is the CLK input signal
Rev. C | Page 10 of 63
Data Sheet
AD9523-1
STATUS OUTPUT PINS—STATUS1, STATUS0
Table 13.
Parameter
VOLTAGE
Output High
Output Low
Min
Typ
Max
Unit
0.4
V
V
Max
Unit
2.94
Test Conditions/Comments
SERIAL CONTROL PORT—SPI MODE
Table 14.
Parameter
CS (INPUT)
Voltage
Input Logic 1
Input Logic 0
Current
Input Logic 1
Input Logic 0
Min
Input Capacitance
SCLK (INPUT) IN SPI MODE
Voltage
Input Logic 1
Input Logic 0
Current
Input Logic 1
Input Logic 0
Input Capacitance
SDIO (WHEN INPUT IS IN BIDIRECTIONAL MODE)
Voltage
Input Logic 1
Input Logic 0
Current
Input Logic 1
Input Logic 0
Input Capacitance
SDIO, SDO (OUTPUTS)
Output Logic 1 Voltage
Output Logic 0 Voltage
TIMING
Clock Rate (SCLK, 1/tSCLK)
Pulse Width High, tHIGH
Pulse Width Low, tLOW
SDIO to SCLK Setup, tDS
SCLK to SDIO Hold, tDH
SCLK to Valid SDIO and SDO, tDV
CS to SCLK Setup, tS
CS to SCLK Setup and Hold, tS, tC
CS Minimum Pulse Width High, tPWH
Typ
2.0
0.8
V
V
30
−110
µA
µA
2
pF
Test Conditions/Comments
CS has an internal 40 kΩ pull-up resistor
The minus sign indicates that, due to the
internal pull-up resistor, current is flowing out
of the AD9523-1
SCLK has an internal 40 kΩ pull-down resistor
in SPI mode but not in I2C mode
2.0
0.8
V
V
240
1
2
µA
µA
pF
2.0
0.8
V
V
1
1
2
µA
µA
pF
2.7
0.4
25
8
12
3.3
0
14
10
0
6
Rev. C | Page 11 of 63
V
V
MHz
ns
ns
ns
ns
ns
ns
ns
ns
AD9523-1
Data Sheet
SERIAL CONTROL PORT—I²C MODE
VDD = VDD3_REF, unless otherwise noted.
Table 15.
Parameter
SDA, SCL (WHEN INPUTTING DATA)
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Current with an Input Voltage Between
0.1 × VDD and 0.9 × VDD
Hysteresis of Schmitt Trigger Inputs
Pulse Width of Spikes That Must Be
Suppressed by the Input Filter, tSPIKE
SDA (WHEN OUTPUTTING DATA)
Output Logic 0 Voltage at 3 mA Sink Current
Output Fall Time from VIHMIN to VILMAX with
a Bus Capacitance from 10 pF to 400 pF
TIMING
Clock Rate (SCL, fI2C)
Bus Free Time Between a Stop and Start
Condition, tIDLE
Setup Time for a Repeated Start Condition,
tSET; STR
Hold Time (Repeated) Start Condition, tHLD; STR
Setup Time for a Stop Condition, tSET; STP
Low Period of the SCL Clock, tLOW
High Period of the SCL Clock, tHIGH
SCL, SDA Rise Time, tRISE
SCL, SDA Fall Time, tFALL
Data Setup Time, tSET; DAT
Data Hold Time, tHLD; DAT
Capacitive Load for Each Bus Line, CB1
1
2
Min
Typ
Max
Unit
0.3 × VDD
+10
V
V
µA
50
V
ns
0.4
250
V
ns
0.7 × VDD
−10
0.015 × VDD
20 + 0.1 CB1
Test Conditions/Comments
Note that all I2C timing values are referred to
VIHMIN (0.3 × VDD) and VILMAX levels (0.7 × VDD)
1.3
400
kHz
µs
0.6
µs
0.6
µs
0.6
1.3
0.6
20 + 0.1 CB1
20 + 0.1 CB1
100
100
880
µs
µs
µs
ns
ns
ns
ns
400
pF
300
300
After this period, the first clock pulse is
generated
This is a minor deviation from the original I²C
specification of 0 ns minimum2
CB is the capacitance of one bus line in picofarads (pF).
According to the original I2C specification, an I2C master must also provide a minimum hold time of 300 ns for the SDA signal to bridge the undefined region of the SCL
falling edge.
Rev. C | Page 12 of 63
Data Sheet
AD9523-1
ABSOLUTE MAXIMUM RATINGS
Table 16.
Parameter
VDD3_PLL, VDD3_REF, VDD3_OUT[x:y],
LDO_VCO to GND
REFA, REFA, REFB, REFB to GND
SCLK/SCL, SDIO/SDA, SDO, CS to GND
OUT0, OUT0, OUT1, OUT1, OUT2, OUT2,
OUT3, OUT3, OUT4, OUT4, OUT5, OUT5,
OUT6, OUT6, OUT7, OUT7, OUT8, OUT8,
OUT9, OUT9, OUT10, OUT10, OUT11,
OUT11, OUT12, OUT12, OUT13, OUT13
to GND
SYNC, RESET, PD, REF_SEL to GND
STATUS0, STATUS1 to GND
SP0, SP1, EEPROM_SEL to GND
VDD1.8_OUT[x:y], LDO_PLL1, LDO_DIV_M1
to GND
Junction Temperature1
Storage Temperature Range
Lead Temperature (10 sec)
1
Rating
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to +3.6 V
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 17. Thermal Resistance
Package Type
72-Lead LFCSP,
10 mm ×
10 mm
Airflow
Velocity
(m/sec)
0
1.0
2.5
θJA1, 2
21.3
20.1
18.1
θJC1, 3
1.7
θJB1, 4
12.6
ΨJT1, 2
0.1
0.2
0.3
Unit
°C/W
°C/W
°C/W
Per JEDEC 51-7, plus JEDEC 51-5 2S2P test board.
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
Per MIL-Std 883, Method 1012.1.
4
Per JEDEC JESD51-8 (still air).
1
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to +3.6 V
2V
2
115°C
−65°C to +150°C
300°C
ESD CAUTION
3
Additional power dissipation information can be found in the
Power Dissipation and Thermal Considerations section.
See Table 17 for θJA.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. C | Page 13 of 63
AD9523-1
Data Sheet
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
PLL1_OUT
ZD_IN
ZD_IN
VDD1.8_OUT[0:1]
OUT0
OUT0
VDD3_OUT[0:1]
OUT1
OUT1
VDD1.8_OUT[2:3]
OUT2
OUT2
VDD3_OUT[2:3]
OUT3
OUT3
EEPROM_SEL
STATUS0/SP0
STATUS1/SP1
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
PIN 1
INDICATOR
AD9523-1
TOP VIEW
(Not to Scale)
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
VDD1.8_OUT[4:5]
OUT4
OUT4
VDD3_OUT[4:5]
OUT5
OUT5
VDD1.8_OUT[6:7]
OUT6
OUT6
VDD3_OUT[6:7]
OUT7
OUT7
VDD1.8_OUT[8:9]
OUT8
OUT8
VDD3_OUT[8:9]
OUT9
OUT9
NOTES
1. THE EXPOSED PADDLE IS THE GROUND CONNECTION ON THE CHIP. IT MUST BE SOLDERED
TO THE ANALOG GROUND OF THE PCB TO ENSURE PROPER FUNCTIONALITY
AND HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS.
09278-002
RESET
CS
SCLK/SCL
SDIO/SDA
SDO
REF_TEST
OUT13
OUT13
VDD3_OUT[12:13]
OUT12
OUT12
VDD1.8_OUT[12:13]
OUT11
OUT11
VDD3_OUT[10:11]
OUT10
OUT10
VDD1.8_OUT[10:11]
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
LDO_PLL1
VDD3_PLL
REFA
REFA
REFB
REFB
LF1_EXT_CAP
OSC_CTRL
OSC_IN
OSC_IN
LF2_EXT_CAP
LDO_VCO
VDD3_VCO
LDO_DIV_M1
PD
REF_SEL
SYNC
VDD3_REF
Figure 2. Pin Configuration
Table 18. Pin Function Descriptions
Pin
No.
1
Mnemonic
LDO_PLL1
Type1
P/O
2
3
VDD3_PLL
REFA
P
I
4
REFA
I
5
REFB
I
6
REFB
I
7
8
9
LF1_EXT_CAP
OSC_CTRL
OSC_IN
O
O
I
10
OSC_IN
I
Description
1.8 V Internal LDO Regulator Decoupling Pin for PLL1. Connect a 0.47 μF decoupling capacitor from
this pin to ground. Note that for best performance, the LDO bypass capacitor must be placed in close
proximity to the device.
3.3 V Supply PLL1 and PLL2. Use the same supply as VCXO.
Reference Clock Input A. Along with REFA, this pin is the differential input for the PLL reference.
Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.
Complementary Reference Clock Input A. Along with REFA, this pin is the differential input for the
PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3V CMOS input.
Reference Clock Input B. Along with REFB, this pin is the differential input for the PLL reference.
Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.
Complementary Reference Clock Input B. Along with REFB, this pin is the differential input for the PLL
reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.
PLL1 External Loop Filter Capacitor. Connect this pin to ground.
Oscillator Control Voltage. Connect this pin to the voltage control pin of the external oscillator.
PLL1 Oscillator Input. Along with OSC_IN, this pin is the differential input for the PLL reference.
Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.
Complementary PLL1 Oscillator Input. Along with OSC_IN, this pin is the differential input for the PLL
reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.
Rev. C | Page 14 of 63
Data Sheet
AD9523-1
Pin
No.
11
12
Mnemonic
LF2_EXT_CAP
LDO_VCO
Type1
O
P/O
13
14
VDD3_VCO
LDO_DIV_M1
P
P/O
15
16
17
PD
REF_SEL
SYNC
I
I
I
18
19
VDD3_REF
RESET
P
I
20
21
CS
SCLK/SCL
I
I
22
23
SDIO/SDA
SDO
I/O
O
24
25
REF_TEST
OUT13
I
O
26
OUT13
O
27
28
VDD3_OUT[12:13]
OUT12
P
O
29
OUT12
O
30
31
VDD1.8_OUT[12:13]
OUT11
P
O
32
OUT11
O
33
34
VDD3_OUT[10:11]
OUT10
P
O
35
OUT10
O
36
37
VDD1.8_OUT[10:11]
OUT9
P
O
38
OUT9
O
39
40
VDD3_OUT[8:9]
OUT8
P
O
41
OUT8
O
42
43
VDD1.8_OUT[8:9]
OUT7
P
O
44
OUT7
O
Description
PLL2 External Loop Filter Capacitor Connection. Connect capacitor to this pin and the LDO_VCO pin.
2.5 V LDO Internal Regulator Decoupling Pin for VCO. Connect a 0.47 μF decoupling capacitor from
this pin to ground. Note that, for best performance, the LDO bypass capacitor must be placed in close
proximity to the device.
3.3 V Supply for VCO and VCO M1 Divider.
1.8 V LDO Regulator Decoupling Pin for VCO Divider M1. Connect a 0.47 μF decoupling capacitor
from this pin to ground. Note that, for best performance, the LDO bypass capacitor must be placed
in close proximity to the device.
Chip Power-Down, Active Low. This pin has an internal 40 kΩ pull-up resistor.
Reference Input Select. This pin has an internal 40 kΩ pull-down resistor.
Manual Synchronization. This pin initiates a manual synchronization and has an internal 40 kΩ pullup resistor.
3.3 V Supply for Output Clock Drivers Reference and VCO Divider M2.
Digital Input, Active Low. Resets internal logic to default states. This pin has an internal 40 kΩ pull-up
resistor.
Serial Control Port Chip Select, Active Low. This pin has an internal 40 kΩ pull-up resistor.
Serial Control Port Clock Signal for SPI Mode (SCLK) or I2C Mode (SCL). Data clock for serial programming. This pin has an internal 40 kΩ pull-down resistor in SPI mode but is high impedance in I²C mode.
Serial Control Port Bidirectional Serial Data In/Data Out for SPI Mode (SDIO) or I²C Mode (SDA).
Serial Data Output. Use this pin to read data in 4-wire mode (high impedance in 3-wire mode). There
is no internal pull-up/pull-down resistor on this pin.
Test Input to PLL1 Phase Detector.
Complementary Square Wave Clocking Output 13. This pin can be configured as one side of
a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
Square Wave Clocking Output 13. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
3.3 V Supply for Output 12 and Output 13 Clock Drivers.
Complementary Square Wave Clocking Output 12. This pin can be configured as one side of
a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
Square Wave Clocking Output 12. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
1.8 V Supply for Output 12 and Output 13 Clock Dividers.
Complementary Square Wave Clocking Output 11. This pin can be configured as one side of
a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
Square Wave Clocking Output 11. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
3.3 V Supply for Output 10 and Output 11 Clock Drivers.
Complementary Square Wave Clocking Output 10. This pin can be configured as one side of
a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
Square Wave Clocking Output 10. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
1.8 V Supply for Output 10 and Output 11 Clock Dividers.
Complementary Square Wave Clocking Output 9. This pin can be configured as one side of
a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
Square Wave Clocking Output 9. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
3.3 V Supply for Output 8 and Output 9 Clock Drivers.
Complementary Square Wave Clocking Output 8. This pin can be configured as one side of
a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
Square Wave Clocking Output 8. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
1.8 V Supply for Output 8 and Output 9 Clock Dividers.
Complementary Square Wave Clocking Output 7. This pin can be configured as one side of
a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
Square Wave Clocking Output 7. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
Rev. C | Page 15 of 63
AD9523-1
Data Sheet
Pin
No.
45
46
Mnemonic
VDD3_OUT[6:7]
OUT6
Type1
P
O
47
OUT6
O
48
49
VDD1.8_OUT[6:7]
OUT5
P
O
50
OUT5
O
51
52
VDD3_OUT[4:5]
OUT4
P
O
53
OUT4
O
54
55
VDD1.8_OUT[4:5]
STATUS1/SP1
P
I/O
56
STATUS0/SP0
I/O
57
EEPROM_SEL
I
58
OUT3
O
59
OUT3
O
60
61
VDD3_OUT[2:3]
OUT2
P
O
62
OUT2
O
63
64
VDD1.8_OUT[2:3]
OUT1
P
O
65
OUT1
O
66
67
VDD3_OUT[0:1]
OUT0
P
O
68
OUT0
O
69
70
VDD1.8_OUT[0:1]
ZD_IN
P
I
71
ZD_IN
I
72
PLL1_OUT
O
EP
EP, GND
GND
1
Description
3.3 V Supply for Output 6 and Supply Output 7 Clock Drivers.
Complementary Square Wave Clocking Output 6. This pin can be configured as one side of
a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
Square Wave Clocking Output 6. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
1.8 V Supply for Output 6 and Output 7 Clock Dividers.
Complementary Square Wave Clocking Output 5. This pin can be configured as one side of
a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
Square Wave Clocking Output 5. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
3.3 V Supply for Output 4 and Output 5 Clock Drivers.
Complementary Square Wave Clocking Output 4. This pin can be configured as one side of
a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
Square Wave Clocking Output 4. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
1.8 V Supply for Output 4 and Output 5 Clock Dividers.
Lock Detect and Other Status Signals (STATUS1)/I2C Address (SP1). This pin has an internal 40 kΩ pulldown resistor.
Lock Detect and Other Status Signals (STATUS0)/I2C Address (SP0). This pin has an internal 40 kΩ pulldown resistor.
EEPROM Select. Setting this pin high selects the register values stored in the internal EEPROM to be
loaded at reset and/or power-up. Setting this pin low causes the AD9523-1 to load the hard-coded
default register values at power-up/reset. This pin has an internal 40 kΩ pull-down resistor.
Complementary Square Wave Clocking Output 3. This pin can be configured as one side of
a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
Square Wave Clocking Output 3. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
3.3 V Supply for Output 2 and Output 3 Clock Drivers.
Complementary Square Wave Clocking Output 2. This pin can be configured as one side of
a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
Square Wave Clocking Output 2. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
1.8 V Supply for Output 2 and Output 3 Clock Dividers.
Complementary Square Wave Clocking Output 1. This pin can be configured as one side of
a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
Square Wave Clocking Output 1. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
3.3 V Supply for Output 0 and Output 1 Clock Drivers.
Complementary Square Wave Clocking Output 0. This pin can be configured as one side of
a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output.
Square Wave Clocking Output 0. This pin can be configured as one side of a differential LVPECL/
LVDS/HSTL output or as a single-ended CMOS output.
1.8 V Supply for Output 0 and Output 1 Clock Dividers.
External Zero Delay Clock Input. Along with ZD_IN, this pin is the differential input for the PLL
reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.
Complementary External Zero Delay Clock Input. Along with ZD_IN, this pin is the differential input
for the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.
Single-Ended CMOS Output from PLL1. This pin has settings for weak and strong in Register 0x1BA,
Bit 4 (see Table 52).
Exposed Paddle. The exposed paddle is the ground connection on the chip. It must be soldered
to the analog ground of the PCB to ensure proper functionality and heat dissipation, noise, and
mechanical strength benefits.
P = power, I = input, O = output, I/O = input/output, P/O = power/output, GND = ground.
Rev. C | Page 16 of 63
Data Sheet
AD9523-1
TYPICAL PERFORMANCE CHARACTERISTICS
fVCXO = 122.88 MHz, REFA differential at 30.72 MHz, fVCO = 2949.12 MHz, and doubler is off, unless otherwise noted.
45
60
40
50
35
40
CURRENT (mA)
CURRENT (mA)
HSTL = 16mA
30
HSTL = 8mA
20
30
25
20
15
10
10
200
400
600
800
1000
1200
FREQUENCY (MHz)
0
09278-003
0
Figure 3. VDD3_OUT[x:y] Current (Typical) vs. Frequency;
HSTL Mode at 16 mA and 8 mA
0
200
400
600
800
FREQUENCY (MHz)
1000
1200
09278-005
5
0
Figure 5. VDD3_OUT[x:y] Current (Typical) vs. Frequency, LVPECL Mode
45
35
40
20pF
30
25
LVDS = 7mA
CURRENT (mA)
30
25
20
15
LVDS = 3.5mA
10pF
2pF
20
15
10
10
5
0
0
200
400
600
800
1000
FREQUENCY (MHz)
1200
Figure 4. VDD3_OUT[x:y] Current (Typical) vs. Frequency;
LVDS Mode at 7 mA and 3.5 mA
0
0
100
200
300
400
500
FREQUENCY (MHz)
Figure 6. VDD3_OUT[x:y] Current (Typical) vs. Frequency;
CMOS Mode at 20 pF, 10 pF, and 2 pF Load
Rev. C | Page 17 of 63
600
09278-006
5
09278-004
CURRENT (mA)
35
AD9523-1
Data Sheet
3.5
4.0
3.0
3.5
HSTL = 16mA
3.0
2.5
10pF
AMPLITUDE (V)
2.0
HSTL = 8mA
1.5
2.5
20pF
2.0
1.5
1.0
1.0
0.5
0.5
0
0
200
400
600
800
1000
1200
FREQUENCY (MHz)
09278-007
0
0
100
200
300
400
500
600
FREQUENCY (MHz)
Figure 7. Differential Voltage Swing vs. Frequency;
HSTL Mode at 16 mA and 8 mA
09278-010
DIFFERENTIAL SWING (V p-p)
2pF
Figure 10. Amplitude vs. Frequency and Capacitive Load;
CMOS Mode at 2 pF, 10 pF, and 20 pF Load
1.6
DIFFERENTIAL SWING (V p-p)
1.4
1.2
1.0
1
0.8
0.6
0.4
0
200
400
600
800
1000
1200
FREQUENCY (MHz)
09278-008
0
CH1 200mV
2.5ns/DIV
40.0GS/s
A CH1
104mV
09278-013
0.2
Figure 11. Output Waveform (Differential), LVPECL at 122.88 MHz
Figure 8. Differential Voltage Swing vs. Frequency, LVPECL Mode
1.4
LVDS = 7mA
1.0
0.8
LVDS = 3.5mA
0.6
1
0.4
0.2
0
200
400
600
800
1000
FREQUENCY (MHz)
Figure 9. Differential Voltage Swing vs. Frequency;
LVDS Mode at 7 mA and 3.5 mA
1200
CH1 500mV Ω
2.5ns/DIV
40.0GS/s
A CH1
80mV
Figure 12. Output Waveform (Differential), HSTL at 16 mA, 122.88 MHz
Rev. C | Page 18 of 63
09278-049
0
09278-009
DIFFERENTIAL SWING (V p-p)
1.2
Data Sheet
AD9523-1
–90
–100
–110
–120
1
–130
2
–140
7
3
–150
4
NOISE:
ANALYSIS RANGE x: START 10kHz TO STOP 40MHz
INTG NOISE: –78.1dBc/40MHz
RMS NOISE: 175.4µRAD
10.0mdeg
RMS JITTER: 151.4fsec
RESIDUAL FM: 2.1kHz
–160
–170
–180
100
1k
10k
100k
FREQUENCY (Hz)
1M
–120
2
–140
7
3
–150
4
–170
NOISE:
ANALYSIS RANGE x: START 10kHz TO STOP 40MHz
INTG NOISE: –81.0dBc/40MHz
RMS NOISE: 126.6µRAD
7.3mdeg
RMS JITTER: 164.0fsec
RESIDUAL FM: 1.7kHz
–180
100
Figure 13. Phase Noise, Output = 184.32 MHz
(VCXO = 122.88 MHz, Crystek VCXO CVHD-950); Doubler On
1k
10k
100k
FREQUENCY (Hz)
1M
5
6
10M
Figure 15. Phase Noise, Output = 122.88 MHz
(VCXO = 122.88 MHz, Crystek VCXO CVHD-950); Doubler On
–80
–80
–100
–110
–120
1
–130
2
3
–140
7
–160
–170
–180
100
NOISE:
ANALYSIS RANGE x: START 10kHz
TO STOP 40MHz
INTG NOISE: –73.1dBc/40MHz
RMS NOISE: 312.0µRAD
17.9mdeg
RMS JITTER: 269.4fsec
RESIDUAL FM: 2.0kHz
1k
10k
100k
FREQUENCY (Hz)
–120
1
–130
2
–150
NOISE:
ANALYSIS RANGE x: START 10kHz
TO STOP 40MHz
INTG NOISE: –76.3dBc/40MHz
RMS NOISE: 217.0µRAD
12.4mdeg
RMS JITTER: 281.1fsec
RESIDUAL FM: 1.6kHz
6
–170
1M
10M
3
–140
–160
5
1kHz, –122.0Bc/Hz
10kHz, –130.7dBc/Hz
100kHz, –129.3dBc/Hz
1MHz, –154.9dBc/Hz
10MHz, –161.5dBc/Hz
40MHz, –162.1dBc/Hz
800kHz, –152.7dBc/Hz
–110
4
09278-012
–150
1:
2:
3:
4:
5:
6:
7:
–90
–180
100
Figure 14. Phase Noise, Output = 184.32 MHz
(VCXO = 122.88 MHz, Crystek VCXO CVHD-950); Doubler On;
Optimized for Low 800 kHz Offset Noise
1k
10k
100k
FREQUENCY (Hz)
7
4
5
1M
10M
Figure 16. Phase Noise, Output = 122.88 MHz
(VCXO = 122.88 MHz, Crystek VCXO CVHD-950); Doubler On;
Optimized for Low 800 kHz Offset Noise
Rev. C | Page 19 of 63
6
09278-015
–100
1kHz, –118.3dBc/Hz
10kHz, –127.5dBc/Hz
100kHz, –126.0dBc/Hz
1MHz, –151.8dBc/Hz
10MHz, –159.6dBc/Hz
40MHz, –160.3dBc/Hz
800kHz, –149.5dBc/Hz
PHASE NOISE (dBc/Hz)
1:
2:
3:
4:
5:
6:
7:
–90
PHASE NOISE (dBc/Hz)
1
–130
6
10M
1kHz, –123.1dBc/Hz
10kHz, –133.8dBc/Hz
100kHz, –140.5dBc/Hz
1MHz, –149.0Bc/Hz
10MHz, –161.5dBc/Hz
40MHz, –162.1dBc/Hz
800kHz, –146.9dBc/Hz
–110
–160
5
1:
2:
3:
4:
5:
6:
7:
–90
09278-113
PHASE NOISE (dBc/Hz)
–100
–80
1kHz, –120.0dBc/Hz
10kHz, –130.6dBc/Hz
100kHz, –137.4dBc/Hz
1MHz, –145.7dBc/Hz
10MHz, –159.6dBc/Hz
40MHz, –160.3dBc/Hz
800kHz, –143.7dBc/Hz
09278-014
1:
2:
3:
4:
5:
6:
7:
PHASE NOISE (dBc/Hz)
–80
AD9523-1
Data Sheet
INPUT/OUTPUT TERMINATION RECOMMENDATIONS
100Ω
HIGH
IMPEDANCE DOWNSTREAM
DEVICE
INPUT
HSTL
OUTPUT
0.1µF
100Ω
HIGH
IMPEDANCE DOWNSTREAM
DEVICE
INPUT
0.1µF
Figure 17. AC-Coupled LVDS Output Driver
Figure 21. AC-Coupled HSTL Output Driver
AD9523-1
AD9523-1
100Ω
HIGH
IMPEDANCE DOWNSTREAM
DEVICE
INPUT
HSTL
OUTPUT
100Ω
HIGH
IMPEDANCE DOWNSTREAM
DEVICE
INPUT
09278-047
09278-143
LVDS
OUTPUT
0.1µF
09278-046
LVDS
OUTPUT
AD9523-1
0.1µF
09278-142
AD9523-1
Figure 18. DC-Coupled LVDS Output Driver
100Ω
0.1µF
HIGH
IMPEDANCE DOWNSTREAM
DEVICE
INPUT
0.1µF
AD9523-1
SELF BIASED
REF, OSC_IN,
ZERO DELAY
INPUTS
100Ω
(OPTIONAL1)
0.1µF
1RESISTOR
VALUE DEPENDS UPON
REQUIRED TERMINATION OF SOURCE.
Figure 19. AC-Coupled LVPECL Output Driver
Figure 23. REF, OSC_IN, and Zero Delay Input Differential Mode
AD9523-1
100Ω
HIGH
IMPEDANCE DOWNSTREAM
DEVICE
INPUT
09278-045
LVPECLCOMPATIBLE
OUTPUT
09278-048
LVPECLCOMPATIBLE
OUTPUT
0.1µF
09278-044
AD9523-1
Figure 22. DC-Coupled HSTL Output Driver
Figure 20. DC-Coupled LVPECL Output Driver
Rev. C | Page 20 of 63
Data Sheet
AD9523-1
TERMINOLOGY
Phase Jitter and Phase Noise
An ideal sine wave can be thought of as having a continuous
and even progression of phase with time from 0° to 360° for
each cycle. Actual signals, however, display a certain amount
of variation from ideal phase progression over time. This
phenomenon is called phase jitter. Although many causes can
contribute to phase jitter, one major cause is random noise,
which is characterized statistically as being Gaussian (normal)
in distribution.
This phase jitter leads to a spreading out of the energy of the
sine wave in the frequency domain, producing a continuous
power spectrum. This power spectrum is usually reported as
a series of values whose units are dBc/Hz at a given offset in
frequency from the sine wave (carrier). The value is a ratio
(expressed in decibels) of the power contained within a 1 Hz
bandwidth with respect to the power at the carrier frequency.
For each measurement, the offset from the carrier frequency is
also given.
It is meaningful to integrate the total power contained within
some interval of offset frequencies (for example, 10 kHz to
10 MHz). This is called the integrated phase noise over that
frequency offset interval and can be readily related to the time
jitter due to the phase noise within that offset frequency interval.
Phase noise has a detrimental effect on the performance of ADCs,
DACs, and RF mixers. It lowers the achievable dynamic range of
the converters and mixers, although they are affected in somewhat
different ways.
Time Jitter
Phase noise is a frequency domain phenomenon. In the time
domain, the same effect is exhibited as time jitter. When observing
a sine wave, the time of successive zero crossings varies. In a square
wave, the time jitter is a displacement of the edges from their
ideal (regular) times of occurrence. In both cases, the variations in
timing from the ideal are the time jitter. Because these variations
are random in nature, the time jitter is specified in seconds root
mean square (rms) or 1 sigma of the Gaussian distribution.
Time jitter that occurs on a sampling clock for a DAC or an
ADC decreases the signal-to-noise ratio (SNR) and dynamic
range of the converter. A sampling clock with the lowest possible
jitter provides the highest performance from a given converter.
Additive Phase Noise
Additive phase noise is the amount of phase noise that is
attributable to the device or subsystem being measured.
The phase noise of any external oscillators or clock sources is
subtracted. This makes it possible to predict the degree to which
the device impacts the total system phase noise when used in
conjunction with the various oscillators and clock sources, each
of which contributes its own phase noise to the total. In many
cases, the phase noise of one element dominates the system
phase noise. When there are multiple contributors to phase
noise, the total is the square root of the sum of squares of the
individual contributors.
Additive Time Jitter
Additive time jitter is the amount of time jitter that is attributable to
the device or subsystem being measured. The time jitter of any
external oscillators or clock sources is subtracted. This makes
it possible to predict the degree to which the device impacts the
total system time jitter when used in conjunction with the various
oscillators and clock sources, each of which contributes its own
time jitter to the total. In many cases, the time jitter of the external
oscillators and clock sources dominates the system time jitter.
Rev. C | Page 21 of 63
AD9523-1
Data Sheet
THEORY OF OPERATION
DETAILED BLOCK DIAGRAM
VCXO
LDO_PLL1
LF1_EXT_CAP
OSC_CTRL
OSC_IN
PLL1_OUT
STATUS0/ STATUS1/
SP0
SP1 LF2_EXT_CAP
LDO_VCO
VDD1.8_OUT[x:y]
STATUS MONITOR
LOCK DETECT/
SERIAL PORT
ADDRESS
÷D1
REFA
÷R1
REF_SEL
REFB
REFB
REF_TEST
÷R1
SWITCHOVER
CONTROL
FANOUT
LOOP
FILTER
P
F
D
CHARGE
PUMP
÷R2
×2
P
F
D
CHARGE
PUMP
LOOP
FILTER
FANOUT
VCO
÷N1
÷N2
PLL2
SDIO/SDA
SDO
SCLK/SCL
CS
RESET
PD
EEPROM_SEL
∆t
EDGE
SELECT
OUT13
OUT13
÷D
∆t
EDGE
SELECT
OUT12
OUT12
÷D
∆t
EDGE
SELECT
OUT11
OUT11
÷D
∆t
EDGE
SELECT
OUT10
OUT10
÷D
∆t
EDGE
SELECT
OUT9
OUT9
÷D
∆t
EDGE
SELECT
OUT8
OUT8
÷D
∆t
EDGE
SELECT
OUT7
OUT7
÷D
∆t
EDGE
SELECT
OUT6
OUT6
÷D
∆t
EDGE
SELECT
OUT5
OUT5
÷D
∆t
EDGE
SELECT
OUT4
÷D
∆t
EDGE
SELECT
OUT3
OUT3
÷D
∆t
EDGE
SELECT
OUT2
OUT2
÷D
∆t
EDGE
SELECT
OUT1
OUT1
÷D
∆t
EDGE
SELECT
OUT0
OUT0
M2
÷R1
PLL1
÷D
M1
LOCK
DETECT
(TEST PATH)
REFA
LOCK
DETECT
CONTROL
INTERFACE
(SDI AND I2C)
VDD3_OUT[x:y]
OUT4
EEPROM
ZD_IN
ZD_IN
AD9523-1
LDO_DIV_MI
VDD3_VCO
SYNC
09278-020
VDD3_PLL
Figure 24. Top Level Diagram
OVERVIEW
The AD9523-1 is a clock generator that employs integer-N-based
phase-locked loops (PLL). The device architecture consists of two
cascaded PLL stages. The first stage, PLL1, consists of an integer
division PLL that uses an external voltage-controlled crystal
oscillator (VCXO) from 15 MHz to 250 MHz. PLL1 has a narrowloop bandwidth that provides initial jitter cleanup of the input
reference signal. The second stage, PLL2, is a frequency
multiplying PLL that translates the first stage output frequency
to a range of 2.94 GHz to 2.96 GHz. PLL2 incorporates an
integer-based feedback divider that enables integer frequency
multiplication. Programmable integer dividers (1 to 1024) follow
PLL2, establishing a final output frequency of 1 GHz or less.
The AD9523-1 includes reference signal processing blocks that
enable a smooth switching transition between two reference inputs.
This circuitry automatically detects the presence of the reference
input signals. If only one input is present, the device uses it as
the active reference. If both are present, one becomes the active
reference and the other becomes the backup reference. If the active
reference fails, the circuitry automatically switches to the backup
reference (if available), making it the new active reference.
A register setting determines what action to take if the failed
reference is once again available: either stay on Reference B or
revert to Reference A. If neither reference is usable, the AD9523-1
supports a holdover mode. A reference select pin (REF_SEL,
Pin 16) is available to manually select which input reference is
active (see Table 42). The accuracy of the holdover is dependent
on the external VCXO frequency stability at half supply voltage.
Any of the divider settings are programmable via the serial
programming port, enabling a wide range of input/output
frequency ratios under program control. The dividers also
include a programmable delay to adjust timing of the output
signals, if required.
The 14 outputs are compatible with LVPECL, LVDS, HSTL, and
3.3 V CMOS logic levels (see the Input/Output Termination
Recommendations section. All differential output logic settings
require a single 100 Ω differential termination.
The loop filters of each PLL are integrated and programmable.
Only a single external capacitor for each of the two PLL loop
filters is required.
The AD9523-1 operates over the extended industrial temperature
range of −40°C to +85°C.
Rev. C | Page 22 of 63
Data Sheet
AD9523-1
COMPONENT BLOCKS—INPUT PLL (PLL1)
PLL1 General Description
Fundamentally, the input PLL (referred to as PLL1) consists of
a phase-frequency detector (PFD), charge pump, passive loop filter,
and an external VCXO operating in a closed loop (see Figure 26).
PLL1 has the flexibility to operate with a loop bandwidth of
approximately 10 Hz to 100 Hz. This relatively narrow loop
bandwidth gives the AD9523-1 the ability to suppress jitter that
appears on the input references (REFA and REFB). The output
of PLL1 then becomes a low jitter phase-locked version of the
reference input system clock.
the external capacitor depends on the use of an external VCXO
and the configuration parameters, such as input clock rate and
desired bandwidth. Normally, a 0.3 µF capacitor allows the loop
bandwidth to range from 10 Hz to 100 Hz and ensures loop
stability over the intended operating parameters of the device (see
Table 43 for RZERO values). The operating loop bandwidth (LBW)
of PLL1 can be used as a metric to estimate the time required for
the PLL to phase lock. In general, PLL1 is phase locked within
10 loop bandwidth time constants, τLBW, where τLBW = 1/LBW.
Therefore, PLL_TO (see Figure 46) equals 10 × τLBW.
LF1_EXT_CAP
PLL1 Reference Clock Inputs
LDO_PLL1
AD9523-1
The AD9523-1 features two separate differential reference clock
inputs, REFA and REFB. These inputs can be configured to
operate in full differential mode or single-ended CMOS mode.
To operate either the REFA input or the REFB input in 3.3 V
CMOS mode, the user must set Bit 5 or Bit 6, respectively, in
Register 0x01A (see Table 40). The single-ended inputs can be
driven by either a dc-coupled CMOS level signal or an ac-coupled
sine wave or square wave.
The differential reference input receiver is powered down when
the differential reference input is not selected, or when the PLL
is powered down. The single-ended buffers power down when
the PLL is powered down, when their respective individual
power-down registers are set, or when the differential receiver is
selected.
The REFB R divider uses the same value as the REFA R divider
unless Bit 7, the enable REFB R divider independent division
control bit in Register 0x01C, is programmed as shown in
Table 42.
CPOLE1
CPOLE2
OSC_CTRL
CHARGE
PUMP
RPOLE2
1kΩ
BUFFER
0.3µF
09278-022
In differential mode, these pins are internally self biased. If
REFA or REFB is driven single-ended, the unused side (REFA,
REFB) should be decoupled via a suitable capacitor to a quiet
ground. Figure 23 shows the equivalent circuit of REFA or REFB.
It is possible to dc couple to these inputs, but the dc operation
point should be set as specified in the Specifications tables.
RZERO
Figure 25. PLL1 Loop Filter
Table 19. PLL1 Loop Filter Programmable Values
RZERO
(kΩ)
883
677
341
135
10
External
1
CPOLE1
(nF)
1.5 fixed
RPOLE2
(kΩ)
165 fixed
CPOLE2
(nF)
0.337 fixed
LF1_EXT_CAP1
(µF)
0.3
External loop filter capacitor.
An external R-C low-pass filter should be used at the OSC_CTRL
output. The values shown in Figure 25 add an additional lowpass pole at ~530 Hz. This R-C network filters the noise
associated with the OSC_CTRL buffer to achieve the best noise
performance at the 1 kHz offset region.
LF1_EXT_CAP
OSC_IN Input
The OSC_IN receiver is powered down when the PLL1 powerdown bit is set (Register 0x233[2] = 1b). When using the
AD9523-1 in a mode of operation that bypasses PLL1, the PLL1
power-down bit must be disabled (Register 0x233[2] = 0b).
REFA
REFA
DIVIDE-BY1, 2, ...1023
REFB
REFB
P
F
D
DIVIDE-BY1, 2, ...1023
3.3V CMOS
OR 1.8V
DIFFERENTIAL
REF_TEST
PLL1 Loop Filter
Rev. C | Page 23 of 63
CHARGE
PUMP
7 BITS,
0.5µA LSB
RPOLE2
CPOLE1
CPOLE2
1.8V LDO
OSC_CTRL
VCXO
DIVIDE-BY1, 2, ...1023
DIVIDE-BY1, 2, ...63
VDD3_PLL
The PLL1 loop filter requires the connection of an external
capacitor from LF1_EXT_CAP (Pin 7) to ground. The value of
RZERO
SWITCHOVER
CONTROL
REF_SEL
OSC_IN
AD9523-1
LDO_PLL1
Figure 26. Input PLL (PLL1) Block Diagram
09278-021
The OSC_IN receiver connects to the PLL1 feedback divider
and to the PLL2 PFD through an optional doubler. This input
receiver is identical to the PLL1 REFA and REFB receivers.
Control bits for this receiver are located in Register 0x01A[1:0].
Figure 23 shows the recommended differential input
termination to the OSC_IN receiver.
AD9523-1
Data Sheet
PLL1 Input Dividers
the charge pump tristates. The device continues operating in this
mode until a reference signal becomes available. Then the device
exits holdover mode, and PLL1 resynchronizes with the active
reference. In addition to tristate, the charge pump can be forced
to VCC/2 during holdover (Register 0x01C, Bit 6; see Table 42).
Each reference input feeds a dedicated reference divider block.
The input dividers provide division of the reference frequency
in integer steps from 1 to 1023. They provide the bulk of the
frequency prescaling that is necessary to reduce the reference
frequency to accommodate the bandwidth that is typically
desired for PLL1.
COMPONENT BLOCKS—OUTPUT PLL (PLL2)
PLL2 General Description
PLL1 Reference Switchover
The output PLL (referred to as PLL2) consists of an optional
input reference doubler, reference divider, phase-frequency
detector (PFD), a partially integrated analog loop filter (see
Figure 27), an integrated voltage-controlled oscillator (VCO),
and a feedback divider. The VCO produces a nominal 3.0 GHz
signal with an output divider that is capable of division ratios of
3, 4, and 5.
The reference monitor verifies the presence/absence of the
prescaled REFA and REFB signals (that is, after division by the
input dividers). The status of the reference monitor guides the
activity of the switchover control logic. The AD9523-1 supports
automatic and manual PLL reference clock switching between
REFA (the REFA and REFA pins) and REFB (the REFB and
REFB pins). This feature supports networking and infrastructure
applications that require redundant references.
The PFD of the output PLL drives a charge pump that increases,
decreases, or holds constant the charge stored on the loop filter
capacitors (both internal and external). The stored charge results
in a voltage that sets the output frequency of the VCO. The
feedback loop of the PLL causes the VCO control voltage to
vary in a way that phase locks the PFD input signals.
There are several configurable modes of reference switchover. The
manual switchover is achieved either via a programming register
setting or by using the REF_SEL pin. The automatic switchover
occurs when REFA disappears and there is a reference on REFB.
The gain of PLL2 is proportional to the current delivered by
the charge pump. The loop filter bandwidth is chosen to reduce
noise contributions from PLL sources that could degrade phase
noise requirements.
The reference automatic switchover can be set to work as follows:
•
Nonrevertive: stay on REFB. Switch from REFA to REFB
when REFA disappears, but do not switch back to REFA
if it reappears. If REFB disappears, then go back to REFA.
Revert to REFA. Switch from REFA to REFB when REFA
disappears. Return to REFA from REFB when REFA returns.
The output PLL has a VCO with multiple bands spanning a range
of 2.94 GHz to 3.1 GHz. However, the actual operating frequency
within a particular band depends on the control voltage that
appears on the loop filter capacitor. The control voltage causes
the VCO output frequency to vary linearly within the selected
band. This frequency variability allows the control loop of the
output PLL to synchronize the VCO output signal with the
reference signal applied to the PFD. Typically, the device
automatically selects the appropriate band as part of its
calibration process (invoked via the VCO control register
at Address 0x0F3, shown in Table 47).
See Table 42 for the PLL1 miscellaneous control register bit settings.
PLL1 Holdover
In the absence of both input references, the device enters holdover mode. Holdover is a secondary function that is provided
by PLL1. Because PLL1 has an external VCXO available as a
frequency source, it continues to operate in the absence of the
input reference signals. When the device switches to holdover,
PLL1_OUT
VDD3_VCO
LDO_VCO
LF2_EXT_CAP
VDD3_PLL
LDO
PLL CORE
1.9V
LDO_DIV_M1
LDO
RZERO
DIVIDE-BY1, 2, 4, 8, 16
PLL_1.8V
CPOLE1
R2
DIVIDE-BY1, 2, 3...31
PFD
×2
AD9523-1
CHARGE PUMP
7 BITS, 3.5µA LSB
CPOLE2
RPOLE2
A/B
COUNTERS
DIVIDE-BY-4
PRESCALER
M1
DIVIDE-BY3, 4, 5,
M2
DIVIDE-BY3, 4, 5,
N DIVIDER
VDD3_REF
Figure 27. Output PLL (PLL2) Block Diagram
Rev. C | Page 24 of 63
TO DIST/
RESYNC
TO DIST/
RESYNC
09278-023
•
Data Sheet
AD9523-1
Input 2× Frequency Multiplier
VCO Divider M1 and VCO Divider M2
The 2× frequency multiplier provides the option to double the
frequency at the PLL2 input. This allows the user to take advantage
of a higher frequency at the input to the PLL (PFD) and, thus,
allows for reduced in-band phase noise and greater separation
between the frequency generated by the PLL and the modulation
spur associated with PFD. However, increased reference spur
separation results in harmonic spurs, introduced by the frequency
multiplier, that increase as the duty cycle deviates from 50% at the
OSC_IN inputs. As such, beneficial use of the frequency multiplier
is application-specific. Typically, a VCXO with proper interfacing
has a duty cycle that is approximately 50% at the OSC_IN inputs.
Note that the maximum output frequency of the 2× frequency
multipliers must not exceed the maximum PFD rate that is
specified in Table 11.
The VCO dividers provide frequency division between the internal
VCO and the clock distribution. Each VCO divider can be set to
divide by 3, 4, or 5. When the AD9523-1 is used without any
zero delay feedback (internal or external), the phase relationship
between the reference inputs and the outputs is a function of
the phase relationship between the OSC input and the reference
inputs. Because the VCO divider is not reset by SYNC, there is
an additional phase variability of up to x VCO periods, where
x = VCO divider setting.
PLL2 Feedback Divider
PLL2 has a feedback divider (N divider) that enables it to provide
integer frequency up-conversion. The PLL2 N divider is a combination of a prescaler (P) and two counters, A and B. The total
divider value is
N = (P × B) + A
where P = 4.
The feedback divider is a dual modulus prescaler architecture, with
a nonprogrammable P that is equal to 4. The value of the B counter
can be from 3 to 63, and the value of the A counter can be from 0 to 3.
However, due to the architecture of the divider, there are constraints,
as listed in Table 45.
PLL2 Loop Filter
The PLL2 loop filter requires the connection of an external
capacitor from LF2_EXT_CAP (Pin 11) to LDO_VCO (Pin 12),
as illustrated in Figure 27. The value of the external capacitor
depends on the operating mode and the desired phase noise
performance. For example, a loop bandwidth of approximately
500 kHz produces the lowest integrated jitter. A lower bandwidth
produces lower phase noise at 1 MHz but increases the total
integrated jitter.
Table 20. PLL2 Loop Filter Programmable Values
RZERO
(Ω)
3250
3000
2750
2500
2250
2100
2000
1850
1
CPOLE1
(pF)
48
40
32
24
16
8
0
RPOLE2
(Ω)
900
450
300
225
CPOLE2
(pF)
Fixed at 16
LF2_EXT_CAP1
(pF)
Typical at 1000
VCO Calibration
The AD9523-1 on-chip VCO must be manually calibrated to
ensure proper operation over process and temperature. This is
accomplished by setting the calibrate VCO bit (Register 0x0F3,
Bit 1) to 1. (This bit is not self clearing.) The setting can be
performed as part of the initial setup before executing the
IO_Update bit (Register 0x234, Bit 0 = 1). A readback bit, VCO
calibration in progress (Register 0x22D, Bit 0), indicates when
a VCO calibration is in progress by returning a logic true (that is,
Bit 0 = 1). If the EEPROM is in use, setting the calibrate VCO bit
to 1 before saving the register settings to the EEPROM ensures
that the VCO calibrates automatically after the EEPROM has
loaded. After calibration, it is recommended that a sync be initiated
(see the Clock Distribution Synchronization section).
Note that the calibrate VCO bit defaults to 0. This bit must
change from 0 to 1 to initiate a calibration sequence. Therefore,
any subsequent calibrations require the following sequence:
1.
2.
3.
4.
Register 0x0F3, Bit 1 (calibrate VCO bit) = 0
Register 0x234, Bit 0 (IO_Update bit) = 1
Register 0x0F3, Bit 1 (calibrate VCO bit) = 1
Register 0x234, Bit 0 (IO_Update bit) = 1
VCO calibration is controlled by a calibration controller that
runs off the OSC_IN input clock. The calibration requires that
PLL2 be set up properly to lock the PLL2 loop and that the
OSC_IN clock be present.
During power-up or reset, the distribution section is automatically
held in sync until the first VCO calibration is finished. Therefore,
no outputs can occur until VCO calibration is complete and PLL2
is locked.
Initiate a VCO calibration under the following conditions:
•
•
External loop filter capacitor.
Rev. C | Page 25 of 63
After changing any of the PLL2 B counter and A counter
settings or after a change in the PLL2 reference clock
frequency. This means that a VCO calibration should be
initiated any time that a PLL2 register or reference clock
changes such that a different VCO frequency is the result.
Whenever system calibration is desired. The VCO is designed
to operate properly over extremes of temperature even
when it is first calibrated at the opposite extreme. However,
a VCO calibration can be initiated at any time, if desired.
AD9523-1
Data Sheet
CLOCK DISTRIBUTION
The clock distribution block provides an integrated solution for
generating multiple clock outputs based on frequency dividing
the PLL2 VCO divider output. OUT4 to OUT9 can use either
VCO Divider M1 or VCO Divider M2, selectable via the register
settings. The distribution output consists of 14 channels (OUT0
to OUT13). Each of the output channels has a dedicated divider
and output driver, as shown in Figure 29. The AD9523-1 also has
the capability to route the VCXO output to four of the outputs
(OUT0 to OUT3).
If the output channel is ac-coupled to the circuit to be clocked,
changing the mode varies the voltage swing to determine sensitivity to the drive level. For example, in LVDS mode, a current of
3.5 mA causes a 350 mV peak voltage. Likewise, in LVPECL mode,
a current of 8 mA causes an 800 mV peak voltage at the 100 Ω load
resistor.
In addition to the four mode bits, each of the 14 Channel 0 to
Channel 13 control registers includes the following control bits:
•
Clock Dividers
The output clock distribution dividers are referred to as D0 to
D13, corresponding to output channels OUT0 through OUT13,
respectively. Each divider is programmable with 10 bits of division
depth that is equal to 1 to 1024. Dividers have duty cycle correction
to always give 50% duty cycle, even for odd divides.
Output Power-Down
Each of the output channels offers independent control of the
power-down functionality via the Channel 0 to Channel 13 control
registers (see Table 51). Each output channel has a dedicated
power-down bit for powering down the output driver. However,
if all 14 outputs are powered down, the entire distribution output
enters a deep sleep mode. Although each channel has a channel
power-down control signal, it may sometimes be desirable to
power down an output driver while maintaining the divider’s
synchronization with the other channel dividers. This is accomplished by placing the output in tristate mode (this works in
CMOS mode, as well).
•
•
•
•
•
•
Invert divider output. Enables the user to choose between
normal polarity and inverted polarity. Normal polarity is the
default state. Inverted polarity reverses the representation of
Logic 0 and Logic 1, regardless of the logic family.
Ignore sync. Makes the divider ignore the SYNC signal
from any source.
Power down channel. Powers down the entire channel.
Lower power mode.
Driver mode.
Channel divider.
Divider phase.
VDD3_OUT[x:y]
1.25V LVDS
VDD – 1.3V LVPECL
HSTL
50Ω ENABLED
CM
COMMON MODE
CIRCUIT
P
Multimode Output Drivers
N
CM
The user has independent control of the operating mode of each of
the fourteen output channels via the Channel 0 to Channel 13
control registers (see Table 51). The operating mode control
includes the following:
–
100Ω LOAD
N
P
Logic family and pin functionality
Output drive strength
Output polarity
The four least significant bits (LSBs) of each of the 14 Channel 0
to Channel 13 control registers comprise the driver mode bits. The
mode value selects the desired logic family and pin functionality
of an output channel, as listed in Table 51. This driver design
allows a common 100 Ω external resistor for all the different
driver modes of operation that are illustrated in Figure 28.
Rev. C | Page 26 of 63
3.5mA/8mA
LVDS/LVPECL
ENABLED
50Ω HSTL
ENABLED
09278-031
•
•
•
+
Figure 28. Multimode Driver
Data Sheet
AD9523-1
Clock Distribution Synchronization
other when PLL2 is ready. The dividers support programmable
phase offsets from 0 to 63 steps, in half periods of the input
clock (for example, the VCO divider output clock). The phase
offsets are incorporated into the dividers through a preset for the
first output clock period of each divider. Phase offsets are
supported only by programming the initial phase and divide
value and then issuing a sync to the distribution (automatically
at startup or manually, if desired).
A block diagram of the clock distribution synchronization
functionality is shown in Figure 29. The synchronization
sequence begins with the primary synchronization signal,
which ultimately results in delivery of a synchronization strobe
to the clock distribution logic.
As indicated, the primary synchronization signal originates
from one of the following sources:
An automatic synchronization of the divider is initiated the first
time that PLL2 locks after a power-up or reset event. Subsequent
lock/unlock events do not initiate a resynchronization of the
distribution dividers unless they are preceded by a power-down
or reset of the part.
In normal operation, the phase offsets are already programmed
through the EEPROM or the SPI/I2C port before the AD9523-1
starts to provide outputs. Although the user cannot adjust the
phase offsets while the dividers are operating, it is possible to
adjust the phase of all the outputs together without powering
down PLL1 and PLL2. This is accomplished by programming
the new phase offset, using Bits[7:2] in Register 0x192 (see
Table 51) and then issuing a divide sync signal by using the
SYNC pin or the sync dividers bit (Register 0x232, Bit 0).
Both sources of the primary synchronization signal are logic OR’d;
therefore, any one of them can synchronize the clock distribution
output at any time. When using the sync dividers bit, the user
first sets and then clears the bit. The synchronization event is the
clearing operation (that is, the Logic 1 to Logic 0 transition of
the bit). The dividers are all automatically synchronized to each
OUTx
DIVIDE
OUT
DIVIDER
PHASE
DRIVER
OUTx
SYNC
VCO OUTPUT DIVIDER
FAN OUT
SYNC (PIN 17)
SYNC
09278-025

When using the SYNC pin (Pin 17), there are 11 VCO divider
output pipe line delays plus one period of the clock from the
rising edge of SYNC to the clock output. There is at least one
extra VCO divider period of uncertainty because the SYNC
signal and the VCO divider output are asynchronous.
Direct synchronization source via the sync dividers bit
(see Table 55, Register 0x232, Bit 0)
Device pin, SYNC (Pin 17)
SYNC DIVIDERS BIT
Figure 29. Clock Distribution Synchronization Block Diagram
SYNC
VCO DIVIDER OUTPUT CLOCK
DIVIDE = 2, PHASE = 0
DIVIDE = 2, PHASE = 6
CONTROL
6 × 0.5 PERIODS
Figure 30. Clock Output Synchronization Timing Diagram
Rev. C | Page 27 of 63
09278-026

AD9523-1
Data Sheet
All outputs that are not programmed to ignore the sync are
disabled temporarily while the sync is active. Note that, if
an output is used for the zero delay path, it also disappears
momentarily. However, this is desirable because it ensures
that all the synchronized outputs have a deterministic phase
relationship with respect to the zero delay output and, therefore,
also with respect to the input.
ZERO DELAY OPERATION
Zero delay operation aligns the phase of the output clocks with
the phase of the external PLL reference input. The OUT0 output
is designed to be used as the output for zero delay. There are
two zero delay modes on the AD9523-1: internal and external
(see Figure 31). Note that the external delay mode provides
better matching than the internal delay mode because the
output drivers are included in the zero delay path.
Internal Zero Delay Mode
The internal zero delay function of the AD9523-1 is achieved
by feeding the output of Channel Divider 0 back to the PLL1
N divider. Bit 5 in Register 0x01B is used to select internal zero
delay mode (see Table 41). In the internal zero delay mode,
the output of Channel Divider 0 is routed back to the PLL1
(N divider) through a mux. PLL1 synchronizes the phase/edge
of the output of Channel Divider 0 with the phase/edge of the
reference input.
Because the channel dividers are synchronized to each other,
the outputs of the channel divider are synchronous with the
reference input.
External Zero Delay Mode
The external zero delay function of the AD9523-1 is achieved
by feeding OUT0 back to the ZD_IN input and, ultimately, back
to the PLL1 N divider. In Figure 31, the change in signal routing
for external zero delay is external to the AD9523-1.
ZD_IN
ZD_IN
OUT0
OUT0
Bit 5 in Register 0x01B is used to select the external zero delay
mode. In external zero delay mode, OUT0 must be routed back
to PLL1 (the N divider) through the ZD_IN and ZD_IN pins.
PLL1 synchronizes the phase/edge of the feedback output clock
with the phase/edge of the reference input. Because the channel
dividers are synchronized to each other, the clock outputs are
synchronous with the reference input. Both the reference path
delay and the feedback delay from ZD_IN are designed to have
the same propagation delay from the output drivers and PLL
components to minimize the phase offset between the clock
output and the reference input to achieve zero delay.
LOCK DETECT
The PLL1 and PLL2 lock detectors issue an unlock condition
when the frequency error is greater than the threshold of the
lock detector. When the PLL is unlocked, there is a random
phase between the reference clock and feedback clock. Due to
the random phase relationship that exists, the unlock condition
can take between 215 × TPFD cycles to 1 × TPFD cycles. A lock
condition always takes 216 × TPFD to lock, but can potentially
take 231 × TPFD cycles depending on how big the phase jump is
and when it occurs in relation to the lock detect restart.
RESET MODES
The AD9523-1 has a power-on reset (POR) and several other ways
to apply a reset condition to the chip.
Power-On Reset
During chip power-up, a power-on reset pulse is issued when
the 3.3 V supply reaches ~2.6 V (<2.8 V) and restores the chip
either to the setting stored in EEPROM (EEPROM pin = 1) or
to the on-chip setting (EEPROM pin = 0). At power-on, the
AD9523-1 executes a sync operation, which brings the outputs
into phase alignment according to the default settings. The
output drivers are held in sync for the duration of the internally
generated power-up sync timer (~70 ms). The outputs begin to
toggle after this period.
Reset via the RESET Pin
ENB
FEEDBACK
DELAY
INTERNAL FB
REFA
REFA
PFD
AD9523-1
09278-027
REF
DELAY
RESET, a reset (an asynchronous hard reset is executed by briefly
pulling RESET low), restores the chip either to the setting stored in
EEPROM (EEPROM pin = 1) or to the on-chip setting (EEPROM
pin = 0). A reset also executes a sync operation, which brings the
outputs into phase alignment according to the default settings.
When EEPROM is inactive (EEPROM pin = 0), it takes ~2 µs for
the outputs to begin toggling after RESET is issued. When
EEPROM is active (EEPROM pin = 1), it takes ~40 ms for the
outputs to toggle after RESET is brought high.
Figure 31. Zero Delay Function
Rev. C | Page 28 of 63
Data Sheet
AD9523-1
Reset via the Serial Port
POWER-DOWN MODE
The serial port control register allows for a reset by setting Bit 2
and Bit 5 in Register 0x000. When Bit 2 and Bit 5 are set, the chip
enters a reset mode and restores the chip either to the setting
stored in EEPROM (EEPROM pin = 1) or to the on-chip setting
(EEPROM pin = 0), except for Register 0x000. Except for the
self clearing bits, Bit 2 and Bit 5, Register 0x000 retains its
previous value prior to reset. During the internal reset, the
outputs hold static. Bit 2 and Bit 5 are self clearing. However,
the self clearing operation does not complete until an additional
serial port SCLK cycle completes, and the AD9523-1 is held in
reset until Bit 2 and Bit 5 self clear.
Chip Power-Down via PD
Reset to Settings in EEPROM when EEPROM Pin = 0 via the
Serial Port
The serial port control register allows the chip to be reset to settings
in EEPROM when the EEPROM pin = 0 via Register 0xB02[1].
This bit is self clearing. This bit does not have any effect when
the EEPROM pin = 1. It takes ~40 ms for the outputs to begin
toggling after the SOFT_EEPROM register is cleared.
Place the AD9523-1 into a power-down mode by pulling the
PD pin low. Power-down turns off most of the functions and
currents inside the AD9523-1. The chip remains in this powerdown state until PD is returned to a logic high state. When
taken out of power-down mode, the AD9523-1 returns to the
settings programmed into its registers prior to the power-down,
unless the registers are changed by new programming while the
PD pin is held low.
POWER SUPPLY SEQUENCING
The AD9523-1 has multiple power supply domains that operate
with 3.3 V, and the output supply domain that operates on 1.8 V.
The 1.8 V supplies should be brought high and stable prior to or
simultaneously with the 3.3 V supplies to ensure proper device
operation. It is recommended to hold the RESETpin low while
both supply domains settle to ensure that the 3.3 V supplies do
not lead the 1.8 V supplies.
Rev. C | Page 29 of 63
AD9523-1
Data Sheet
SERIAL CONTROL PORT
SPI/I²C PORT SELECTION
The AD9523-1 has two serial interfaces, SPI and I2C. Users can
select either the SPI or I2C, depending on the states (logic high,
logic low) of the two logic level input pins, SP1 and SP0, when
power is applied or after a RESET (each pin has an internal
40 kΩ pull-down resistor). When both SP1 and SP0 are low,
the SPI interface is active. Otherwise, I2C is active with three
different I2C slave address settings (seven bits wide), as shown
in Table 21. The five MSBs of the slave address are hardware
coded as 11000, and the two LSBs are determined by the logic
levels of the SP1 and SP0 pins.
I2C Bus Characteristics
Table 22. I2C Bus Definitions
Abbreviation
S
Sr
P
A
A
W
R
One pulse on the SCL clock line is generated for each data bit
that is transferred.
The data on the SDA line must not change during the high period
of the clock. The state of the data line can change only when the
clock on the SCL line is low.
DATA LINE
STABLE;
DATA VALID
SCL
Figure 32. Valid Bit Transfer
Address
SPI
I2C: 1100000
I2C: 1100001
I2C: 1100010
A start condition is a transition from high to low on the SDA
line while SCL is high. The start condition is always generated
by the master to initialize the data transfer.
A stop condition is a transition from low to high on the SDA
line while SCL is high. The stop condition is always generated
by the master to end the data transfer.
I²C SERIAL PORT OPERATION
The AD9523-1 I2C port is based on the I2C fast mode standard.
The AD9523-1 supports both I2C protocols: standard mode
(100 kHz) and fast mode (400 kHz).
The AD9523-1 I2C port has a 2-wire interface consisting of a serial
data line (SDA) and a serial clock line (SCL). In an I2C bus system,
the AD9523-1 is connected to the serial bus (data bus SDA and
clock bus SCL) as a slave device, meaning that no clock is generated
by the AD9523-1. The AD9523-1 uses direct 16-bit (two bytes)
memory addressing instead of traditional 8-bit (one byte) memory
addressing.
SDA
SCL
S
P
START
CONDITION
STOP
CONDITION
09278-161
SP0
Low
High
Low
High
CHANGE
OF DATA
ALLOWED
SDA
Table 21. Serial Port Mode Selection
SP1
Low
Low
High
High
Definition
Start
Repeated start
Stop
Acknowledge
No acknowledge
Write
Read
09278-160
The AD9523-1 serial control port is a flexible, synchronous
serial communications port that allows an easy interface with
many industry-standard microcontrollers and microprocessors.
The AD9523-1 serial control port is compatible with most
synchronous transfer formats, including Philips I2C, Motorola®
SPI, and Intel® SSR protocols. The AD9523-1 I2C implementation
deviates from the classic I2C specification in two specifications,
and these deviations are documented in Table 15 of this data
sheet. The serial control port allows read/write access to all
registers that configure the AD9523-1.
Figure 33. Start and Stop Conditions
A byte on the SDA line is always eight bits long. An acknowledge
bit must follow every byte. Bytes are sent MSB first.
Rev. C | Page 30 of 63
Data Sheet
AD9523-1
Data is then sent over the serial bus in the format of nine clock
pulses, one data byte (eight bits) from either master (write mode)
or slave (read mode), followed by an acknowledge bit from the
receiving device. The number of bytes that can be transmitted per
transfer is unrestricted. In write mode, the first two data bytes
immediately after the slave address byte are the internal memory
(control registers) address bytes with the high address byte first.
This addressing scheme gives a memory address of up to 216 − 1 =
65,535. The data bytes after these two memory address bytes are
register data written into the control registers. In read mode, the
data bytes after the slave address byte are register data read from
the control registers. A single I2C transfer can contain multiple data
bytes that can be read from or written to control registers whose
address is automatically incremented starting from the base
memory address.
The acknowledge bit is the ninth bit attached to any 8-bit data
byte (see Figure 34). An acknowledge bit is always generated by
the receiving device (receiver) to inform the transmitter that the
byte has been received. It is accomplished by pulling the SDA
line low during the ninth clock pulse after each 8-bit data byte.
The no acknowledge bit is the ninth bit attached to any 8-bit
data byte. A no acknowledge bit is always generated by the
receiving device (receiver) to inform the transmitter that the
byte has not been received. It is accomplished by leaving the SDA
line high during the ninth clock pulse after each 8-bit data byte.
Data Transfer Process
The master initiates data transfer by asserting a start condition.
This indicates that a data stream follows. All I2C slave devices
connected to the serial bus respond to the start condition.
The master then sends an 8-bit address byte over the SDA line,
consisting of a 7-bit slave address (MSB first), plus an R/W bit.
This bit determines the direction of the data transfer, that is,
whether data is written to or read from the slave device
(0 = write, 1 = read).
When all data bytes are read or written, stop conditions are
established. In write mode, the master (transmitter) asserts
a stop condition to end data transfer during the 10th clock pulse
following the acknowledge bit for the last data byte from the slave
device (receiver). In read mode, the master device (receiver)
receives the last data byte from the slave device (transmitter) but
does not pull it low during the ninth clock pulse. This is known as a
no acknowledge bit. Upon receiving the no acknowledge bit, the
slave device knows that the data transfer is finished and releases
the SDA line. The master then takes the data line low during the
low period before the 10th clock pulse and high during the 10th
clock pulse to assert a stop condition.
The peripheral whose address corresponds to the transmitted
address responds by sending an acknowledge bit. All other devices
on the bus remain idle while the selected device waits for data
to be read from or written to it. If the R/W bit is 0, the master
(transmitter) writes to the slave device (receiver). If the R/W bit is 1,
the master (receiver) reads from the slave device (transmitter).
The format for these commands is described in the Data
Transfer Format section.
MSB
ACKNOWLEDGE FROM
SLAVE-RECEIVER
1
SCL
2
3 TO 7
8
9
1
ACKNOWLEDGE FROM
SLAVE-RECEIVER
2
3 TO 7
8
9
S
10
P
09278-162
SDA
Figure 34. Acknowledge Bit
MSB = 0
1
SCL
2
3 TO 7
8
9
1
ACKNOWLEDGE FROM
SLAVE-RECEIVER
2
3 TO 7
8
9
S
10
P
09278-163
ACKNOWLEDGE FROM
SLAVE-RECEIVER
10
P
09278-164
SDA
Figure 35. Data Transfer Process (Master Write Mode, 2-Byte Transfer Used for Illustration)
MSB = 1
SDA
ACKNOWLEDGE FROM
MASTER-RECEIVER
1
SCL
2
3 TO 7
8
9
1
NO ACKNOWLEDGE
FROM
SLAVE-RECEIVER
2
3 TO 7
8
S
Figure 36. Data Transfer Process (Master Read Mode, 2-Byte Transfer Used for Illustration)
Rev. C | Page 31 of 63
9
AD9523-1
Data Sheet
follows a write to Register 0x234, thereby ending the I2C transfer.
For an I2C data read transfer containing multiple data bytes,
the peripheral drives data bytes of 0x00 for subsequent reads that
follow a read from Register 0x234.
A repeated start (Sr) condition can be used in place of a stop
condition. Furthermore, a start or stop condition can occur at
any time; partially transferred bytes are discarded.
For an I2C data write transfer containing multiple data bytes,
the peripheral drives a no acknowledge for the data byte that
Data Transfer Format
Send byte format. The send byte protocol is used to set up the register address for subsequent commands.
S
Slave Address
W
A
RAM Address High Byte
A
RAM Address Low Byte
A
P
A
P
A
P
A
P
Write byte format. The write byte protocol is used to write a register address to the RAM, starting from the specified RAM address.
S
Slave Address
W
A
RAM Address
High Byte
A
RAM Address
Low Byte
A
RAM
Data 0
RAM
Data 1
A
RAM
Data 2
A
Receive byte format. The receive byte protocol is used to read the data byte(s) from the RAM, starting from the current address.
S
Slave Address
R
A
RAM Data 0
A
RAM Data 1
A
RAM Data 2
Read byte format. The combined format of the send byte and the receive byte.
S
Slave
Address
W
A
RAM Address
High Byte
A
RAM Address
Low Byte
A
Sr
Slave
Address
R
A
RAM
Data 0
A
RAM
Data 1
A
RAM
Data 2
I²C Serial Port Timing
SDA
tSET; DAT
tFALL
tLOW
tFALL
tHLD; STR
tRISE
tSPIKE
tRISE
tIDLE
tHLD; STR
S
tHLD; DAT
tHIGH
tSET; STP
tSET; STR
Sr
Figure 37. I²C Serial Port Timing
Table 23. I2C Timing Definitions
Parameter
fI2C
tIDLE
tHLD; STR
tSET; STR
tSET; STP
tHLD; DAT
tSET; DAT
tLOW
tHIGH
tRISE
tFALL
tSPIKE
Description
I²C clock frequency
Bus idle time between stop and start conditions
Hold time for repeated start condition
Setup time for repeated start condition
Setup time for stop condition
Hold time for data
Setup time for data
Duration of SCL clock low
Duration of SCL clock high
SCL/SDA rise time
SCL/SDA fall time
Voltage spike pulse width that must be suppressed by the input filter
Rev. C | Page 32 of 63
P
S
09278-165
SCL
Data Sheet
AD9523-1
SPI SERIAL PORT OPERATION
Pin Descriptions
than eight SCLK cycles). Raising the CS pin on a nonbyte
boundary terminates the serial transfer and flushes the buffer.
SCLK (serial clock) is the serial shift clock. This pin is an input.
SCLK is used to synchronize serial control port reads and writes.
Write data bits are registered on the rising edge of this clock,
and read data bits are registered on the falling edge. This pin is
internally pulled down by a 40 kΩ resistor to ground.
In streaming mode (see Table 24), any number of data bytes can
be transferred in a continuous stream. The register address is
automatically incremented or decremented (see the SPI MSB/LSB
First Transfers section). CS must be raised at the end of the last
byte to be transferred, thereby ending streaming mode.
SDIO (serial data input/output) is a dual-purpose pin and acts
either as an input only (unidirectional mode) or as an input/
output (bidirectional mode). The AD9523-1 defaults to the
bidirectional I/O mode.
Communication Cycle—Instruction Plus Data
SDO (serial data out) is used only in the unidirectional I/O mode
as a separate output pin for reading back data. SDO is always
active; therefore, the unidirectional I/O mode should not be
used in a multislave environment.
CS (chip select bar) is an active low control that gates the read
and write cycles. When CS is high, SDIO is in a high impedance
state. This pin is internally pulled up by a 40 kΩ resistor to
VDD3_REF.
CS
SDIO/SDA
AD9523-1
SERIAL
CONTROL
PORT
SDO
09278-034
SCLK/SCL
Figure 38. Serial Control Port
SPI Mode Operation
In SPI mode, single or multiple byte transfers are supported,
as well as MSB first or LSB first transfer formats. The AD9523-1
serial control port can be configured for a single bidirectional
I/O pin (SDIO only) or for two unidirectional I/O pins (SDIO/
SDO). By default, the AD9523-1 is in bidirectional mode. Short
instruction mode (8-bit instructions) is not supported. Only
long (16-bit) instruction mode is supported.
A write or a read operation to the AD9523-1 is initiated by
pulling CS low.
The CS stalled high mode is supported in data transfers where
three or fewer bytes of data (plus instruction data) are transferred
(see Table 24). In this mode, the CS pin can temporarily return
high on any byte boundary, allowing time for the system controller
to process the next byte. CS can go high only on byte boundaries;
however, it can go high during either phase (instruction or data)
of the transfer.
During this period, the serial control port state machine enters
a wait state until all data is sent. If the system controller decides
to abort the transfer before all of the data is sent, the state machine
must be reset either by completing the remaining transfers or by
returning CS low for at least one complete SCLK cycle (but fewer
There are two parts to a communication cycle with the
AD9523-1. The first part writes a 16-bit instruction word into
the AD9523-1, coincident with the first 16 SCLK rising edges.
The instruction word provides the AD9523-1 serial control port
with information regarding the data transfer, which is the
second part of the communication cycle. The instruction word
defines whether the upcoming data transfer is a read or a write,
the number of bytes in the data transfer, and the starting
register address for the first byte of the data transfer.
Write
If the instruction word is for a write operation, the second part
is the transfer of data into the serial control port buffer of the
AD9523-1. Data bits are registered on the rising edge of SCLK.
The length of the transfer (one, two, or three bytes or streaming
mode) is indicated by two bits (W1, W0) in the instruction byte.
When the transfer is one, two, or three bytes but not streaming, CS
can be raised after each sequence of eight bits to stall the bus
(except after the last byte, where it ends the cycle). When the bus
is stalled, the serial transfer resumes when CS is lowered. Raising
the CS pin on a nonbyte boundary resets the serial control port.
During a write, streaming mode does not skip over reserved or
blank registers, and the user can write 0x00 to the reserved
register addresses.
Because data is written into a serial control port buffer area, and
not directly into the actual control registers of the AD9523-1, an
additional operation is needed to transfer the serial control port
buffer contents to the actual control registers of the AD9523-1,
thereby causing them to become active. The update registers
operation consists of setting the self clearing IO_Update bit,
Bit 0 of Register 0x234 (see Table 57). Any number of data bytes
can be changed before executing an update registers operation.
The update registers simultaneously actuates all register changes
that have been written to the buffer since any previous update.
Read
The AD9523-1 supports only the long instruction mode. If the
instruction word is for a read operation, the next N × 8 SCLK
cycles clock out the data from the address specified in the
instruction word, where N is 1 to 3 as determined by Bits[W1:W0].
If N = 4, the read operation is in streaming mode, continuing
until CS is raised. During an SPI read, serial data on SDIO (or
SDO, in 4-wire mode) transitions on the SCLK falling edge, and
is normally sampled on the SCLK rising edge. To read the last
bit correctly, the SPI host must be able to tolerate a zero hold
Rev. C | Page 33 of 63
AD9523-1
Data Sheet
time. In cases where zero hold time is not possible, the user can
either use streaming mode and delay the rising edge of CS, or
sample the serial data on the SCLK falling edge. However, to
sample the data correctly on the SCLK falling edge, the user must
ensure that the setup time is greater than tDV (time data valid).
Streaming mode does not skip over reserved or blank registers.
SPI MSB/LSB FIRST TRANSFERS
The default mode of the AD9523-1 serial control port is the
bidirectional mode. In bidirectional mode, both the sent data
and the readback data appear on the SDIO pin. It is also possible
to set the AD9523-1 to unidirectional mode. In unidirectional
mode, the readback data appears on the SDO pin.
When LSB first is set by Register 0x000, Bit 1, and Register 0x000,
Bit 6, it takes effect immediately because it affects only the
operation of the serial control port and does not require that
an update be executed.
A readback request reads the data that is in the serial control port
buffer area or the data that is in the active registers (see Figure 39).
CS
SDIO/SDA
SERIAL
CONTROL
PORT
UPDATE
REGISTERS
SDO
BUFFER
REGISTERS
ACTIVE
REGISTERS
09278-035
SCLK/SCL
Figure 39. Relationship Between Serial Control Port Buffer Registers and
Active Registers
SPI INSTRUCTION WORD (16 BITS)
The MSB of the instruction word is R/W, which indicates
whether the instruction is a read or a write. The next two bits
([W1:W0]) indicate the length of the transfer in bytes. The final
13 bits are the address ([A12:A0]) at which to begin the read or
write operation.
For a write, the instruction word is followed by the number of
bytes of data indicated by Bits[W1:W0] (see Table 24).
Table 24. Byte Transfer Count
W1
0
0
1
1
W0
0
1
0
1
Bytes to Transfer
1
2
3
Streaming mode
The AD9523-1 instruction word and byte data can be MSB first
or LSB first. Any data written to Register 0x000 must be mirrored:
Bit 7 is mirrored to Bit 0, Bit 6 to Bit 1, Bit 5 to Bit 2, and Bit 4 to
Bit 3. This makes it irrelevant whether LSB first or MSB first is
in effect. The default for the AD9523-1 is MSB first.
When MSB first mode is active, the instruction and data bytes
must be written from MSB to LSB. Multibyte data transfers in
MSB first format start with an instruction byte that includes the
register address of the most significant data byte. Subsequent
data bytes must follow in order from the high address to the
low address. In MSB first mode, the serial control port internal
address generator decrements for each data byte of the
multibyte transfer cycle.
When LSB first mode is active, the instruction and data bytes
must be written from LSB to MSB. Multibyte data transfers in
LSB first format start with an instruction byte that includes the
register address of the least significant data byte, followed by
multiple data bytes. In a multibyte transfer cycle, the internal
byte address generator of the serial port increments for each byte.
The AD9523-1 serial control port register address decrements
from the register address just written toward 0x000 for
multibyte I/O operations if the MSB first mode is active
(default). If the LSB first mode is active, the register address of
the serial control port increments from the address just written
toward 0x234 for multibyte I/O operations. Unused addresses
are not skipped for these operations.
For multibyte accesses that cross Address 0x234 or Address 0x000
in MSB first mode, the SPI internally disables writes to subsequent
registers and returns zeros for reads to subsequent registers.
Streaming mode always terminates when crossing address
boundaries (as shown in Table 25).
Table 25. Streaming Mode (No Addresses Are Skipped)
Bits[A12:A0] select the address within the register map that is
written to or read from during the data transfer portion of the
communications cycle. Only Bits[A11:A0] are needed to cover
the range of the 0x234 registers used by the AD9523-1. Bit A12
must always be 0. For multibyte transfers, this address is the
starting byte address. In MSB first mode, subsequent bytes
decrement the address.
Write Mode
MSB First
Rev. C | Page 34 of 63
Address Direction
Decrement
Stop Sequence
…, 0x001, 0x000, stop
Data Sheet
AD9523-1
Table 26. Serial Control Port, 16-Bit Instruction Word, MSB First
MSB
I15
I14
I13
I12
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
I0
LSB
R/W
W1
W0
A12 = 0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CS
SCLK DON'T CARE
R/W W1 W0 A12 A11 A10 A9
A8
A7
A6 A5
A4 A3 A2
A1 A0
16-BIT INSTRUCTION HEADER
D7 D6 D5
D4 D3
D2 D1
D0
D7
REGISTER (N) DATA
D6 D5
D4 D3 D2
D1 D0
DON'T CARE
09278-038
SDIO DON'T CARE
DON'T CARE
REGISTER (N – 1) DATA
Figure 40. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes of Data
CS
SCLK
DON'T CARE
DON'T CARE
R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
SDO DON'T CARE
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
16-BIT INSTRUCTION HEADER
REGISTER (N) DATA
REGISTER (N – 1) DATA
REGISTER (N – 2) DATA
REGISTER (N – 3) DATA
DON'T
CARE
09278-039
SDIO
Figure 41. Serial Control Port Read—MSB First, 16-Bit Instruction, Four Bytes of Data
tHIGH
tDS
tS
tDH
CS
DON'T CARE
SDIO
DON'T CARE
DON'T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
A6
A5
D4
D3
D2
D1
D0
DON'T CARE
09278-040
SCLK
tC
tCLK
tLOW
Figure 42. Serial Control Port Write—MSB First, 16-Bit Instruction, Timing Measurements
CS
SCLK
DATA BIT N
09278-041
tDV
SDIO
SDO
DATA BIT N – 1
Figure 43. Timing Diagram for Serial Control Port Register Read
CS
SCLK DON'T CARE
A0 A1 A2 A3
A4
A5 A6 A7
A8
A9 A10 A11 A12 W0 W1 R/W D0 D1 D2 D3 D4
16-BIT INSTRUCTION HEADER
D5 D6
REGISTER (N) DATA
D7
D0
D1 D2
D6
REGISTER (N + 1) DATA
Figure 44. Serial Control Port Write—LSB First, 16-Bit Instruction, Two Bytes of Data
Rev. C | Page 35 of 63
D3 D4 D5
D7
DON'T CARE
09278-042
SDIO DON'T CARE
DON'T CARE
AD9523-1
Data Sheet
tC
tS
CS
tCLK
tHIGH
SCLK
tLOW
tDS
SDIO
BIT N
BIT N + 1
Figure 45. Serial Control Port Timing—Write
Table 27. Serial Control Port Timing
Parameter
tDS
tDH
tCLK
tS
tC
tHIGH
tLOW
tDV
Description
Setup time between data and rising edge of SCLK
Hold time between data and rising edge of SCLK
Period of the clock
Setup time between the CS falling edge and SCLK rising edge (start of communication cycle)
Setup time between the SCLK rising edge and CS rising edge (end of communication cycle)
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
SCLK to valid SDIO and SDO (see Figure 43)
Rev. C | Page 36 of 63
09278-043
tDH
Data Sheet
AD9523-1
EEPROM OPERATIONS
The AD9523-1 contains an internal EEPROM (nonvolatile
memory). The EEPROM can be programmed by the user to
create and store a user-defined register setting file when the
power is off. This setting file can be used for power-up and chip
reset as a default setting. The EEPROM size is 512 bytes. See
Table 58 and Table 59 for descriptions of the EEPROM registers
that control EEPROM operation.
3.
4.
During the data transfer process, the write and read registers
are generally not available via the serial port, except for one
readback bit: Status_EEPROM (Register 0xB00, Bit 0).
To determine the data transfer state through the serial port in
SPI mode, users can read the value of the Status_EEPROM bit
(1 = data transfer in process and 0 = data transfer complete).
In I²C mode, the user can address the AD9523-1 slave port with the
external I²C master (send an address byte to the AD9523-1). If the
AD9523-1 responds with a no acknowledge bit, the data transfer
was not received. If the AD9523-1 responds with an acknowledge
bit, the data transfer process is complete. The user can monitor the
Status_EEPROM bit or use Register 0x232, Bit 4, to program the
STATUS0 pin to monitor the status of the data transfer (see Table 55).
5.
To transfer all 512 bytes to the EEPROM, it takes approximately
46 ms. To transfer the contents of the EEPROM to the active
register, it takes approximately 40 ms.
RESET, a hard reset (an asynchronous hard reset is executed by
briefly pulling RESET low), restores the chip either to the setting
stored in EEPROM (the EEPROM pin = 1) or to the on-chip
setting (the EEPROM pin = 0). A hard reset also executes a
SYNC operation that brings the outputs into phase alignment
according to the default settings. When EEPROM is inactive
(the EEPROM pin = 0), it takes ~2 µs for the outputs to begin
toggling after RESET is issued. When EEPROM is active (the
EEPROM pin = 1), it takes ~40 ms for the outputs to toggle after
RESET is brought high.
WRITING TO THE EEPROM
The EEPROM cannot be programmed directly through the serial
port interface. To program the EEPROM and store a register
setting file, follow these steps:
1.
2.
Program the AD9523-1 registers to the desired circuit state.
If the user wants PLL2 to lock automatically after power-up,
the calibrate VCO bit (Register 0x0F3, Bit 1) must be set to 1.
This allows VCO calibration to start automatically after
register loading. Note that a valid input reference signal
must be present during VCO calibration.
Program the EEPROM buffer registers, if necessary (see
the Programming the EEPROM Buffer Segment section).
This step is necessary only if users want to use the EEPROM
to control the default settings of some (but not all) of the
AD9523-1 registers, or if they want to control the register
setting update sequence during power-up or chip reset.
Set the enable EEPROM write bit (Bit 0, Register 0xB02)
to 1 to enable the EEPROM.
Set the REG2EEPROM bit (Bit 0, Register 0xB03) to 1.
This starts the process of writing data into the EEPROM to
create the EEPROM setting file. This enables the EEPROM
controller to transfer the current register values, as well as
the memory address and instruction bytes from the EEPROM
buffer segment, into the EEPROM. After the write process
is completed, the internal controller sets bit REG2EEPROM
back to 0.
Bit 0 of the Status_EEPROM register (Register 0xB00)
is used to indicate the data transfer status between the
EEPROM and the control registers (1 = data transfer in
process, and 0 = data transfer complete). At the beginning
of the data transfer, the Status_EEPROM bit is set to 1 by
the EEPROM controller and cleared to 0 at the end of the
data transfer. The user can access Status_EEPROM via the
STATUS0 pin when the STATUS0 pin is programmed to
monitor the Status_EEPROM bit. Alternatively, the user
can monitor the Status_EEPROM bit directly.
When the data transfer is complete (Status_EEPROM = 0),
set the enable EEPROM write bit (Register 0xB02, Bit 0) to 1.
Clearing the enable EEPROM write bit to 0 disables
writing to the EEPROM.
To ensure that the data transfer has completed correctly, verify
that the EEPROM data error bit (Register 0xB01, Bit 0) = 0.
A value of 1 in this bit indicates a data transfer error. When an
EEPROM save/load transfer is complete, wait a minimum of
10 µs before starting the next EEPROM save/load transfer.
READING FROM THE EEPROM
The following reset-related events can start the process of
restoring the settings stored in the EEPROM to the control
registers. When the EEPROM_SEL pin is set high, do any of
the following to initiate an EEPROM read:
•
•
•
Power up the AD9523-1.
Perform a hardware chip reset by pulling the RESET pin
low and then releasing RESET.
Set the self clearing soft reset bit (Bit 5, Register 0x000) to 1.
When the EEPROM_SEL pin is set low, set the self clearing
Soft_EEPROM bit (Bit 1, Register 0xB02) to 1. The AD9523-1
then starts to read the EEPROM and loads the values into the
AD9523-1 registers. If the EEPROM_SEL pin is low during reset
or power-up, the EEPROM is not active, and the AD9523-1
default values are loaded instead.
When using the EEPROM to automatically load the AD9523-1
register values and lock the PLL, the calibrate VCO bit (Bit 1,
Register 0x0F3) must be set to 1 when the register values are
written to the EEPROM. This allows VCO calibration to start
automatically after register loading. A valid input reference
signal must be present during VCO calibration.
Rev. C | Page 37 of 63
AD9523-1
Data Sheet
To ensure that the data transfer has completed correctly, verify
that the EEPROM data error bit (Register 0xB01, Bit 0) is set to 0.
A value of 1 in this bit indicates a data transfer error. When an
EEPROM save/load transfer is complete, wait a minimum of
10 µs before starting the next EEPROM save/load transfer.
PROGRAMMING THE EEPROM BUFFER SEGMENT
The EEPROM buffer segment is a register space that allows the
user to specify which groups of registers are stored to the EEPROM
during EEPROM programming. Normally, this segment does
not need to be programmed by the user. Instead, the default
power-up values for the EEPROM buffer segment allow the
user to store all of the register values from Register 0x000 to
Register 0x234 to the EEPROM.
For example, if the user wants to load only the output driver
settings from the EEPROM without disturbing the PLL register
settings currently stored in the EEPROM, the EEPROM buffer
segment can be modified to include only the registers that apply
to the output drivers and exclude the registers that apply to the
PLL configuration.
There are two parts to the EEPROM buffer segment: register
section definition groups and operational codes. Each register
section definition group contains the starting address and
number of bytes to be written to the EEPROM. Note that any
register within the EEPROM buffer segment can be defined as a
part of a definition group or an operational code.
If the AD9523-1 register map were continuous from Address 0x000
to Address 0x234, only one register section definition group
would consist of a starting address of 0x000 and a length of
563 bytes. However, this is not the case. The AD9523-1 register
map is noncontiguous, and the EEPROM is only 512 bytes long.
Therefore, the register section definition group tells the EEPROM
controller how the AD9523-1 register map is segmented.
There are three operational codes: IO_Update, end-of-data, and
pseudo-end-of-data. It is important that the EEPROM buffer
segment always have either an end-of-data or a pseudo-end-ofdata operational code and that an IO_Update operation code
appear at least once before the end-of-data operational code.
Register Section Definition Group
The register section definition group is used to define a continuous
register section for the EEPROM profile. It consists of three bytes.
The first byte defines how many continuous register bytes are in
this group. If the user inputs 0x000 in the first byte, it means
there is only one byte in this group. If the user inputs 0x001, it
means there are two bytes in this group. The maximum number
of registers in one group is 128.
IO_Update (Operational Code 0x80)
The EEPROM controller uses this operational code to generate
an IO_Update signal to update the active control register bank
from the buffer register bank during the download process.
At a minimum, there should be at least one IO_Update
operational code after the end of the final register section
definition group. This is needed so that at least one IO_Update
occurs after all of the AD9523-1 registers are loaded when the
EEPROM is read. If this operational code is absent during a
write to the EEPROM, the register values loaded from the
EEPROM are not transferred to the active register space, and
these values do not take effect after they are loaded from the
EEPROM to the AD9523-1.
End-of-Data (Operational Code 0xFF)
The EEPROM controller uses the end of data operational code
to terminate the data transfer process between EEPROM and
the control register during the upload and download process. The
last item appearing in the EEPROM buffer segment should be
either this operational code or the pseudo-end-of-data
operational code.
Pseudo-End-of-Data (Operational Code 0xFE)
The AD9523-1 EEPROM buffer segment has 23 bytes that can
contain up to seven register section definition groups. If the
user wants to define more than seven register section definition
groups, the pseudo-end-of-data operational code can be used.
During the upload process, when the EEPROM controller
receives the pseudo-end-of-data operational code, it halts
the data transfer process, clears the REG2EEPROM bit (Bit 0,
Register 0xB03), and enables the AD9523-1 serial port. The
user can then program the EEPROM buffer segment again and
reinitiate the data transfer process by setting the REG2EEPROM
bit to 1 and the IO_Update bit (Register 0x234, Bit 0) to 1. The
internal I²C master then begins writing to the EEPROM, starting
from the EEPROM address held from the last writing.
This sequence enables more discrete instructions to be written
to the EEPROM than would otherwise be possible due to the
limited size of the EEPROM buffer segment. It also permits the
user to write to the same register multiple times with a different
value each time.
The next two bytes are the low byte and high byte of the
memory address (16 bits) of the first register in this group.
Rev. C | Page 38 of 63
Data Sheet
AD9523-1
Table 28. Example of an EEPROM Buffer Segment
Register Address (Hex)
Bit 7 (MSB)
Start EEPROM Buffer Segment
0xA00
0
0xA01
0xA02
0xA03
0
0xA04
0xA05
0xA06
0
0xA07
0xA08
0xA09
0xA0A
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
Number of bytes of the first group of registers (Bits[6:0])
Address of the first group of registers (Bits[15:8])
Address of the first group of registers (Bits[7:0])
Number of bytes of the second group of registers (Bits[6:0])
Address of the second group of registers (Bits[15:8])
Address of the second group of registers (Bits[7:0])
Number of bytes of the third group of registers (Bits[6:0])
Address of the third group of registers (Bits[15:8])
Address of the third group of registers (Bits[7:0])
IO_Update operational code (0x80)
End-of-data operational code (0xFF)
Rev. C | Page 39 of 63
AD9523-1
Data Sheet
DEVICE INITIALIZATION FLOWCHARTS
The flowcharts in this section show a typical AD9523-1
initialization routine using an evaluation software generated
setup file (.stp) and calibration routines designed for robust
system startup. Other valid start up sequences exist and, as
such, these flow charts are provided as recommendations.
The count variables (RST_COUNT and CAL_COUNT) in the
AD9523-1 device initialization flow chart act as system level
count limits for the loop to prevent an infinite loop. These
count variables are not AD9523-1 device settings or status
readbacks.
Rev. C | Page 40 of 63
Data Sheet
AD9523-1
START
USER POWER
SUPPLIES
INITIALIZATION AND
POWER-ON RESET
WAIT
APPLY VDD
(ALL DOMAINS)
VDD SETTLED?
NO
YES
POR: WAIT 60ms
CHIP LEVEL RESET LOOP
APPLY REFERENCE
INPUT(S)
ISSUE A PIN LEVEL
RESET OR SOFT RESET
RST_COUNT =
RST_COUNT + 1
RST_COUNT = 0
SUBPROCESS:
WRITE REGISTERS
FROM
SETUP FILE
PLL2 RECALIBRATION LOOP
CAL_COUNT = 0
WRITE:
R0x0F3[1] = 0
ISSUE VCO
CALIBRATION
COMMAND
WRITE:
R0x234 = 0x01
WRITE:
R0x0F3[1] = 1
WRITE:
R0x234 = 0x01
NO
CAL_COUNT =
CAL_COUNT + 1
CAL_COUNT > 1
START TIMEOUT CLOCK:
TIME = 0
NO
YES
YES
RST_COUNT >0
RAISE FLAG FOR
DEBUGGING.
READ:
R0x22C TO R0x22D
PLL2 LOCK
DETECT POLLING
LOOP
NO
R0x22C[1] = 1
NO
TIMEOUT CLOCK:
TIME > 100ns
YES
YES
START TIMEOUT CLOCK:
TIME = 0
PLL1 LOCK
DETECT POLLING
LOOP
NO
R0x22C[0] = 1
NO
TIMEOUT CLOCK:
TIME >PLL2_TO1
YES
END
1PLL2_TO IS A CALCULATED TIMEOUT VALUE. SEE THE THEORY OF OPERATION, COMPONENT BLOCKS—INPUT PLL (PLL1) FOR ITS FORMULA.
Figure 46. AD9523-1 Device Initialization
Rev. C | Page 41 of 63
09278-145
YES
AD9523-1
Data Sheet
SOFTWARE
GENERATED
AD9523-1 SETUP
FILE
START
WRITE:
R0x000 TO R0x006
WRITE:
R0x010 TO R0x01D
WRITE:
R0x0F0 TO R0x0F9
WRITE:
R0x190 TO R0x1BB
WRITE:
R0x230 TO R0x233
WRITE:
R0xA00 TO R0xA16
END
09278-146
WRITE:
R0x234 = 0x01
Figure 47. Subprocess: Write Registers from Setup File
Rev. C | Page 42 of 63
Data Sheet
AD9523-1
POWER DISSIPATION AND THERMAL CONSIDERATIONS
The AD9523-1 is a multifunctional, high speed device that
targets a wide variety of clock applications. The numerous
innovative features contained in the device each consume
incremental power. If all outputs are enabled in the maximum
frequency and mode that have the highest power, the safe
thermal operating conditions of the device may be exceeded.
Careful analysis and consideration of power dissipation and
thermal management are critical elements in the successful
application of the AD9523-1 device.
The AD9523-1 device is specified to operate within the
industrial temperature range of –40°C to +85°C. This
specification is conditional, however, such that the absolute
maximum junction temperature is not exceeded (as specified
in Table 16). At high operating temperatures, extreme care must
be taken when operating the device to avoid exceeding the
junction temperature and potentially damaging the device.
A maximum junction temperature is listed in Table 1 with the
ambient operating range. The ambient range and maximum
junction temperature specifications ensure the performance of
the device, as guaranteed in the Specifications section.
Many variables contribute to the operating junction temperature
within the device, including
•
•
•
•
Selected driver mode of operation
Output clock speed
Supply voltage
Ambient temperature
The combination of these variables determines the junction
temperature within the AD9523-1 device for a given set of
operating conditions.
The AD9523-1 is specified for an ambient temperature (TA). To
ensure that TA is not exceeded, an airflow source can be used.
Use the following equation to determine the junction
temperature on the application PCB:
Values of ΨJB are provided for package comparison and PCB
design considerations.
CLOCK SPEED AND DRIVER MODE
Clock speed directly and linearly influences the total power
dissipation of the device and, therefore, the junction temperature.
Two operating frequencies are listed under the incremental power
dissipation parameter in Table 3. Using linear interpretation is
a sufficient approximation for frequency not listed in the table.
When calculating power dissipation for thermal consideration,
the amount of power dissipated in the 100 Ω resistor should be
removed. If using the data in Table 2, this power is already
removed. If using the current vs. frequency graphs provided in
the Typical Performance Characteristics section, the power into
the load must be subtracted, using the following equation:
Differential Output Voltage Swing 2
100 Ω
EVALUATION OF OPERATING CONDITIONS
The first step in evaluating the operating conditions is to
determine the maximum power consumption (PD) internal to
the AD9523-1. The maximum PD excludes power dissipated in
the load resistors of the drivers because such power is external
to the device. Use the power dissipation specifications listed in
Table 3 to calculate the total power dissipated for the desired
configuration. The base typical configuration parameter in
Table 3 lists a power of 434.7 mW, which includes one LVPECL
output at 122.88 MHz. If the frequency of operation is not listed
in Table 3, see the Typical Performance Characteristics section,
current vs. frequency and driver mode to calculate the power
dissipation; then add 20% for maximum current draw. Remove
the power dissipated in the load resistor to achieve the most
accurate power dissipation internal to the AD9523-1. See Table 29
for a summary of the incremental power dissipation from the
base power configuration for two different examples.
Table 29. Temperature Gradient Examples
TJ = TCASE + (ΨJT × PD)
where:
TJ is the junction temperature (°C).
TCASE is the case temperature (°C) measured by the user at the
top center of the package.
ΨJT is the value from Table 17.
PD is the power dissipation of the AD9523-1.
Values of θJA are provided for package comparison and PCB
design considerations. θJA can be used for a first-order
approximation of TJ by the equation
TJ = TA + (θJA × PD)
where TA is the ambient temperature (°C).
Values of θJC are provided for package comparison and PCB
design considerations when an external heat sink is required.
Description
Example 1
Base Typical
Configuration
Output Driver
Output Driver
Output Driver
Total Power
Example 2
Base Typical
Configuration
Output Driver
Total Power
Rev. C | Page 43 of 63
Mode
Frequency
(MHz)
Maximum
Power (mW)
434.7
6 × LVPECL
3 × LVDS
3 × LVDS
122.88
61.44
245.76
306
89
135
966
434.7
13 × LVPECL
983.04
2066
2500
AD9523-1
Data Sheet
The second step is to multiply the power dissipated by the thermal
impedance to determine the maximum power gradient. For
this example, a thermal impedance of θJA = 20.1°C/W was used.
Example 1
(966 mW × 20.1°C/W) = 19.4°C
THERMALLY ENHANCED PACKAGE MOUNTING
GUIDELINES
See the AN-772 Application Note, A Design and Manufacturing
Guide for the Lead Frame Chip Scale Package (LFCSP), for more
information about mounting devices with an exposed paddle.
With an ambient temperature of 85°C, the junction temperature is
TJ = 85°C + 19.4°C = 104°C
This junction temperature is below the maximum allowable.
Example 2
(2500 mW × 20.1°C/W) = 50.2°C
With an ambient temperature of 85°C, the junction temperature is
TJ = 85°C + 50°C = 135°C
This junction temperature exceeds the maximum allowable
range. To operate in the condition of Example 2, the ambient
temperature must be lowered to 65°C.
Rev. C | Page 44 of 63
Data Sheet
AD9523-1
CONTROL REGISTERS
CONTROL REGISTER MAP
Register addresses that are not listed in Table 30 are not used, and writing to those registers has no effect. Registers that are marked as
reserved should never have their values changed. When writing to registers with bits that are marked reserved, the user should take care
to always write the default value for the reserved bits.
Table 30. Control Register Map
Addr
Register
(Hex)
Name
Serial Port Configuration
SPI mode
0x000
serial port
configuration
I2C mode
serial port
configuration
Readback
0x004
control
EEPROM
0x005
customer
0x006
version ID
Input PLL (PLL1)
PLL1 REFA
0x010
R divider
0x011
control
0x012
0x013
PLL1 REFB
R divider
control
0x014
PLL1 reference
test divider
PLL1 reserved
PLL1 feedback
N divider
control
0x015
0x016
0x017
0x018
PLL1 charge
pump control
0x019
(MSB)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Soft reset
Reserved
Reserved
Soft reset
Reserved
LSB first/
address
increment
Reserved
Soft reset
Reserved
Reserved
Soft reset
LSB first/
address
increment
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SDO
active
(LSB)
Bit 0
Default
Value
(Hex)
SDO active
0x00
Reserved
0x00
Read back
active registers
0x00
EEPROM customer version ID[7:0] (LSB)
EEPROM customer version ID[15:8] (MSB)
10-bit REFA R divider[7:0] (LSB)
Reserved
10-bit REFB R divider[7:0] (LSB)
Reserved
Reserved
Reserved
Reserved
Reserved
0x00
0x00
10-bit REFA R divider[9:8]
(MSB)
10-bit REFB R divider[9:8]
(MSB)
REF_TEST divider
Reserved
Reserved
Reserved Reserved
10-bit PLL1 feedback divider[7:0] (LSB)
Reserved
PLL1
charge
pump
tristate
Reserved
Reserved
Reserved
0x01A
PLL1
input receiver
control
REF_TEST
input
receiver
enable
REFB
differential
receiver
enable
REFA
differential
receiver
enable
0x01B
REF_TEST,
REFA, REFB,
and ZD_IN
control
Bypass
REF_TEST
divider
Bypass
feedback
divider
Zero delay
mode
0x01C
PLL1
miscellaneous
control
Enable
REFB
R divider
independent
division
control
OSC_CTRL
control
voltage to
VCC/2
when ref
clock fails
Reserved
OSC_IN signal
feedback
for PLL1
Antibacklash
pulse width control
REFA
receiver
enable
Input
REFA, REFB
receiver
powerdown
control
enable
ZD_IN
differential
receiver
mode
enable
ZD_IN
singleended
receiver
mode
enable
(CMOS
mode)
Reference selection mode
Rev. C | Page 45 of 63
0x00
0x00
0x00
Reserved
Reserved
10-bit PLL1 feedback divider[9:8]
(MSB)
PLL1 charge pump control
Enable SPI
control of
antibacklash
pulse width
REFB receiver
enable
0x00
0x00
0x00
0x00
0x00
0x0C
PLL1 charge pump mode
0x00
OSC_IN
single-ended
receiver
mode enable
(CMOS mode)
OSC_IN
differential
receiver
mode enable
0x00
REFB
single-ended
receiver
mode enable
(CMOS mode)
REFA
single-ended
receiver
mode enable
(CMOS mode)
0x00
Bypass REFB
R divider
Bypass REFA
R divider
0x00
AD9523-1
Addr
(Hex)
0x01D
Register
Name
PLL1 loop
filter zero
resistor control
Output PLL (PLL2)
PLL2 charge
0x0F0
pump control
PLL2
0x0F1
feedback
N divider
control
0x0F2
PLL2 control
Data Sheet
(MSB)
Bit 7
Reserved
VCO control
0x0F4
VCO dividers
Reserved
0x0F5
PLL2 loop
filter control
(9 bits)
PLL2 R2
divider
Clock Distribution
Channel 0
0x190
control
0x191
0x192
0x193
0x194
0x195
0x196
0x197
0x198
0x199
0x19A
0x19B
0x19C
0x19D
0x19E
0x19F
0x1A0
0x1A1
Channel 1
control
Channel 2
control
Channel 3
control
Channel 4
control
Channel 5
control
Bit 4
Reserved
A counter
0x0F3
0x0F7
Bit 5
Reserved
Bit 3
Bit 2
Bit 1
PLL1 loop filter, RZERO
PLL2 charge pump control
PLL2 lock
detector
powerdown
Reserved
0x0F6
Bit 6
Reserved
(LSB)
Bit 0
Reserved
VCO
Divider M2
powerdown
Reserved
Enable SPI
control of
antibacklash
pulse width
Force release
Reserved
of distribution
sync when
PLL2 is
unlocked
VCO Divider M2
Pole 2 resistor (RPOLE2)
Reserved
Reserved
Reserved
Reserved
Reserved
Invert
divider
output
Ignore
sync
Power
down
channel
Invert
divider
output
Invert
divider
output
Invert
divider
output
Invert
divider
output
Ignore
sync
Ignore
sync
Ignore
sync
Ignore
sync
Ignore
sync
Reserved
0x04
Antibacklash
pulse width control
Treat
reference
as valid
Force
VCO to
midpoint
frequency
Reserved
VCO
Divider
M1
powerdown
Zero resistor (RZERO)
Reserved
Invert
divider
output
0x00
B counter
Enable
frequency
doubler
PLL2 charge pump mode
Calibrate VCO
(not autoclearing)
Reserved
VCO Divider M1
Pole 1 capacitor (CPOLE1)
Reserved
Reserved
Reserved
Bypass internal
RZERO resistor
PLL R2 divider
Lower power
mode
10-bit channel divider[7:0] (LSB)
Divider phase[5:0]
Power
Lower power
down
mode
channel
10-bit channel divider[7:0] (LSB)
Divider phase[5:0]
Lower power
Power
mode
down
channel
10-bit channel divider[7:0] (LSB)
Divider phase[5:0]
Lower power
Power
mode
down
channel
10-bit channel divider[7:0] (LSB)
Divider phase[5:0]
Lower power
Power
mode
down
channel
10-bit channel divider[7:0] (LSB)
Divider phase[5:0]
Power
Lower power
down
mode
channel
10-bit channel divider[7:0] (LSB)
Divider phase[5:0]
Rev. C | Page 46 of 63
Default
Value
(Hex)
0x00
0x03
0x00
0x00
0x00
0x00
0x00
Driver mode
0x00
10-bit channel divider[9:8] (MSB)
Driver mode
0x1F
0x04
0x20
10-bit channel divider[9:8] (MSB)
Driver mode
0x1F
0x04
0x00
10-bit channel divider[9:8] (MSB)
Driver mode
0x1F
0x04
0x20
10-bit channel divider[9:8] (MSB)
Driver mode
0x1F
0x04
0x00
10-bit channel divider[9:8] (MSB)
Driver mode
0x1F
0x04
0x20
10-bit channel divider[9:8] (MSB)
0x1F
0x04
Data Sheet
Addr
(Hex)
0x1A2
0x1A3
0x1A4
0x1A5
0x1A6
0x1A7
0x1A8
0x1A9
0x1AA
0x1AB
0x1AC
0x1AD
0x1AE
0x1AF
0x1B0
0x1B1
0x1B2
0x1B3
0x1B4
0x1B5
0x1B6
0x1B7
0x1B8
0x1B9
0x1BA
0x1BB
Register
Name
Channel 6
control
Channel 7
control
Channel 8
control
Channel 9
control
Channel 10
control
Channel 11
control
Channel 12
control
Channel 13
control
AD9523-1
(MSB)
Bit 7
Invert
divider
output
Invert
divider
output
Invert
divider
output
Invert
divider
output
Invert
divider
output
Invert
divider
output
Invert
divider
output
Invert
divider
output
PLL1 output
control
PLL1 output
channel
control
Readback
0x22C
Readback 0
PLL1
output
driver
powerdown
0x22D
Readback 1
Status
PLL2
reference
clock
Reserved
0x22E
0x22F
Readback 2
Readback 3
Reserved
Reserved
Bit 6
Ignore
sync
Bit 5
Power
down
channel
Bit 4
Lower power
mode
Bit 3
Bit 2
Bit 1
Driver mode
(LSB)
Bit 0
10-bit channel divider[7:0] (LSB)
Divider phase[5:0]
10-bit channel divider[9:8] (MSB)
Lower power
Ignore
Power
Driver mode
mode
sync
down
channel
10-bit channel divider[7:0] (LSB)
Divider phase[5:0]
10-bit channel divider[9:8] (MSB)
Lower power
Ignore
Power
Driver mode
mode
sync
down
channel
10-bit channel divider[7:0] (LSB)
Divider phase[5:0]
10-bit channel divider[9:8] (MSB)
Lower power
Ignore
Power
Driver mode
mode
sync
down
channel
10-bit channel divider[7:0] (LSB)
Divider phase[5:0]
10-bit channel divider[9:8] (MSB)
Lower power
Ignore
Power
Driver mode
mode
sync
down
channel
10-bit channel divider[7:0] (LSB)
Divider phase[5:0]
10-bit channel divider[9:8] (MSB)
Lower power
Ignore
Power
Driver mode
mode
sync
down
channel
10-bit channel divider[7:0] (LSB)
Divider phase[5:0]
10-bit channel divider[9:8] (MSB)
Lower power
Ignore
Power
Driver mode
mode
sync
down
channel
10-bit channel divider[7:0] (LSB)
Divider phase[5:0]
10-bit channel divider[9:8] (MSB)
Lower power
Ignore
Power
Driver mode
mode
sync
down
channel
10-bit channel divider[7:0] (LSB)
Divider phase[5:0]
10-bit channel divider[9:8] (MSB)
PLL1 output
Out PLL1 output
CLK2 select[2:0]
CMOS driver
strength
Route VCXO
Route VCXO
Route
Route
CLK2 select[5:3]
Reserved
clock to Ch 0
clock to Ch 1
VCXO
VCXO
divider input
divider input
clock to
clock to
Ch 2
Ch 3
divider
divider
input
input
Status
PLL2
feedback
clock
Reserved
Status
VCXO
Status
REF_TEST
Status
REFB
Status
REFA
Lock detect
PLL2
Lock detect
PLL1
Reserved
Reserved
Holdover
active
Reserved
VCO
calibration
in progress
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Selected
reference
(in auto
mode)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Rev. C | Page 47 of 63
Default
Value
(Hex)
0x00
0x1F
0x04
0x20
0x1F
0x04
0x00
0x1F
0x04
0x20
0x1F
0x04
0x00
0x1F
0x04
0x20
0x1F
0x04
0x00
0x1F
0x04
0x20
0x1F
0x04
0x00
0x80
AD9523-1
Addr
(Hex)
Other
0x230
0x231
0x232
0x233
Register
Name
(MSB)
Bit 7
Bit 6
Status signals
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Enable Status_
EEPROM on
STATUS0 pin
Reserved
Reserved
Reserved
Reserved
Power-down
control
Update all
registers
EEPROM Buffer
EEPROM
0xA00
Buffer Segment
Register 1 to
0xA01
EEPROM
Buffer Segment
0xA02
Register 3
EEPROM
0xA03
Buffer Segment
Register 4 to
0xA04
EEPROM
Buffer Segment
0xA05
Register 6
EEPROM
0xA06
Buffer Segment
Register 7 to
0xA07
EEPROM
Buffer Segment
0xA08
Register 9
EEPROM
0xA09
Buffer Segment
Register 10 to
0xA0A
EEPROM
Buffer Segment
0xA0B
Register 12
EEPROM
0xA0C
Buffer Segment
0xA0D Register 13 to
EEPROM
Buffer Segment
0xA0E
Register 15
EEPROM
0xA0F
Buffer Segment
Register 16 to
0xA10
EEPROM
Buffer Segment
0xA11
Register 18
EEPROM
0xA12
Buffer Segment
Register 19 to
0xA13
EEPROM
Buffer Segment
0xA14
Register 21
EEPROM
0xA15
Buffer Segment
Register 22
0x234
Data Sheet
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Status Monitor 0 control
Status Monitor 1 control
STATUS1 STATUS0
Reserved
pin
pin
divider
divider
enable
enable
Reserved
PLL1
powerdown
PLL2
power-down
Reserved
(LSB)
Bit 0
Sync dividers
(manual
control)
0: sync signal
inactive
1: dividers
held in sync
(same as
SYNC pin low)
Distribution
power-down
IO_Update
Default
Value
(Hex)
0x00
0x00
0x00
0x07
0x00
Instruction (data)[7:0] (serial port configuration register)
0x00
High byte of register address (serial port configuration register)
0x00
Low byte of register address (serial port configuration register)
0x00
Instruction (data)[7:0] (reaback control register)
0x02
High byte of register address (reaback control register)
0x00
Low byte of register address (reaback control register)
0x04
Instruction (data)[7:0] (PLL segment)
0x0E
High byte of register address (PLL segment)
0x00
Low byte of register address (PLL segment)
0x10
Instruction (data)[7:0] (PECL/CMOS output segment)
0x0E
High byte of register address (PECL/CMOS output segment)
0x00
Low byte of register address (PECL/CMOS output segment)
0xF0
Instruction (data)[7:0] (divider segment)
0x2B
High byte of register address (divider segment)
0x01
Low byte of register address (divider segment)
0x90
Instruction (data)[7:0] (clock input and REF segment)
0x01
High byte of register address (clock input and REF segment)
0x01
Low byte of register address (clock input and REF segment)
0xE0
Instruction (data)[7:0] (other segment)
0x03
High byte of register address (other segment)
0x02
Low byte of register address (other segment)
0x30
I/O update
0x80
Rev. C | Page 48 of 63
Data Sheet
Addr
(Hex)
0xA16
Register
Name
EEPROM
Buffer Segment
Register 23
EEPROM Control
Status_
0xB00
EEPROM
(read only)
EEPROM error
0xB01
checking
readback
(read only)
EEPROM
0xB02
Control 1
EEPROM
0xB03
Control 2
AD9523-1
(MSB)
Bit 7
Bit 6
Bit 5
Bit 4
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 3
End of data
Bit 2
Bit 1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Soft_EEPROM
Reserved
Reserved
Reserved
Reserved
Reserved
Rev. C | Page 49 of 63
(LSB)
Bit 0
Default
Value
(Hex)
0xFF
Status_
EEPROM
(read only)
EEPROM
data error
(read only)
0x00
Enable
EEPROM write
REG2EEPROM
0x00
0x00
0x00
AD9523-1
Data Sheet
CONTROL REGISTER MAP BIT DESCRIPTIONS
Serial Port Configuration (Address 0x000 to Address 0x006)
Table 31. SPI Mode Serial Port Configuration
Address
0x000
0x004
Bits
7
Bit Name
SDO active
6
LSB first/
address
increment
5
Soft reset
4
[3:0]
Reserved
Mirror[7:4]
0
Read back
active registers
Description
Selects unidirectional or bidirectional data transfer mode. This bit is ignored in I2C mode.
0: SDIO pin used for write and read; SDO is high impedance (default).
1: SDO used for read; SDIO used for write; unidirectional mode.
SPI MSB or LSB data orientation. This bit is ignored in I2C mode.
0: data-oriented MSB first; addressing decrements (default).
1: data-oriented LSB first; addressing increments.
Soft reset.
1 (self clearing): soft reset; restores default values to internal registers.
Reserved.
Bits[3:0] should always mirror Bits[7:4] so that it does not matter whether the part is in MSB first or LSB
first mode (see Register 0x000, Bit 6). Set bits as follows:
Bit 0 = Bit 7.
Bit 1 = Bit 6.
Bit 2 = Bit 5.
Bit 3 = Bit 4.
For buffered registers, serial port readback reads from actual (active) registers instead of from the buffer.
0 (default): reads values currently applied to the internal logic of the device.
1: reads buffered values that take effect on the next assertion of the I/O update.
Table 32. I2C Mode Serial Port Configuration
Address
0x000
0x004
Bits
[7:6]
5
Bit Name
Reserved
Soft reset
4
[3:0]
Reserved
Mirror[7:4]
0
Read back
active registers
Description
Reserved.
Soft reset.
1 (self clearing): soft reset; restores default values to internal registers.
Reserved.
Bits[3:0] should always mirror Bits[7:4]. Set bits as follows:
Bit 0 = Bit 7.
Bit 1 = Bit 6.
Bit 2 = Bit 5.
Bit 3 = Bit 4.
For buffered registers, serial port readback reads from actual (active) registers instead of from the buffer.
0 (default): reads values currently applied to the internal logic of the device.
1: reads buffered values that take effect on the next assertion of the I/O update.
Table 33. EEPROM Customer Version ID
Address
0x005
Bits
[7:0]
0x006
[7:0]
Bit Name
EEPROM
customer
version ID (LSB)
EEPROM
customer
version ID (MSB)
Description
16-bit EEPROM ID, Bits[7:0]. This register, along with Register 0x006, allows the user to store a unique
ID to identify which version of the AD9523-1 register settings is stored in the EEPROM. It does not
affect AD9523-1 operation in any way (default: 0x00).
16-bit EEPROM ID, Bits[15:8]. This register, along with Register 0x005, allows the user to store a unique
ID to identify which version of the AD9523-1 register settings is stored in the EEPROM. It does not
affect AD9523-1 operation in any way (default: 0x00).
Rev. C | Page 50 of 63
Data Sheet
AD9523-1
Input PLL (PLL1) (Address 0x010 to Address 0x01D)
Table 34. PLL1 REFA R Divider Control
Address
0x010
Bits
[7:0]
0x011
[1:0]
Bit Name
REFA R divider
Description
10-bit REFA R divider, Bits[7:0] (LSB). Divide-by-1 to divide-by-1023.
00000000, 00000001: divide-by-1.
10-bit REFA R divider, Bits[9:8] (MSB).
Table 35. PLL1 REFB R Divider Control1
Address
0x012
Bits
[7:0]
0x013
[1:0]
1
Bit Name
REFB R divider
Description
10-bit REFB R divider, Bits[7:0] (LSB). Divide-by-1 to divide-by-1023.
00000000, 00000001: divide-by-1.
10-bit REFB R divider, Bits[9:8] (MSB).
Requires Register 0x01C, Bit 7 = 1 for division that is independent of REFA division.
Table 36. PLL1 Reference Test Divider
Address
0x014
Bits
[7:6]
[5:0]
Bit Name
Reserved
REF_TEST divider
Description
Reserved.
6-bit reference test divider. Divide-by-1 to divide-by-63.
000000, 000001: divide-by-1.
Table 37. PLL1 Reserved
Address
0x015
Bits
[7:0]
Bit Name
Reserved
Description
Reserved.
Table 38. PLL1 Feedback N Divider Control
Address
0x016
Bits
[7:0]
0x017
[1:0]
Bit Name
PLL1 feedback N divider control
(N_PLL1)
Description
10-bit feedback divider, Bits[7:0] (LSB). Divide-by-1 to divide-by-1023.
00000000, 00000001: divide-by-1.
10-bit feedback divider, Bits[1:0] (MSB).
Table 39. PLL1 Charge Pump Control
Address
0x018
Bits
7
[6:0]
Bit Name
PLL1 charge pump tristate
PLL1 charge pump control
0x019
[7:5]
4
Reserved
Enable SPI control of antibacklash
pulse width
[3:2]
Antibacklash pulse width control
[1:0]
PLL1 charge pump mode
Description
Tristates the PLL1 charge pump.
These bits set the magnitude of the PLL1 charge pump current. Granularity is ~0.5 μA
with a full-scale magnitude of ~63.5 μA.
Reserved.
Controls the functionality of Register 0x019, Bits[3:2].
0 (default): the device automatically controls the antibacklash period.
1: antibacklash period defined by Register 0x019, Bits[3:2].
Controls the PFD antibacklash period. These bits default to the high setting unless
reprogrammed using Register 0x019[4] = 1b. The high setting decreases the
maximum allowable PLL1 PFD rate. See Table 7 for ranges.
00: minimum.
01: low.
10: high(initial state unless changed via Register 0x019[4] = 1b).
11: maximum.
Controls the mode of the PLL1 charge pump.
00: tristate.
01: pump up.
10: pump down.
11 (default): normal.
Rev. C | Page 51 of 63
AD9523-1
Data Sheet
Table 40. PLL1 Input Receiver Control
Address
0x01A
Bits
7
Bit Name
REF_TEST input receiver enable
6
REFB differential receiver enable
5
REFA differential receiver enable
4
REFB receiver enable
3
REFA receiver enable
2
Input REFA and REFB receiver
power-down control enable
1
OSC_IN single-ended receiver
mode enable (CMOS mode)
0
OSC_IN differential receiver mode
enable
Description
1: enabled.
0: disabled (default).
1: differential receiver mode.
0: single-ended receiver mode (also depends on Register 0x01B, Bit 1) (default).
1: differential receiver mode.
0: single-ended receiver mode (also depends on Register 0x01B, Bit 0) (default).
REFB receiver power-down control mode only when Bit 2 = 1.
1: enable REFB receiver.
0: power-down (default).
REFA receiver power-down control mode only when Bit 2 = 1.
1: enable REFA receiver.
0: power-down (default).
Enables control over power-down of the input receivers, REFA and REFB.
1: power-down control enabled.
0: both receivers enabled (default).
Selects which single-ended input pin is enabled when in the single-ended receiver
mode (Register 0x01A, Bit 0 = 0).
1: negative receiver from oscillator input (OSC_IN pin) selected.
0: positive receiver from oscillator input (OSC_IN pin) selected (default).
1: differential receiver mode.
0: single-ended receiver mode (also depends on Bit 1) (default).
Table 41. REF_TEST, REFA, REFB, and ZD_IN Control
Address
0x01B
Bits
7
Bit Name
Bypass REF_TEST divider
6
Bypass feedback divider
5
Zero delay mode
4
OSC_IN signal feedback for PLL1
3
ZD_IN single-ended receiver
mode enable (CMOS mode)
2
ZD_IN differential receiver mode
enable
REFB single-ended receiver mode
enable (CMOS mode)
1
0
REFA single-ended receiver mode
enable (CMOS mode)
Description
Puts the divider into bypass mode (same as programming the divider word to 0 or 1).
1: divider in bypass mode (divide = 1).
0: divider normal operation.
Puts the divider into bypass mode (same as programming the divider word to 0 or 1).
1: divider in bypass mode (divide = 1).
0: divider normal operation.
Selects the zero delay mode used (via the ZD_IN pin) when Register 0x01B, Bit 4 = 0.
Otherwise, this bit is ignored.
1: internal zero delay mode. The zero delay receiver is powered down. The internal
zero delay path from Distribution Divider Channel 0 is used.
0: external zero delay mode. The ZD_IN receiver is enabled.
Controls the input PLL feedback path, local feedback from the OSC_IN receiver or
zero delay mode.
1: OSC_IN receiver input used for the input PLL feedback (non-zero delay mode).
0: zero delay mode enabled (also depends on Register 0x01B, Bit 4 to select the
zero delay path.
Selects which single-ended input pin is enabled when in the single-ended receiver
mode (Register 0x01B, Bit 2 = 0).
1: ZD_IN pin enabled.
0: ZD_IN pin enabled.
1: differential receiver mode.
0: single-ended receiver mode (also depends on Register 0x01B, Bit 3).
Selects which single-ended input pin is enabled when in single-ended receiver mode
(Register 0x01A, Bit 6 = 0).
1: REFB pin enabled.
0: REFB pin enabled.
Selects which single-ended input pin is enabled when in single-ended receiver mode
(Register 0x01A, Bit 5 = 0).
1: REFA pin enabled.
0: REFA pin enabled.
Rev. C | Page 52 of 63
Data Sheet
AD9523-1
Table 42. PLL1 Miscellaneous Control
Address
0x01C
1
Bits
7
Bit Name
Enable REFB R divider
independent division control
6
OSC_CTRL control voltage to
VCC/2 when reference clock fails
5
[4:2]
Reserved
Reference selection mode
1
Bypass REFB R divider
0
Bypass REFA R divider
Description
1: REFB R divider is controlled by Register 0x012 and Register 0x013.
0: REFB R divider is set to the same setting as the REFA R divider (Register 0x010
and Register 0x011). This requires that, for the loop to stay locked, the REFA and
REFB input frequencies must be the same.
High permits the OSC_CTRL control voltage to be forced to midsupply when the
feedback or input clocks fail. Low tristates the charge pump output.
1: OSC_CTRL control voltage goes to VCC/2.
0: OSC_CTRL control voltage tracks the tristated (high impedance) charge pump
(through the buffer).
Reserved.
Programs the REFA, REFB mode selection (default = 000).
REF_SEL
Bit 4
Bit 3
Bit 2
Description
Pin
X1
0
0
0
Nonrevertive: stay on REFB.
X1
0
0
1
Revert to REFA.
X1
0
1
0
Select REFA.
X1
0
1
1
Select REFB.
1
1
0
1
X
X
REF_SEL pin = 0 (low): REFA.
1
1
X1
X1
REF_SEL pin = 1 (high): REFB.
Puts the divider into bypass mode (same as programming divider word to 0 or 1).
1: divider in bypass mode (divide = 1).
0: divider normal operation.
Puts the divider into bypass mode (same as programming divider word to 0 or 1).
1: divider in bypass mode (divide = 1).
0: divider normal operation.
X = don’t care.
Table 43. PLL1 Loop Filter Zero Resistor Control
Address
0x01D
Bits
[7:4]
[3:0]
Bit Name
Reserved
PLL1 loop filter, RZERO
Description
Reserved.
Programs the value of the zero resistor, RZERO.
Bit 3
Bit 2
Bit 1
Bit 0
RZERO Value (kΩ)
0
0
0
0
883
0
0
0
1
677
0
0
1
0
341
0
0
1
1
135
0
1
0
0
10
0
1
0
1
10
0
1
1
0
10
0
1
1
1
10
1
0
0
0
Use external resistor
Output PLL (PLL2) (Address 0x0F0 to Address 0x0F7)
Table 44. PLL2 Charge Pump Control
Address
0x0F0
Bits
[7:0]
Bit Name
PLL2 charge pump control
Description
These bits set the magnitude of the PLL2 charge pump current. Granularity is ~3.5 μA
with a full-scale magnitude of ~900 μA.
Rev. C | Page 53 of 63
AD9523-1
Data Sheet
Table 45. PLL2 Feedback N Divider Control
Address
0x0F1
Bits
[7:6]
[5:0]
Bit Name
A counter
B counter
A Counter (Bits[7:6])
A=0
A = 0 or A = 1
A = 0 to A = 2
A = 0 to A = 2
A = 0 to A = 3
Description
A counter word.
B counter word.
Feedback Divider Constraints
B Counter (Bits[5:0])
B=3
B=4
B=5
B=6
B≥7
Allowed N Division (4 × B + A)
12
16, 17
20, 21, 22
24, 25, 26
28, 29 … continuous to 255
Table 46. PLL2 Control
Address
0x0F2
Bits
7
Bit Name
PLL2 lock detector power-down
6
5
Reserved
Enable frequency doubler
4
Enable SPI control of antibacklash
pulse width
[3:2]
Antibacklash pulse width control
[1:0]
PLL2 charge pump mode
Description
Controls power-down of the PLL2 lock detector.
1: lock detector powered down.
0: lock detector active.
Default = 0; value must remain 0.
Enables doubling of the PLL2 reference input frequency.
1: enabled.
0: disabled.
Controls the functionality of Register 0x0F2, Bits[2:1].
0 (default): device automatically controls the antibacklash period.
1: antibacklash period defined by Register 0x0F2, Bits[2:1].
Controls the PFD antibacklash period. These bits default to the high setting unless
reprogrammed using Register 0x0F2[4] = 1b. The high setting decreases the
maximum allowable PLL2 PFD rate. See Table 11 for ranges.
00 minimum.
01: low.
10: high (initial state unless changed via Register 0x0F2[4] = 1b).
11: maximum.
Controls the mode of the PLL2 charge pump.
00: tristate.
01: pump up.
10: pump down.
11 (default): normal.
Table 47. VCO Control
Address
0x0F3
Bits
[7:5]
4
Bit Name
Reserved
Force release of distribution sync
when PLL2 is unlocked
3
Treat reference as valid
2
Force VCO to midpoint frequency
1
Calibrate VCO (not autoclearing)
0
Reserved
Description
Reserved.
0 (default): distribution is held in sync (static) until the output PLL locks. Then it is
automatically released from sync with all dividers synchronized.
1: overrides the PLL2 lock detector state; forces release of the distribution from sync.
0 (default): uses the PLL1 VCXO indicator to determine when the reference clock to
the PLL2 is valid.
1: treats the reference clock as valid even if PLL1 does not consider it to be valid.
Selects VCO control voltage functionality.
0 (default): normal VCO operation.
1: forces VCO control voltage to midscale.
1: initiates VCO calibration (this is not an autoclearing bit).
0: resets the VCO calibration.
Reserved.
Rev. C | Page 54 of 63
Data Sheet
AD9523-1
Table 48. VCO Divider Control
Address
0x0F4
Bits
7
6
[5:4]
3
2
[1:0]
Bit Name
Reserved
VCO Divider M2
power-down
VCO Divider M2
Reserved
VCO Divider M1
power-down
VCO Divider M1
Description
Reserved.
1: powers down the divider.
0: normal operation.
Note that VCO Divider M2 connects to Output Channel 4 through Output Channel 9.
Bit 5
Bit 4
Divider Value
0
0
Divide-by-3
0
1
Divide-by-4
1
0
Divide-by-5
1
1
Divide-by-3
Reserved.
1: powers down the divider.
0: normal operation.
Note that VCO Divider M1 connects to all output channels.
Bit 1
Bit 0
Divider Value
0
0
Divide-by-3
0
1
Divide-by-4
1
0
Divide-by-5
1
1
Divide-by-3
Table 49. PLL2 Loop Filter Control
Address
0x0F5
Bits
[7:6]
[5:3]
[2:0]
0x0F6
[7:1]
0
Bit Name
Pole 2 resistor (RPOLE2)
Description
Bit 7
0
0
1
1
Bit 6
0
1
0
1
RPOLE2
(Ω)
900
450
300
225
Bit 5
0
0
0
0
1
1
1
1
Bit 4
0
0
1
1
0
0
1
1
Bit 3
0
1
0
1
0
1
0
1
Zero resistor (RZERO)
Pole 1 capacitor (CPOLE1)
Reserved
Bypass internal RZERO
resistor
RZERO
(Ω)
3250
2750
2250
2100
3000
2500
2000
1850
CPOLE1
(pF)
0
8
16
24
24
32
40
48
Bit 2
Bit 1
Bit 0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Reserved.
Bypasses the internal RZERO resistor (RZERO = 0 Ω). Requires the use of a series external zero
resistor. This bit is the MSB of the loop filter control register (Address 0x0F5 and Address 0x0F6).
Rev. C | Page 55 of 63
AD9523-1
Data Sheet
Table 50. PLL2 R2 Divider
Address
0x0F7
Bits
[7:5]
[4:0]
Bit Name
Reserved
PLL2 R2 divider
Description
Reserved.
Divide-by-1 to divide-by-31.
00000, 00001: divide-by-1.
Clock Distribution (Register 0x190 to Register 0x1B9)
Table 51. Channel 0 to Channel 13 Control (This Same Map Applies to All 14 Channels)
Address
0x190
Bits
7
6
Bit Name
Invert divider output
Ignore sync
5
Power down channel
4
Lower power mode
(differential modes only)
[3:0]
Driver mode
Description
Inverts the polarity of the divider’s output clock.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
1: powers down the entire channel.
0: normal operation.
Reduces power used in the differential output modes (LVDS/LVPECL/HSTL). This
reduction may result in power savings but at the expense of performance. Note that
this bit does not affect output swing and current, just the internal driver power.
1: low strength/lower power.
0: normal operation.
Driver mode.
Bit 3 Bit 2 Bit 1 Bit 0 Driver Mode
0
0
0
0
Tristate output
0
0
0
1
LVPECL (8 mA)
0
0
1
0
LVDS (3.5 mA)
0
0
1
1
LVDS (7 mA)
0
1
0
0
HSTL-0 (16 mA)
0
1
0
1
HSTL-1 (8 mA)
0
1
1
0
CMOS (both outputs in phase)
+ Pin: true phase relative to divider output
− Pin: true phase relative to divider output
0
1
1
1
CMOS (opposite phases on outputs)
+ Pin: true phase relative to divider output
− Pin: complement phase relative to divider output
1
0
0
0
CMOS
+ Pin: true phase relative to divider output
− Pin: high-Z
1
0
0
1
CMOS
+ Pin: high-Z
− Pin: true phase relative to divider output
1
0
1
0
CMOS
+ Pin: high-Z
− Pin: high-Z
1
0
1
1
CMOS (both outputs in phase)
+ Pin: complement phase relative to divider output
− Pin: complement phase relative to divider output
1
1
0
0
CMOS (both outputs out of phase)
+ Pin: complement phase relative to divider output
− Pin: true phase relative to divider output
1
1
0
1
CMOS
+ Pin: complement phase relative to divider output
− Pin: high-Z
1
1
1
0
CMOS
+ Pin: high-Z
− Pin: complement phase relative to divider output
1
1
1
1
Tristate output
Rev. C | Page 56 of 63
Data Sheet
AD9523-1
Address
0x191
Bits
[7:0]
0x192
[7:2]
Bit Name
Channel divider,
Bits[7:0] (LSB)
Divider phase
[1:0]
Channel divider, Bits[9:8] (MSB)
Description
Division = Channel Divider Bits[9:0] + 1. For example, [9:0] = 0 is divided by 1, [9:0] = 1
is divided by 2 … [9:0] = 1023 is divided by 1024. 10-bit channel divider, Bits[7:0] (LSB).
Divider initial phase after a sync is asserted relative to the divider input clock (from the
VCO divider output). LSB = ½ of a period of the divider input clock.
Phase = 0: no phase offset.
Phase = 1: ½ period offset, …
Phase = 63: 31.5 period offset.
10-bit channel divider, Bits[9:8] (MSB).
Table 52. PLL1 Output Control (PLL1_OUT, Pin 72)
Address
0x1BA
Bits
[7:5]
Bit Name
CLK2 select[2:0]
4
PLL1 output CMOS driver
strength
[3:0]
PLL1 output divider
Description
Bits[2:0] of the VCO divider channel select.
Bit 7 selects Channel Output 6.
Bit 6 selects Channel Output 5.
Bit 5 selects Channel Output 4.
0: VCO Divider M1.
1: VCO Divider M2.
CMOS driver strength.
1: weak.
0: strong.
0000: divide-by-1.
0001: divide-by-2 (default).
0010: divide-by-4.
0100: divide-by-8.
1000: divide-by-16.
No other inputs permitted.
Table 53. PLL1 Output Channel Control
Address
0x1BB
Bits
7
[6:4]
Bit Name
PLL1 output driver power-down
CLK2 select[5:3]
3
Route VCXO clock to
Channel 3 divider input
Route VCXO clock to
Channel 2 divider input
Route VCXO clock to
Channel 1 divider input
Route VCXO clock to
Channel 0 divider input
2
1
0
Description
PLL1 output driver power-down.
Bits[5:3] of the VCO divider channel select.
Bit 6 selects Channel Output 9.
Bit 5 selects Channel Output 8.
Bit 4 selects Channel Output 7.
0: VCO Divider M1.
1: VCO Divider M2.
1: channel uses VCXO clock. Routes VCXO clock to divider input.
0: channel uses VCO divider output clock.
1: channel uses VCXO clock. Routes VCXO clock to divider input.
0: channel uses VCO divider output clock.
1: channel uses VCXO clock. Routes VCXO clock to divider input.
0: channel uses VCO divider output clock.
1: channel uses VCXO clock. Routes VCXO clock to divider input.
0: channel uses VCO divider output clock.
Rev. C | Page 57 of 63
AD9523-1
Data Sheet
Readback (Address 0x22C to Address 0x22D)
Table 54. Readback Registers (Readback 0 and Readback 1)
Address
0x22C
0x22D
Bits
7
Bit Name
Status PLL2 reference clock
6
Status PLL2 feedback clock
5
Status VCXO
4
Status REF_TEST
3
Status REFB
2
Status REFA
1
Lock detect PLL2
0
Lock detect PLL1
[7:4]
3
Reserved
Holdover active
2
Selected reference
(in auto mode)
1
0
Reserved
VCO calibration in progress
Description
1: OK.
0: off/clocks are missing.
1: OK.
0: off/clocks are missing.
1: OK.
0: off/clocks are missing.
1: OK.
0: off/clocks are missing.
1: OK.
0: off/clocks are missing.
1: OK.
0: off/clocks are missing.
1: locked.
0: unlocked.
1: locked.
0: unlocked.
Reserved.
1: holdover is active (both references are missing).
0: normal operation.
Selected reference (applies only when the device automatically selects the reference;
for example, not in manual control mode).
1: REFB.
0: REFA.
Reserved.
1: VCO calibration in progress.
0: VCO calibration not in progress.
Rev. C | Page 58 of 63
Data Sheet
AD9523-1
Other (Address 0x230 to Address 0x234)
Table 55. Status Signals
Address
0x230
Bits
[7:6]
[5:0]
Bit Name
Reserved
Status Monitor 0 control
Description
Reserved.
Bit 5
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Muxout
0
0
0
0
0
0
GND
0
0
0
0
0
1
PLL1 and PLL2 locked
0
0
0
0
1
0
PLL1 locked
0
0
0
0
1
1
PLL2 locked
0
0
0
1
0
0
Both references are missing (REFA and REFB)
0
0
0
1
0
1
Both references are missing and PLL2 is locked
0
0
0
1
1
0
REFB selected (applies only to auto select mode)
0
0
0
1
1
1
REFA is OK
0
0
1
0
0
0
REFB is OK
0
0
1
0
0
1
REF_TEST is OK
0
0
1
0
1
0
VCXO is OK
0
0
1
0
1
1
PLL1 feedback is OK
0
0
1
1
0
0
PLL2 reference clock is OK
0
0
1
1
0
1
Reserved
0
0
1
1
1
0
REFA and REFB are OK
0
0
1
1
1
1
All clocks are OK (except REF_TEST)
0
1
0
0
0
0
PLL1 feedback is divide-by-2
0
1
0
0
0
1
PLL1 PFD down divide-by-2
0
1
0
0
1
0
PLL1 REF divide-by-2
0
1
0
0
1
1
PLL1 PFD up divide-by-2
0
1
0
1
0
0
GND
0
1
0
1
0
1
GND
0
1
0
1
1
0
GND
0
1
0
1
1
1
GND
Note that all bit combinations after 010111 are reserved.
Rev. C | Page 59 of 63
AD9523-1
Data Sheet
Address
0x231
Bits
[7:6]
[5:0]
Bit Name
Reserved
Status Monitor 1 control
0x232
[7:5]
4
Reserved
Enable Status_EEPROM
on STATUS0 pin
STATUS1 pin divider
enable
3
2
STATUS0 pin divider
enable
1
0
Reserved
Sync dividers
(manual control)
Description
Reserved.
Bit 5
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Muxout
0
0
0
0
0
0
GND
0
0
0
0
0
1
PLL1 and PLL2 locked
0
0
0
0
1
0
PLL1 locked
0
0
0
0
1
1
PLL2 locked
0
0
0
1
0
0
Both references are missing (REFA and REFB)
0
0
0
1
0
1
Both references are missing and PLL2 is locked
0
0
0
1
1
0
REFB selected (applies only to auto select mode)
0
0
0
1
1
1
REFA is OK
0
0
1
0
0
0
REFB is OK
0
0
1
0
0
1
REF_TEST is OK
0
0
1
0
1
0
VCXO is OK
0
0
1
0
1
1
PLL1 feedback is OK
0
0
1
1
0
0
PLL2 reference clock is OK
0
0
1
1
0
1
Reserved
0
0
1
1
1
0
REFA and REFB are OK
0
0
1
1
1
1
All clocks are OK (except REF_TEST)
0
1
0
0
0
0
GND
0
1
0
0
0
1
GND
0
1
0
0
1
0
GND
0
1
0
0
1
1
GND
0
1
0
1
0
0
PLL2 feedback is divide-by-2
0
1
0
1
0
1
PLL2 PFD down divide-by-2
0
1
0
1
1
0
PLL2 REF divide-by-2
0
1
0
1
1
1
PLL2 PFD up divide-by-2
Note that all bit combinations after 010111 are reserved.
Reserved.
Enables the EEPROM status on the STATUS0 pin.
1: enable status.
Enables a divide-by-4 on the STATUS1 pin, allowing dynamic signals to be viewed at a lower
frequency (such as the PFD input clocks). Not to be used with dc states on the status pins,
which occur when the settings of Register 0x231, Bits[5:0] are in the range of 000000 to 001111.
1: enabled.
0: disabled.
Enables a divide-by-4 on the STATUS0 pin, allowing dynamic signals to be viewed at a lower
frequency (such as the PFD input clocks). Not to be used with dc states on the status pins,
which occur when the settings of Register 0x230, Bits[5:0] are in the range of 000000 to 001111.
1: enable.
0: disable.
Reserved.
Set bit to put dividers in sync; clear bit to release. Functions like SYNC pin low.
1: sync.
0: normal.
Rev. C | Page 60 of 63
Data Sheet
AD9523-1
Table 56. Power-Down Control
Address
0x233
Bits
[7:3]
2
Bit Name
Reserved
PLL1 power-down
1
PLL2 power-down
0
Distribution
power-down
Description
Reserved.
1: power-down (default).
0: normal operation.
1: power-down (default).
0: normal operation.
Powers down the distribution.
1: power-down (default).
0: normal operation.
Table 57. Update All Registers
Address
0x234
Bits
[7:1]
0
Bit Name
Reserved
IO_Update
Description
Reserved.
This bit must be set to 1 to transfer the contents of the buffer registers into the active registers,
which happens on the next SCLK rising edge. This bit is self clearing; that is, it does not have to be
set back to 0.
1 (self clearing): update all active registers to the contents of the buffer registers.
EEPROM Buffer (Address 0xA00 to Address 0xA16)
Table 58. EEPROM Buffer Segment
Address
0xA00
to
0xA16
Bits
[7:0]
Bit Name
EEPROM Buffer
Segment Register 1
to EEPROM Buffer
Segment Register 23
Description
The EEPROM buffer segment section stores the starting address and number of bytes that are to
be stored and read back to and from the EEPROM. Because the register space is noncontiguous,
the EEPROM controller needs to know the starting address and number of bytes in the register
space to store and retrieve from the EEPROM. In addition, there are special instructions for the
EEPROM controller: operational codes (that is, IO_Update and end-of-data) that are also stored in
the EEPROM buffer segment. The on-chip default setting of the EEPROM buffer segment registers
is designed such that all registers are transferred to/from the EEPROM, and an IO_Update is issued
after the transfer (see the Programming the EEPROM Buffer Segment section).
EEPROM Control (Address 0xB00 to Address 0xB03)
Table 59. Status_EEPROM
Address
0xB00
Bits
[7:1]
0
Bit Name
Reserved
Status_EEPROM
(read only)
Description
Reserved.
This read-only bit indicates the status of the data transferred between the EEPROM and the buffer
register bank during the writing and reading of the EEPROM. This signal is also available at the
STATUS0 pin when Register 0x232, Bit 4, is set.
0: data transfer is complete.
1: data transfer is not complete.
Table 60. EEPROM Error Checking Readback
Address
0xB01
Bits
[7:1]
0
Bit Name
Reserved
EEPROM data error
(read only)
Description
Reserved.
This read-only bit indicates an error during the data transfer between the EEPROM and the buffer.
0: no error; data is correct.
1: incorrect data detected.
Rev. C | Page 61 of 63
AD9523-1
Data Sheet
Table 61. EEPROM Control 1
Address
0xB02
Bits
[7:2]
1
Bit Name
Reserved
Soft_EEPROM
0
Enable EEPROM write
Description
Reserved.
When the EEPROM_SEL pin is tied low, setting the Soft_EEPROM bit resets the AD9523-1
using the settings saved in EEPROM.
1: soft reset with EEPROM settings (self clearing).
Enables the user to write to the EEPROM.
0: EEPROM write protection is enabled. User cannot write to EEPROM (default).
1: EEPROM write protection is disabled. User can write to EEPROM.
Table 62. EEPROM Control 2
Address
0xB03
Bits
[7:1]
0
Bit Name
Reserved
REG2EEPROM
Description
Reserved.
Transfers data from the buffer register to the EEPROM (self clearing).
1: setting this bit initiates the data transfer from the buffer register to the EEPROM (writing
process); it is reset by the I²C master after the data transfer is done.
Rev. C | Page 62 of 63
Data Sheet
AD9523-1
OUTLINE DIMENSIONS
10.10
10.00 SQ
9.90
0.60
0.42
0.24
0.60
0.42
0.24
0.30
0.23
0.18
55
54
72
1
PIN 1
INDICATOR
PIN 1
INDICATOR
9.85
9.75 SQ
9.65
0.50
BSC
0.50
0.40
0.30
18
37
19
36
TOP VIEW
BOTTOM VIEW
0.80 MAX
0.65 TYP
12° MAX
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
0.25 MIN
8.50 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VNND-4
06-25-2012-A
1.00
0.85
0.80
6.15
6.00 SQ
5.85
EXPOSED
PAD
Figure 48. 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
10 mm × 10 mm Body, Very Thin Quad
(CP-72-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD9523-1BCPZ
AD9523-1BCPZ-REEL7
AD9523-1/PCBZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
72-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
72-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
Z = RoHS Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2010–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09278-0-9/15(C)
Rev. C | Page 63 of 63
Package Option
CP-72-7
CP-72-7