AN-1066: Power Supply Considerations for AD9523, AD9524, and AD9523-1 Low Noise Clocks (Rev. 0) PDF

AN-1066
APPLICATION NOTE
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Power Supply Considerations for AD9523, AD9524, and AD9523-1 Low Noise Clocks
by Matthew Felmlee
The AD9523, AD9524, and AD9523-1 clock products offer
an alternative single-chip solution with superior integration,
performance, and power consumption characteristics.
INTRODUCTION
This application note is a guide to help users understand how
the design of the power supply management can affect the
performance of the Analog Devices, Inc., AD9523, AD9524,
and AD9523-1 family of low noise and low power clock
products. Also described are the details of system board layout
and frequency planning.
In all applications, the clock products require 1.8 V and 3.3 V
supplies. Various noise and coupling scenarios should be considered during system board design to ensure that all noise and
spurious impact are understood.
VCXO
LDO_PLL1
LF1_EXT_CAP
OSC_CTRL
OSC_IN
OSC_IN
PLL1_OUT
STATUS0/ STATUS1/
SP0
SP1 LF2_EXT_CAP
LDO_VCO VDD1.8_OUT[x:y] VDD3_OUT[x:y]
STATUS MONITOR
LOCK DETECT/
SERIAL PORT
ADDRESS
÷D1
REFA
REFA
LOCK
DETECT
÷R1
SWITCHOVER
CONTROL
REF_SEL
FANOUT
REF_TEST
P
F
D
∆t
EDGE
SELECT
OUT13
OUT13
÷D
∆t
EDGE
SELECT
OUT12
OUT12
÷D
∆t
EDGE
SELECT
OUT11
OUT11
÷D
∆t
EDGE
SELECT
OUT10
OUT10
÷D
∆t
EDGE
SELECT
OUT9
OUT9
÷D
∆t
EDGE
SELECT
OUT8
OUT8
÷D
∆t
EDGE
SELECT
OUT7
OUT7
÷D
∆t
EDGE
SELECT
OUT6
OUT6
÷D
∆t
EDGE
SELECT
OUT5
OUT5
÷D
∆t
EDGE
SELECT
OUT4
OUT4
÷D
∆t
EDGE
SELECT
OUT3
OUT3
÷D
∆t
EDGE
SELECT
OUT2
OUT2
÷D
∆t
EDGE
SELECT
OUT1
OUT1
÷D
∆t
EDGE
SELECT
OUT0
OUT0
M1
LOOP
FILTER
LOCK
DETECT
CHARGE
PUMP
P
F
D
÷R1
REFB
REFB
÷D
÷R2
×2
FANOUT
CHARGE
PUMP
LOOP
FILTER
VCO
M2
÷R1
÷N1
÷N2
PLL1
PLL2
SDIO/SDA
SDO
SCLK/SCL
CS
RESET
PD
EEPROM_SEL
CONTROL
INTERFACE
(SDI AND I2C)
EEPROM
ZD_IN
ZD_IN
AD9523-1
LDO_DIV_MI
VDD3_VCO
Figure 1. AD9523-1 Top Level Diagram
Rev. 0 | Page 1 of 12
SYNC
08921-001
VDD3_PLL
AN-1066
Application Note
TABLE OF CONTENTS
Introduction ...................................................................................... 1 Power Supply Noise...........................................................................3 Revision History ............................................................................... 2 Power Supply Configuration............................................................5 Noise Source Basics .......................................................................... 3 REVISION HISTORY
11/10—Revision 0: Initial Version
Rev. 0 | Page 2 of 12
Application Note
AN-1066
0
NOISE SOURCE BASICS
–10
Noise sources can be grouped into one of two categories:
intrinsic circuit device noise and external interference. Circuit
noise is common to all integrated circuit designs and includes
sources such as thermal noise, flicker noise, and shot noise.
External source examples include power supply noise and
electromagnetic interference. This application note focuses on
external noise sources of power supply noise and noise
associated with coupling from one clock output to another.
–20
(dBc/Vrms)
–30
–40
–50
–60
–70
VDD3_OUT9 dBc/Vrms HSTL 16mA
VDD3_PLL2 dBc/Vrms HSTL 16mA
VDD3_PLL1 dBc/Vrms HSTL 16mA
VDD1.8_OUT9 dBc/Vrms HSTL 16mA
–80
1
10
100
1k
10k
FREQUENCY (kHz)
Figure 2. AD9523 Supply Pushing Gain
Following is an example of how to derive the LDO noise
requirements for the VDD3_OUT[x:y] supply (other supply
pins are done similarly).
–80
1:
2:
3:
4:
5:
6:
7:
–90
–100
1kHz, –123.1dBc/Hz
10kHz, –133.8dBc/Hz
100kHz, –140.5dBc/Hz
1MHz, –149.0Bc/Hz
10MHz, –161.5dBc/Hz
40MHz, –162.1dBc/Hz
800kHz, –146.9dBc/Hz
–110
–120
1
–130
2
–140
3
–150
–160
–170
7
4
NOISE:
ANALYSIS RANGE x: START 10kHz TO STOP 40MHz
INTG NOISE: –81.0dBc/40MHz
RMS NOISE: 126.6µRAD
7.3mdeg
RMS JITTER: 164.0fsec
RESIDUAL FM: 1.7kHz
–180
100
1k
10k
100k
FREQUENCY (Hz)
1M
5
10M
6
09278-014
To measure the PSR of the circuit power supply, an ac signal is
placed on the dc power pin, and the spur that is generated is
measured at the clock output. This ac signal generates an AMto-AM, AM-to-PM, or a combination of both at the clock
output. As previously mentioned in the case of an ADC, it only
responds to a phase jitter. If using a spectrum analyzer to
measure the spurious signal, there is no easy way to determine
if the spurious tone is AM or PM. Either a limiting amplifier is
required before the spectrum analyzer or an ADC can be used
to measure the clock spurious. The spurious signal is a measure
of the output phase noise generated from the amplitude input
ripple over a wide frequency range (10 Hz to 10 MHz is
common) and is expressed in decibels (dBc/V rms). The data
illustrated in Figure 2 is the amount of phase noise (spurious)
specified in dBc/Hz vs. per 1 V rms of sinusoidal tone on each
of the power supplies of a 122.88 MHz clock signal.
–90
PHASE NOISE (dBc/Hz)
Power supply rejection (PSR) is how well a circuit rejects ripple
coming from the input power supply at various frequencies.
This is very critical to maintain the very low noise and spurious
performance that is required in many RF and wireless applications. In the case of an ADC clock application, amplitude noise
(AM) is not as critical to the encode clock of an ADC because
the sampling occurs at the clock edge. In this case, clock jitter
or phase noise is the dominant cause of reduced ADC performance (see the AN-756 Application Note, Sampled Systems
and the Effects of Clock Phase Noise and Jitter). However, if
AM noise is converted to PM noise (time jitter), the ADC performance is degraded. For this reason, when referring to PSR in
this application note, it is the measure of rejection of AM-to-PM
conversion.
08921-002
POWER SUPPLY NOISE
Figure 3. AD9523-1 Phase Noise, Output = 122.88 MHz
(VCXO = 122.88 MHz, Crystek VCXO CVHD-950); Doubler On
From Figure 3, the 100 kHz offset phase noise is −137.7 dBc/Hz.
To only impact the phase noise by 0.5 dB, the noise due to
power supply must be at least 10 dB below or −147.7 dBc/Hz.
From Figure 2, there is 25 dB of internal power supply rejection
of the VDD3_OUT9 supply pin. Therefore, the noise on this pin
can be −147.7 dBc/Hz − (−25 dBc V rms) = 10(−122.7 dBrms/20) = 0.7 μV
rms at 100 kHz offset.
Rev. 0 | Page 3 of 12
AN-1066
Application Note
Table 1 lists typical phase noise requirements for either the
VCXO sent to any of the outputs or the standard PLL2 sent to
the outputs. Noise specification for the supply pins were then
generated using the method described previously. The results
are listed in Table 2 through Table 5.
Table 1. VCXO and PLL at Output Driver Requirements
VCXO at Output
−128
−140
−145
−148
−156
Clock at Output
−123
−135
−137
−139
−156
Table 2. VDD3_PLL1 Noise Specifications
Supply Characteristics: VDD3.3_PLL1
Noise spectral density at 1 kHz
VCXO
Clock
Noise spectral density at 10 kHz
VCXO
Clock
Noise spectral density at 100 kHz
VCXO
Clock
Noise spectral density at 800 kHz
Output Ripple from 1 kHz to 60 MHz
Unit
8
14
μV/√Hz max
μV/√Hz max
59
105
μV/√Hz max
μV/√Hz max
12
33
2
6
μV/√Hz max
μV/√Hz max
μV/√Hz max
mV p-p max
Unit
μV/√Hz max
μV/√Hz max
μV/√Hz max
μV/√Hz max
mV p-p max
Supply Characteristics: VDD3.3_OUT[x:y]
14 Outputs
Noise Spectral Density at 1 kHz
VCXO
Clock
Noise Spectral Density at 10 kHz
VCXO
Clock
Noise Spectral Density at 100 kHz
VCXO
Clock
Output Ripple from 1 kHz to 60 MHz
Unit
359
638
nV/√Hz max
nV/√Hz max
90
160
nV/√Hz max
nV/√Hz max
32
91
18
0.26
nV/√Hz max
nV/√Hz max
nV/√Hz max
mV p-p max
Limit
Unit
2.5
4.5
μV/√Hz max
μV/√Hz max
0.7
1.2
μV/√Hz max
μV/√Hz max
0.25
0.8
2
μV/√Hz max
μV/√Hz max
mV p-p max
Figure 4 contains two phase noise traces of a 122.88 MHz clock
output. One trace has elevated noise in the region of 10 kHz
from the other. This due to the 1.8 V output supply noise being
too high. The other trace that is lower in this region is measured
while using an Analog Devices ADP150 1.8 V linear regulator
as the output supply.
–90
–95
–100
PHASE NOISE (dBc/Hz)
Limit
40
48
17
2
16
Limit
Table 5. VDD3_OUT[x:y] Noise Specifications
Limit
Table 3. VDD3_PLL2 Noise Specifications
Supply Characteristics: VDD3.3_PLL2
Noise Spectral Density at 1 kHz
Noise Spectral Density at 10 kHz
Noise Spectral Density at 100 kHz
Noise Spectral Density at 800 kHz
Output Ripple from 1 kHz to 60 MHz
Supply Characteristics: VDD1.8_OUT[x:y]
Noise Spectral Density at 1 kHz
VCXO
Clock
Noise Spectral Density at 10 kHz
VCXO
Clock
Noise Spectral Density at 100 kHz
VCXO
Clock
Noise Spectral Density at 800 kHz
Output Ripple from 1 kHz to 60 MHz
–105
–110
–115
–120
–125
–130
–135
–140
–145
–150
–155
–160
1:
2:
3:
4:
5:
6:
7:
x:
1
100Hz, –102.7482dBc/Hz
1kHz, –122.0441dBc/Hz
10kHz, –131.9688dBc/Hz
100kHz, –140.3949dBc/Hz
1MHz, –148.7617dBc/Hz
10MHz, –161.2288dBc/Hz
40MHz, –161.8934dBc/Hz
START 1kHz
STOP 40MHz
CENTER 20.0005MHz
SPAN 39.999MHz
2
3
4
NOISE:
ANALYSIS RANGE X: BAND MARKER
ANALYSIS RANGE Y: BAND MARKER
INTG NOISE: –79.9945dBc/40MHz
RMS NOISE: 141.51µRAD
8.10795mdeg
RMS JITTER: 183.285fsec
RESIDUAL FM: 1.71012kHz
–165
–170
100
1k
10k
100k
5
7
6
1M
10M
FREQUENCY (Hz)
Figure 4. Example of Power Supply Noise Causing Noise
Rev. 0 | Page 4 of 12
08921-104
Freq
1
10
40
100
800
Table 4. VDD1.8_OUT[x:y] Noise Specifications
Application Note
AN-1066
The green, bordered areas highlight sections of the output
channels that share the same 1.8 V and 3.3 V supply
connection. The connections are in pairs and for this reason
have the highest coupling to each other.
POWER SUPPLY CONFIGURATION
Figure 5 illustrates the various power supply connections for the
AD9523. Notes provide information to what circuit blocks are
powered from each supply pin and how interaction of various
supply domains may cause spurious signals.
The red and blue circles highlight how the supply domains are
shared on the evaluation board.
Figure 6 illustrates the power supply routing of the output
channel circuit blocks of the AD9523. The same routing applies
for the AD9524, minus OUT6 through OUT13. Figure 7 is for
AD9523-1. These figures are used to illustrate the sources of
channel-to-channel coupling, which consist of the following:
Shared supplies (dividers/drivers)
Package (bond wire proximity)
Evaluation board (traces/terminations)
VCO dividers (supplies/muxes pertain to AD9523-1 dual
dividers)
3.3V FOR EACH PAIR OF OUTPUTS NEEDS TO BE SEPARATED
FROM EACH OTHER FOR OPTIMIZED ISOLATION BETWEEN PAIRS.
IF THEY ARE ALL THE SAME FREQUENCY OUTPUT, 3.3V CAN BE TOGETHER.
THIS IS A PLL2 SUPPLY
(EVERYTHING EXCEPT VCO/VCO_DIV)
AND NEEDS TO BE ISOLATED.
PLL1_OUT
ZD_IN
ZD_IN
VDD1.8_PLL2
OUT0
OUT0
VDD3_OUT[0:1]
OUT1
OUT1
VDD1.8_OUT[0:3]
OUT2
OUT2
VDD3_OUT[2:3]
OUT3
OUT3
EEPROM_SEL
STATUS0/SP0
STATUS1/SP1
1.8V FOR EACH PAIR OF OUTPUT
NEEDS TO BE SEPARATED
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
PLL1_OUT IS NOT
RECOMMENDED TO BE USED
WHEN SPUR IS A CONCERN.
3.3V
1.8V
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
PLL1 1.8V LDO BP
PLL1 SUPPLY
AD9523
THE EXPOSED PAD IS THE ELECTRICAL GND
AND A THERMAL DISSIPATION PAD; FOR
BOTH REASONS, A SOLID GND CONNECTION
IS REQUIRED
VCO DIVIDER 1.8V LDO BP
VCO AND VCO DIVIDER SUPPLY
VCO LDO BYPASS
PLL1 REF SUPPLY
VDD1.8_OUT[4:5]
OUT4
OUT4
IF THIS PAIR IS USED
VDD3_OUT[4:5] FOR RxADC, ITS 3.3V
OUT5
SHOULD BE ISOLATED.
OUT5
VDD1.8_OUT[6:7]
OUT6
BECAUSE THE ADC IS ON TOP
OUT6
AND THE DAC IS ON THE BOTTOM,
VDD3_OUT[6:7] ASSIGNING THIS PAIR FOR LVDS IS
OUT7
GOOD FOR ISOLATION.
OUT7
VDD1.8_OUT[8:9]
OUT8
IF THIS PAIR IS USED
OUT8
VDD3_OUT[8:9] FOR TxDAC, ITS 3.3V
OUT9
SHOULD BE ISOLATED.
OUT9
WITHIN A PAIR, THE ISOLATION IS IN
THE WORST CASE; AVOID USING THE
SAME PAIR FOR 2 DIFFERENT FREQUENCIES.
SINGLE-ENDED OUTPUT IS ALWAYS A STRONG
NOISE SOURCE TO OTHER OUTPUTS,
SO PLACE THEM CAREFULLY.
IF THIS GROUP IS CONFIGURED AS CMOS, ITS 3.3V
MUST BE ISOLATED FROM OTHERS. FOR UNUSED CMOS PIN,
CONSIDER SETTING IT TO OPPOSITE POLARITY AND PLACE A
DUMMY CAPACITIVE LOAD ON IT TO MINIMIZE ITS NOISE ON THE SUPPLY.
NOTES
1. A PAIR OF OUTPUTS SHARE A SUPPLY PIN. FOR EXAMPLE, PIN 47 (OUT6)/PIN 46 (OUT6) AND PIN 44 (OUT7)/PIN 43 (OUT7)
SHARE THE SAME SUPPLY, PIN 48 (VDD1.8_OUT[6:7]).
Figure 5. Power Supply Connections of the AD9523
Rev. 0 | Page 5 of 12
08921-105
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
3.3V FOR PIN 2, PIN 13, AND PIN 18
NEEDS TO BE SEPARATED
FROM EACH OTHER
FOR OPTIMIZED ISOLATION.
LDO_PLL1
VDD3_PLL1
REFA
REFA
REFB
REFB
LF1_EXT_CAP
OSC_CTRL
OSC_IN
OSC_IN
LF2_EXT_CAP
LDO_PLL2
VDD3_PLL2
LDO_VCO
PD
REF_SEL
SYNC
VDD3_REF
RESET
CS
SCLK/SCL
SDIO/SDA
SDO
REF_TEST
OUT13
OUT13
VDD3_OUT[12:13]
OUT12
OUT12
VDD1.8_OUT[12:13]
OUT11
OUT11
VDD3_OUT[10:11]
OUT10
OUT10
VDD1.8_OUT[10:11]
•
•
•
•
AN-1066
Application Note
SHARED IN DIE
(1.8V*)
SHARED ON
BOARD
(3.3V)
SHARED ON
BOARD
(1.8V)
OUT13
OUT13
OUT12
OUT12
÷D
∆t
EDGE SELECT
÷D
∆t
EDGE SELECT
÷D
∆t
EDGE SELECT
÷D
∆t
EDGE SELECT
÷D
∆t
EDGE SELECT
÷D
∆t
EDGE SELECT
÷D
∆t
EDGE SELECT
÷D
∆t
EDGE SELECT
÷D
∆t
EDGE SELECT
÷D
∆t
EDGE SELECT
OUT5
OUT5
OUT4
OUT4
÷D
∆t
EDGE SELECT
OUT3
OUT3
÷D
∆t
EDGE SELECT
OUT2
OUT2
÷D
∆t
EDGE SELECT
÷D
∆t
EDGE SELECT
OUT1
OUT1
OUT0
OUT0
OUT11
OUT11
OUT10
OUT10
OUT9
OUT9
OUT8
OUT8
OUT7
OUT7
OUT6
OUT6
NOTES
1. SAME CONNECTIONS APPLY FOR THE AD9524,
MINUS OUT6 THROUGH OUT13.
*OUT0 TO OUT3 SHARE 1.8V.
08921-004
SHARED IN DIE
(3.3V)
Figure 6. Output Driver Power Supply Connections of the AD9523
M1
÷3, ÷4, ÷5
M2
÷3, ÷4, ÷5
FANOUT
SHARED IN DIE
(1.8V)
SHARED ON
BOARD
(3.3V)
SHARED ON
BOARD
(1.8V)
OUT13
OUT13
OUT12
OUT12
÷D
∆t
EDGE SELECT
÷D
∆t
EDGE SELECT
÷D
∆t
EDGE SELECT
÷D
∆t
EDGE SELECT
÷D
∆t
EDGE SELECT
÷D
∆t
EDGE SELECT
÷D
∆t
EDGE SELECT
÷D
∆t
EDGE SELECT
÷D
∆t
EDGE SELECT
÷D
∆t
EDGE SELECT
OUT5
OUT5
OUT4
OUT4
÷D
∆t
EDGE SELECT
OUT3
OUT3
÷D
∆t
EDGE SELECT
OUT2
OUT2
÷D
∆t
EDGE SELECT
OUT1
OUT1
÷D
∆t
EDGE SELECT
OUT0
OUT0
FANOUT
OUT11
OUT11
OUT10
OUT10
OUT9
OUT9
OUT8
OUT8
OUT7
OUT7
OUT6
OUT6
Figure 7. Output Driver Power Supply Connections of the AD9523-1
Rev. 0 | Page 6 of 12
08921-005
SHARED IN DIE
(3.3V)
Application Note
AN-1066
How to Interpret Table 6
One method to lower the coupling is to use the lowest output
amplitude possible for each of the outputs, For example, when a
low noise critical output is operating in LVPECL mode, configure an aggressor channel to operate in LVDS mode. The simple
fact that LVDS has less ac voltage swing lowers the coupling.
On the left most column of Table 6 are the measured outputs
with a clock frequency of 245.76 MHz. Across the top of Table 6
lists another output configured for 15.68 MHz, referred to as
the aggressor. Each one of these outputs was turned on in
LVPECL mode one at a time while at the same time having one
aggressor turned on. The highest spurious level was recorded
as a result of either the sum or the difference of the measured
channel and the aggressor. The level of the spur was divided
into three different categories to illustrate the coupling
mechanism.
Observe Row OUT5 and Column OUT8, listed as L. In this
case, the 3.3 V and 1.8 V supplies are separated on the AD9523,
and only the 1.8 V domain is shared on the board.
REF LVL
5dBm
MARKER 1 [T1]
4.05dBm
245.99198397MHz
1
RBW
VBW
SWT
5
0
Category H is the highest category. An H occurs whenever the
aggressor shares the same 3.3 V and 1. 8 V on the die. Nothing
can be done externally to the part to reduce this coupling.
Proper frequency planning by putting the same frequency on
these outputs eliminates coupling.
10kHz
10kHz
10s
1 [T1]
1 [T1]
–10
2 [T1]
–20
3 [T1]
(dBm)
–30
Category M is the moderate category. An M occurs whenever
the VDD1.8_OUT supply is located between the measured
output and the aggressor, for example measuring OUT10 with
the aggressor on OUT9. These outputs do not share the 3.3 V
and 1.8 V supplies on the die, but the 1.8 V supply for Channel 10
is located directly beside the aggressor, OUT9.
4 [T1]
RF ATT 30dB
UNIT
dBm
4.05dBm
245.99198397MHz
–72.79dB
122.64529858MHz
–72.78dB
–123.44689379MHz
–79.50dB
188.37675351MHz
–80.09dB
157.11422846MHz
–40
–50
–60
1
2
–70
4
3
–90
–95
CENTER 245.5911824MHz
40MHz/
SPAN 400MHz
08921-006
–80
Figure 8. OUT5 with Aggressor OUT8
Category L is the lowest category. An L occurs whenever the
measured channel supply is from the aggressor. Proper frequency planning is achieved by placing channels such that
their sum and difference frequency fall outside the band of
the measured frequency.
The AD9523 evaluation board was designed to separate the
supply domain as much as possible. It is costly to have a
separate LDO regulator for each supply pin. For example,
OUT4 through OUT7 share the same LDO regulator. The
supply connections on the evaluation board were designed to
have a star connection back to the LDO output.
Table 6. Channel-to-Channel Coupling for AD9523-1 1
1.8 V Board
3.3 V Board
On-Chip
Measured
Outputs
(245.76 MHz)
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
1
OUT0 to OUT3
OUT0 to OUT3
3.3 V and 1.8 V
3.3 V and 1.8 V
OUT4 to OUT9
OUT4 to OUT7
OUT8 to OUT9
3.3 V and 1.8 V
3.3 V and 1.8 V
3.3 V and 1.8 V
Aggressor (15.68 MHz)
OUT0
OUT4
L
L
L
L
H
M
M
L
L
L
L
L
L
L
L
L
L
OUT1
H
M
M
L
L
L
L
L
L
L
L
L
L
OUT2
M
M
H
L
L
L
L
L
L
L
L
L
L
OUT3
M
M
H
L
L
L
L
L
L
L
L
L
L
H
M
M
L
L
L
L
L
L
OUT5
L
L
L
L
H
M
M
L
L
L
L
L
L
OUT6
L
L
L
L
M
M
H
M
M
L
L
L
L
OUT7
L
L
L
L
M
M
H
M
M
L
L
L
L
L = lowest coupling, M = moderate coupling, H = highest coupling.
Rev. 0 | Page 7 of 12
OUT8
L
L
L
L
L
L
M
M
H
M
M
L
L
OUT9
L
L
L
L
L
L
M
M
H
M
M
L
L
OUT10 to OUT13
OUT10 to OUT13
3.3 V and 1.8 V
3.3 V and 1.8 V
OUT10
L
L
L
L
L
L
L
L
L
L
H
M
M
OUT11
L
L
L
L
L
L
L
L
L
L
H
M
M
OUT12
L
L
L
L
L
L
L
L
L
L
M
M
H
OUT13
L
L
L
L
L
L
L
L
L
L
M
M
H
AN-1066
Application Note
VCO Divider M1 and M2 Coupling (AD9523-1 Only)
The AD9523-1 offers two parallel VCO dividers to provide
additional frequency planning and flexibility. The outputs from
the VCO dividers, M1 and M2, couple to each other to some
degree. Table 7 and Table 8 provide the amount of couple that
can be expected for each divider setting. The tables have the
following conditions:
•
They list the highest mixing product (m × ωc ± n × ωm)
between M1 and M2 dividers in an 800 MHz span.
•
The numbers below spur levels are the spur frequency
offsets from the carrier.
•
The numbers below the divisors are the output frequencies
of the dividers.
•
M1 mixes onto M2 more than M2 does onto M1.
Spurs are present on both sidebands, but Table 7 and Table 8 list
only the highest spurs in an 800 MHz span (carrier ± 400 MHz).
Therefore, for some divider settings, the actual aggressor
frequencies happen to fall just outside of this span. For example,
when M2 = ÷3, its output is roughly 1 GHz, and when M1 = ÷5,
its output is roughly 600 MHz. If given a channel being driven
by M2 (1 GHz) and let M1 be the aggressor (600 MHz), coupling
spurs pop up at ±200 MHz while only one of the ±400 MHz
spurs is visible within the 800 MHz span. The 600 MHz aggressor frequency (fc – 400 MHz) is present at −56.7 dBc, but it is
not the highest spur measured. Instead, a different mixed product at −54.9 dBc was recorded in Table 8 and that happened to
be +200 MHz offset from the carrier. Table 7 and Table 8 list all
possible combinations of VCO divider settings and the respective coupling between them. The measurements were completed
with both PLLs unlocked (pump up), and no other frequencies
present on the board. A free running VCO essentially drives the
VCO dividers such that the only spurs present on the spectrum
are those of the VCO dividers coupling to one another.
Table 7. Measured Channel on VCO Divider M1 Aggressor Channel on VCO Divider M2
AD9523-1 VCO DIV Coupling
Measured VCO Divider (M1)
÷3, 996.6 MHz
÷4, 746.6 MHz
÷5, 597.0 MHz
÷3, 996.6 MHz
−72.3, 333.46 MHz
−68.4, 250 MHz
−67.6, 200 MHz
Aggressor (M2)
÷4, 746.6 MHz
−57.3, 250.0 MHz
−73.6, 250 MHz
−63.2, 150 MHz
÷5, 597.0 MHz
−64.1, 200 MHz
−73.1, 300 MHz
−75.4, 400 MHz
Table 8. Measured Channel on VCO Divider M2 Aggressor Channel on VCO Divider M1
AD9523-1 VCO DIV Coupling
Measured VCO Divider (M2)
÷3, 996.6 MHz
÷4, 746.6 MHz
÷5, 597.0 MHz
Aggressor (M1)
÷4, 746.6 MHz
−54.9, 250 MHz
−76.8, 250 MHz
−62.1, 150 MHz
÷3, 996.6 MHz
<−80, no spurs
−60.8, 250 MHz
−58.1, 200 MHz
Rev. 0 | Page 8 of 12
÷5, 597.0 MHz
−54.9, 200 MHz
−58.7, 150 MHz
<−80, no spurs
Application Note
AN-1066
A VCO divider of 3 and a VCO divider of 4 are needed. Refer to
Table 7 and Table 8 to determine which divider, M1 or M2,
should be set to ÷3 or ÷4. Table 10 lists a summary of spurious
levels of all the different combinations of ÷3 and ÷4 at M1 and
M2 outputs.
Example Output-to-Output Coupling Considerations
This section considers the AD9523-1 configuration for a
4Rx/4Tx radio implementation. The required frequencies
are summarized in Table 9.
Table 9. 4Rx/4Tx Example
No. of Required
Frequencies
2
4
2
4
2
Function
Two dual Rx ADCs, 14-bit,
IF 140 MHz
Two dual Tx DACs, 14-bit,
IF 140 MHz
CPRI™
LO reference
Tx digital predistortion
(DPD) ADC 12-bit
Table 10. M1 and M2 Divider Summary
Frequency (MHz)
184.32
983.04
122.88
61.44
245.76
Each of the required clocks has different noise and spurious
requirements. Typically, the Rx ADC and Tx DAC have the
lowest noise and spurious requirements. Both are 14 bits that
produce a very low SNR (approximately 76 dB SNR), and there
is no additional filtering in this part of the signal chain to
remove any clock spurious.
The CPRI clock specification typically has a noise and spurious
requirement specified in the range from 12 kHz to 20 MHz
offset. Therefore, coupling from other clock outputs outside of
this range may not be of concern.
The LO reference clocks at 61.44 MHz are references for other
local oscillators in the system. The bandwidths of these PLLs are
often designed to be 50 kHz. The response of the LO PLL is that
of a high order low-pass filter, and spurs on the 61.44 MHz
reference are filtered by this response. Therefore, spurs on the
61.44 MHz clocks that are >10 MHz offset are attenuated.
The Tx DPD ADC clocks at 245.76 MHz are used in the digital
predistortion system. The ADC has two fewer bits than the Tx
DAC or Rx ADC, making it approximately 12 dB less sensitive
to noise and spurs.
Select VCO Frequency and VCO Divider
The highest required frequency is 983.04 MHz. This implies a
VCO frequency of 2949.12 MHz with a VCO division of 3. An
Rx ADC frequency of 184.32 MHz is not an integer division
of 983.04 MHz. Therefore, both M1 and M2 VCO dividers are
required. Setting the other VCO divider to 4 produces a frequency of 737.28 MHz, and a channel division of 4 produces
the required 184.32 MHz for the Rx ADC.
Measured
M1 ÷ 3
M1 ÷ 4
M2 ÷ 3
M2 ÷ 4
Aggressor
M2 ÷4
M2 ÷3
M1 ÷4
M1 ÷3
Spur (dBc)
−57.3
−68.4
−55.9
−60.8
From Table
Table 7
Table 7
Table 8
Table 8
The summary shows that when M1 is set to ÷4 and M2 is set to
÷3, the coupling spur is the lowest of −68.4 dBc at 250 MHz offset.
However, before choosing this combination, the final required
frequency must be considered. The spurious levels listed in Table 7
and Table 8 are measured at the VCO divider output frequency
(channel divider = 1). The VCO divider output is divided down
by any further channel division. Using this scenario of M1 set to
÷4, the 737.28 MHz output of M1 must be further divided by 4
to produce the final frequency of 184.32 MHz. This means that
the −68.4 dBc spur on a 737.28 MHz carrier is now reduced by 12
dB to −80.4 dBc on the 184.32 MHz clock.
20 × log(chdiv = 4)
where chdiv is the channel divider.
For the case of an M2 output of 983.04 MHz, if a Tx IF of 140 MHz
is used, the spur is scaled by 17 dB.
20 × log(983.04 MHz/140 MHz)
See the AN-756 Application Note for further details on how
clock spurs and noise affect the ADC noise. Because Table 7 and
Table 8 list only the highest spur, any other VCO coupling spur
is lower than the spurious levels listed in Table 7 and Table 8.
For this example, M1 is set to ÷4 and M2 is set to ÷3.
Assign Frequency to Output Channel
The next step is to assign each frequency to an output channel.
The first consideration is to group the same frequencies on the
outputs that share 3.3 V and 1.8 V internal supply domains.
This means OUT0 and OUT1, OUT2 and OUT3, …, OUT12
and OUT13 are all pairs. The second consideration is the location of the aggressor to the shared 1.8 V supply. For example,
OUT13 and OUT12 share the same 1.8 V supply, but OUT11 is
adjacent to VDD1.8_OUT[12:13].
Rev. 0 | Page 9 of 12
AN-1066
Application Note
ZONE 1
I
I
0.5fS
I
I
1.5fS
fS
2 fS
I
I
3fS
2.5fS
3.5fS
ZONE 2
B
I
I
0.5fS
I
1.5fS
fS
I
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2 fS
I
3fS
2.5fS
3.5fS
ZONE 3
C
I
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0.5fS
I
fS
I
1.5fS
I
2 fS
I
2.5fS
I
3fS
3.5fS
08921-108
A
08921-109
Figure 9. Undersampling Nyquist Zones
Figure 10. ADC FFT fIN = 140 MHz, fCLOCK = 184.32 MHz
For the case of the ADC and DAC, Figure 9 can be used to determine how a clock spurious can alias into the band of interest.
For the example of the Rx ADC, fS = 184.32 MHz, the IF of
140 MHz is in Zone 2, and the IF input aliases to 44.32 MHz.
A clock spur is located on the IF at the same offset as on the
clock. The location of where it aliases can be determined based
on Figure 9. Choose the coupling spur with the least amount of
impact from the aliasing effects of the ADC and DAC.
occurs at the difference between the frequencies of the VCO
divider outputs: 983.04 MHz − 737.28 MHz = 245.76 MHz.
To determine the location on the FFT of the ADC, find the
location of the spurious 140 MHz ± 245.76 MHz. One spur is
at 385.76 MHz, which is in Nyquist Zone 5 and is located at
385.76 MHz − 368.64 MHz = 17 MHz. The other spur falls in
Zone 2 and aliases to 78.5 MHz. The spurious locations match
what was measured in Figure 10.
Figure 10 shows the FFT results of the Rx ADC when all AD9523-1
outputs are running, as configured in Figure 11. The IF frequency
is 44 MHz as expected. There are worst other spurs at 78 MHz
and 17 MHz at −78 dBFs. As previously calculated, a spur
The remaining 61.44 MHz and 122.88 MHz clocks are such
a large offset from the 983.04 MHz that neither clock has any
impact on the system. Figure 11 illustrates the final AD9523-1
output frequency configuration.
Rev. 0 | Page 10 of 12
AN-1066
08921-110
Application Note
Figure 11. AD9523-1 Example Output-to-Output Coupling Considerations
Rev. 0 | Page 11 of 12
AN-1066
Application Note
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
AN08921-0-11/10(0)
Rev. 0 | Page 12 of 12
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