NB3W800LMNGEVB Evaluation Board Manual Contents Introduction .......................................................................................................................................................................................................... 2 Board Features ................................................................................................................................................................................................... 3 Board Layout ....................................................................................................................................................................................................... 3 Power Supplies ................................................................................................................................................................................................... 4 Control Pins......................................................................................................................................................................................................... 4 Differential Clock Inputs and Outputs .............................................................................................................................................................. 5 USB & I2C / SMBus Interface ........................................................................................................................................................................... 6 Pre Power Up...................................................................................................................................................................................................... 6 Power Up Sequence .......................................................................................................................................................................................... 6 Board Schematic ................................................................................................................................................................................................ 7 Bill Of Materials ................................................................................................................................................................................................... 9 1 NB3W800LMNGEVB Evaluation Board Manual Introduction The NB3W800LMNGEVB evaluation board was developed for the NB3W800L (HCSL-Compatible low power NMOS push pull Output). This evaluation board was designed to provide a flexible and convenient platform to quickly evaluate, characterize and verify the operation of the NB3W800L devices. This evaluation board manual contains: Information on the NB3W800L Evaluation Board Assembly Instructions Test and Measurement Setup Procedures Board Schematic and Bill of Materials This manual should be used in conjunction with the device datasheet which contains full technical details on the device specifications and operation. Top View Bottom View 2 Board Features One Board Design/Layout: ● Accommodates the electrical characterization of the NB3W800L (Low power NMOS Push pull outputs) ● Accommodates a custom QFN-48 pogo-pin socket for lab evaluation, or a soldered down QFN-48 package. ● Incorporates on board SDI I2C/SMBus interface circuitry; powered from a USB connection, minimizing cabling. ● Convenient and compact board layout ● 3.3V power supply device operation ● Differential inputs and output signals are accessed via SMA connectors or high impedance probes The evaluation board is with 10” output traces, with 85-Ω differential trace impedance. All Inputs & Outputs have signal access via side-launch SMA connectors, installed, except SDA and SCL. - SDA and SCL can be externally accessed by means of jumper headers & “test-point” anvils (for use with minigrabber cables) Each control pin can be managed directly through an SMA connector or manually with a H/L jumper header; H = VCC, L = DUTGND. Other Board Features There are no vias on the differential I/O metal traces so as to eliminate via impedance and stub effects on the high-speed I/Os. This board accommodates a custom QFN-48 socket for lab evaluation, so there is a socket keep-out area. Stand-offs are installed. Board Layout The NB3W800L QFN-48 Evaluation Board provides a high bandwidth, 43-Ω controlled impedance environment and is implemented in four layers. All layers are constructed with FR4 dielectric material. The first layer is the primary signal layer, including all of the differential inputs and outputs. The second layer is the ground plane. It is dedicated for the SMA connector ground plane and for DUT ground. The third layer is dedicated as the power plane. A portion of this 3rd layer is designated for the device VDD and VDDIO power planes. The fourth layer contains control lines, power supply banana jacks and device power pin bypass capacitors. Layer Stack L1 (top) Signal (FR4) L2 DUTGND (device ground) and SMA Ground, SMAGND L3 VDD, VDDIO (separate device power supplies) L4 (bottom), power supply by-pass capacitors, control pin traces and banana jacks 3 Power Supplies Each VDD, VDDIO and GND power supply have a separate side-launch banana jack Board Layer #2 = SMAGND = DUTGND = 0V. GND Banana Jack = negative power supply for DUTGND and SMAGND. Exposed Pad (EP): The exposed pad footprint on the board is mechanically connected (soldered) to the exposed pad of the QFN-48 package, and is electrically connected to DUTGND power supply, the negative supply of the device. Board Layer #3 = VDDx Power Supplies VDD = positive power supply for VDDA (pins #3, 44) VDDIO = positive power supply for VDDIO (pins #10, 15, 19, 27, 34, 38, 42) VDD & VDDIO have the power supply filtering per datasheet, and the bypass caps are located on top, by the banana jacks. All VDD/VDDA /VDDIO device pins have 0.1uF bypass caps installed on bottom side of package pins. Board is capable of measuring device IDD & IDDIO. Control Pins Each control pin can be managed directly through an SMA connector or manually with a H/L jumper header; Tri-Level Input Pins - HBW_BYP_LBW# On the 85ohm, 10inch output trace boards, the tri level input pin, HBW, has a 4.7kohm pull up to VDD and a 4.7kohm pull down to GND resistors; defaults to midlevel. Need to jumper for a High or jumper for a Low. HBW - At J31 header, there is a 4.7kΩ pull-up to VDDIO and a 4.7kΩ pull-down to GND for manual control. OE# Pins (Output Enable/Disable Function) There are eight OE# pins available to control differential outputs DIF0/0# to DIF7/7#. All of the OE#s can be controlled individually: 1) externally via the SMA connector for evaluation purposes, no jumper installed on OE#. 2) automatically by GUI control when jumper is installed on OE# in middle header. 3) manually with the convenient High/Low OE# jumper headers. 100M_133M# - Frequency Selection The 100M_133M# frequency selection pin can be controlled manually with the High/Low header jumper (J34) at the SMA or externally with a control signal through the SMA connector; H = 100MHz, L = 133MHz. PWRGD/PWRDN The PWRGD/PWRDN pin can be controlled manually with the High/Low header jumper (J54) at the SMA connector or externally with a control signal through the SMA connector; H = PWRGD, L = PWRDN. 4 Differential Clock Inputs and Outputs Differential Inputs - CLK_IN & CLK_IN# The differential Clock input traces, CLK_IN/CLK_IN#, are routed from the SMA connectors on the right side directly to the DUT; there are no vias on metal traces. CLK_IN & CLK_IN# have resistor pads (R40 & R41) to GND just outside the keep-out area of the socket to terminate a signal generator, if used. 50-ohm resistors are installed. Remove these resistors if CLK_IN & CLK_IN# are driven by another IC device. Differential Outputs - DIFx and DIFx# All eight differential output metal traces are designed to have equal length from the device under test (DUT) pins to the SMA connectors. These outputs have 43-ohm trace impedance (FR4), 85-ohm line-to-line. All of the outputs have SMA connectors installed; there are no vias on the metal traces. Each DIFx output has a provision for CLoad at the SMA; 2pF capacitors are installed on all outputs. Rs & Rp – Located close to DUT, just outside socket area. 43-ohm board - Installed with Rs = 27-Ω and Rp = not installed. HCSL outputs are typically terminated with 50-Ω to ground. This can be easily accomplished by connecting the HCSL outputs to the 50-Ω internal impedance in the oscilloscope. Series R provision at SMA A 0-ohm series resistor is installed between the end of the transmission line and the SMA connector: – – For measuring HCSL outputs with a Hi-Z probe. For measuring HCSL outputs with a 50-Ω scope head. Hi-Z Probe Use 1) Single-ended Hi-Z probes or, 2) Differential Hi-Z probe; (see layout below) A “solder gap” is employed at each output SMA connector. Short the gap with a solder blob or 0-Ω resistor to enable use of a Hi-Z probe. This solder gap is shorted with a 0-ohm resistor. Holes for headers to connect to Hi-Z probes are available, but the header pins are not installed. An optional component can be installed on each output. Additional capacitance loading can be accomplished with this board feature. The NB3W800L EVB was designed with the flexibility to configure the board to measure the differential HCSL or low power NMOS Push Pull outputs with a 50-ohm scope head or High impedance FET probe. The following figure describes the board’s output features: Optional component to Ground, if needed, when shorted to output trace. Ground CLoad (2pF) installed Series R = 0-ohms installed Hi-Z probe Short for use with Hi-Z probe; 0-ohms installed 5 FB_OUT & FB_OUT# - External Feedback Termination Since the FB_OUT & FB_OUT# pins do not drive transmission lines, the board layout has these pins loaded/terminated per datasheet; These pins have series R pads, R82 & R83, to GND located close to the DUT, just outside the socket area. USB & I2C / SMBus Interface The NB3W800L EVB has an on-board I2C/SMBus interface circuitry located in the lower left section of the board. This circuitry will interface with the program and the device via the SDA and SCL input pins, and can control the OE# pins, PLL Mode and Frequency Select directly from the GUI. SCL & SDA - The SMBus Clock (SCL) and Data (SDA) pins are exercised through the on-board I2C interface. In order to enable the I2C control of the DUT, header jumpers J52 & J53 must be shorted. The I2C / SMBus interface circuitry is powered separately from the USB type-B connection and is isolated from device VDD and VDDIO. The USB GND is connected to DUTGND. “Test-point anvils” TP7 & TP8 are available for external control of the device’s SCL and SDA pins by another off-board programmer, allowing other SMBus emulators to be used to program the DUT. If used, remove both jumpers J52 & J53. NB3W800L Evaluation Board Quick Start Lab Set-Up User’s Guide Pre Power Up 1) Connect power supply cables to VDD, VDDIO and DUTGND banana jacks; (do not turn power on, yet) 2) Connect a signal generator to the SMA connectors for the CLK_IN & CLK_IN# inputs, pins 4 and 5. 50‐ohm termination resistors are installed for a signal generator on the board. Set‐up appropriate input signal levels according to the device data sheet. 3) Ensure the PWRGD/PWRDN# pin (Pin #1) is in the Low state before power up (PWRDN#). There is a jumper (J37) on pin 1 to easily select between High and Low. 4) The 100M_133M# and HBW_BYP_LBW pins need to be hardware selected with jumpers J36 and J33 respectively. Power Up Sequence 1) Turn on power supply, 3.3V (VDD & VDDIO) 2) Move PWRGD/PWRDN# jumper to logic High, PWRGD 3) Turn on the Differential Clock Signal for the CLK_IN inputs (HCSL input, VIL = 0V, VIH = 700mV, Frequency based on J36 selection to 100 MHz or 133MHz) 4) Monitor DIF_x/DIF_x# outputs on oscilloscope 6 Value = DNI Value2 = DNI Board Schematic OE_IO[0..7] Value = 27 Value2 = 33 J2 OE0# J4 OE1# J7 OE2# J10 OE3# 1. Trace lenght and the impedance of the nets CLKINR, CLKINR#, CLKIN, and CLKINR# must be same as the outputs. 2. CLKINR and CLKINR# origin should be as close to pin as possible. 3. CLKINR and CLKINR# should be exactly same as any of the output traces w.r.t. load. CLKINR# J19 PR4 SG13 2 1 SMA Jack, End Launch 0 R25 2 1 SMA Jack, End Launch 0 R30 J29 2.0pF_DNP 1 J20 CLKIN# 2 C13 2.0pF_DNP 1 J24 R32 OE7# R31 C11 2.0pF_DNP 2 1 SG21 1 3 5 J1 OE_N1 SMA Jack, End Launch OE_IO1 J5 OE_N2 SMA Jack, End Launch OE_IO2 0_DNP 1 1 1 should be close to SMA VDDIO 1 3 5 2 4 6 VDDIO 1 3 5 2 4 6 VDDIO 1 3 5 2 4 6 VDDIO 1 3 5 2 4 6 VDDIO 1 3 5 2 4 6 VDDIO 2 1 49.9 R41 2 1 R48 17 1 DIF1# 27 OE4# DIF2 21 1 DIF2 27 OE5# DIF2# 22 1 DIF2# 27 OE6# DIF3 25 1 DIF3 27 OE7# DIF3# 26 1 DIF3# 27 CLK_IN DIF4 28 1 DIF4 27 CLK_IN# DIF4# 29 1 DIF4# 27 HBW_BY P_LBW# DIF5 32 1 DIF5 27 100M_133M# DIF5# 33 1 DIF5# 27 VDDIO PWRGD_PWRDN# DIF6 35 1 DIF6 1 7 SCL DIF6# 36 1 DIF6# SDA 27 DIF7 39 1 DIF7 27 DIF7# 40 1 DIF7# + 2 1 R75 2.2 600 VDDA_3 2 1 R76 2.2 1 J44 2 1 1 C26 10uF 10V 1 C22 1uF 10V TP3 C23 1 VDDA_44 100nF 1 2 2 1 C24 1uF 10V 1 R8 2 R11 2 1 SG5 1 R12 OUT1 4 1 2 2 R15 1 R19 2.0pF 2 1 2 C4 2 SG7 1 2.0pF 1 R16 2 SG9 1 2 1 R20 2 SG11 2.0pF 1 R24 2 SG12 2 1 2 SG15 2 SG14 2.0pF 1 R29 2 1 2 C10 SG17 2.0pF 1 R36 2 1 SG22 1 R43 2 2 1 2 C14 2 SG23 2.0pF 1 1 R50 2 SG24 2 SG26 2 C15 SG25 1 R54 2.0pF 1 2 C16 2 J15 DIF1# SMA Jack, End Launch 0 DIF2 SMA Jack, End Launch 2 J17 0 DIF2# SMA Jack, End Launch 2 J22 DIF3 SMA Jack, End Launch 0 2 J25 0 DIF3# SMA Jack, End Launch 0 2 J28 DIF4 SMA Jack, End Launch 2 J30 0 DIF4# SMA Jack, End Launch 2 J32 DIF5 SMA Jack, End Launch R52 SG27 2.0pF 1 R58 2 1 1 2 SG29 1 R62 2 0 2 J35 1 0 2 J39 DIF6 SMA Jack, End Launch R60 SG30 DIF5# SMA Jack, End Launch R56 SG28 DNI 42.2 OUT6 2 PR9 DNI C17 2.0pF DNI 42.2 2 OUT_N6 2 1 DNI 2 C18 SG31 2.0pF 1 R66 2 1 DNI 42.2 2 SG33 1 R70 2 0 2 J40 2 J41 1 0 DIF7 SMA Jack, End Launch R68 SG34 DIF6# SMA Jack, End Launch R64 OUT7 2 1 SG32 2 PR10 DNI C19 2.0pF DNI 42.2 2 OUT_N7 R73 1 DNI 42.2 2 1 0 R46 OUT_N5 2 DNI R69 1 DNI 42.2 2 1 J11 PR8 DNI R65 2 R39 OUT5 1 1 SG20 DNI 42.2 2 R61 0 PR7 2.0pF OUT_N4 1 DIF1 SMA Jack, End Launch R34 DNI 42.2 2 C12 DNI R57 1 SG18 2 1 J8 R27 OUT4 2 DNI R53 1 DNI 42.2 2 1 2 PR5 C8 DNI R49 DIF0# SMA Jack, End Launch R22 OUT_N3 1 1 DNI 42.2 2 R42 0 DIF0 SMA Jack, End Launch R18 SG10 OUT3 1 1 DNI 42.2 2 C6 DNI R35 J6 PR3 2.0pF 2 1 2 R14 OUT_N2 R28 1 SG8 DNI 42.2 2 C5 DNI 1 0 R10 SG6 DNI 42.2 2 R23 J3 PR2 C3 DNI 1 2 R6 SG4 DNI 42.2 2 OUT_N0 3 1 2 1 2 C20 SG35 2.0pF 1 R74 2 SG36 1 0 R72 2 J42 DIF7# SMA Jack, End Launch DNI 42.2 600 2 C27 10uF 10V VDDA1 C25 44 100nF 10 15 19 27 34 38 42 100nF cap on each VDD and VDDA pin, as close to the DUT as possible 1 C28 1 100nF 2 1 C29 100nF 2 C30 1 100nF 2 C31 1 100nF 2 C32 1 100nF 2 VDDA2 2 VDDIO 2 1 + SG3 PR1 VDDA_44 1 TP4 FB2 3 VDDA_3 1 2 2 VDDIO 2 0 R2 1 DNI 42.2 2.0pF 1 SG2 TP2 2 1 C21 10uF 10V 2 OUT2 VDD VDD 1 C2 DNI 1 FB1 1 2.0pF R4 2 TP1 J43 2 DNI R71 VDD 1 OUT_N1 1 R67 27 SG1 2 R63 6 SDA R7 DNI R59 SCL 2 2 R55 27 1 DNI R51 1 J37 1 R45 VDDIO 1 2 3 SMA Jack, End Launch DIF1# 2 J54 PWR OE3# 2 C1 R38 47 1 2 3 J36 1 DIF1 2 VDDIO SMA Jack, End Launch 16 27 R3 2 R33 J34 100M_133M# 27 R26 48 J33 DIF1 4.7K 1 2 3 SMA Jack, End Launch OE2# 49.9 4.7K J31 HBW_BYP_LBW# DIF0# 1 DIF0# R21 5 R47 1 VDDIO OE1# 14 R17 CLKIN PR6 OUT0 1 R13 4 R40 2 R9 41 J26 R37(49.9) and R38(49.9) connector. 2 4 6 37 J21 OE_N7 SMA Jack, End Launch OE_IO7 1 3 5 DIF0 1 DIF0 R5 31 J18 OE_N6 SMA Jack, End Launch OE_IO6 VDDIO 30 J14 OE_N5 SMA Jack, End Launch OE_IO5 2 4 6 24 J12 OE_N4 SMA Jack, End Launch OE_IO4 1 3 5 OE0# 13 R1 23 J9 OE_N3 SMA Jack, End Launch OE_IO3 VDDIO 2 4 6 18 2 2 CLKINR SG19 2 1 SMA Jack, End Launch 0 R37 2 1 SMA Jack, End Launch 0 R44 OE5# 2.0pF_DNP 1 0_DNP J27 J16 OE6# C9 2 CLKIN# CLKIN OE4# CLKINR# SG16 CLKINR J23 C7 2 J13 11 OE_N0 SMA Jack, End Launch OE_IO0 C33 VDDIO 1 100nF 2 VDD7 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 C34 100nF NC/IREF NC1 NC2 2 J46 GND 46 1 2 2 NC3 GNDA NC4 FB3 600 49 45 43 1 20 1 12 1 0 R78 0 R79 0 R80 0 R81 R77 2 Value = DNI Value2 = DNI 2 2 J45 1 2 3 VDD J47 1 2 3 VDD J48 1 2 3 VDD J49 1 2 3 VDD 2 2 TP5 EP FBOUT#/NC# Place the FB5 ferrite bead where GNDA and GND islands1 of copper meet in layout. 1 FBOUT# 8 1 1 1 TP6 FBOUT/NC R83 2 FBOUT Value = DNI 1 Value2 = DNI Keep Pin 8 and Pin 9 test points as close to the DUT as possible. Under the keep-out area of the socket. 0_DNP 1 2 9 R84 R82 2 Value = DNI Value2 = DNI FBOUT# 1 0 2 J50 FBOUT# SMA Jack, End Launch R85 SG37 PR11 1 U1 DNI NB3W800L 0_DNP 2 R91(0 ohm) and R92(0 ohm) R86 should be placed suchSG38 a way so that their uninstallment can completely disconnect the trace with zero stud. FBOUT 1 0 R87 2 J51 FBOUT SMA Jack, End Launch 7 3V3 1 1 R88 10K 1 TP7 SCL 2 SCL J52 2 R89 10K 2 U2 FT2232H 16 1 17 2 SDA 1 J53 18 1 19 TP8 SDA 21 OE_IO0 22 OE_IO1 23 OE_IO2 24 OE_IO3 26 OE_IO4 27 OE_IO5 28 OE_IO6 29 OE_IO7 30 32 33 34 TCK TDI 3V3 VCCIO1 VCCIO2 VCCIO3 VCCIO4 TDO VREGIN TMS VREGOUT GPIOL0 GPIOL1 VCORE1 VCORE2 VCORE4 1 1 R92 10K U3 93LC46B 3V3 8 7 1 2 C49 100nF 10V 6 5 2 VCC CS NC2 CLK NC1 DIN GND DOUT 1 R93 10K 2 R94 10K 2 63 1 62 2 61 3 4 1 R96 2.2K 2 1 5 11 15 25 35 47 51 10 2 1 C36 100nF 1 C37 100nF 2 C38 100nF 2 2 49 12 37 64 1 1 C39 4.7uF 6.3V 1 C40 100nF 1 C41 100nF 2 C42 100nF 2 2 GPIOL3 GPIOH0 3V3 GPIOH1 VPLL GPIOH2 VPHY 9 1 FB4 2 4 1 600 GPIOH3 1 1 GPIOH4 GPIOH5 1 C44 100nF C43 4.7uF 6.3V 2 2 2 FB5 2 1 600 C46 100nF C45 4.7uF 6.3V 2 GPIOH6 BDBUS0 BDBUS1 BDBUS2 BDBUS3 BDBUS4 BDBUS5 BDBUS6 BDBUS7 BCBUS0 BCBUS1 BCBUS2 BCBUS3 BCBUS4 BCBUS5 BCBUS6 BCBUS7 7 USB_DM 8 USB_DP RESET# 14 USB_RST# REF 6 1 R91 1 C48 D1 2 PACDN004 3 OSCI EEDATA OSCO EPAD SUSPEND# PWREN# TEST Y1 12 MHz 10pF 1 5 C R95 2 1 470 2 1 2 LED1 TP9 USB 5V 3V3 3 3 65 1 C50 C 4 1 2 36 60 6 USB 2 1 2 USB 1 C47 10nF 16V 2 12K 1% 2 J62 3 10K 2 EECLK AGND R90 1 1 3V3 2 4 4 EECS GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 1 USB_5V GPIOH7 DP 48 52 53 54 55 57 58 59 50 1 C35 100nF 2 DM 3V3 1 GPIOL2 OE_IO[0..7] 38 39 40 41 43 44 45 46 20 31 42 56 3 10pF 1 13 2 1 1 1 1 1 C52 1uF 10V C53 100nF 2 1 U4 NCP4586, 3.3V 5 IN OUT 3V3 1 EN GND TP10 NC 4 2 C51 1uF 10V 2 TP11 GND TP12 GND TP13 GND TP14 GND 8 Bill Of Materials NB3W800L 85 Ohms, 10" trace board Item Quantity Part Number 1 2 3 20 2 4 C1005C0G1H020C TR3A106K010C2000 GRM155R61A105ME15D 4 5 6 7 8 9 10 11 20 1 3 1 2 1 3 2 0402ZD104KAT2A C1608X5R1A106M C1005X5R0J475M 0402YC103KAT2A GRM1555C1H100JZ01D PACDN004SR BLM18KG601SN1D BLM15AG601SN1D 12 8 67996-206HLF 13 33 142-0701-801 14 15 16 17 18 19 20 7 1 1 1 2 1 1 961103-6404-AR 571-0500 571-0700 571-0100 961102-6404-AR USB-B1SMHSW6 LTST-C190KGKT 21 11 No Part 22 16 ERJ-2GEJ270X 23 27 CRCW04020000Z0ED 24 25 19 16 ERJ-2RKF42R2X ERJ-2RKF42R2X Reference C1,C2,C3,C4,C5,C6,C7,C8, C9,C10,C11,C12,C13,C14, C15,C16,C17,C18,C19,C20 C21,C26 C22,C24,C51,C52 C23,C25,C28,C29,C30,C31, C32,C33,C34,C35,C36,C37, C38,C40,C41,C42,C44,C46, C49,C53 C27 C39,C43,C45 C47 C48,C50 D1 FB1,FB2,FB3 FB4,FB5 J1,J5,J9,J12,J14,J18,J21, J26 J2,J3,J4,J6,J7,J8,J10, J11,J13,J15,J16,J17,J19, J20,J22,J23,J24,J25,J27, J28,J29,J30,J31,J32,J34, J35,J39,J40,J41,J42,J50, J51,J54 J33,J36,J37,J45,J47,J48, J49 J43 J44 J46 J52,J53 J62 LED1 PR1,PR2,PR3,PR4,PR5,PR6, PR7,PR8,PR9,PR10,PR11 R1,R5,R9,R13,R17,R21,R26, R33,R38,R45,R51,R55,R59, R63,R67,R71 R2,R6,R10,R14,R18,R22, R25,R27,R30,R34,R37,R39, R44,R46,R56,R60,R64,R68, R72,R78,R79,R80,R81,R84, R85,R86,R87 R3,R7,R11,R15,R19,R23, R28,R35,R42,R49,R53,R57, R61,R65,R69,R73,R77,R82, R83 R4,R8,R12,R16,R20,R24, Part PCB Footprint Vendor Vendor PN Mfr 2.0pF 10uF 1uF c0402 c1206 c0402 DigiKey DigiKey DigiKey 445-4863-1-ND 718-1300-1-ND 490-5409-1-ND TDK Vishay Murata 100nF 10uF 4.7uF 10nF 10pF PACDN004 600 600 c0402 c0603 C0402 C0402 C0402 sot_143 L0603 L0402 DigiKey DigiKey DigiKey DigiKey DigiKey Mouser DigiKey DigiKey 478-1129-1-ND 445-6853-1-ND 445-7395-1-ND 478-1114-1-ND 490-1278-1-ND 748-PACDN004SR 490-5258-1-ND 490-1006-1-ND AVX TDK TDK AVX Murata ON Semi Murata Murata Header 2x3 Thru-Hole berg_2x3_2p54 SMA Jack, End Launch sma_jack_end_launch DigiKey Digikey Digikey Digikey Digikey Digikey Digikey 609-3210-ND J502-ND J502-ND J502-ND J502-ND J502-ND J502-ND FCI Johnson Components Johnson Components Johnson Components Johnson Components Johnson Components Johnson Components Header 3-pin Banana Jack, Thru-Hole, Red Banana Jack, Thru-Hole, Yellow Banana Jack, Thru-Hole, Black Header 2-pin Conn, USB-B, SMT LED, Green hdr_1x3_2p54 con_571-0500 con_571-0500 con_571-0500 hdr_1x2_2p54 con_usb_b_ra led_0603 DigiKey Mouser Mouser Mouser DigikEY DigiKey DigiKey 3M9448-ND 164-6219 164-7170 164-6218 3M9447-ND ED2994-ND 160-1435-1-ND 3M Deltron Deltron Deltron 3M On Shore Technology Lite-On 4 Round Pads, .060 with .040 Hole berg_2x2_2p54 27 r0402 DigiKey P27JCT-ND Panasonic 0 r0402 DigiKey 541-0.0JCT-ND Vishay DNI DNI 42.2 r0402 r0402 DigiKey DigiKey P42.2LCT-ND P42.2LCT-ND Panasonic Panasonic Remarks DNP C7, C9, C11, C13 DNP R78, R79, R80, R81, R84, R86 9 26 27 28 29 30 31 32 33 34 2 2 2 1 2 6 1 1 1 CRCW06030000Z0EA ERJ-3EKF49R9V ERJ-3GEYJ472V CRCW04020000Z0ED ERJ-3GEYJ2R2V ERJ-2GEJ103X ERJ-2RKF1202X ERJ-2GEJ471X ERJ-2GEJ222X 35 38 No Part 36 37 38 39 40 8 2 4 1 1 5015 No Part No Part DNI NB3W800L FT2232HQ-REEL R29,R36,R43,R50,R54,R58, R62,R66,R70,R74 R31,R32 R40,R41 R47,R48 R52 R75,R76 R88,R89,R90,R92,R93,R94 R91 R95 R96 SG1,SG2,SG3,SG4,SG5,SG6, SG7,SG8,SG9,SG10,SG11, SG12,SG13,SG14,SG15,SG16, SG17,SG18,SG19,SG20,SG21, SG22,SG23,SG24,SG25,SG26, SG27,SG28,SG29,SG30,SG31, SG32,SG33,SG34,SG35,SG36, SG37,SG38 TP1,TP2,TP3,TP4,TP5,TP6, TP7,TP8 TP9,TP10 TP11,TP12,TP13,TP14 U1 U2 41 1 93LC46BT-I/ST 42 43 1 1 NCP4586DSN33T1G ABM8G-12.000MHZ-4Y-T3 0 49.9 4.7K 0 2.2 10K 12K 470 2.2K r0603 r0603 r0603 r0402 r0603 r0402 r0402 r0402 r0402 DigiKey DigiKey DigiKey DigiKey DigiKey DigiKey DigiKey DigiKey DigiKey 541-0.0JCT-ND P49.9HCT-ND P4.7KGCT-ND 541-0.0JCT-ND P2.2GCT-ND P10KJCT-ND P12.0KLCT-ND P470JCT-ND P2.2KJCT-ND Vishay Panasonic Panasonic Vishay Panasonic Panasonic Panasonic Panasonic Panasonic Solder Gap r0201 Test Point, SMT Test Pad 30 x 60 mil Test Pad 50 x 100 mil DNI NB3W800L FT2232H tp_70_135 tp_30_60 tp_50_100 MODULE_48QFN_0P40 qfn_64_0p5 DigiKey 5015KCT-ND Keystone On Semi DigiKey ON Semi FTDI 93LC46B tssop_8_4p4w_0p65 NCP4586, 3.3V 12 MHz sot23_5p CRY-4P-SMD1 DigiKey ON Semi DigiKey 768-1025-1-ND 93LC46BT-I/STCTND U3 U4 Y1 NCP4586DSN33T1G 535-10901-1-ND ON Semi Abracon Corp DNP R31, R32 Microchip 10