NB4N527SMNEVB Evaluation Board User's Manual for NB4N527S http://onsemi.com EVAL BOARD USER’S MANUAL INTRODUCTION Board Lay−Up The 16−lead QFN evaluation board is implemented in four layers with split (dual) power supplies (Figure 2, Evaluation Board Lay−up). For standard lab setup, a split (dual) power supply is essential to enable the 50 W internal impedance in the oscilloscope as a device termination. The first layer or primary trace layer is 0.005, thick Rogers RO6002 material, which is designed to have equal electrical length on all signal traces from the device under the test (DUT) to the sense output. The second layer is the 1.0 oz. copper ground plane. The FR4 dielectric material is placed between the second and third layer, and between the third and fourth layer. The third layer is also a 1.0 oz copper ground plane. The fourth layer is the secondary trace layer. ON Semiconductor has developed an evaluation board for the NB4N527S device as a convenience for the customers interested in performing their own device engineering assessment. This board provides a high bandwidth 50 W controlled impedance environment. The pictures in Figure 1 show the top and bottom view of the evaluation board, which can be configured in several different ways. This evaluation board manual contains: • Information on 16−lead QFN Evaluation Board • Assembly Instructions • Appropriate Lab Setup • Bill of Materials This manual should be used in conjunction with the NB4N527S device data sheet, which contains full technical details on the device specifications and operation. Top View Bottom View Figure 1. Top and Bottom View of the 16 QFN Evaluation Board © Semiconductor Components Industries, LLC, 2012 February, 2012 − Rev. 2 1 Publication Order Number: EVBUM2077/D NB4N527SMNEVB Figure 2. Evaluation Board Lay−up Connecting Power and Ground Planes to VEE, but must be THERMALLY connected to a sufficient heat conduit such as a thermal plane Exact supply voltage values that need to be applied can be found in Table 1 and Figures 4 and 5. Top side of the evaluation board has the four surfaces mount test point clips labeled VCC, VEE, SMA_GND, and DUT_GND. DUT_GND is connected to the exposed flag of the QFN package. For proper operation, the exposed flag is recommended to be ELECTRICALLY left floating or tied Table 1. Power Supply Levels Power Supply Span VCC VEE SMA_GND DUT_GND 3.0 V 1.75 V −1.25 V 0V Float or VEE 3.3 V 2.05 V −1.25 V 0V Float or VEE 3.6 V 2.35 V −1.25 V 0V Float or VEE Stimulus (Generator) Termination For the LVDS configuration, VTDx pin pads of the D0 or D1 input has to be shorted to form 100 W across differential lines. This configuration is accomplished by moving the jumper wire from SMA_GND ring to complementary VTDx pin pad (example: VTD0 and VTD0b for D0 input and VTD1 and VTD1b for D1 input). All ECL outputs need to be terminated to VTT (VTT = VCC –2.0 V = GND) via a 50 W resistor. The current board design utilizes the internal resistors and the VTDx pins are wired to ground. (More information on termination is provided in AN8020). If evaluation does not require use of internal termination resistors, 0402 chip resistor pads are provided on the bottom side of the evaluation board. The jumper wires of the VTDx pin pads should be removed (J1, J4, J13 and J15 to SMA_GND jumper). Solder the chip resistors to the bottom side of the board between the appropriate input of the device pin pads and the ground pads (for split power supply setup). Likewise for CML outputs, CML stimulus signal need to be terminated to VCC via a 50 W resistor. If internal resistors are used, the VTDx pin pads should be wired to VCC. To accomplish this configuration, the jumper wire has to be moved from SMA_GND ring to VCC ring on the bottom of the board. DUT Termination For standard lab setup and test, a split (dual) power supply is required enabling the 50 W internal impedance in the oscilloscope to be used as a termination of the signals (in split power supply setup SMA_GND is the system ground, VCC is varied, and VEE is –1.25 V; see Table 1, Power Supply Levels). Board Components Configuration The NB4N527SMNEVB evaluation board requires eight side SMA connectors. Placement locations are described in Table 2 and Figure 3. Table 2. SMA Connectors and Jumpers Placement Device J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 No Yes Yes No No No No No Yes Yes Yes No No Yes Yes No SMA_GND No No SMA_GND VEE No No VCC No No No No SMA_GND No No SMA_GND Connector Wire http://onsemi.com 2 J16 NB4N527SMNEVB 4 x Surface Mount Test Points 8 x SMA Connectors ÉÉ ÎÎ ÎÎ ÉÉ ÎÎÉÉ ÉÉ ÎÎ J15 J14 J16 J1 J2 C4 J13 C2 D U T J3 J12 2 x 10 mF Decoupling Capacitors on the back of the PCB (C4, C2) J11 J10 J4 J9 J8 J5 J6 J7 Top View VEE Pin 1 Pad VCC Wire SMA_GND SMA_GND DUT_GND Bottom View 4 x 0.01 mF or 0.1 mF Decoupling Capacitors (C1, C3, C5, C6) Figure 3. Components Placement http://onsemi.com 3 NB4N527SMNEVB DO DO QO Connect output of the generator to the input pins labeled J2, J3, J14, J15 D1 (D0/D0B, D1/D1B) Note: Internal termination pins are connected to the SMA GND on the PCB. QO D1 Q1 Connect outputs of the device labeled J9, J10, J11 and J12 (Q0/Q0B, Q1/Q1B) directly to the scope head. Q1 Figure 4. Lab Setup for NB4N527S Power Supply VCC GND VEE Differential Signal Generator Test Measuring Equipment Out Channel 1 D U T Out Channel 2 Trigger Trigger Figure 5. Simplified Equipment Lab Setup Block Diagram 3. Connect a test measurement device on the device output SMA connectors. 1. Connect appropriate power supplies to VCC, VEE, SMA_GND, and SMA_DUT. 2. Connect a signal generator to the input SMA connectors. Setup input signal according to the device data sheet. NOTE: The test measurement device must contain 50 W termination. http://onsemi.com 4 NB4N527SMNEVB Table 3. Bill of Materials Components Manufacturer Description Part Number Qty. Web Site SMA Connector Johnson* Rosenberger SMA Connector, Side Launch, Gold Plated 142−0701−851 32K243−40ME3 8 http://www.johnsoncomponents.com http://www.rosenbergerna.com Surface Mount Test Points Keystone* SMT Miniature Test Point 5015 4 http://www.keyelco.com Chip Capacitor AVC Corporation* 0603 0.01 mF " 10% 10 mF " 10% 06035C103KAT2A 4 http://www.avxcorp.com T491C106K016AS 2 Chip Resistor Panasonic* 0402 50 W " 1% Presicion Thick Film Chip Resistor ERJ−2RKF49R9X Optional** http://www.panasonic.com Evaluation Board ON Semiconductor QFN 16 Evaluation Board ECLQFN16EVB 1 http://www.onsemi.com Device Samples ON Semiconductor QFN 16 Package Device NB4N527SMN 1 http://www.onsemi.com *Components are available through most distributors, i.e. www.newark.com, www.Digikey.com http://onsemi.com 5 NB4N527SMNEVB Top Layer Second Layer (SMA_GND Plane) Figure 6. Gerber Files http://onsemi.com 6 NB4N527SMNEVB Third Layer (DUT_GND Trace) Bottom Layer Figure 7. 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