PDF Data Sheet Rev. A

High Performance, 3.2 GHz, 14-Output
Fanout Buffer
HMC7043
Data Sheet
The HMC7043 is designed to meet the requirements of multicarrier
GSM and LTE base station designs, and offers a wide range of
clock management and distribution features to simplify baseband
and radio card clock tree designs.
FEATURES
JEDEC JESD204B support
Low additive jitter: <15 fs rms at 2457.6 MHz (12 kHz to 20 MHz)
Very low noise floor: −155.2 dBc/Hz at 983.04 MHz
Up to 14 LVDS, LVPECL, or CML type device clocks (DCLKs)
Maximum CLKOUTx/CLKOUTx and SCLKOUTx/SCLKOUTx
frequency of 3200 MHz
JESD204B-compatible system reference (SYSREF) pulses
25 ps analog and ½ clock input cycle digital delay
independently programmable on each of 14 clock
output channels
SPI-programmable adjustable noise floor vs. power consumption
SYSREF valid interrupt to simplify JESD204B synchronization
Supports deterministic synchronization of multiple
HMC7043 devices
RFSYNCIN pin or SPI-controlled SYNC trigger for output
synchronization of JESD204B
GPIO alarm/status indicator to determine system health
Clock input to support up to 6 GHz
48-lead, 7 mm × 7 mm LFCSP package
The HMC7043 provides 14 low noise and configurable outputs
to offer flexibility in interfacing with many different components in
a base transceiver station (BTS) system, such as data converters,
local oscillators, transmit/receive modules, field programmable
gate arrays (FPGAs), and digital front-end ASICs. The HMC7043
can generate up to seven DCLK and SYSREF clock pairs per the
JESD204B interface requirements.
The system designer can generate a lower number of DCLK and
SYSREF pairs, and configure the remaining output signal paths
for independent phase and frequency. Both the DCLK and SYSREF
clock outputs can be configured to support different signaling
standards, including CML, LVDS, LVPECL, and LVCMOS, and
different bias conditions to adjust for varying board insertion losses.
One of the unique features of the HMC7043 is the independent
flexible phase management of each of the 14 channels. All
14 channels feature both frequency and phase adjustment. The
outputs can also be programmed for 50 Ω or 100 Ω internal and
external termination options.
APPLICATIONS
JESD204B clock generation
Cellular infrastructure (multicarrier GSM, LTE, W-CDMA)
Data converter clocking
Phase array reference distribution
Microwave baseband cards
The HMC7043 device features an RF SYNC feature that synchronizes multiple HMC7043 devices deterministically, that is, ensures
that all clock outputs start with the same edge. This operation is
achieved by rephrasing the nested HMC7043 or SYSREF control
unit/divider, deterministically, and then restarting the output
dividers with this new phase.
GENERAL DESCRIPTION
The HMC7043 is a high performance clock buffer for the
distribution of ultralow phase noise references for high speed data
converters with either parallel or serial (JESD204B type) interfaces.
The HMC7043 is offered in a 48-lead, 7 mm × 7 mm LFCSP
package with an exposed pad connected to ground.
FUNCTIONAL BLOCK DIAGRAM
CLKIN/
CLKIN
RFSYNCIN/
RFSYNCIN
CLKOUT0
CLKOUT0
SCLKOUT1
SCLKOUT1
÷
CLKOUT12
CLKOUT12
SCLKOUT13
SCLKOUT13
SYSREF
CONTROL
SPI
CONTROL
INTERFACE
SLEN
14-CLOCK
DISTRIBUTION
13114-001
SDATA
÷
SCLK
Figure 1.
Rev. A
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HMC7043
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Terminology .................................................................................... 14
Applications ....................................................................................... 1
Theory of Operation ...................................................................... 15
General Description ......................................................................... 1
Detailed Block Diagram ............................................................ 16
Functional Block Diagram .............................................................. 1
Clock Input Network ................................................................. 16
Revision History ............................................................................... 2
Clock Output Network .............................................................. 17
Specifications..................................................................................... 3
Typical Programming Sequence............................................... 23
Conditions ..................................................................................... 3
Power Supply Considerations ................................................... 24
Supply Current .............................................................................. 3
Serial Control Port ......................................................................... 26
Digital Input/Output (I/O) Electrical Specifications ............... 4
Serial Port Interface (SPI) Control ........................................... 26
Clock Input Path Specifications.................................................. 4
Control Registers ............................................................................ 27
Additive Jitter and Phase Noise Characteristics ....................... 5
Control Register Map ................................................................ 27
Clock Output Distribution Specifications................................. 5
Control Register Map Bit Descriptions ................................... 32
Clock Output Driver Characteristics ......................................... 6
Applications Information .............................................................. 40
Absolute Maximum Ratings ............................................................ 8
Evaluation PCB And Schematic ............................................... 40
ESD Caution .................................................................................. 8
Outline Dimensions ....................................................................... 42
Pin Configuration and Function Descriptions ............................. 9
Ordering Guide .......................................................................... 42
Typical Performance Characteristics ........................................... 11
Typical Application Circuits.......................................................... 13
REVISION HISTORY
5/16—Rev. 0 to Rev. A
Changes to Table 3 ............................................................................. 4
Change to Maximum Operating Frequency Parameter, Table 7 ..... 7
Added Figure 6, Renumbered Sequentially ................................ 11
Change to Synchronization FSM/Pulse Generator
Timing Section ................................................................................. 21
Changes to Table 20 ........................................................................ 28
Change to Table 22 ......................................................................... 33
Changes to Table 28 ........................................................................ 34
Changes to Table 29 ........................................................................ 35
Change to Table 31 ......................................................................... 36
Change to Table 38 ......................................................................... 37
Changes to Table 41 ........................................................................ 39
12/15—Revision 0: Initial Version
Rev. A | Page 2 of 42
Data Sheet
HMC7043
SPECIFICATIONS
VCC = 3.3 V ± 5%, and TA = 25°C, unless otherwise noted. Minimum and maximum values are given over the full VCC and TA (−40°C to
+85°C) variation, as listed in Table 1.
CONDITIONS
Table 1.
Parameter 1
SUPPLY VOLTAGE, VCC
VCC1_CLKDIST
VCC2_OUT
Min
Typ
Max
Unit
Test Conditions/Comments
3.135
3.135
3.3
3.3
3.465
3.465
V
V
VCC3_OUT
3.135
3.3
3.465
V
VCC4_CLKIN
VCC5_SYSREF
VCC6_OUT
3.135
3.135
3.135
3.3
3.3
3.3
3.465
3.465
3.465
V
V
V
VCC7_OUT
3.135
3.3
3.465
V
3.3 V ± 5%, supply voltage for CLK distribution
3.3 V ± 5%, supply voltage for Output Channel 2 and
Output Channel 3
3.3 V ± 5%, supply voltage for Output Channel 4, Output
Channel 5, Output Channel 6 and Output Channel 7
3.3 V ± 5%, supply voltage for the clock input path
3.3 V ± 5%, supply voltage for the common SYSREF divider
3.3 V ± 5%, supply voltage for Output Channel 8, Output
Channel 9, Output Channel 10, and Output Channel 11
3.3 V ± 5%, supply voltage for Output Channel 0, Output
Channel 1, Output Channel 12, and Output Channel 13
−40
−30
+25
+36
+85
+98
°C
°C
100
°C
TEMPERATURE
Ambient Temperature Range, TA
Temperature of Printed Circuit Board
(PCB) Connected to Exposed Pad
Junction Temperature, TJ
1
Maximum values are guaranteed by design and characterization.
SUPPLY CURRENT
For detailed test conditions, see Table 17 and Table 18.
Table 2
Parameter 1, 2
CURRENT CONSUMPTION 3
VCC1_CLKDIST
VCC2_OUT 4
VCC3_OUT4
Min
Typ
Max
Unit
87
90
52
125
250
500
mA
mA
mA
VCC4_CLKIN
16
25
mA
VCC5_SYSREF
VCC6_OUT4
23
90
35
500
mA
mA
VCC7_OUT4
100
500
mA
Total Current
458
Test Conditions/Comments
Typical value is given at TA = 25°C with two LVDS clocks at divide by 8
Typical value is given at 25°C with two LVDS high performance clocks,
fundamental frequency of the clock input (fO), two SYSREF clocks (off )
Typical value is given at TA = 25°C with RF synchronization (RFSYNC) input
buffer off
Typical value is given at TA = 25°C with internal RF SYNC path off
Typical value is given at 25°C with two LVDS high performance clocks at
divide by 2, two SYSREF clocks (off )
Typical value is given at 25°C with two LVDS clocks at divide by 8, two SYSREF
clocks (off )
mA
Maximum values are guaranteed by design and characterization.
Currents include LVDS termination currents.
3
Maximum values are for all circuits enabled in their worst case power consumption mode, PVT variations, and accounting for peak current draw during temporary
synchronization events.
4
Typical specification applies to a normal usage profile (Profile 1 in Table 17) but very low duty cycle currents (sync events) and some optional features are disabled.
This specification assumes output configurations as described in the test conditions/comments column.
1
2
Rev. A | Page 3 of 42
HMC7043
Data Sheet
DIGITAL INPUT/OUTPUT (I/O) ELECTRICAL SPECIFICATIONS
Table 3.
Parameter
DIGITAL INPUT SIGNALS (RESET, SLEN, SCLK)
Safe Input Voltage Range
Input Load
Input Voltage
Input Logic High
Input Logic Low
SPI Bus Frequency
DIGITAL BIDIRECTIONAL SIGNALS
CONFIGURED AS INPUTS (SDATA, GPIO)
Safe Input Voltage Range
Input Capacitance
Input Resistance
Input Voltage
Input Logic High
Input Logic Low
Input Hysteresis
GPIO ALARM MUXING/DELAY
Delay from Internal Alarm/Signal to
General-Purpose Output (GPO) Driver
DIGITAL BIDIRECTIONAL SIGNALS
CONFIFURED AS OUTPUTS (SDATA, GPIO)
CMOS Mode
Logic 1 Level
Logic 0 Level
Output Drive Resistance (RDRIVE)
Output Driver Delay (tDGPO)
Min
Typ
Max
Unit
+3.6
V
pF
VCC
0.5
10
V
V
MHz
+3.6
V
pF
GΩ
VCC
0.24
0.2
V
V
V
Occurs around 0.85 V
2
ns
Does not include tDGPO
−0.1
0.3
1.2
0
−0.1
0.4
50
1.22
0
1.6
1.9
0
50
1.5 + 42 × CLOAD
Maximum Supported DC Current 1
Open-Drain Mode
Logic 1 Level
Logic 0 Level
Pull-Down Impedance
Maximum Supported Sink Current1
1
0.13
60
2.2
0.1
V
V
Ω
ns
0.6
mA
3.6
V
0.28
V
Ω
mA
5
Test Conditions/Comments
Approximately 1.5 ns + 0.69 × RDRIVE × CLOAD
(CLOAD in nF)
External 1 kΩ pull-up resistor
3.6 V maximum permitted; specifications set by
external supply
Against a 1 kΩ external pull-up resistor to 3.3 V
Guaranteed by design and characterization for long-term reliability.
CLOCK INPUT PATH SPECIFICATIONS
Table 4.
Parameter
CLK INPUT (CLKIN) CHARACTERISTICS
Recommended Input Power, AC-Coupled
Differential
Single-Ended 1
Return Loss
Clock Input Frequency (fCLKIN)
Common-Mode Range
1
Min
Typ
−6
−10
Max
Unit
+8
+6
200
3200
dBm
dBm
dB
MHz
200
0.4
6000
2.4
MHz
V
−12
Guaranteed by design and characterization.
Rev. A | Page 4 of 42
Test Conditions/Comments
Noise floor degrade by 3 dB at fCLKIN = 2400 MHz
When terminated with 100 Ω differential
Fundamental mode; if <1 GHz, set the low frequency
clock input path enable bit (Register 0x0064, Bit 0)
Using clock input ÷ 2
Data Sheet
HMC7043
ADDITIVE JITTER AND PHASE NOISE CHARACTERISTICS
Table 5.
Parameter 1
ADDITIVE JITTER
RMS Additive Jitter
Min
Typ
Max
Unit
<30
fs rms
<15
fs rms
−144.3
−154.8
−155.2
dBc/Hz
dBc/Hz
dBc/Hz
CLOCK OUTPUT PHASE NOISE
Absolute Phase Noise
Offset = 1 MHz
Offset = 10 MHz
Offset = 20 MHz
1
Test Conditions/Comments
HMC7044 used as a clock source (see Figure 3)
Clock output frequency (fCLKOUT) = 983.04 MHz, BW = 12 kHz to 20 MHz,
clock input slew rate ≥ 8 ns
fCLKOUT = 2457.6 MHz, BW = 12 kHz to 20 MHz, clock input slew rate ≥ 4 ns
HMC830 used as a clock source and configured to produce
983.04 MHz at the output (see Figure 4), input slew rate > 1 V/ns
fCLKOUT = 983.04 MHz, fCLKOUT = 983.04 MHz, divide by 1 at the output
fCLKOUT = 983.04 MHz, fCLKOUT = 2949.12 MHz, divide by 3 at the output
fCLKOUT = 983.04 MHz, fCLKOUT = 983.04 MHz, divide by 1 at the output
Guaranteed by design and characterization.
CLOCK OUTPUT DISTRIBUTION SPECIFICATIONS
Table 6.
Parameter
CLOCK OUTPUT SKEW
CLKOUTx/CLKOUTx to SCLKOUTx/SCLKOUTx Skew
Within One Clock Output Pair
Any CLKOUTx/CLKOUTx to Any SCLKOUTx/SCLKOUTx
Min
PROPAGATION DELAY CLKIN to CLKOUTx and SCLKOUTx1
CLOCK OUTPUT DIVIDER CHARACTERISTICS
12-Bit Divider Range
SYSREF CLOCK OUTPUT DIVIDER CHARACTERISTICS
12-Bit Divider Range
770
CLOCK OUTPUT ANALOG FINE DELAY
Analog Fine Delay
Adjustment Range1
Resolution
Maximum Analog Fine Delay Frequency
CLOCK OUTPUT COARSE DELAY (FLIP FLOP BASED)
Coarse Delay Adjustment Range
Coarse Delay Resolution
Maximum Frequency Coarse Delay
CLOCK OUTPUT COARSE DELAY (SLIP BASED)
Coarse Delay
Adjustment Range
Resolution
Maximum Frequency Coarse Delay
1
Typ
Unit
Test Conditions/Comments
15
|ps|
30
|ps|
Same pair, same type termination and
configuration
Any pair, same type termination and
configuration
fCLKIN = 983.04 MHz, all VCC set to 3.3 V
820
Max
870
ps
1
4094
1, 3, 5, and all even numbers up to 4094
1
4094
1, 3, 5, and all even numbers up to 4094;
pulse generator behavior is only
supported for divide ratios ≥ 32
135
670
ps
ps
MHz
24 delay steps, fCLKOUT = 983.04 MHz
fCLKOUT = 983.04 MHz (2949.12 MHz/3)
17
169.54
1500
½ CLKIN period
ps
MHz
17 delay steps
fCLKIN = 2949.12 MHz
1 to ∞
339.08
1600
CLKIN period
ps
MHz
25
1600
0
Guaranteed by design and characterization.
Rev. A | Page 5 of 42
fCLKIN = 2949.12 MHz
HMC7043
Data Sheet
CLOCK OUTPUT DRIVER CHARACTERISTICS
Table 7.
Parameter
CML MODE (LOW POWER)
−3 dB Bandwidth
Output Rise Time
Min
Output Fall Time
Output Duty Cycle 1
Differential Output Voltage Magnitude
47.5
Common-Mode Output Voltage
CML MODE (HIGH POWER)
−3 dB Bandwidth
Output Rise Time
Output Fall Time
Output Duty Cycle1
Differential Output Voltage Magnitude
47.5
Differential Output
Voltage Magnitude
Power
Common-Mode Output Voltage
LVPECL MODE
−3 dB Bandwidth
Output Rise Time
Output Fall Time
Output Duty Cycle1
Differential Output Voltage Magnitude
47.5
Differential Output
Voltage Magnitude
Power
Common-Mode Output Voltage
LVDS MODE (LOW POWER)
Maximum Operating Frequency
Output Rise Time
Output Fall Time
Output Duty Cycle1
Differential Output Voltage Magnitude
Common-Mode Output Voltage
47.5
Typ
Max
1950
175
145
185
145
50
1390
1360
VCC − 1.05
1500
250
165
255
170
50
2000
1800
52.5
52.5
Unit
MHz
ps
ps
ps
ps
%
mV p-p diff
mV p-p diff
V
MHz
ps
ps
ps
ps
%
mV p-p diff
mV p-p diff
590
−3.6
VCC − 1.6
mV p-p diff
dBm diff
V
2400
135
130
135
130
50
1760
1850
MHz
ps
ps
ps
ps
%
mV p-p diff
mV p-p diff
52.5
930
0.3
VCC − 1.3
mV p-p diff
dBm diff
V
1700
135
100
135
95
50
390
1.1
MHz
ps
ps
ps
ps
%
mV p-p diff
V
52.5
Rev. A | Page 6 of 42
Test Conditions/Comments
RL = 100 Ω, 9.6 mA
Differential output voltage = 980 mV p-p diff
fCLKOUT = 245.76 MHz, 20% to 80%
fCLKOUT = 983.04 MHz, 20% to 80%
fCLKOUT = 245.76 MHz, 20% to 80%
fCLKOUT = 983.04 MHz, 20% to 80%
fCLKOUT = 1075 MHz (2150 MHz/2)
fCLKOUT = 245.76 MHz (2949.12 MHz/12)
fCLKOUT = 983.04 MHz (2949.12 MHz/3)
fCLKOUT = 245.76 MHz (2949.12 MHz/12)
RL = 100 Ω, 14.5 mA
Differential output voltage = 1470 mV p-p diff
fCLKOUT = 245.76 MHz, 20% to 80%
fCLKOUT = 983.04 MHz, 20% to 80%
fCLKOUT = 245.76 MHz, 20% to 80%
fCLKOUT = 983.04 MHz, 20% to 80%
fCLKOUT = 1075 MHz (2150 MHz/2)
fCLKOUT = 245.76 MHz (2949.12 MHz/12)
fCLKOUT = 983.04 MHz (2949.12 MHz/3)
fCLKOUT = 3200 MHz
fCLKOUT = 3200 MHz
fCLKOUT = 245.76 MHz (2949.12 MHz/12)
RL = 150 Ω, 4.8 mA
Differential output voltage = 1240 mV p-p diff
fCLKOUT = 245.76 MHz, 20% to 80%
fCLKOUT = 983.04 MHz, 20% to 80%
fCLKOUT = 245.76 MHz, 20% to 80%
fCLKOUT = 983.04 MHz, 20% to 80%
fCLKOUT = 1075 MHz (2150 MHz/2)
fCLKOUT = 245.76 MHz (2949.12 MHz/12)
fCLKOUT = 983.04 MHz (2949.12 MHz/3)
fCLKOUT = 3200 MHz
fCLKOUT = 3200 MHz
fCLKOUT = 245.76 MHz (2949.12 MHz/12)
1.75 mA
Differential output voltage = 320 mV p-p diff
fCLKOUT = 245.76 MHz, 20% to 80%
fCLKOUT = 983.04 MHz, 20% to 80%
fCLKOUT = 245.76 MHz, 20% to 80%
fCLKOUT = 983.04 MHz, 20% to 80%
fCLKOUT = 1075 MHz (2150 MHz/2)
fCLKOUT = 245.76 MHz (2949.12 MHz/12)
fCLKOUT = 245.76 MHz (2949.12 MHz/12)
Data Sheet
Parameter
LVDS MODE (HIGH POWER)
Maximum Operating Frequency
Output Rise Time
HMC7043
Min
Output Fall Time
Output Duty Cycle1
Differential Output Voltage Magnitude
Common-Mode Output Voltage
CMOS MODE
Maximum Operating Frequency
Output Rise Time
Output Fall Time
Output Duty Cycle1
Output Voltage
High
Low
1
47.5
47.5
Typ
Max
1700
145
105
145
100
50
750
730
1.1
52.5
600
425
420
50
52.5
VCC
VCC − 0.5
0.07
0.5
Unit
MHz
ps
ps
ps
ps
%
mV p-p diff
mV p-p diff
V
Test Conditions/Comments
3.5 mA
Differential output voltage = 600 mV p-p diff
fCLKOUT = 245.76 MHz, 20% to 80%
fCLKOUT = 983.04 MHz, 20% to 80%
fCLKOUT = 245.76 MHz, 20% to 80%
fCLKOUT = 983.04 MHz, 20% to 80%
fCLKOUT = 1075 MHz (2150 MHz/2)
fCLKOUT = 245.76 MHz (2949.12 MHz/12)
fCLKOUT = 983.04 MHz (2949.12 MHz/3)
fCLKOUT = 245.76 MHz (2949.12 MHz/12)
MHz
ps
ps
%
Single-ended output voltage = 940 mV p-p diff
fCLKOUT = 245.76 MHz, 20% to 80%
fCLKOUT = 245.76 MHz, 20% to 80%
fCLKOUT = 1075 MHz (2150 MHz/2)
V
V
V
V
Load current = 1 mA
Load current = 10 mA
Load current = 1 mA
Load current = 10 mA
Guaranteed by design and characterization.
Rev. A | Page 7 of 42
HMC7043
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 8.
Parameter
VCC1, VCC2, VCC3, VCC4, VCC5, VCC6, VCC7 to
Ground
Maximum Junction Temperature
Thermal Resistance (Channel to Ground Pad)
Storage Temperature Range
Operating Temperature Range
Peak Reflow Temperature
ESD Sensitivity Level
Human Body Model (HBM)
Charged Device Model (CDM)1
1
Rating
−0.3 V to +3.6 V
125°C
7°C/W
−65°C to +125°C
−40°C to +85°C
260°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Class 1C
Class 4
Per JESD22-C101-F (CDM) standard.
Rev. A | Page 8 of 42
Data Sheet
HMC7043
48
47
46
45
44
43
42
41
40
39
38
37
VCC7_OUT
CLKOUT12
CLKOUT12
SCLKOUT13
SCLKOUT13
SCLKOUT11
SCLKOUT11
CLKOUT10
CLKOUT10
VCC6_OUT
CLKOUT8
CLKOUT8
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
HMC7043
TOP VIEW
(Not to Scale)
36
35
34
33
32
31
30
29
28
27
26
25
SCLKOUT9
SCLKOUT9
GPIO
SDATA
SCLK
SLEN
VCC5_SYSREF
RFSYNCIN
RFSYNCIN
VCC4_CLKIN
CLKIN
CLKIN
NOTES
1. RSV = RESERVED PIN AND MUST BE TIED TO GROUND.
2. CONNECT THE EXPOSED PAD TO A HIGH QUALITY RF/DC GROUND.
13114-002
VCC2_OUT
RSV
SCLKOUT5
SCLKOUT5
CLKOUT4
CLKOUT4
VCC3_OUT
CLKOUT6
CLKOUT6
SCLKOUT7
SCLKOUT7
RSV
13
14
15
16
17
18
19
20
21
22
23
24
CLKOUT0 1
CLKOUT0 2
SCLKOUT1 3
SCLKOUT1 4
RESET 5
BGAPBYP1 6
LDOBYP2 7
VCC1_CLKDIST 8
SCLKOUT3 9
SCLKOUT3 10
CLKOUT2 11
CLKOUT2 12
Figure 2.
Table 9. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
Mnemonic
CLKOUT0
CLKOUT0
SCLKOUT1
SCLKOUT1
RESET
BGAPBYP1
Type 1
O
O
O
O
I
7
LDOBYP2
8
9
10
11
12
13
VCC1_CLKDIST
SCLKOUT3
SCLKOUT3
CLKOUT2
CLKOUT2
VCC2_OUT
P
O
O
O
O
P
14
15
16
17
18
19
RSV
SCLKOUT5
SCLKOUT5
CLKOUT4
CLKOUT4
VCC3_OUT
R
O
O
O
O
P
20
21
22
23
24
25
26
CLKOUT6
CLKOUT6
SCLKOUT7
SCLKOUT7
RSV
CLKIN
CLKIN
O
O
O
O
R
I
I
Description
True Clock Output Channel 0. Default DCLK profile.
Complementary Clock Output Channel 0. Default DCLK profile.
True Clock Output Channel 1. Default SYSREF profile.
Complementary Clock Output Channel 1. Default SYSREF profile.
Device Reset Input. Active high. For normal operation, set RESET to 0.
Band Gap Bypass Capacitor Connection. Connect a 4.7 µF capacitor to ground. This pin affects all
internally regulated supplies.
LDO Bypass 2. Connect a 4.7 µF capacitor to ground. The internal digital supply is 1.8 V. This pin is the
LDO bypass for the SYSREF section.
3.3 V Supply for CLK Distribution.
True Clock Output Channel 3. Default SYSREF profile.
Complementary Clock Output Channel 3. Default SYSREF profile.
True Clock Output Channel 2. Default DCLK profile.
Complementary Clock Output Channel 2. Default DCLK profile.
Power Supply for Clock Group 1 (Southwest)—Channel 2 and Channel 3. See the Clock Grouping,
Skew, and Crosstalk section.
Reserved Pin. This pin must be tied to ground.
True Clock Output Channel 5. Default SYSREF profile.
Complementary Clock Output Channel 5. Default SYSREF profile.
True Clock Output Channel 4. Default DCLK profile.
Complementary Clock Output Channel 4. Default DCLK profile.
Power Supply for Clock Group 2 (South)—Channel 4, Channel 5, Channel 6, and Channel 7. See the
Clock Grouping, Skew, and Crosstalk section.
True Clock Output Channel 6. Default DCLK profile.
Complementary Clock Output Channel 6. Default DCLK profile.
True Clock Output Channel 7. Default SYSREF profile.
Complementary Clock Output Channel 7. Default SYSREF profile.
Reserved Pin. This pin must be tied to ground.
Complementary Clock Input.
True Clock Input.
Rev. A | Page 9 of 42
HMC7043
Data Sheet
Pin No.
27
28
29
30
31
32
33
34
35
36
37
38
39
Mnemonic
VCC4_CLKIN
RFSYNCIN
RFSYNCIN
VCC5_SYSREF
SLEN
SCLK
SDATA
GPIO
SCLKOUT9
SCLKOUT9
CLKOUT8
CLKOUT8
VCC6_OUT
Type 1
P
I
I
P
I/O
I/O
I/O
I/O
O
O
O
O
P
40
41
42
43
44
45
46
47
48
CLKOUT10
CLKOUT10
SCLKOUT11
SCLKOUT11
SCLKOUT13
SCLKOUT13
CLKOUT12
CLKOUT12
VCC7_OUT
O
O
O
O
O
O
O
O
P
EP
1
Description
Power Supply for the Clock Input Path.
True RF Synchronization Input with Deterministic Delay.
Complementary RF Synchronization Input with Deterministic Delay.
Power Supply for Common SYSREF Divider.
SPI Latch Enable.
SPI Clock.
SPI Data.
Programmable General-Purpose Input/Output.
True Clock Output Channel 9. Default SYSREF profile.
Complementary Clock Output Channel 9. Default SYSREF profile.
True Clock Output Channel 8. Default DCLK profile.
Complementary Clock Output Channel 8. Default DCLK profile.
Power Supply for Clock Group 3 (North)—Channel 8, Channel 9, Channel 10, and Channel 11. See the
Clock Grouping, Skew, and Crosstalk section.
True Clock Output Channel 10. Default DCLK profile.
Complementary Clock Output Channel 10. Default DCLK profile.
True Clock Output Channel 11. Default SYSREF profile.
Complementary Clock Output Channel 11. Default SYSREF profile.
True Clock Output Channel 13. Default SYSREF profile.
Complementary Clock Output Channel 13. Default SYSREF profile.
True Clock Output Channel 12. Default DCLK profile.
Complementary Clock Output Channel 12. Default DCLK profile.
Power Supply for Clock Group 0 (Northwest)—Channel 0, Channel 1, Channel 12, and Channel 13. See
the Clock Grouping, Skew, and Crosstalk section.
Exposed Pad. Connect the exposed pad to a high quality RF/dc ground.
O is output, I is input, P is power, R is reserved, and I/O is input/output.
Rev. A | Page 10 of 42
Data Sheet
HMC7043
TYPICAL PERFORMANCE CHARACTERISTICS
–120
–130
–140
HMC7044 AS CLOCK SOURCE:
OUTPUT FREQ = 983.04MHz
OUTPUT POWER = 3.7dBm
1MHz, –140.56dBc/Hz
5MHz, –153.26dBc/Hz
10MHz, –154.28dBc/Hz
20MHz, –154.85dBc/Hz
RMS JITTER (12kHz TO 20MHz): 73.74fs
–150
1
10
10000
1000
100
FREQUENCY OFFSET (kHz)
1.65
1.50
1.35
1.20
1.05
0.90
0.75
0.60
0.45
0.30
0.15
1.5
2.0
2.5
3.5
3.0
Figure 6.Differential Output Voltage vs. Frequency over Various Modes
–120
HMC830 AS CLOCK SOURCE:
OUTPUT FREQ = 983.04MHz
OUTPUT POWER = 4dBm
1MHz, –144.49dBc/Hz
5MHz, –158.38dBc/Hz
10MHz,–162.61dBc/Hz
20MHz, –164.29dBc/Hz
–130
–140
–150
HMC7043 OUTPUT:
AT FUNDEMENTAL MODE
1MHz, –144.31 dBc/Hz
5MHz, –153.46 dBc/Hz
10MHz, –154.78 dBc/Hz
20MHz, –155.18 dBc/Hz
1
10
100
1000
10000
FREQUENCY OFFSET (kHz)
1.00
0.75
0.5
0.25
1G
3G
Figure 7. LVPECL Differential Output Power vs. Frequency over Various
Temperatures
3.5
0.4
LVPECL
CML100 HIGH
CML100 LOW
LVDS HIGH
CMOS (NOT IN
DIFFERENTIAL MODE)
0.3
CLKOUT0/CLKOUT0 VOLTAGE (V)
2.5
1.25
FREQUENCY (Hz)
Figure 4. Absolute Phase Noise Measured at 983.04 MHz at Output
3.0
1.5
0
100M
13114-004
–160
–40°C
+25°C
+85°C
1.75
13114-205
–110
DIFFERENTIAL OUTPUT VOLTAGE (Vp-p DIFF)
2.00
HMC830-CLOCK SOURCE
HMC7043
PHASE NOISE (dBc/Hz)
1.80
FREQUENCY (GHz)
–100
2.0
1.5
1.0
0.5
0.2
0.1
0
–0.1
–0.2
–0.3
0
100M
1G
FREQUENCY (Hz)
3.2G
–0.4
13114-206
DIFFERENTIAL OUTPUT VOLTAGE (Vp-p DIFF)
1.95
0
1.0
Figure 3. Additive Jjitter at 983.04 MHz at Output
–170
LVPECL
CML100 HIGH
CML100 LOW
LVDS HIGH
2.10
0
0.4
0.8
1.2
1.6
2.0
TIME (ns)
Figure 5. Differential Output Power vs. Frequency over Various Modes
Rev. A | Page 11 of 42
Figure 8. Differential CLKOUT0/CLKOUT0 at 2457 MHz, LVPECL
13114-007
–160
13114-003
PHASE NOISE (dBc/Hz)
–110
2.25
HMC7043 OUTPUT:
AT FUNDEMENTAL MODE
1MHz, –140.30 dBc/Hz
5MHz, –151.02 dBc/Hz
10MHz, –151.77 dBc/Hz
20MHz, –151.97 dBc/Hz
RMS JITTER = 77.01fs
13114-100
HMC7044-CLOCK SOURCE
HMC7043
DIFFERENTIAL OUTPUT VOLTAGE (V p-p)
–100
0.6
2.5
0.4
2.0
0.2
1.5
0
1.0
–0.2
0.5
1.0
0.6
CLOCK OUTPUT VOLTAGE (V)
0.4
0.2
0
–0.2
–0.4
–0.6
–0.4
0
–0.8
CLKOUT0
CLKOUT2
5
4
6
7
8
10
9
TIME (ns)
–0.6
695
0.2
1.5
0
1.0
–0.2
0.5
–0.4
0
–0.6
0
200
400
600
800
–0.5
1000
TIME (ns)
0.2
1.5
0
1.0
–0.2
0.5
–0.4
0
–0.6
330
335
340
345
–0.5
350
TIME (ns)
Figure 11. Output Channel Synchronization Before Rephase
–40°C
+25°C
+85°C
DELAY STEP
Figure 13. Analog Delay Step Size vs. Delay Step over Temperature,
LVPECL at 983.04 MHz
800
–40°C
+27°C
+85°C
700
600
DELAY STEP SIZE (ps)
2.0
CLOCK GROUP VALID PHASE ALARM VOLTAGE (V)
CLOCK OUTPUT VOLTAGE (V)
0.4
20
10
500
400
300
200
100
0
–100
–200
13114-010
2.5
CLKOUT0
CLKOUT2
VALID PHASE ALARM
25
15
Figure 10. Output Channel Synchronization Before and After Rephase
0.6
–0.5
715
30
DELAY STEP SIZE (ps)
2.0
CLOCK GROUP VALID PHASE ALARM VOLTAGE (V)
0.4
710
Figure 12. Output Channel Synchronization After Rephase
13114-009
CLOCK OUPUT VOLTAGE (V)
2.5
CLKOUT0
CLKOUT2
VALID PHASE ALARM
705
TIME (ns)
Figure 9. Differential CLKOUT0/CLKOUT0 Voltage at 614.4 MHz, LVPECL
0.6
700
13114-012
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
2
1
FUND:FUNDAMENTAL MODE AT 2949.12MHz
DIS: ANALOG DELAY IS DISABLED AT 983.04MHz
FUND
DIS
0
13114-008
–1.0
VALID PHASE ALARM
0
2
4
6
8 10 12 14 16 18 20 22 24 26 28 30
DELAY STEP
13114-013
CLKOUT0/CLKOUT0 VOLTAGE (V)
0.8
CLOCK GROUP VALID PHASE ALARM VOLTAGE (V)
Data Sheet
Figure 14. Analog Delay vs. Delay Setting over Temperature, LVPECL at
983.04 MHz
Rev. A | Page 12 of 42
13114-011
HMC7043
Data Sheet
HMC7043
TYPICAL APPLICATION CIRCUITS
HIGH
IMPEDANCE DOWNSTREAM
DEVICE
INPUT
100Ω
LVDS
OUTPUT
HIGH
IMPEDANCE DOWNSTREAM
DEVICE
INPUT
100Ω
0.1µF
13114-018
LVDS
OUTPUT
HMC7043
0.1µF
13114-014
HMC7043
Figure 15. AC-Coupled LVDS Output Driver
Figure 19. DC-Coupled LVDS Output Driver
VCC
HMC7043
100Ω
HMC7043
LVPECLCOMPATIBLE
OUTPUT
0.1µF
HIGH
IMPEDANCE DOWNSTREAM
DEVICE
INPUT
0.1µF
CML
OUTPUT
50Ω
50Ω
13114-015
100Ω
DOWNSTREAM
DEVICE
(LVPECL)
50Ω
13114-019
100Ω
GND
Figure 16. AC-Coupled CML (Configured High-Z) Output Driver
HMC7043
0.1µF
VCC
100Ω
CML
OUTPUT
HIGH
IMPEDANCE DOWNSTREAM
DEVICE
INPUT
VCC
100Ω
13114-016
100Ω
0.1µF
CML
OUTPUT
Figure 17. AC-Coupled CML (Internal) Output Driver
0.1µF
Figure 21. DC-Coupled CML (Internal) Output Driver
HMC7043
SELF BIASED
REF, VCXO
INPUTS
13114-017
3.3V
DRIVER
0.1µF
DOWNSTREAM
DEVICE
(CML)
100Ω
13114-020
100Ω
HMC7043
0.1µF
0.1µF
13114-021
HMC7043
Figure 20. DC-Coupled LVPECL Output Driver
Figure 22. CLKIN, RFSYNCIN Input Single-Ended Mode
Figure 18. CLKIN/CLKIN , RFSYNCIN Input Differential Mode
Rev. A | Page 13 of 42
HMC7043
Data Sheet
TERMINOLOGY
Phase Jitter and Phase Noise
An ideal sine wave has a continuous and even progression of
phase with time from 0° to 360° for each cycle. Actual signals,
however, display a certain amount of variation from ideal phase
progression over time. This phenomenon is phase jitter. Although
many causes can contribute to phase jitter, one major cause is
random noise, which is characterized statistically as being
Gaussian (normal) in distribution.
This phase jitter leads to the energy of the sine wave in the
frequency domain spreading out, producing a continuous power
spectrum. This power spectrum is usually reported as a series of
values whose units are dBc/Hz at a given offset in frequency from
the sine wave (carrier). The value is a ratio (expressed in decibels)
of the power contained within a 1 Hz bandwidth with respect to
the power at the carrier frequency. For each measurement, the
offset from the carrier frequency is also given.
It is meaningful to integrate the total power contained within some
interval of offset frequencies (for example, 10 kHz to 10 MHz).
This is the integrated phase noise over that frequency offset
interval and can be readily related to the time jitter due to the
phase noise within that offset frequency interval.
Phase noise has a detrimental effect on the performance of analogto-digital converters (ADCs), digital-to-analog converters (DACs),
and RF mixers. It lowers the achievable dynamic range of the
converters and mixers, although they are affected in somewhat
different ways.
Time Jitter
Phase noise is a frequency domain phenomenon. In the time
domain, the same effect is exhibited as time jitter. When observing
a sine wave, the time of successive zero crossings varies. In a square
wave, the time jitter is a displacement of the edges from their
ideal (regular) times of occurrence. In both cases, the variations in
timing from the ideal are the time jitter. Because these variations
are random in nature, the time jitter is specified in seconds root
mean square (rms) or 1 sigma of the Gaussian distribution.
Time jitter that occurs on a sampling clock for a DAC or an
ADC decreases the signal-to-noise ratio (SNR) and dynamic
range of the converter. A sampling clock with the lowest possible
jitter provides the highest performance from a given converter.
Additive Phase Noise
Additive phase noise is the amount of phase noise that is
attributable to the device or subsystem being measured.
The phase noise of any external oscillators or clock sources is
subtracted, which makes it possible to predict the degree to
which the device impacts the total system phase noise when
used in conjunction with the various oscillators and clock
sources, each of which contributes a phase noise to the total. In
many cases, the phase noise of one element dominates the
system phase noise. When there are multiple contributors to
phase noise, the total is the square root of the sum of squares of
the individual contributors.
Additive Time Jitter
Additive time jitter is the amount of time jitter that is attributable to
the device or subsystem being measured. The time jitter of any
external oscillators or clock sources is subtracted, which makes
it possible to predict the degree to which the device impacts the
total system time jitter when used in conjunction with the various
oscillators and clock sources, each of which contributes a time
jitter to the total. In many cases, the time jitter of the external
oscillators and clock sources dominates the system time jitter.
Rev. A | Page 14 of 42
Data Sheet
HMC7043
THEORY OF OPERATION
The HMC7043 is a high performance, clock distribution IC
designed for extending the number of clock signals across the
system with minimal noise contribution. The device can be
used for distributing the noise sensitive reference clocks for high
speed data converters with either parallel or serial (JESD204B)
interfaces, FPGAs, and local oscillators. The HMC7043 is
designed to meet the requirements of demanding base station
designs, and offers a wide range of clock management and
distribution features to simplify baseband and radio card clock
tree designs. The device provides 14 low noise and configurable
outputs to offer flexibility in distributing clocks while applying
frequency division, phase adjustment, cycle slip, and external
signal synchronization options.
The HMC7043 generates up to seven DCLK and SYSREF clock
pairs per the JESD204B interface requirements. The system
designer can generate a lower number of DCLK and SYSREF
pairs, and configure the remaining output signal paths as
DCLKs, additional SYSREFs, or other reference clocks with
independent phase and frequency adjustment. Frequency
adjustment can be accomplished by selecting the appropriate
output divider values.
One of the unique features of the HMC7043 is the independent
flexible phase management of each of the 14 channels. Using a
combination of divider slip based, digital (coarse) and analog
(fine) delay adjustments, each channel can be programmed to
have a different phase offset. The phase adjustment capability
allows the designer to offset board flight time delay variations,
match data converter sample windows, and meet JESD204B
synchronization challenges. The output signal path design of
the HMC7043 is implemented to ensure both linear phase
adjustment steps and minimal noise perturbation when phase
adjustment circuits are turned on.
The HMC7043 provides output clock signals of up to 3.2 GHz,
while having the flexibility to support input reference frequencies of
up to 6 GHz when the internal clock division blocks are turned on.
The higher frequency support enables higher bandwidth RF
designs, and allows for distribution of low noise RF phase-locked
loop (PLL) voltage controlled oscillator (VCO) outputs as well
as other critical clocks across the system.
One of the key challenges in JESD204B system design is ensuring
the synchronization of data converter frame alignment across
the system, from the FPGA or digital front end (DFE) to ADCs
and DACs through a large clock tree that may comprise multiple
clock generation and distribution ICs.
There are two input paths on the HMC7043; one is for the clock
signal that is distributed, and the other may be used as an external
synchronization signal. In typical JESD204B systems, serial data
converter interfaces, there may be a need to ensure that all clock
signals that are sent to the data converters have phases which are
controlled by an FPGA. By virtue of the RF SYNC input, the
device ensures that output signals have a deterministic phase
alignment to this synchronization input. The RF SYNC input
can also implement multiple device clock trees by nesting more
than one HMC7043 to generate an even larger clock distribution
network, while still maintaining phase alignment across the
clock tree.
Offering excellent crosstalk, frequency isolation, and spurious
performance, the device generates independent frequencies in
both single-ended and differential formats including LVPECL,
LVDS, CML, and CMOS, and different bias conditions to
offset varying board insertion losses. The outputs can also be
programmed for ac or dc coupling and 50 Ω or 100 Ω internal
and external termination options.
The HMC7043 is programmed via a 3-wire serial port interface
(SPI). The HMC7043 is offered in a 48-lead, 7 mm × 7 mm,
LFCSP package with the exposed pad to ground.
Rev. A | Page 15 of 42
HMC7043
Data Sheet
DETAILED BLOCK DIAGRAM
CLK DISTRIBUTION PATH
CLKOUT0
MUX
SCLKOUT1
SCLKOUT1
MUX
CLKOUT2
CLKOUT2
MUX
SCLKOUT3
SCLKOUT3
MUX
CLKOUT4
CLKOUT4
MUX
SCLKOUT5
SCLKOUT5
MUX
CLKOUT6
CLKOUT6
MUX
SCLKOUT7
SCLKOUT7
MUX
ANALOG
DELAY
COARSE
DIGITAL
DELAY
DIVIDER
(1 TO 4094)
ANALOG
DELAY
DIVIDER
(1 TO 4094)
SYNC/PULSOR
CONTROL
CYCLE
SLIP/
SYNC
ANALOG
DELAY
DIVIDER
(1 TO 4094)
CYCLE
SLIP/
SYNC
ANALOG
DELAY
DIVIDER
(1 TO 4094)
CYCLE
SLIP/
SYNC
CYCLE
SLIP/
SYNC
ANALOG
DELAY
DIVIDER
(1 TO 4094)
CYCLE
SLIP/
SYNC
CYCLE
SLIP/
SYNC
ANALOG
DELAY
DIVIDER
(1 TO 4094)
CYCLE
SLIP/
SYNC
CYCLE
SLIP/
SYNC
ANALOG
DELAY
DIVIDER
(1 TO 4094)
CYCLE
SLIP/
SYNC
CYCLE
SLIP/
SYNC
LDOBYP2
DIVIDER
(1 TO 4094)
COARSE
DIGITAL
DELAY
DIVIDER
(1 TO 4094)
COARSE
DIGITAL
DELAY
DIVIDER
(1 TO 4094)
COARSE
DIGITAL
DELAY
FUNDAMENTAL MODE
CYCLE
SLIP/
SYNC
CYCLE
SLIP/
SYNC
FUNDAMENTAL MODE
LDOs
COARSE
DIGITAL
DELAY
FUNDAMENTAL MODE
FUNDAMENTAL MODE
COARSE
DIGITAL
DELAY
DIVIDER
(1 TO 4094)
FUNDAMENTAL MODE
FUNDAMENTAL MODE
COARSE
DIGITAL
DELAY
COARSE
DIGITAL
DELAY
FUNDAMENTAL MODE
FUNDAMENTAL MODE
COARSE
DIGITAL
DELAY
DIVIDER
(1 TO 4094)
FUNDAMENTAL MODE
FUNDAMENTAL MODE
COARSE
DIGITAL
DELAY
RFSYNCIN
GPI
SPI
TO LEAF DIVIDERS
CYCLE
SLIP/
SYNC
FUNDAMENTAL MODE
COARSE
DIGITAL
DELAY
RFSYNCIN
SYSREF TIMER
FUNDAMENTAL MODE
COARSE
DIGITAL
DELAY
CLKIN
CYCLE
SLIP/
SYNC
FUNDAMENTAL MODE
ANALOG
DELAY
BGABYP1
DIVIDER
(1 TO 4094)
DIVIDER
(1 TO 4094)
COARSE
DIGITAL
DELAY
FUNDAMENTAL MODE
CLKOUT8
ANALOG
DELAY
MUX
ANALOG
DELAY
MUX
ANALOG
DELAY
MUX
ANALOG
DELAY
MUX
ANALOG
DELAY
MUX
ANALOG
DELAY
MUX
CLKOUT8
SCLKOUT9
SCLKOUT9
CLKOUT10
CLKOUT10
SCLKOUT11
SCLKOUT11
CLKOUT12
CLKOUT12
SCLKOUT13
SPI
ALARM GENERATION
DEVICE
CONTROL
SDATA SCLK SLEN
GPIO
RESET
SCLKOUT13
13114-022
CLKOUT0
COARSE
DIGITAL
DELAY
CLKIN
DIVIDER
÷1, ÷2
Figure 23. Detailed Block Diagram
2.8V
Input Termination Network—Common for All Input Buffers
The two clock and RFSYNC input buffers share similar architecture
and control features. The input termination network is configurable
to 100 Ω, 200 Ω, and 2 kΩ differentially. It is typically ac-coupled
on the board, and uses the on-chip resistive divider to set the
internal common-mode voltage, VCM, to 2.1 V.
By closing the 50 Ω termination switch (see Figure 24), the network
also can serve as the termination system for an LVPECL driver.
Although the input termination network for the two clock and
RFSYNC input buffers is identical, the buffer behind the
network is different.
50Ω,
100Ω,
1kΩ
4kΩ
5kΩ
1pF
50Ω
50Ω,
100Ω,
1kΩ
13033-045
CLOCK INPUT NETWORK
Figure 24. On-Chip Termination Network for Clock and RFSYNC Buffers
Recommendations for Normal Use
For both buffer types, unless there are extenuating circumstances
in the application, use 100 Ω differential termination resistors
to control reflections, to use the on-chip dc bias network to set
the common mode level, and to externally ac couple the input
signals in. Do not use a receiver side dc termination of the
LVPECL signal.
Rev. A | Page 16 of 42
Data Sheet
HMC7043
Single-Ended Operation
•
The buffers can support a single-ended signal with slightly reduced
input sensitivity and bandwidth. If driving any of the buffers
single-ended, ac couple the unused leg of the buffer to ground
at the input of the die.
•
•
Fine phase control of synchronization channels with
respect to the DCLK channel
Frequency coverage to satisfy typical clock rates in systems
Skew between SYSREF and DCLK channels that is much
less than a DCLK period
Spur and crosstalk performance that does not impact
system budgets
•
Maximum Signal Swing Considerations
The internal supplies to these input buffers are supplied directly
from 3.3 V. The ESD network and parasitic diodes can generally
shunt away excess power and protect the internal circuits
(withstanding reference powers above 13 dBm). Nevertheless,
to protect from latch-up concerns, the signals on the reference
inputs must not exceed the 3.3 V internal supply. For a 2.1 V
common mode, 50 Ω single-ended source, this allows ~1200 mV
of amplitude, or 11 dBm maximum reference power.
The HMC7043 output network supports the following recommended features, which are sometimes critical in user applications:
•
Deterministic synchronization of the output channels with
respect to an external signal (RFSYNC), which allows
multichip synchronization and clean expansion to larger
systems
Pulse generator behavior to temporarily generate a
synchronization pulse stream at a user request
The flexibility to define unused JESD204B SYSREF and
DCLK channels for other purposes
Glitchless phase control of signals relative to each other
50% duty cycle clocks with odd division ratios
Multimode output buffers with a variety of swings and
termination options
Skew between all channels is much less than a DCLK period
Adjustable performance vs. power consumption for less
sensitive clock channels
•
CLOCK OUTPUT NETWORK
•
The HMC7043 is a high performance clock buffer, is appropriate
for JESD204B data converters, and much of the uniqueness of a
JESD204B clock generation chip relates to the array of output
channels. In this device, the output network requirements include
•
•
A large number of device clock (DCLK) and synchronization
(SYSREF) channels
Very good phase noise floor of the DCLK channels that can
be connected to critical data converter sample clock inputs
Deterministic phase alignment between all output channels
relative to one another
•
•
SYSREF INPUT NETWORK
RF
SYNC
D Q
RESET
SYSREF TIMER
CLKIN PATH
SYNC/PULSE GENERATOR
CONTROL
PULSE GENERATOR REQUEST (FROM SPI OR GPI PIN)
SYNC REQUEST (FROM SPI OR GPI PIN)
SYNC_FSM_STATE
OUTPUT CHANNEL ×14
LEAF CONTROLLER
CLOCK
GATING
DIVIDER
DIGITAL
DELAY AND
RETIME
13114-023
•
•
•
•
Figure 25. Clock Output Network Simplified Diagram
Rev. A | Page 17 of 42
HMC7043
Data Sheet
Each of the 14 output channels are logically identical. The only
distinction between the SYSREF and DCLK channels is in the
SPI configuration, and in how they are used. Each channel
contains independent dividers, phase adjustment, and analog
delay circuits. This combination provides the ultimate flexibility,
cleanly accommodating nonJESD204B devices in the system.
In addition to the 14 output channel dividers, an internal SYSREF
timer continually operates, and the synchronization of the output
channel dividers occurs deterministically with respect to this
timer, which the user can rephased deterministically by the user
through GPI or SPI or deterministically by using the RFSYNCIN/
RFSYNCIN differential pins.
The pulse generator functionality of the JESD204B standard
involves temporarily generating SYSREF output pulses, with
appropriate phasing, to downstream devices. The centralized
SYSREF timer and the associated SYNC/pulse generator control
manage the process of enabling the intended SYSREF channels,
phasing them, and then disabling them for signal integrity and
power saving advantages.
Basic Output Divider Channel
Each of the 14 output channels are logically identical, and support
divide ratios from 1 to 4094. The supported odd divide ratios
(1, 3, or 5) have 50.0% duty cycle. The only distinction between
a SYSREF channel and a device clock channel is in the SPI
configuration and the typical usage of a given channel.
For basic functionality and phase control, each output path
consists of the following:
•
•
•
•
•
•
Divider—generates the logic signal of the appropriate
frequency and phase
Digital phase adjust—adjusts the phase of each channel in
increments of ½ clock input cycles
Retimer—a low noise flip flop to retime the channel,
removing any accumulated jitter
Analog fine delay—provides a number of ~25 ps delay steps
Selection mux—selects the fundamental, divider, analog
delay, or an alternate path
Multimode output buffer—low noise LVDS, CML, CMOS,
or LVPECL
The digital phase adjuster and retimer launch on either clock
phase of the clock input, depending on the digital phase adjust
setpoint (Coarse Digital Delay[4:0]).
To support divider synchronization, arbitrary phase slips, and
pulse generator modes, the following blocks are included:
•
•
A clock gating stage pauses the clock for synchronization
or slip operations
An output channel leaf (×14) controller that manages slip,
synchronization, and pulse generators with information
from the SYSREF finite state machine (FSM)
Each channel has an array of control signals. Some of the
controls are described in Table 10.
System wide broadcast signals can be triggered from the SPI or
general-purpose input (GPI) port to issue a SYNC command
(to align dividers to the system internal SYSREF timer), issue a
pulse generator stream, (temporarily exporting SYSREF signals to
receivers), or to cause the dividers to slip a number of clock
input cycles to adjust their phases.
Individual dividers can be made sensitive to these events by
adjusting their slip enable, SYNC enable, and Start-Up Mode[1:0]
configuration, as described in Table 11.
When output buffers are configured in CMOS mode and phase
alignment is required among the outputs, additional multislip
delays must be issued for Channel 0, Channel 3, Channel 5,
Channel 6, Channel 9, Channel 10, and Channel 13. The value
of the delay must be as large as half of the selected divider ratio.
Note that this requirement of having additional multislip delays
is not needed when the channels are used in LVPECL, CML, or
LVDS mode.
If a channel is configured to behave as a pulse generator, to
temporarily power up and power down according to the GPI
and SPI pulse generator commands; additional controls define the
behavior outside of the pulse generator chain (see Table 12).
Each divider has an additional phase offset register that adjusts
the start phase or influences the behavior of slip events sent via
the SPI (see Table 13).
Table 14 outlines the typical configuration combinations for a
DCLK channel relative to a SYSREF synchronization channel.
Note that other combinations are possible. Synchronization of
downstream devices can be managed manually, or by using the
pulse generator functionality of the HMC7043. See the Typical
Programming Sequence section for more information about the
differences between the two methods.
Rev. A | Page 18 of 42
Data Sheet
HMC7043
Table 10. Basic Divider Controls
Bit Name
Channel Enable
12-Bit Channel Divider[11:0]
High Performance Mode
Coarse Digital Delay[4:0]
Fine Analog Delay[4:0]
Output Mux Selection[1:0]
Force Mute[1]
Description
Channel enable. If set to 0, the channel is disabled. If set to 1, the channel can be enabled depending on the
settings of the Start-Up Mode[1:0], Seven Pairs of 14-Channel Outputs Enable[6:0], and sleep mode bits.
Divide ratio.12-bit divide ratio, split across two words (MSB and LSB). Set to 0 if not using the channel divider
(Output Mux Selection[1:0] = 2 or 3)
High performance mode. Adjusts the divider and buffer bias to improve swing/phase noise slightly at the expense of
power. The performance advantage is about 1 dB, and the current penalty depends on whether the divider is enabled.
Digital delay. Adjusts the phase of the divider signal by up to 17 ½ cycles of the clock input. This circuit is
practically noiseless; however, note that a low amount of additional current is consumed.
Analog delay. Adjusts the delay of the divider signal in increments of ~25 ps. Set Output Mux Selection[1:0] = 1
to expose this channel. Exposing this channel causes phase noise degradation of up to 12 dB; therefore, do not use
on noise sensitive DCLK channels.
Output mux selection. 00 = divider channel, 01 = analog delay, 10 = other channel of pair, 11 = input clock.
Fundamental mode can be generated with the divider (12-Bit Channel Divider[11:0] = 1), or via Output Mux
Selection[1:0] = 10 and 12-Bit Channel Divider[11:0] = 0. Because the divider path consumes power and degrades
phase noise slightly, the fundamental mux path is recommended, but at a cost of a deterministic skew vs. a path that
is divider-based. Such skew can be compensated for with delay (digital and analog) on the divider-based path.
Force mute. If 1, and the channel enable is true (channel enable = 1) and Force Mute[0] = 0, the signal just
before the output buffer is asynchronously forced to Logic 0. To see the effect of this, the output buffer must
be enabled, which is dependent on the dynamic driver enable and Start-Up Mode[1:0] controls.
Table 11. Channel Features
Bit Name
Slip Enable
SYNC Enable
Start-Up Mode[1:0]
Description
Slip enable. A channel processes slip requests broadcast from the SPI or GPI (or, if multislip enable = 1, initiated
following a recognized SYNC or pulse generator startup).
SYNC enable. A channel processes synchronization events broadcast from the SPI or GPI or due to SYNC/RF SYNC (via
the SYSREF FSM) to reset the phase. This signal can be safely toggled on and off to adjust SYNC sensitivity without
risking the state of the divider.
00 = asynchronous (normal mode). The divider starts with uncontrolled phase. It is rephased by SYNC events if SYNC
enable = 1.
11 = dynamic (pulse generator mode). The divider monitors pulse generator events broadcast from the SYSREF
controller. It is powered up just before a pulse generator chain, rephased at the start, and powered down after the
pulse generator chain. This mode is only supported for divide ratios > 31.
Table 12. Pulse Generator Mode Behavior Options
Bit Name
Dynamic Driver Enable
Force Mute[0]
Description
Dynamic output buffer enable (pulse generator mode only).
0 = the output buffer is simply enabled/disabled with the main channel enable.
1 = the output buffer enable is controlled together with the channel divider, which allows it to dynamically power
down outside pulse generator events.
Idle at Logic 0 (pulse generator mode only).
1 = if the buffer remains on outside of the pulse generator chain, drive to Logic 0.
0 = if the buffer remains on outside of the pulse generator chain, allow the outputs to float naturally to
approximately VCM.
Rev. A | Page 19 of 42
HMC7043
Data Sheet
Table 13. Multislip Configuration
Bit Name
Multislip Enable
12-Bit Multislip Digital Delay[11:0]
Description
Allow multislip. This bit determines whether the 12-Bit Multislip Digital Delay[11:0] parameter is used
for multislip operations. Note that a multislip operation is automatically started following a SYNC or
pulse generator initiation if multislip enable = 1.
Multislip amount. If multislip enable = 1, any slip events (caused by GPI, SPI, SYNC, or pulse generator
events) repeat the number of times set by 12-Bit Multislip Digital Delay[11:0] to adjust the phase by the
multislip amount × clock input cycles. A value of 0 is not supported if multislip enable = 1. Note that
phase slips are free from a noise and current perspective, that is, no additional power is needed and
with no noise degradation, but they take some time to occur. Each slip operation takes a number of
nanoseconds to complete, and thus the phases do not necessarily stabilize immediately. An alarm is
available for the user to indicate when all phase operations are complete.
Table 14. Typical Configuration Combinations
Bit Name
12-Bit Channel Divider[11:0]
Start-Up Mode-Bit
Fine Analog Delay[4:0]
Coarse Digital Delay[4:0]
Slip Enable
Multislip Enable
High Performance Mode
Sync Enable
Dynamic Driver Enable
Force Mute[1:0]
DCLK
Small
Normal
Off
Optional
Optional
Optional
Optional
On
Don’t care
Don’t care
Pulse Generator SYSREF
Big
Pulse generator
Optional
Optional
Optional
Off
Off
On
On
On
Synchronization FSM/Pulse Generator Timing
Figure 25 show a block diagram of the interface of the SYNC/
pulse generator control to the divider channels and the internal
SYSREF timer.
The SYSREF timer counts in periods defined by SYSREF
Timer[11:0], a 12-bit setting from the SPI. The SYSREF
timer sequences the enable, reset, and startup, and disables
the downstream dividers in the event of sync or pulse generator
requests. Program the SYSREF timer count to a submultiple of
the lowest output frequency in the clock network, and never
faster than 4 MHz. To synchronize the divider channels, it is
recommended, though not required, that the SYSREF Timer[11:0]
bits be set to a related frequency that is either a factor or
multiple of other frequencies on the IC.
The pulse generator is defined with respect to the periods of
this SYSREF timer, not with respect to the output period. This
behavior of the pulse generator leads to a timing constraint that
must be considered to prevent any runt pulses from affecting
the pulse generator stream.
Manual SYSREF
Big
Normal
Optional
Optional
Optional
Optional
Off
On
Don’t care
Don’t care
NonJESD204B
Any
Normal
Off
Optional
Optional
Optional
Optional
Optional
Don’t care
Don’t care
Figure 27 shows the start-up behavior of an example divider
that is configured as a pulse generator, with a period matching
the internal SYSREF period.
The startup of the pulse stream occurs a fixed number of clock
input cycles after the FSM transitions to the start phase. Disabling
the pulse generator stream where the logic path is forced to zero
comes from a combinational path directly from the FSM.
Because the divider has the option for nearly arbitrary phase
adjustment, the stop condition can arrive when the pulse stream
is a Logic 1 and create a runt pulse.
For phase offsets of zero to (50% − 8) clock input cycles, and at
clock input frequencies <3 GHz, this condition is met naturally
within the design. For clock input frequencies >3 GHz, it is
recommended to use digital delay or slip offsets to increase the
natural phase offset and avoid the stress conditions.
The situation is avoided by never applying phase offset more
than (50% − 8) clock input cycles to an output channel
configured as a pulse generator.
Rev. A | Page 20 of 42
Data Sheet
HMC7043
RF_SYNC
RESET
PULSE
GENERATOR
SETUP
NOTIFY CHANNEL FSM
WHAT TYPE OF EVENT
IS COMING
POWER DIVIDERS/SYNC BLOCKS,
PAUSE BLOCKS, RESET LATCHES
CLEAR
REMOVE LATCH RESET,
PREPARE TO START CLOCKS
WAIT
SYNC
REQUEST
START CLOCKS,
WITH CLEAN TIMING,
SMALL PIPELINE DELAY
STARTUP
PULSE
GENERATOR
TIMEOUT?
WAIT UNTIL THE NUMBER OF
PULSE GENERATOR CYCLES
EXPIRES
DONE
REMOVE POWER
13114-125
SYNC
SETUP
PULSE
GENERATOR
REQUEST
Figure 26. Synchronization FSM Flowchart
FSM STATE
STARTUP
PULSE GENERATOR = 2
DONE
DIVIDER CHANNEL
IF MUTE SIGNAL ARRIVES QUICKLY
RELATIVE TO SIGNAL TRAIN,
NO RUNT PULSE
FIXED NUMBER OF CLOCK INPUT CYCLES
FROM STATE CHANGE TO STARTUP, AND
ANY INTENTIONAL DIGITAL/ANALOG OFFSET
FSM STATE
STARTUP
PULSE GENERATOR = 2
DONE
IF CONTROL IS TOO LATE
RELATIVE TO SIGNAL TRAIN,
THERE IS A RUNT PULSE
Figure 27. Start-Up Behavior of an Example Divider Configured as a Pulse Generator
Rev. A | Page 21 of 42
13114-126
DIVIDER CHANNEL
HMC7043
Data Sheet
Clock Grouping, Skew, and Crosstalk
Table 15. Supply Pin Clock Grouping by Location
Although the output channels are logically independent, for
physical reasons, they are first grouped into pairs, called clock
groups. Each clock group shares a reference, an input buffer,
and a SYNC retime flip flop originating from the clock
distribution network.
Supply Pin
VCC2_OUT
Location
Southwest
Clock Group
1
VCC3_OUT
South
2
3
The second level of grouping is according to the supply pin. Clock
Group 1 (Channel 2 and Channel 3) is on an independent supply,
and the other supply pins are each responsible for two clock groups.
VCC6_OUT
As the output channels are more tightly coupled (by sharing a
clock group or by sharing a supply pin), the skew is minimized.
However, the isolation between those channels suffers.
Northeast
4
5
VCC7_OUT
Northwest
6
Table 15 shows the clock grouping by location, and Table 16
show the typical skew and isolation that can be expected and how
it scales with distance between output channels.
0
Isolation improves as either the aggressor or the affected
frequencies decrease. Nevertheless, for particularly important
clock channels where spurious tones must be minimized,
carefully consider their frequency and channel configurations
to isolate continuously running frequencies onto different
supply domains. Channels configured as pulse generators are
normally not an issue, because they are disabled during normal
operation.
Table 16. Typical Skew and Isolation vs. Distance
Distance
Distant Supply Group
Closest Neighbor on
Different Supply Group
Shared Supply
Same Clock Group
Typical
Skew (ps)
±20
±15
1 GHz Isolation,
Differential (dB)
90 to 100
70
±10
±10
60
45
Output Buffer Details
CLKOUT8
CLKOUT8
VCC6_OUT
CLKOUT10
CLKOUT10
SCLKOUT11
SCLKOUT11
SCLKOUT13
SCLKOUT13
CLKOUT12
CLKOUT12
NORTHEAST
VCC7_OUT
NORTHWEST
CLKOUT0
CLKOUT0
SCLKOUT9
SCLKOUT9
SCLKOUT1
SCLKOUT1
GPIO
RESET
SPI
BGAPBYP1
VCC5_
SYSREF
LDOBYP2
RFSYNCIN
RFSYNCIN
VCC1_
CLKDIST
VCC4_
CLKIN
SCLKOUT3
SCLKOUT3
Figure 28. Clock Grouping
Rev. A | Page 22 of 42
SCLKOUT7
SCLKOUT7
CLKOUT6
CLKOUT6
VCC3_OUT
SCLKOUT5
SCLKOUT5
VCC2_OUT
CLKOUT4
CLKOUT4
SOUTH
13114-026
CLKIN
CLKIN
CLKOUT2
CLKOUT2
SOUTHWEST
Channel
2
3
4
5
6
7
8
9
10
11
12
13
0
1
Data Sheet
HMC7043
Figure 28 shows the clock groups by supply pin location on the
package. With appropriate supply pin bypassing, the spurious
noise of the outputs is improved.
Table 15 describes how the supply pins of each of the 14 clock
channels are connected within the seven clock groups. Clock
channels that are closest to each other have the best channel to
channel skew performance, but they also have the lowest
isolation from each other. Select critical signals that require
high isolation from each other from groups with distant supply
pin locations. An example of the expected isolation and channel
to channel skew performance of the HMC7043 at 1 GHz is
provided in Table 16.
7.
8.
9.
10.
11.
SYSREF Valid Interrupt
One of the challenges in a JESD204B system is to control and
minimize the latency from the primary system controller IC,
typically an ASIC or FPGA, to the data converters. To estimate
the correct amount of latency in the system, the designer must
know the time required for a master clock generator like the
HMC7043 to provide the correct output phases at each output
channel after receiving the synchronization request. Typically, a
period of time is required on the device to implement the
change requests on the outputs due to internal state machine
cycles, data transfers, and any propagation delays. The SYSREF
valid interrupt is a function to notify the user that the correct
output settings and phase relationships are established, allowing
the user to identify quickly that the desired SYSREF and device
clock states are presented at the outputs of the HMC7043.
The user has the flexibility to assign the SYSREF valid interrupt to
a GPO pin or to use a software flag, set via Register 0x007D, Bit 2,
which the user may poll as necessary. The flag notifies the user
when the system is configured and operating in the desired
state, or conversely when it is not ready.
TYPICAL PROGRAMMING SEQUENCE
2.
3.
4.
5.
6.
13.
The system is initialized.
For power savings and the reduction of the cross coupling of
frequencies on the HMC7043, shut down the SYSREF channels.
1.
2.
Program each JESD204B slave to ignore the SYSREF input
channel.
On the HMC7043, disable the individual channel enable bits
of each SYSREF channel.
To resynchronize one or more of the JESD204B slaves, use the
following procedure:
To initialize the HMC7043 to an operational state, use the
following programming procedure:
1.
12.
Issue a software restart to reset the system and initiate
calibration. Toggle the restart dividers/FSMs bit to 1 and
then back to 0.
Send a sync request via the SPI (set the reseed request bit)
to align the divider phases and send any initial pulse
generator stream.
Wait six SYSREF periods (6 × SYSREF Timer[11:0]) to
allow the outputs to phase appropriately (~3 μs in typical
configurations).
Confirm that the outputs have all reached their phases by
checking that the clock outputs phases status bit = 1.
At this time, initialize any other devices in the system.
Configure the slave JESD204B devices in the system to
operate with the SYSREF signal outputs from the HMC7043.
The SYSREF channels from the HMC7043 can be on either
asynchronously or dynamically, and may temporarily turn
on for a pulse generator stream.
Slave JESD204B devices in the system must be configured
to monitor the input SYSREF signal exported from the
HMC7043. At this point, SYSREF channels from the
HMC7043 can either be on asynchronously (running) or on
dynamically (temporarily turn on for a pulse generator train).
When all JESD204B slaves are powered and ready, send a
pulse generator request to send out a pulse generator chain on
any SYSREF channels programmed for pulse generator mode.
1.
Connect the HMC7043 to the rated power supplies. No
specific power supply sequencing is necessary.
Release the hardware reset by switching from Logic 1 to
Logic 0 when all supplies are stable.
Load the configuration updates (provided by Analog
Devices, Inc.) to specific registers (see Table 40).
Program the SYSREF timer. Set the divide ratio (a submultiple
of the lower output channel frequency). Set the pulse
generator mode configuration, for example, selecting the
level sensitivity option and the number of pulses desired.
Program the output channels. Set the output buffer modes
(for example, LVPECL, CML, and LVDS). Set the divide
ratio, channel start-up mode, coarse/analog delays, and
performance modes.
Ensure the clock input signal are provided to CLKIN.
2.
3.
4.
5.
Rev. A | Page 23 of 42
Set the channel enable and SYNC enable bit of the SYSREF
channel of interest.
To prevent an output channel from responding to a sync
request, disable the SYNC enable mask of each channel so
that it continues to run normally without a phase adjustment.
Issue a reseed request to phase the SYSREF channel
properly with respect to the DCLK.
Enable the JESD204B slave sensitivity to the SYSREF channel.
If the SYSREF channel is in pulse generator mode, wait at
least 20 SYSREF periods from Step 3, and issue a pulse
generator request.
HMC7043
Data Sheet
POWER SUPPLY CONSIDERATIONS
The output buffers are susceptible to supply with a certain
extent. The output buffers are also susceptible to supply noise,
but to a lesser extent. A noise tone of −60 dBV at a 40 MHz
offset results in a −90 dBc tone at the output of the buffers in
CML mode and −85 dBc in LVPECL mode. This result is a
relatively flat frequency response, and these numbers are
measured differentially. Phase noise/spurs caused by supply
noise on the output buffers do not scale with output frequency.
Table 17 lists the supply network of the HMC7043 by pin, showing
the relevant functional blocks. Three different usage profiles are
defined for the network, not including the output channel
supplies, which are accounted for separately.
The values listed under Profile 0 to Profile 2 in Table 17 and Table 18
are the typical currents of that block or feature. If a number is not
listed in a profile column, a typical profile does not exist for that
block or feature, but the user can mix and match features outside
of the profile list, and can determine what the power consumption
is going to be given the current listings per feature.
Table 17. Supply Network of the HMC7043 by Pin for VCC1_CLKDIST, VCC4_CLKIN, and VCC5_SYSREF
Circuit Block
VCC1_CLKDIST
Regulator to 1.8 V, Bypassed on LDOBYP2
SYSREF Timer
GPO Driver in High Speed Mode2
Clock Input Distribution Network
Sync Retiming Network
Subtotal for VCC1_CLKDIST
VCC4_CLKIN
CLKIN/CLKIN Buffer
CLKIN/CLKIN Path
RFSYNCIN/RFSYNCIN4 Retimer
Comment
Profile1
1
Typical Current (mA)
0
2
1
2
2
1
2
Minimum possible value
84
8
84
34
Minimum possible value3
8
10
87
36
16
16
16
16
16
Extra current for divide by 2
2
7
3
9
RFSYNCIN/RFSYNCIN Buffer
Subtotal or VCC4_CLKIN
0
VCC5_SYSREF
SYSREF Input Network
SYSREF Counter Base
SYSREF Counter, SYNC Network
Subtotal for VCC5_SYSREF
11
12
4
27
Subtotal (Without Output Paths)
1
11
12
0
23
0
10
126
52
Profile 0 is sleep mode; Profile 1 is power-up defaults, SYSREF timer running and RFSYNC buffer is disabled; Profile2 is only one clock output enabled, SYSREF timer is
not running and RFSYNC buffer is disabled.
The current is highly dependent on rate of input/output and load of input/output traces. For heavily loaded traces, it is recommended to use a series resistance of
~100 Ωto minimize the IR drop on the internal regulator during transitions.
3
A temporary current only.
4
Transient current in synchronization mode, can be temporarily enabled when using external synchronization.
2
Rev. A | Page 24 of 42
Data Sheet
HMC7043
Table 18. Supply Network of the HMC7043 by Pin for the Clock Output Network
Profile1
Per Output Channel
Digital Regulator and Other Sources
Buffer
LVPECL
CML100
High Power
Low Power
LVDS
High Power
Low Power
CMOS
Channel Mux
Different Power Modes Deleted
Digital Delay
Off
Setpoint > 1
Analog Delay
Off
Minimum Setting
Maximum Setting
Divider Logic
0
÷1
÷2
÷3
÷4
÷5
÷6
÷8
÷16
÷32
÷2044
SYNC Logic3
Slip Logic3
Subtotal
Comment
Typical Current (mA)
2.5
Including term currents
43
Including term currents
31
24
At 307 MHz
10
8
25
Included2
2
At 100 MHz, both sections
0
0.5
1
2.5
2
2.5
43
43
Not using divider path
2
43
2
2
3
Included2
9
9
0
Included2
27
24
31
28
30
26
28
29
29
29
4
4
0
3
9
9
0
29
29
2.5
1
4
2.5
10
Included2
3
Glitchless mode enabled
3
2.5
48
87
13
89
Profile 0 is sleep mode; Profile 1 is fundamental mode; Profile 2 is SYSREF channel matched to fundamental mode; Profile 3 is LVDS—high power signal source from
other channel; and Profile 4 is worst case configuration for power consumption of a channel.
2
The base current consumption of the circuit (for example, mux) is included in the buffer typical current.
3
Currents only occur temporarily during a synchronization event.
Rev. A | Page 25 of 42
HMC7043
Data Sheet
SERIAL CONTROL PORT
SERIAL PORT INTERFACE (SPI) CONTROL
Typical Write Cycle
The HMC7043 can be controlled via the SPI using 24-bit
registers and three pins: serial port enable (SLEN) serial data
input/output (SDATA), and serial clock (SCLK).
1.
A typical write cycle is shown in Figure 30 and occurs as follows:
The master (host) asserts both SLEN and SDATA to
indicate a read, followed by a rising edge SCLK. The slave
(HMC7043) reads SDIO on the first rising edge of SCLK
after SLEN. Setting SDATA low initiates a write.
The host places the 2-bit multibyte field to be written to
low (0) on the next two falling edges of SCLK. The
HMC7043 registers the 2-bit multibyte field on the next
two rising edges of SCLK.
The host places the13-bit address field (A12 to A0), MSB
first, on SDATA on the next 13 falling edges of SCLK. The
HMC7043 registers the 13-bit address field (MSB first) on
SDIO over the next 13 rising edges of SCLK.
The host places the 8-bit data (D7 to D0) MSB first on the
next eight falling edges of SCLK. The HMC7043 register
the 8-bit data (D7 to D0) MSB first on the next eight rising
edges of SCLK.
The final rising edge of SCLK performs the internal data
transfer into the register file, updating the configuration of
the device.
Deassertion of SLEN completes the register write cycle.
The 24-bit register, shown in Table 19, consists of the following:
•
•
•
•
1-bit read/write command
2-bit multibyte field (W1, W0)
13-bit address field (A12 to A0)
8-bit data field (D7 to D0)
2.
3.
Table 19. SPI Bit Map
MSB
Bit 23
R/W
Bit 22
W1
Bit 21
W0
LSB
Bits[7:0]
D7 to D0
Bits[20:8]
A12 to A0
4.
Typical Read Cycle
A typical read cycle is shown in Figure 29 and occurs as follows:
3.
4.
5.
1
SCLK
SDATA
X
2
READ W1
3
W0
5.
6.
4
5
A12
A11
16
A0
17
D7
18
D6
24
D0
13114-128
2.
The master (host) asserts both SLEN and SDATA to
indicate a read, followed by a rising edge SCLK. The slave
(HMC7043) reads SDATA on the first rising edge of SCLK
after SLEN. Setting SDATA high initiates a read.
The host places the 2-bit multibyte field to be written to
low (0) on the next two falling edges of SCLK. The
HMC7043 registers the 2-bit multibyte field on the next
two rising edges of SCLK.
The host places the 13-bit address field (A12 to A0) MSB
first on SDATA on the next 13 falling edges of SCLK. The
HMC7043 registers the 13-bit address field (MSB first) on
SDATA over the next 13 rising edges of SCLK.
The host registers the 8-bit data on the next eight rising
edges of SCLK. The HMC7043 places 8-bit data (D7 to D0)
MSB first on the next eight falling edges of SCLK.
Deassertion of SLEN completes the register read cycle.
SLEN
Figure 29. SPI Timing Diagram, Read Operation
1
SCLK
SDATA
X
WRITE
2
W1
3
W0
4
5
A12
A11
16
A0
17
D7
18
D6
24
D0
13114-129
1.
SLEN
Figure 30. SPI Timing Diagram, Write Operation
Rev. A | Page 26 of 42
Data Sheet
HMC7043
CONTROL REGISTERS
CONTROL REGISTER MAP
Table 20. Control Register Map
Address
Register Name
(Hex)
Global Control
0x0000
Global soft reset
control
0x0001
Global request
and mode
control
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
Input Buffer
0x000A
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Reserved
Reseed
request
High performance
distribution path
Reserved
Reserved
Mute output
drivers
Pulse
generator
request
Reserved
Global enable
control
Reserved
RF
Reserved
SYSREF
reseeder
timer
enable
enable
Seven Pairs of 14-Channel Outputs Enable[6:0]
Reserved
Reserved
Global mode
and enable
control
Global clear
alarms
Global
miscellaneous
control
Restart
dividers/
FSMs
Multislip
request
Reserved
Bit 0 (LSB)
Default
Value
(Hex)
Soft reset
0x00
Sleep mode
0x00
Reserved
0x00
Reserved
0x34
0x7F
0x0F
Reserved
Clear alarms
Reserved
Reserved (scratchpad)
Reserved
0x00
0x00
0x00
0x00
CLKIN0/CLKIN0
input buffer
control
Reserved
Input Buffer Mode[3:0]
Buffer enable
0x07
CLKIN1/CLKIN1
input buffer
control
GPIO/SDATA Control
0x0046
GPI control
0x0050
GPO control
Reserved
Input Buffer Mode[3:0]
Buffer enable
0x07
GPI enable
GPO enable
0x00
0x37
SDATA enable
0x03
0x000B
0x0054
Reserved
GPO Selection[4:0]
SDATA control
Analog delay
common
control
Alarm Masks Register
0x0071
Alarm mask
control
Reserved
Pulse Generator Mode Selection[2:0]
Reserved
SYNC
retime
Reserved
SYNC invert
polarity
SYSREF Timer[7:0] (LSB)
Reserved
Divide
by 2 on
clock
input
Reserved
Reserved
Sync
request
mask
Reserved
Product ID Value[7:0] (LSB)
Product ID Value[15:8] (Mid)
Product ID Value[23:16] (MSB)
Rev. A | Page 27 of 42
Clock
outputs
phase
status
mask
SYSREF
sync
status
mask
0x00
0x04
0x00
0x01
SYSREF Timer[11:8](MSB)
Reserved
0x0065
Product ID Registers
0x0078
Product ID
0x0079
0x007A
GPO
mode
SDATA
mode
Reserved
SYSREF/SYNC
0x005A
Pulse generator
control
0x005B
SYNC control
0x005C
SYSREF timer
control
0x005D
Clock Distribution Network
0x0064
Clock input
control
GPI Selection [2:0]
Reserved
Low
frequency
clock input
0x00
Analog delay
low power
mode
0x00
Reserved
0x10
HMC7043
Data Sheet
Address
Register Name
Bit 7 (MSB)
(Hex)
Alarm Readback Status Registers
0x007B
Readback
register
0x007D
Alarm readback
0x007F
Alarm readback
SYSREF Status Register
0x0091
SYSREF status
register
Other Controls
0x0098
Reserved
0x0099
Reserved
0x009D
Reserved
0x009E
Reserved
0x009F
Reserved
0x00A0
Reserved
0x00A2
Reserved
0x00A3
Reserved
0x00A4
Reserved
0x00AD
Reserved
0x00B5
Reserved
0x00B6
Reserved
0x00B7
Reserved
0x00B8
Reserved
Clock Distribution
0x00C8
Channel
Output 0
control
0x00C9
0x00CA
0x00CB
0x00CC
0x00CD
0x00CE
0x00CF
0x00D0
0x00D2
0x00D3
0x00D4
0x00D5
0x00D6
0x00D7
0x00D8
0x00D9
0x00DA
Channel
Output 1
control
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Reserved
Reserved
Sync
request
status
Bit 0 (LSB)
Default
Value
(Hex)
Alarm signal
Reserved
Clock
outputs
phases
status
SYSREF
sync
status
Reserved
Reserved
Reserved
Channel
outputs
FSM busy
SYSREF FSM State[3:0]
0x00
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
High
performance
mode
SYNC enable
Slip enable
Reserved
0x00
0x00
0xAA
0xAA
0x55
0x56
0x03
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Start-Up Mode[1:0]
Multislip
enable
Channel
enable
12-Bit Channel Divider[7:0] (LSB)
12-Bit Channel Divider[11:8] (MSB)
Fine Analog Delay[4:0]
Coarse Digital Delay[4:0]
12-Bit Multislip Digital Delay[7:0] (LSB)
Reserved
12-Bit Multislip Digital Delay[11:8] (MSB)
Reserved
Output Mux Selection[1:0]
Idle at Zero[1:0]
Dynamic
Driver Mode[1:0]
Reserved
Driver Impedance[1:0]
driver
enable
High
SYNC enable
Slip enable Reserved
Start-Up Mode[1:0]
Multislip Channel
performance
enable
enable
mode
12-Bit Channel Divider[7:0] (LSB)
Reserved
12-Bit Channel Divider[11:8] (MSB)
Reserved
Fine Analog Delay[4:0]
Reserved
Coarse Digital Delay[4:0]
12-Bit Multislip Digital Delay[7:0] (LSB)
Reserved
12-Bit Multislip Digital Delay[11:8] (MSB)
Reserved
Output Mux Selection[1:0]
Idle at Zero[1:0]
Dynamic
Driver Mode[1:0]
Reserved
Driver Impedance[1:0]
driver
enable
Reserved
Reserved
Reserved
Rev. A | Page 28 of 42
0xF3
0x04
0x00
0x00
0x00
0x00
0x00
0x00
0x01
0xFD
0x00
0x01
0x00
0x00
0x00
0x00
0x00
0x30
Data Sheet
Address
(Hex)
0x00DC
Register Name
Channel
Output 2
control
0x00DD
0x00DE
0x00DF
0x00E0
0x00E1
0x00E2
0x00E3
0x00E4
0x00E6
Channel
Output 3
control
Channel
Output 4
control
0x00F1
0x00F2
0x00F3
0x00F4
0x00F5
0x00F6
0x00F7
0x00F8
0x00FA
0x00FB
0x00FC
0x00FD
0x00FE
0x00FF
0x0100
0x0101
0x0102
Bit 7 (MSB)
High
performance
mode
Bit 6
SYNC enable
Bit 5
Slip enable
Bit 4
Reserved
Channel
Output 5
control
Bit 3
Bit 2
Start-Up Mode[1:0]
Bit 1
Multislip
enable
Bit 0 (LSB)
Channel
enable
12-Bit Channel Divider[7:0] (LSB)
12-Bit Channel Divider[11:8] (MSB)
Fine Analog Delay[4:0]
Coarse Digital Delay[4:0]
12-Bit Multislip Digital Delay[7:0] (LSB)
Reserved
12-Bit Multislip Digital Delay[11:8] (MSB)
Reserved
Output Mux Selection[1:0]
Idle at Zero[1:0]
Dynamic
Driver Mode[1:0]
Reserved
Driver Impedance[1:0]
driver
enable
High
SYNC enable
Slip enable Reserved
Start-Up Mode[1:0]
Multislip Channel
performance
enable
enable
mode
12-Bit Channel Divider[7:0] (LSB)
Reserved
12-Bit Channel Divider[11:8] (MSB)
Reserved
Fine Analog Delay[4:0]
Reserved
Coarse Digital Delay[4:0]
12-Bit Multislip Digital Delay[7:0] (LSB)
Reserved
12-Bit Multislip Digital Delay[11:8] (MSB)
Reserved
Output Mux Selection[1:0]
Idle at Zero[1:0]
Dynamic
Driver Mode[1:0]
Reserved
Driver Impedance[1:0]
driver
enable
High
SYNC enable
Slip enable Reserved
Start-Up Mode[1:0]
Multislip Channel
performance
enable
enable
mode
12-Bit Channel Divider[7:0] (LSB)
Reserved
12-Bit Channel Divider[11:8] (MSB)
Reserved
Fine Analog Delay[4:0]
Reserved
Coarse Digital Delay[4:0]
12-Bit Multislip Digital Delay[7:0] (LSB)
Reserved
12-Bit Multislip Digital Delay[11:8] (MSB)
Reserved
Output Mux Selection[1:0]
Idle at Zero[1:0]
Dynamic
Driver Mode[1:0]
Reserved
Driver Impedance[1:0]
driver
enable
High
SYNC enable
Slip enable Reserved
Start-Up Mode[1:0]
Multislip Channel
performance
enable
enable
mode
12-Bit Channel Divider[7:0] (LSB)
Reserved
12-Bit Channel Divider[11:8] (MSB)
Reserved
Fine Analog Delay[4:0]
Reserved
Coarse Digital Delay[4:0]
12-Bit Multislip Digital Delay[7:0] (LSB)
Reserved
12-Bit Multislip Digital Delay[11:8] (MSB)
Reserved
Output Mux Selection[1:0]
Idle at Zero[1:0]
Dynamic
Driver Mode[1:0]
Reserved
Driver Impedance[1:0]
driver
enable
Reserved
Reserved
Reserved
0x00E7
0x00E8
0x00E9
0x00EA
0x00EB
0x00EC
0x00ED
0x00EE
0x00F0
HMC7043
Rev. A | Page 29 of 42
Default
Value
(Hex)
0xF3
0x08
0x00
0x00
0x0
0x00
0x00
0x00
0x01
0xFD
0x00
0x01
0x00
0x00
0x00
0x00
0x00
0x30
0xF3
0x02
0x00
0x00
0x00
0x00
0x00
0x00
0x01
0xFD
0x00
0x01
0x00
0x00
0x00
0x00
0x00
0x30
HMC7043
Address
(Hex)
0x0104
Register Name
Channel
Output 6
control
0x0105
0x0106
0x0107
0x0108
0x0109
0x010A
0x010B
0x010C
0x010E
Channel
Output 7
control
Channel
Output 8
control
0x0119
0x011A
0x011B
0x011C
0x011D
0x011E
0x011F
0x0120
0x0122
0x0123
0x0124
0x0125
0x0126
0x0127
0x0128
0x0129
0x012A
Bit 7 (MSB)
High
performance
mode
Bit 6
SYNC enable
Bit 5
Slip enable
Bit 4
Reserved
Channel
Output 9
control
Bit 3
Bit 2
Start-Up Mode[1:0]
Bit 1
Multislip
enable
Bit 0 (LSB)
Channel
enable
12-Bit Channel Divider[7:0] (LSB)
12-Bit Channel Divider[11:8] (MSB)
Fine Analog Delay[4:0]
Coarse Digital Delay[4:0]
12-Bit Multislip Digital Delay[7:0] (LSB)
Reserved
12-Bit Multislip Digital Delay[11:8] (MSB)
Reserved
Output Mux Selection[1:0]
Idle at Zero[1:0]
Dynamic
Driver Mode[1:0]
Reserved
Driver Impedance[1:0]
driver
enable
High
SYNC enable
Slip enable Reserved
Start-Up Mode[1:0]
Multislip Channel
performance
enable
enable
mode
12-Bit Channel Divider[7:0] (LSB)
Reserved
12-Bit Channel Divider[11:8] (MSB)
Reserved
Fine Analog Delay[4:0]
Reserved
Coarse Digital Delay[4:0]
12-Bit Multislip Digital Delay[7:0] (LSB)
Reserved
12-Bit Multislip Digital Delay[11:8] (MSB)
Reserved
Output Mux Selection[1:0]
Idle at Zero[1:0]
Dynamic
Driver Mode[1:0]
Reserved
Driver Impedance[1:0]
driver
enable
High
SYNC enable
Slip enable Reserved
Start-Up Mode[1:0]
Multislip Channel
performance
enable
enable
mode
12-Bit Channel Divider[7:0] (LSB)
Reserved
12-Bit Channel Divider[11:8] (MSB)
Reserved
Fine Analog Delay[4:0]
Reserved
Coarse Digital Delay[4:0]
12-Bit Multislip Digital Delay[7:0] (LSB)
Reserved
12-Bit Multislip Digital Delay[11:8] (MSB)
Reserved
Output Mux Selection[1:0]
Idle at Zero[1:0]
Dynamic
Driver Mode[1:0]
Reserved
Driver Impedance[1:0]
driver
enable
High
SYNC enable
Slip enable Reserved
Start-Up Mode[1:0]
Multislip Channel
performance
enable
enable
mode
12-Bit Channel Divider[7:0] (LSB)
Reserved
12-Bit Channel Divider[11:8] (MSB)
Reserved
Fine Analog Delay[4:0]
Reserved
Coarse Digital Delay[4:0]
12-Bit Multislip Digital Delay[7:0] (LSB)
Reserved
12-Bit Multislip Digital Delay[11:8] (MSB)
Reserved
Output Mux Selection[1:0]
Idle at Zero[1:0]
Dynamic
Driver Mode[1:0]
Reserved
Driver Impedance[1:0]
driver
enable
Reserved
Reserved
Reserved
0x010F
0x0110
0x0111
0x0112
0x0113
0x0114
0x0115
0x0116
0x0118
Data Sheet
Rev. A | Page 30 of 42
Default
Value
(Hex)
0xF3
0x02
0x00
0x00
0x00
0x00
0x00
0x00
0x01
0xFD
0x00
0x01
0x00
0x00
0x00
0x00
0x00
0x30
0xF3
0x02
0x00
0x00
0x00
0x00
0x00
0x00
0x01
0xFD
0x00
0x01
0x00
0x00
0x00
0x00
0x00
0x30
Data Sheet
Address
(Hex)
0x012C
Register Name
Channel
Output 10
control
0x012D
0x012E
0x012F
0x0130
0x0131
0x0132
0x0133
0x0134
0x0136
Channel
Output 11
control
Channel
Output 12
control
0x0141
0x0142
0x0143
0x0144
0x0145
0x0146
0x0147
0x0148
0x014A
0x014B
0x014C
0x014D
0x014E
0x014F
0x0150
0x0151
0x0152
Bit 7 (MSB)
High
performance
mode
Bit 6
SYNC enable
Bit 5
Slip enable
Bit 4
Reserved
Channel
Output 13
control
Bit 3
Bit 2
Start-Up Mode[1:0]
Bit 1
Multislip
enable
Bit 0 (LSB)
Channel
enable
12-Bit Channel Divider[7:0] (LSB)
12-Bit Channel Divider[11:8] (MSB)
Fine Analog Delay[4:0]
Coarse Digital Delay[4:0]
12-Bit Multislip Digital Delay[7:0] (LSB)
Reserved
12-Bit Multislip Digital Delay[11:8] (MSB)
Reserved
Output Mux Selection[1:0]
Idle at Zero[1:0]
Dynamic
Driver Mode[1:0]
Reserved
Driver Impedance[1:0]
driver
enable
High
SYNC enable
Slip enable Reserved
Start-Up Mode[1:0]
Multislip Channel
performance
enable
enable
mode
12-Bit Channel Divider[7:0] (LSB)
Reserved
12-Bit Channel Divider[11:8] (MSB)
Reserved
Fine Analog Delay[4:0]
Reserved
Coarse Digital Delay[4:0]
12-Bit Multislip Digital Delay[7:0] (LSB)
Reserved
12-Bit Multislip Digital Delay[11:8] (MSB)
Reserved
Output Mux Selection[1:0]
Idle at Zero[1:0]
Dynamic
Driver Mode[1:0]
Reserved
Driver Impedance[1:0]
driver
enable
High
SYNC enable
Slip enable Reserved
Start-Up Mode[1:0]
Multislip Channel
performance
enable
enable
mode
12-Bit Channel Divider[7:0] (LSB)
Reserved
12-Bit Channel Divider[11:8] (MSB)
Reserved
Fine Analog Delay[4:0]
Reserved
Coarse Digital Delay[4:0]
12-Bit Multi-Slip Digital Delay[7:0] (LSB)
Reserved
12-Bit Multislip Digital Delay[11:8] (MSB)
Reserved
Output Mux Selection[1:0]
Idle at Zero[1:0]
Dynamic
Driver Mode[1:0]
Reserved
Driver Impedance[1:0]
driver
enable
High
SYNC enable
Slip enable Reserved
Start-Up Mode [1:0]
Multislip Channel
performance
enable
enable
mode
12-Bit Channel Divider[7:0] (LSB)
Reserved
12-Bit Channel Divider[11:8] (MSB)
Reserved
Fine Analog Delay[4:0]
Reserved
Coarse Digital Delay[4:0]
12-Bit Multislip Digital Delay[7:0] (LSB)
Reserved
12-Bit Multislip Digital Delay[11:8] (MSB)
Reserved
Output Mux Selection[1:0]
Idle at Zero[1:0]
Dynamic
Driver Mode[1:0]
Reserved
Driver Impedance[1:0]
driver
enable
Reserved
Reserved
Reserved
0x0137
0x0138
0x0139
0x013A
0x013B
0x013C
0x013D
0x013E
0x0140
HMC7043
Rev. A | Page 31 of 42
Default
Value
(Hex)
0xF3
0x02
0x00
0x00
0x00
0x00
0x00
0x00
0x01
0xFD
0x00
0x01
0x00
0x00
0x00
0x00
0x00
0x30
0xF3
0x10
0x00
0x00
0x00
0x00
0x00
0x00
0x01
0xFD
0x00
0x01
0x00
0x00
0x00
0x00
0x00
0x30
HMC7043
Data Sheet
CONTROL REGISTER MAP BIT DESCRIPTIONS
Global Control (Register 0x0000 to Register 0x0009)
Table 21. Global Soft Reset Control
Address
0x0000
Bits
[7:1]
0
Bit Name
Reserved
Soft reset
Settings
Description
Reserved
Resets all registers, dividers, and FSMs to default values
Access
RW
Table 22. Global Request and Mode Control
Address
0x0001
Bits
7
Bit Name
Reseed request
6
High performance
distribution path
Settings
0
1
0x0002
5
4
3
2
1
0
[7:2]
1
Reserved
Reserved
Mute output drivers
Pulse generator request
Restart dividers/FSMs
Sleep mode
Reserved
Multislip request
0
Reserved
Description
Requests the centralized resync timer and FSM to reseed any of the output
dividers that are programmed to pay attention to sync events. This signal is
rising edge sensitive, and is only acknowledged if the resync FSM has
completed all events (has finished any previous pulse generator and/or
sync events, and is in the done state (SYSREF FSM State[3:0] = 0010).
High performance distribution path select. The clock distribution path
has two modes.
Power priority.
Noise priority. Provides the option for better noise floors on the divided
output signals.
Reserved.
Reserved.
Mutes the output drivers (dividers still run in the background).
Asks for a pulse stream (see the Typical Programming Sequence section).
Resets all dividers and FSMs. Does not affect configuration registers.
Forces shutdown. Output network, and I/O buffers are disabled.
Reserved.
Requests a slip or multislip event from all divider channels that are
sensitive to slip or multislip commands. The dividers are rising edge
sensitive and take some time to process the request, after which the
phase synchronization alarm is asserted.
Reserved.
Access
RW
RW
Table 23. Global Enable Control
Address
0x0003
0x0004
Bits
[7:6]
5
[4:3]
2
1
0
7
[6:0]
Bit Name
Reserved
RF reseeder enable
Reserved
SYSREF timer enable
Reserved
Reserved
Reserved
Seven Pairs of 14-Channel Outputs Enable[6:0]
Settings
[0]
[1]
[2]
[3]
[4]
[5]
[6]
Description
Reserved
Enable RF reseed for SYSREF
Reserved
Enable internal SYSREF time reference
Reserved
Reserved
Reserved
Enable Channel 0 and 1
Enable Channel 2 and 3
Enable Channel 4 and 5
Enable Channel 6 and 7
Enable Channel 8 and 9
Enable Channel 10 and 11
Enable Channel 12 and 13
Access
RW
RW
Table 24. Global Mode and Enable Control
Address
0x0005
Bits
[7:0]
Bit Name
Reserved
Settings
Description
Reserved
Rev. A | Page 32 of 42
Access
RW
Data Sheet
HMC7043
Table 25. Global Clear Alarms
Address
0x0006
Bits
[7:1]
0
Bit Name
Reserved
Clear alarms
Settings
Description
Reserved
Clear latched alarms
Access
RW
Description
Reserved.
Reserved. The user can write/read to this register to confirm input/outputs
to the HMC7043. This register does not affect device operation.
Reserved.
Access
RW
RW
Table 26. Global Miscellaneous Control
Address
0x0007
0x0008
Bits
[7:0]
[7:0]
Bit Name
Reserved
Reserved (scratchpad)
0x0009
[7:0]
Reserved
Settings
RW
Input Buffer (Register 0x000A to Register 0x000B)
Table 27. CLKIN/CLKIN and RFSYNCIN/RFSYNCIN Input Buffer Control
Address
0x000A, 0x000B
Bits
[7:5]
[4:1]
Bit Name
Reserved
Input Buffer Mode[3:0]
Settings
[0]
[1]
[2]
[3]
0
Buffer enable
Description
Reserved
Input buffer control
Enable internal 100 Ω termination
Enable ac coupling input mode
Enable LVPECL input mode
High-Z input enable
Enable input buffer
Access
RW
GPIO/SDATA Control (Register 0x0046 to Register 0x0054)
Table 28. GPI Control
Address
0x0046
Bits
[7:4]
[3:1]
Bit Name
Reserved
GPI Selection[2:0]
Settings
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
1
GPI enable
Description
Reserved
Select the GPI functionality, Bits[2:0]
Select the GPI functionality, Bits[2:0]
Reserved
Put the chip into sleep mode
Issue a mute
Issue a pulse generator request
Issue a reseed request
Issue a restart request
Reserved
Issue a slip request
Reserved
Reserved
Reserved
Reserved
Reserved.
Reserved
Reserved.
GPI function enable. Before changing the function of the pin, disable it first,
and then reenable it after the function change. 1
Note that it is possible to have a GPIO delete pin configured as both an output and an input.
Rev. A | Page 33 of 42
Access
RW
HMC7043
Data Sheet
Table 29. GPO Control
Address
0x0050
Bits
7
[6:2]
Bit Name
Reserved
GPO Selection[4:0]
Settings
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
1
GPO mode
0
1
0
GPO enable
Description
Reserved
Select the GPO functionality, Bits[4:0]
Alarm signal
SDATA from SPI communication
SYSREF sync status has not synchronized since reset
Clock outputs phase status
Sync request status signal
Channel outputs FSM busy
SYSREF FSM State 0
SYSREF FSM State 1
SYSREF FSM State 2
SYSREF FSM State 3
Force Logic 1 to GPO
Force Logic 0 to GPO
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Pulse generator request status signal
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Selects the mode of GPO driver
Open-drain mode
CMOS mode
GPO driver enable
Access
RW
Table 30. SDATA Control
Address
0x0054
Bits
[7:2]
1
Bit Name
Reserved
SDATA mode
Settings
0
1
0
SDATA enable
Description
Reserved
Selects the mode of SDATA driver
Open-drain mode
CMOS mode
SDATA driver enable
Rev. A | Page 34 of 42
Access
RW
Data Sheet
HMC7043
SYSREF/SYNC (Register 0x005A to Register 0x005D)
Table 31. Pulse Generator Control
Address
0x005A
Bits
[7:3]
[2:0]
Bit Name
Reserved
Pulse Generator
Mode
Selection[2:0]
Settings
Description
Reserved.
SYSREF output enable with pulse generator.
Level sensitive. When the GPI is configured to issue a pulse generator
request (GPI Selection[2:0] = 100), or a pulse generator request is issued
through the SPI or as a SYNC pin-based pulse generator, run the pulse
generator. Otherwise, stop the pulse generator.
1 pulse.
2 pulses.
4 pulses.
8 pulses.
16 pulses.
16 pulses.
Continuous mode (50% duty cycle).
Access
RW
Settings
Description
Reserved
Access
RW
0
1
Bypass the retime (non-deterministic SYNC event condition)
Retime the external SYNC (deterministic SYNC event condition)
Reserved
SYNC polarity (must be 0 if not using CLKIN/CLKIN as the input)
Positive
Negative
000
001
010
011
100
101
110
111
Table 32. SYNC Control
Address
0x005B
Bits
[7:3]
2
1
0
Bit Name
Reserved
SYNC retime
Reserved
SYNC polarity
0
1
Table 33. SYSREF Timer Control
Address
0x005C
Bits
[7:0]
Bit Name
SYSREF Timer[7:0]
(LSB)
0x005D
[7:4]
[3:0]
Reserved
SYSREF Timer[11:8]
(MSB)
Settings
Description
12-bit SYSREF timer setpoint LSB. This sets the internal beat frequency of
the master timer, which controls synchronization and pulse generator
events. Set the 12-bit timer to a submultiple of the lowest output SYSREF
frequency, and program it to be no faster than 4 MHz.
Reserved.
12-bit SYSREF timer setpoint MSB.
Access
RW
RW
Clock Distribution Network (Register 0x0064 to Register 0x0065)
Table 34. Clock Input Control
Address
0x0064
Bits
[7:2]
1
0
Bit Name
Reserved
Divide by 2 on clock input
Low frequency clock input
Settings
Description
Reserved
Use divide by 2 on clock input path
Changes bias to Class A for low frequency clock input
Access
RW
Table 35. Analog Delay Common Control
Address
0x0065
Bits
[7:1]
0
Bit Name
Reserved
Analog delay low
power mode
Settings
Description
Reserved.
Analog delay is low power mode. Can save power for low settings of analog
delay, but is not glitchless between setpoints.
Rev. A | Page 35 of 42
Access
RW
HMC7043
Data Sheet
Alarm Masks Register (Register 0x0071)
Table 36. Alarm Mask Control Register
Address
0x0071
Bits
[7:5]
4
3
2
1
0
Bit Name
Reserved
Sync request mask
Reserved
Clock outputs phase status
mask
SYSREF sync status mask
Reserved
Settings
Description
Reserved
If set, allow sync request signals to generate an alarm signal
Reserved
If set, allow clock output phases status signal to generate an alarm
signal
If set, allow SYSREF sync status signal to generate an alarm signal
Reserved
Access
RW
Product ID Registers (Register 0x0078 to 0x007A)
Table 37. Product ID Registers
Address
0x0078
0x0079
0x007A
Bits
[7:0]
[7:0]
[7:0]
Bit Name
Product ID Value[7:0] (LSB)
Product ID Value[15:8] (Mid)
Product ID Value[23:16] (MSB)
Settings
Description
24-bit product ID value low
24-bit product ID value mid
24-bit product ID value high
Access
R
R
R
Alarm Readback Status Registers (Register 0x007B to 0x007F)
Table 38. Alarm Readback Status Registers
Address
0x007B
0x007D
Bits
[7:1]
0
[7:5]
4
3
2
1
Bit Name
Reserved
Alarm signal
Reserved
Sync request status
Reserved
Clock outputs phases
status
Settings
0
1
SYSREF sync status
0
1
0x007F
0
[7:0]
Reserved
Reserved
1
Description
Reserved.
Readback alarm status from SPI.
Reserved.
Unsynchronized.
Reserved.
SYSREF alarm.
SYSREF of the HMC7043 is not valid; that is, the phase output is not stable.
SYSREF of the HMC7043 is valid; that is, the phase output is stable.
SYSREF SYNC status alarm.
The HMC7043 has been synchronized with an external sync pulse or a
sync request from the SPI.
The HMC7043 never synchronized with an external sync pulse or a sync
request from the SPI.
Reserved.
Reserved.
Rev. A | Page 36 of 42
Access
R
R
R
Data Sheet
HMC7043
SYSREF Status Register (Register 0x0091)
Table 39. SYSREF Status
Address
0x0091
Bits
[7:5]
4
[3:0]
Bit Name
Reserved
Channel outputs
FSM busy
SYSREF FSM
State[3:0]
Settings
0000
0010
0100
0101
0110
1010
1011
1100
1101
1110
1111
Description
Reserved.
One of clock outputs FSM requested clock, and it is running.
Access
R
Indicates the current step of the SYSREF reseed process. Note that the three
different progressions are caused by different trigger events (reseed, pulse
generator, reserved).
Reset.
Done.
Get ready.
Get ready.
Get ready.
Running (pulse generator).
Start.
Power up.
Power up.
Power up.
Clear reset.
Bias Settings (Register 0x0096 to Register 0x00B8)
For optimum performance of the chip, Register 0x0098 to Register 0x00B8 must be programmed to a different value than their default value.
Table 40. Reserved Registers
Address
0x0098
0x0099
0x009D
0x009E
0x009F
0x00A0
0x00A2
0x00A3
0x00A4
0x00AD
0x00B5
0x00B6
0x00B7
0x00B8
Bits
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Bit Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Settings
Description
Reserved
Reserved
Reserved
Reserved
Clock output driver low power setting (set to 0x4D instead of default value)
Clock output driver high power setting (set to 0xDF instead of default value)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Rev. A | Page 37 of 42
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
HMC7043
Data Sheet
Clock Distribution (Register 0x00C8 to Register 0x0152)
The bit descriptions in Table 41 apply to all 14 channels.
Table 41. Channel 0 to Channel 13 Control
Address
0x00C8, 0x00D2, 0x00DC,
0x00E6, 0x00F0, 0x00FA,
0x0104, 0x010E, 0x0118,
0x0122, 0x012C, 0x0136,
0x0140, 0x014A
Bits
7
Bit Name
High performance
mode
6
SYNC enable
5
Slip enable
4
[3:2]
Reserved
Start-Up
Mode[1:0]
Settings 1
00
01
10
11
1
Multislip enable
0
1
0x00C9, 0x00D3, 0x00DD,
0x00E7, 0x00F1, 0x00FB,
0x0105, 0x010F, 0x0119,
0x0123, 0x012D, 0x0137,
0x0141, 0x014B
0x00CA, 0x00D4, 0x00DE,
0x00E8, 0x00F2, 0x00FC,
0x0106, 0x0110, 0x011A,
0x0124, 0x012E, 0x0138,
0x0142, 0x014C
0x00CB, 0x00D5, 0x00DF,
0x00E9, 0x00F3, 0x00FD,
0x0107, 0x0111, 0x011B,
0x0125, 0x012F, 0x0139,
0x0143, 0x014D
0x00CC, 0x00D6, 0x00E0,
0x00EA, 0x00F4, 0x00FE,
0x0108, 0x0112, 0x011C,
0x0126, 0x0130, 0x013A,
0x0144, 0x014E
0x00CD, 0x00D7, 0x00E1,
0x00EB, 0x00F5, 0x00FF,
0x0109, 0x0113, 0x011D,
0x0127, 0x0131, 0x013B,
0x0145, 0x014F
Description
High performance mode. Adjusts the divider and buffer
bias to improve swing/phase noise at the expense of
power.
Susceptible to SYNC event. The channel can process a
SYNC event to reset the phase.
Susceptible to slip event. The channel can process a slip
request from SPI or GPI. Note that if slip enable is true,
but multislip is off, a channel slips by 1 clock input cycle
on an explicit slip request broadcast from the SPI/GPI.
Reserved.
Configures the channel to normal mode with
asynchronous startup, or to a pulse generator mode with
dynamic start-up. Note that this must be set to
asynchronous mode if the channel is unused.
Asynchronous.
Reserved.
Reserved.
Dynamic.
Allow multislip operation (default = 0 for SYSREF, 1 for
DCLK).
Do not engage automatic multislip on channel startup.
Multislip events after SYNC or pulse generator request, if
the slip enable bit = 1.
Channel enable. If this bit is 0, channel is disabled.
12-bit channel divider setpoint LSB. The divider supports
even divide ratios from 2 to 4094. The supported odd
divide ratios are 1, 3, and 5. All even and odd divide ratios
have 50.0% duty cycle.
Access
RW
0
[7:0]
Channel enable
12-Bit Channel
Divider[7:0] (LSB)
[7:4]
[3:0]
Reserved
12-Bit Channel
Divider[11:8]
(MSB)
Reserved.
12-bit channel divider setpoint MSB.
RW
[7:5]
[4:0]
Reserved
Fine Analog
Delay[4:0]
Reserved.
24 fine delay steps. Step size = 25 ps. Values bigger than
23 has no effect on analog delay.
RW
[7:5]
[4:0]
Reserved
Coarse Digital
Delay[4:0]
RW
[7:0]
12-Bit Multislip
Digital Delay[7:0]
(LSB)
Reserved.
17 coarse delay steps. Step size = ½ input clock cycle. This
flip flop (FF)-based digital delay does not increase noise
level at the expense of power. Values bigger than 17 have
no effect on coarse delay.
12-bit multislip digital delay amount LSB. Step size =
(delay amount: MSB + LSB) × input clock cycles. If
multislip enable bit = 1, any slip events (caused by GPI,
SPI, SYNC, or pulse generator events) repeat the number
of times set by 12-Bit Multislip Digital Delay[11:0] to
adjust the phase by step size.
Rev. A | Page 38 of 42
RW
RW
Data Sheet
HMC7043
Address
0x00CE, 0x00D8, 0x00E2,
0x00EC, 0x00F6, 0x0100,
0x010A, 0x0114, 0x011E,
0x0128, 0x0132, 0x013C,
0x0146, 0x0150
0x00CF, 0x00D9, 0x00E3,
0x00ED, 0x00F7, 0x0101,
0x010B, 0x0115, 0x011F,
0x0129, 0x0133, 0x013D,
0x0147, 0x0151
Bits
[7:4]
[3:0]
Bit Name
Reserved
12-Bit Multislip
Digital Delay[11:8]
(MSB)
[7:2]
[1:0]
Reserved
Output Mux
Selection[1:0]
0x00D0, 0x00DA, 0x00E4,
0x00EE, 0x00F8, 0x0102,
0x010C, 0x0116, 0x0120,
0x012A, 0x0134, 0x013E,
0x0148, 0x0152
[7:6]
Settings 1
00
01
10
11
Idle at Zero[1:0]
00
01
10
11
5
[4:3]
Dynamic driver
enable
0
1
Driver Mode[1:0]
00
01
10
11
2
[1:0]
1
Reserved
Driver
Impedance[1:0]
00
01
10
11
Description
Reserved.
12-bit multislip digital delay amount MSB.
Access
RW
Reserved.
Channel output mux selection.
Channel divider output.
Analog delay output.
Other channel of the clock group pair.
Input clock (fundamental). Fundamental can also be
generated with 12-bit channel divider ratio = 1.
Idle at Logic 0 selection (pulse generator mode only).
Force to Logic 0 or VCM.
Normal mode (selection for DCLK).
Reserved.
Force to Logic 0.
Force outputs to float, goes naturally to VCM.
Dynamic driver enable (pulse generator mode only).
Driver is enabled/disabled with channel enable bit.
Driver is dynamically disabled with pulse generator events.
Output driver mode selection.
CML mode.
LVPECL mode.
LVDS mode.
CMOS mode.
Reserved.
Output driver impedance selection for CML mode.
Internal resistor disable.
Internal 100 Ω resistor enable per output pin.
Reserved.
Internal 50 Ω resistor enable per output pin.
RW
X means don’t care.
Rev. A | Page 39 of 42
RW
HMC7043
Data Sheet
APPLICATIONS INFORMATION
EVALUATION PCB AND SCHEMATIC
RAMP UP
3°C/SECOND MAX
217°C
150°C TO 200°C
RAMP DOWN
6°C/SECOND MAX
480 SECONDS MAX
TIME (Second)
20 TO 40
SECONDS
Figure 31. Pb-Free Reflow Solder Profile
Figure 32. Evaluation PCB Layout, Top Side
Rev. A | Page 40 of 42
13114-031
60 TO 180
SECONDS
13114-029
The typical Pb-free reflow solder profile shown in Figure 31 is
based on JEDEC J-STD-20C.
260 – 5/0°C
TEMPERATURE (°C)
For the circuit board in this application, use RF circuit design
techniques. Ensure that signal lines have 50 Ω impedance.
Connect the package ground leads and exposed paddle directly
to the ground plane similar to that shown in Figure 32 and
Figure 33. Use a sufficient number of via holes to connect the
top and bottom ground planes. The evaluation circuit board is
available from Analog Devices, Inc., upon request.
60 TO 150
SECONDS
HMC7043
13114-030
Data Sheet
Figure 33. Evaluation PCB Layout, Bottom Side
Rev. A | Page 41 of 42
HMC7043
Data Sheet
OUTLINE DIMENSIONS
PIN 1
INDICATOR
7.10
7.00 SQ
6.90
0.31
0.25
0.19
37
PIN 1
INDICATOR
48
1
36
0.50
BSC
5.66
5.60 SQ
5.54
EXPOSED
PAD
25
0.45
0.40
0.35
TOP VIEW
0.90
0.85
0.80
13
24
BOTTOM VIEW
5.50 REF
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
PKG-000000
11-20-2015-B
SEATING
PLANE
12
Figure 34. 48-Lead Lead Frame Chip Scale Package [LFCSP]
7 mm × 7 mm Body and 0.85 mm Package Height
(HCP-48-1)
Dimensions shown in millimeters
NOTE 1
NOTE 6
1.85
1.75
1.65
16.30
16.00
15.70
2.10
2.00
1.90
4.10
4.00
3.90
12.10
12.00
11.90
A
0.35
0.30
0.25
Ø 1.5 ~ 1.6
7.60
7.50
7.40
7.35
7.25
7.15
NOTE 6
NOTE 4
TOP VIEW
7.35
7.25
7.15
A
Ø 1.5 MIN
DETAIL A
DIRECTION OF FEED
NOTE 4
1.20
1.10
1.00 NOTE 5
SECTION A-A
0.25
NOTES:
1. 10 SPROCKET HOLE PITCH CUMUL ATIVE TOLERANCE ± 0.20
2. CAMBER IN COMPLIANCE WITH EIA 481
3. MATERIAL: CONDUCTIVE BLACK PO LYSTYRENE
4. MEASURED ON A PLANE 0.30 mm ABOVE THE BOTTOM OF
THE POCKET
5. MEASURED FROM A PLANE ON THE INSIDE BOTTOM OF
THE POCKET TO THE TOP SURFACE OF THE CARRIER
6. POCKET POSITION RELATIVE TO SPROCKET HOLE MEASURED
AS TRUE POSITION OF POCKET, NOT POCKET HOLE
R 0.25
12-10-2015-A
DETAIL A
Figure 35. LFCSP Tape and Reel Outline Dimensions
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
HMC7043LP7FE
Temperature Range
−40oC to +85°C
Lead Finish
NiPdAu
MSL Rating 2
MSL-3
HMC7043LP7FETR
−40oC to +85°C
NiPdAu
MSL-3
EK1HMC7043LP7F
−40°C to +85°C
Package Description
48-Lead Lead Frame Chip
Scale Package [LFCSP]
48-Lead Lead Frame Chip
Scale Package [LFCSP]
Evaluation Kit
E = RoHS Compliant Part.
The maximum peak reflow temperature is 260°C for the HMC7043LP7FE.
3
Four-digit lot number represented by XXXX.
1
2
©2015–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13114-0-5/16(A)
Rev. A | Page 42 of 42
Package Option
HCP-48-1
HCP-48-1
Branding 3
7043
XXXX
7043
XXXX