### AN-1235: AC Signal Processing Using the AD5450/AD5451/AD5452/AD5453 Current Output DACs (Rev. B) PDF

```AN-1235
APPLICATION NOTE
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Current Output DACs
CIRCUIT FUNCTION AND BENEFITS
two-quadrant multiplying operation or a unipolar output voltage
10-/12-/14-bit current output DACs, respectively. These devices
operate from a VDD power supply of 2.5 V to 5.5 V, making them
suited to battery-powered applications and many other applications
that include signal attenuation, channel equalization, and waveform
generation. The AD8038 is a high speed, voltage feedback amplifier
with an exceptionally low quiescent current and operates with a
VDD1 supply of +5 V and a VSS of −5 V, providing a high slew rate of
425 V/µs and is used as the current-to-voltage converter in this
circuit. With the configuration used in Figure 1, the output voltage
is given by
This circuit provides two-quadrant signal multiplication using a
It provides a multiplying bandwidth of up to 12 MHz, allowing
the user to accurately condition ac signals with bandwidths up to
this frequency. The circuit is well suited for ac signal conditioning
applications in the communications, industrial, and medical
market segments.
CIRCUIT DESCRIPTION
Table 1. Devices Connected/Referenced
Product
VOUT = −VIN × (D/2N)
Description
8-/10-/12-/14-bit multiplying DAC
where:
VIN is applied to the reference input of the DAC and is an ac input
signal in this configuration.
D is the digital word loaded to the DAC, and D = 0 to 255 (8-bit
AD5450), D = 0 to 1023 (10-bit AD5451), D = 0 to 4095 (12-bit
AD5452), and D = 0 to 16,383 (14-bit AD5453).
N is the DAC resolution.
Low power, high performance amplifier
Figure 1 shows a typical application circuit configuration for a
current output multiplying DAC in an ac signal processing
AD5452, or AD5453 DAC can easily be configured to provide a
VDD = +5V
VDD
VIN
VREF
CC = 1.8pF
VDD1 = +5V
RFB
IOUT1
VOUT = 0V TO –VREF
GND
VDD
VSS = –5V
SYNC SCLK SDIN
10µF
0.1µF
AGND
µCONTROLLER
VSS
10µF
0.1µF
10µF
0.1µF
08619-001
VDD1
Figure 1. AC Signal Processing Configuration Using a Multiplying Current Output DAC (Simplified Schematic: Decoupling and All Connections Not Shown)
Rev. B | Page 1 of 2
AN-1235
Application Note
The compensation capacitor, CC, used in the circuit controls the
dynamic performance of the circuit effectively determining the
circuit settling and output overshoot characteristics. Figure 2
shows the measured ac multiplying bandwidth of the circuit shown
in Figure 1. This is essentially the frequency response of the
DAC when an ac reference is applied to its reference input pin.
Figure 2 shows that multiplying bandwidths of up to 12 MHz
have been achieved.
Kester, Walt. The Data Conversion Handbook. Chapter 3, 7.
Analog Devices. 2005.
MT-015 Tutorial, Basic DAC Architectures II: Binary DACs.
Analog Devices.
MT-031 Tutorial, Grounding Data Converters and Solving the
Mystery of AGND and DGND. Analog Devices.
MT-033 Tutorial, Voltage Feedback Op Amp Gain and
Bandwidth. Analog Devices.
3
TA = 25°C
VDD = 5V
MT-035 Tutorial, Op Amp Inputs, Outputs, Single-Supply, and
Rail-to-Rail Issues. Analog Devices.
0
MT-101 Tutorial, Decoupling Techniques. Analog Devices.
–3
ADIsimPower Design Tool. Analog Devices.
Voltage Reference Wizard Design Tool, Analog Devices.
–6
–9
10k
VREF
VREF
VREF
VREF
VREF
Data Sheets
= ±2V, AD8038 C COMP = 1pF
= ±2V, AD8038 C COMP = 1.5pF
= ±0.15V, AD8038 C COMP = 1pF
= ±0.15V, AD8038 C COMP = 1.5pF
= ±0.15V, AD8038 C COMP = 1.8pF
100k
1M
10M
FREQUENCY (Hz)
100M
08619-002
GAIN (dB)
Figure 2. AC Multiplying Bandwidth Performance
In any circuit where ac performance is important, careful
consideration is given to the layout to ensure that the rated
performance is achieved. Design the printed circuit board (PCB)
so that the analog and digital sections are separated and confined
to certain areas of the board. If the DAC is in a system where
multiple devices require an AGND-to-DGND connection, make
the connection at one point only. Establish the star ground
point as close as possible to the device.
These DACs must have ample supply bypassing of 10 µF in parallel
with 0.1 µF on the supply located as close to the package as
possible, ideally right up against the device. The 0.1 µF capacitor
must have low effective series resistance (ESR) and low effective
series inductance (ESL), like the common ceramic types that
provide a low impedance path to ground at high frequencies,
to handle transient currents due to internal logic switching. In
addition, apply low ESR, 1 µF to 10 µF tantalum capacitors at
the supplies to minimize transient disturbance and filter out
low frequency ripple
REVISION HISTORY
5/13—Rev. A to Rev. B
Document Title Changed from CN-0054 to AN-1235 ....... Universal
1/10—Rev. 0 to Rev. A
Updated Format .................................................................. Universal
Changes to Circuit Description .......................................................2
Changes to Figure 2 ...........................................................................2
10/09—Revision 0: Initial Version
To optimize high frequency performance, locate the I-V amplifier
as close to the DAC as possible. The inclusion of a compensation
capacitor, CC, influences the overshoot and settling time
characteristics of the circuit, as shown in Figure 2. Figure 61