AN-1094 APPLICATION NOTE One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com Multiplying DACs—Fixed Reference, Waveform Generation Applications by Liam Riordan INTRODUCTION BASIC THEORY Used with an amplifier with sufficient ac performance, a multiplying digital-to-analog converter’s (DAC) R-2R architecture makes it ideal for low noise, low glitch, fast settling applications. This application note details the basic theory behind current output multiplying DACs, and why these DACs are suitable for waveform generation from a fixed dc input reference. Multiplying DACs offer an ideal building block for waveform generation applications. The buffered current output DAC architecture is based on a noninverting gain amplifier structure. A multiplying DAC uses an R-2R architecture to replicate the functionality of the variable RDAC resistor shown in Figure 1. The input impedance to the DAC seen at the VREF pin is fixed, while the output impedance is code dependent to give the equivalent variable RDAC value. See also, www.analog.com/MultiplyingDAC. The terms AD55xx and AD54xx used in this application note reference the multiplying DACs listed on www.analog.com/MultiplyingDAC. FUNCTIONAL BLOCK DIAGRAM DC REFERENCE MULTIPLYING DAC RFB VREF 0V A1 0V INVERTED OUTPUT Figure 1. Unipolar Inverting Configuration Rev. 0 | Page 1 of 8 09339-001 RDAC AN-1094 Application Note TABLE OF CONTENTS Introduction ...................................................................................... 1 Stability Issues ................................................................................4 Basic Theory ...................................................................................... 1 Key DAC Specifications for Waveform Generation .....................5 Functional Block Diagram .............................................................. 1 Settling Time ..................................................................................5 Multiplying DACs ............................................................................. 3 Midscale Glitch ..............................................................................5 Bipolar Operation ......................................................................... 3 Digital SFDR ..................................................................................6 Positive Voltage Input/Positive Voltage Output ....................... 3 Choosing the Correct Op Amp .......................................................7 Rev. 0 | Page 2 of 8 Application Note AN-1094 MULTIPLYING DACS BIPOLAR OPERATION In a multiplying DAC, current is steered to either the virtual ground connected to the IOUT1 node or the ground node (in some parts this is the IOUT2 node), which allows for a very low glitch output voltage (see Figure 2). In some applications, it may be necessary to generate a bipolar output voltage from a fixed input reference voltage. This can be easily achieved by adding a second amplifier and some external resistors as shown in Figure 3. One of the key advantages in using an IOUT DAC in this configuration is that the integrated RFB resistor is matched to the RDAC equivalent resistor allowing for very low gain temperature coefficient errors. The second amplifier basically provides a gain of 2, where biasing the external amplifier with an offset from the reference results in bipolar operation. When an output amplifier is connected in unipolar mode, as shown in Figure 2, the output voltage is given by D × V REF 2n where: D is the fractional representation of the digital word loaded to the DAC. D = 0 to 255 (8-bit AD5450) = 0 to 1023 (10-bit AD5451) = 0 to 4095 (12-bit AD5452) = 0 to 16,383 (14-bit AD5453) = 0 to 65536 (16-bit AD5543) n = the number of bits. D VOUT = VREF × n − 1 − VREF 2 POSITIVE VOLTAGE INPUT/POSITIVE VOLTAGE OUTPUT To generate a positive voltage output, an external inverting op amp circuit can be used to provide an additional inversion of either the input or the output. Because some multiplying DACs include uncommitted matched resistors (with tracking temperature coefficients), a positive output can be obtained simply by connecting an additional op amp (A2 in Figure 4), which could be the companion op amp within a dual device. The output signal of a multiplying DAC is proportional to the product of the reference input and the digital input number. +VE VREF VDD 0V C1 RFB VREF AD55xx SYNC SCLK GENERATED WAVEFORM IOUT1 A1 0V GND SDIN AGND 09339-002 MICROCONTROLLER Figure 2. Multiplying DAC, VOUT = 0 V to −VREF R3 10kΩ R2 +VE VREF VREF 0V AD55xx R1 SYNC SCLK GENERATED WAVEFORM C1 RFB VDD R5 10kΩ R4 5kΩ IOUT1 A1 A2 GND SDIN MICROCONTROLLER 0V AGND NOTES 1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. ADJUST R1 FOR VOUT = 0V WITH CODE HALF SCALE LOADED TO DAC. 2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTORS R3 AND R4. Figure 3. Multiplying DAC, VOUT = −VREF to +VREF Rev. 0 | Page 3 of 8 09339-003 VOUT = − The transfer function of this circuit shows that both negative and positive output voltages are created as the input data (D) is incremented from zero scale (VOUT = −VREF) to midscale (VOUT = 0 V ) to full scale (VOUT = +VREF). AN-1094 Application Note A2 C2 VREF RCOM ROFS RFB GENERATED REFERENCE C1 +VE VREF R1 0V IOUT1 VDD AD55xx SYNC SCLK SDN A1 0V GND AGND 09339-004 MICROCONTROLLER *UNCOMITTED RESISTOR VERSIONS ONLY. Figure 4. Multiplying DAC, VOUT = 0 V to VREF STABILITY ISSUES An important component to take into account in achieving the desired waveform conditioning signal is the compensation capacitor. The internal output capacitance of the DAC introduces a pole into the open-loop response that can cause ringing or instability in the closed-loop ramp profiling circuit. To compensate for this, an external feedback capacitor, C1, is usually connected in parallel with the internal RFB of the DAC (see Figure 2). If the value of C1 is too small, it can produce ringing at the output, and if the value of C1 is too large, it can adversely affect the settling time of the system. Because the internal output capacitance of the DAC varies with code, it is difficult to fix a precise value for C1. The value is best approximated according to the following equation: C1 = 2 CO 1 × 2π × R FB GBW where: GBW is the small signal unity gain bandwidth product of the op amp in use. CO is the output capacitance of the DAC. Rev. 0 | Page 4 of 8 Application Note AN-1094 KEY DAC SPECIFICATIONS FOR WAVEFORM GENERATION MIDSCALE GLITCH Provided the DAC is driven from true wideband low impedance sources (reference voltage and grounding pins), it settles quickly. Consequently, the slew rate and settling time of a multiplying DAC is predominantly determined by the op amp. Among the specifications that determine the ac performance of the op amp are its input capacitance, which must be kept to a minimum and the 3 dB small signal bandwidth. Note that the bandwidth of an op amp is limited due to the large load it has to drive in the feedback resistor of the DAC. A feedback resistor of, for example, 10 kΩ is a significant load to drive and is the dominating pole in determining the bandwidth of the circuit configuration. AD5444 AND AD8065 –1.66 TA = 25°C VREF = 3.5V AD8038 AMP CCOMP = 1.8pF VDD = 5V 0x7FF TO 0x800 NRG = 2.154nVs –1.68 VDD = 3V 0x7FF TO 0x800 NRG = 1.794nVs –1.70 –1.72 –1.74 VDD = 3V 0x800 TO 0x7FF –1.76 –1.78 –1.80 50 VDD = 5V 0x800 TO 0x7FF NRG = 0.694nVs 75 100 125 150 175 TIME (ns) Figure 6. Midscale Glitch CH1 200mV M 400ns A CH1 412mV 09339-005 1 Figure 5. 100 ns Settling Time Rev. 0 | Page 5 of 8 200 225 250 09339-006 SETTLING TIME For an R-2R structure, the major glitch, caused by a code change, occurs at the 1 LSB change around midscale. In a 12-bit system, such as the AD5444, the midscale change is the 7FFH to 800H code change or the 800H to 7FFH code change. If significant, these glitches can have an unwanted affect in any motor/valve/ actuator control application. When the multiplying DAC tries to change from 7FFH to 800H, the MSB switch in the DAC switches at a slower speed then the other switches. Therefore, for a few nanoseconds, the DAC sees 000H before the MSB switch is set to 1. The orange trace in Figure 6 is an example of this, where the output heads towards 0 V before the MSB switches and brings the DAC output back to 800H. OUTPUT VOLTAGE (V) Some of the key selected ac specifications that must be taken into account when generating a waveform from a fixed reference input voltage include settling time, midscale glitch, and digital SFDR. AN-1094 Application Note DIGITAL SFDR For Figure 7, a 12-bit AD5444 is used to generate a 20 kHz sine wave with an update rate of 1 MHz. This gives 50 sample points per period. The AD5444 has a maximum update rate of 2.7 MSPS. To generate a waveform with more sample points a faster update rate is required. A parallel interfaced AD5445 has an update rate of 20 MSPS. 0 TA = 25°C VDD = 5V VREF = 3.5V AD8038 AMPLIFIER –20 where: N = number of sample points. Clock = update rate of DAC. fOUT = output frequency of a generated waveform. –40 SFDR (dB) An ideal sine wave has an infinite number of points per cycle. However, a digitally created sine wave is limited by the fixed update rate and resolution of a DAC. The number of points per cycle is given by Clock N= f OUT –60 –80 –100 –120 0 100 200 300 400 FREQUENCY (kHz) Figure 7. Wideband SFDR, fOUT = 20 kHz, Clock = 1 MHz Rev. 0 | Page 6 of 8 500 09339-007 Spurious-free dynamic range (SFDR) is the usable dynamic range of a DAC before spurious noise interferes or distorts the fundamental signal. SFDR is the measure of difference in amplitude between the fundamental and the largest harmonically or nonharmonically related spur from dc to full Nyquist bandwidth (half the DAC sampling rate). Narrow-band SFDR is a measure of SFDR over an arbitrary window size. Application Note AN-1094 CHOOSING THE CORRECT OP AMP Multiplying DAC circuit performance is strongly dependent on the ability of the selected op amp to maintain the voltage null at the ladder output and perform the current-to-voltage conversion. For best dc accuracy, it is important to select an operational amplifier with low offset voltage and bias current to keep errors commensurate with the resolution of the DAC. Detailed op amp specifications are included in device data sheets. For applications where a digital waveform is to be generated from a fixed dc reference, a high slew rate, high bandwidth, low noise op amp is required. This is to ensure that the output voltage settles accurately and quickly enough before the next DAC code change. The gain bandwidth of an op amp circuit is limited by the impedance level of the feedback network and the gain configuration. To determine what GBW is required, a useful guideline is to select an op amp with a –3 dB bandwidth that is 10 times the frequency of the reference signal. If the slew rate of the op amp is not given careful consideration, it can limit the multiplying DAC. As a rule for the AD54xx and AD55xx parts, an op amp with a slew rate of 100 V/µs is generally sufficient. Table 1 is a selection of operational amplifiers that can be used for multiplying applications. Table 1. Selection of Suitable Analog Devices High Speed Op Amps Part No. AD8065 AD8066 AD8021 AD8038 Supply Voltage (V) 5 to 24 5 to 24 5 to 24 3 to 12 BW @ ACL (MHz) 145 145 490 350 Slew Rate (V/µs) 180 180 120 425 VOS (Maximum) (µV) 1500 1500 1000 3000 IB (Maximum) (nA) 0.006 0.006 10,500 750 ADA4899 AD8057 AD8058 AD8061 AD8062 AD9631 5 to 12 3 to 12 3 to 12 2.7 to 8 2.7 to 8 ±3 to ±6 600 325 325 320 320 320 310 850 850 650 650 1300 35 5000 5000 6000 6000 10,000 100 500 500 350 350 7000 Rev. 0 | Page 7 of 8 Packages SOIC-8, SOT-23-5 SOIC-8, MSOP-8 SOIC-8, MSOP-8 SOIC-8, SC70-5, SOT-23-5 LFCSP-8, SOIC-8 SOT-23-5, SOIC-8 SOIC-8, MSOP-8 SOT-23-5, SOIC-8 SOIC-8, MSOP-8 SOIC-8, PDIP-8 AN-1094 Application Note NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. AN09339-0-9/10(0) Rev. 0 | Page 8 of 8

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