AD5623R-EP Data Sheet

Dual 12-Bit nanoDAC with
±10 ppm/°C On-Chip Reference
AD5623R-EP
Enhanced Product
The AD5623R-EP has an on-chip 2.5 V reference giving a
maximum full-scale output of 5 V. The on-chip reference is off
at power-up, allowing the use of an external reference.
FEATURES
Low power, smallest pin-compatible, dual nanoDAC: 12 bits
User-selectable external or internal reference
External reference default
On-chip 2.5 V, ±10 ppm/°C reference
10-lead MSOP
4.5 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to zero scale
Per channel power-down
Serial interface up to 50 MHz
Hardware LDAC and CLR functions
The AD5623R-EP incorporates a power-on reset circuit that
ensures that the output of the DACs powers up to 0 V and
remains there until a valid write takes place. The AD5623R-EP
contains a power-down feature that reduces the current
consumption of the device to 0.48 μA at 5 V and provides
software-selectable output loads while in power-down mode.
The low power consumption of this device in normal operation
makes it ideally suited to portable, battery-operated equipment.
The AD5623R-EP uses a versatile, 3-wire serial interface that
operates at clock rates of up to 50 MHz, and is compatible with
standard SPI, QSPI™, MICROWIRE™, and DSP interface
standards. The on-chip precision output amplifier enables railto-rail output swing to be achieved. Additional application and
technical information can be found in the AD5623R data sheet.
ENHANCED PRODUCT FEATURES
Supports defense and aerospace applications (AQEC)
Extended temperature range: −55°C to +105°C
Controlled manufacturing baseline
One assembly/test site
One fabrication site
Enhanced product change notification
Qualification data available on request
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
APPLICATIONS
Process control
Data acquisition systems
Dual 12-Bit DAC.
On-Chip 2.5 V, ±10 ppm/°C Reference.
Available in 10-Lead MSOP.
Low Power. Typically consumes 1.25 mW at 5 V. 4.5 μs
maximum settling time.
GENERAL DESCRIPTION
Table 1. Related Device
The AD5623R-EP, a member of the nanoDAC® family, is a low
power, dual 12-bit buffered voltage output digital-to-analog
converter (DAC) that operates from a single 4.5 V to 5.5 V
supply and is guaranteed monotonic by design.
Part No.
AD5623R
Description
2.7 V to 5.5 V, dual 12-bit nanoDAC, with external
reference
FUNCTIONAL BLOCK DIAGRAM
VDD
VREFIN /VREFOUT
2.5V
REFERENCE
LDAC
SCLK
DAC
REGISTER
STRING
DAC A
BUFFER
VOUTA
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
BUFFER
VOUTB
INTERFACE
LOGIC
DIN
AD5623R-EP
LDAC CLR
POWER-ON
RESET
GND
POWER-DOWN
LOGIC
12105-001
SYNC
INPUT
REGISTER
Figure 1.
Rev. A
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Tel: 781.329.4700 ©2014–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD5623R-EP
Enhanced Product
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ............................................................6
Enhanced Product Features ............................................................ 1
ESD Caution...................................................................................6
Applications ....................................................................................... 1
Pin Configuration and Function Descriptions..............................7
General Description ......................................................................... 1
Typical Performance Characteristics ..............................................8
Product Highlights ........................................................................... 1
Applications Information .............................................................. 13
Functional Block Diagram .............................................................. 1
Using a Reference as a Power Supply ....................................... 13
Revision History ............................................................................... 2
Outline Dimensions ....................................................................... 14
Specifications..................................................................................... 3
Ordering Guide .......................................................................... 14
AC Characteristics ........................................................................ 4
Timing Characteristics ................................................................ 4
REVISION HISTORY
9/15—Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
Added Enhanced Product Features Section.................................. 1
Change to Table 5 ............................................................................. 6
Changes to Using a Reference as a Power Supply Section and
Figure 33 .......................................................................................... 13
Deleted Terminology Section ....................................................... 13
Deleted Theory of Operation Section, Digital-to-Analog
Architecture Section, Figure 33; Renumbered Sequentially,
Resistor String Section, Output Amplifier Section, Figure 34,
Internal Reference Section, External Reference Section, and
Serial Interface Section .................................................................. 15
Deleted Input Shift Register Section, Table 7; Renumbered
Sequentially, Table 8, SYNC Interrupt Section, Power-On Reset
Section, Software Reset Section, Table 9, Figure 35, and
Figure 36 .......................................................................................... 16
Deleted Power-Down Modes Section, Table 10 to Table 13, and
Figure 37 .......................................................................................... 17
Deleted LDAC Function Section, Synchronous LDAC Section,
Asynchronous LDAC Section, Table 14 to Table 16, and Internal
Reference Setup Section................................................................. 18
Deleted Microprocessor Interfacing Section, AD5623R-EP to
Blackfin® ADSP-BF53x Interface Section, Figure 38, AD5623R-EP
to M68HC11/MC68L11 Interface Section, Figure 39, AD5623R-EP
to 80C51 Interface Section, Figure 40, AD5623R-EP to
MICOWIRE Interface Section, and Figure 41............................ 19
Deleted Power Supply Bypassing and Grounding Section ....... 20
4/14—Revision 0: Initial Version
Rev. A | Page 2 of 16
Enhanced Product
AD5623R-EP
SPECIFICATIONS
VDD = 4.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN/VREFOUT = VDD; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1
STATIC PERFORMANCE2
Resolution
Relative Accuracy, INL
Differential Nonlinearity, DNL
Zero-Scale Error
Offset Error
Full-Scale Error
Gain Error
Zero-Scale Error Drift
Gain Temperature Coefficient
DC Power Supply Rejection Ratio
DC Crosstalk
External Reference
Min
DC Output Impedance
Short-Circuit Current
Power-Up Time
REFERENCE INPUTS
Reference Current
Reference Input Range
Reference Input Impedance
REFERENCE OUTPUT
Output Voltage
Reference Temperature Coefficient3
Output Impedance
LOGIC INPUTS3
Input Current
Input Low Voltage (VINL)
Input High Voltage (VINH)
Pin Capacitance
POWER REQUIREMENTS
VDD
IDD (Normal Mode)4
Internal Reference Off
Internal Reference On
IDD (All Power-Down Modes)5
Max
±1
±1.5
±1
+12
±12
±1
±1.5
12
Unit
Test Conditions/Comments
±2
±2.5
−100
Bits
LSB
LSB
mV
mV
% of FSR
% of FSR
µV/°C
ppm
dB
Of FSR/°C
DAC code = midscale; VDD = 5 V ± 10%
10
10
5
25
20
10
µV
µV/mA
µV
µV
µV/mA
µV
Due to full-scale output change; RL = 2 kΩ to GND or VDD
Due to load current change
Due to powering down (per channel)
Due to full-scale output change; RL = 2 kΩ to GND or VDD
Due to load current change
Due to powering down (per channel)
+2
±1
−0.1
Internal Reference
OUTPUT CHARACTERISTICS3
Output Voltage Range
Capacitive Load Stability
Typ
0
VDD
2
10
0.5
30
4
170
0.75
VDD = 5 V
Coming out of power-down mode; VDD = 5 V
VREFIN/VREFOUT = VDD = 5.5 V
2.505
V
ppm/°C
kΩ
At ambient
±2
0.8
µA
V
V
pF
pF
All digital inputs
VDD = 5 V
VDD = 5 V
DIN, SCLK, and SYNC
LDAC and CLR
5.5
V
0.45
1
1
mA
mA
µA
2
3
19
0.25
0.8
0.48
RL = ∞
RL = 2 kΩ
µA
V
kΩ
±10
7.5
4.5
All 1s loaded to DAC register
200
VDD
26
2.495
V
nF
nF
Ω
mA
μs
Guaranteed monotonic by design
All 0s loaded to DAC register
Temperature range = −55°C to +105°C, typical at +25°C.
Linearity calculated using a reduced code range: Code 32 to Code 4064. Output unloaded.
3
Guaranteed by design and characterization, but not production tested.
4
Interface inactive. All DACs active. DAC outputs unloaded.
5
Both DACs powered down.
1
2
Rev. A | Page 3 of 16
VINH = VDD and VINL = GND
VDD = 4.5 V to 5.5 V
VDD = 4.5 V to 5.5 V
VDD = 4.5 V to 5.5 V, VINH = VDD and VINL = GND
AD5623R-EP
Enhanced Product
AC CHARACTERISTICS
VDD = 4.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN/VREFOUT = VDD; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter1, 2
SLEW RATE
FEEDTHROUGH
Digital Feedthrough
Reference Feedthrough
CROSSTALK
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
MULTIPLYING BANDWIDTH
TOTAL HARMONIC DISTORTION
OUTPUT CHARACTERISTICS
Digital-to-Analog Glitch Impulse
Output Voltage Settling Time
Output Noise Spectral Density
Output Noise
1
2
Min
Typ
1.8
Max
Unit
V/µs
Test Conditions/Comments
0.1
−90
nV-sec
dB
VREFIN/VREFOUT = 2 V ± 0.1 V p-p, frequency 10 Hz to 20 MHz
0.1
1
4
1
4
340
−80
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
kHz
dB
External reference
Internal reference
External reference
Internal reference
VREFIN/VREFOUT = 2 V ± 0.1 V p-p
VREFIN/VREFOUT = 2 V ± 0.1 V p-p, frequency = 10 kHz
nV-sec
µs
nV/√Hz
nV/√Hz
μV p-p
1 LSB change around major carry
¼ to ¾ scale settling to ±0.5 LSB
DAC code = midscale, 1 kHz
DAC code = midscale, 10 kHz
0.1 Hz to 10 Hz
10
3
120
100
15
4.5
Guaranteed by design and characterization, but not production tested.
Temperature range = −55°C to +105°C, typical at +25°C.
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VINL + VINH)/2.
VDD = 4.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter1
t12
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
1
2
Limit at TMIN, TMAX
20
9
9
13
5
5
0
15
13
0
10
15
5
0
300
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to SCLK fall ignore
SCLK falling edge to SYNC fall ignore
LDAC pulse width low
SCLK falling edge to LDAC rising edge
CLR pulse width low
SCLK falling edge to LDAC falling edge
CLR pulse activation time
Guaranteed by design and characterization, but not production tested.
Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V.
Rev. A | Page 4 of 16
Enhanced Product
AD5623R-EP
Timing Diagram
t10
t1
t9
SCLK
t8
t3
t4
t2
t7
SYNC
t6
t5
DIN
DB23
DB0
t14
t11
LDAC1
t12
LDAC2
VOUT
t13
t15
12105-002
CLR
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
Figure 2. Serial Write Operation
Rev. A | Page 5 of 16
AD5623R-EP
Enhanced Product
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Parameter
VDD to GND
VOUTx to GND
VREFIN/VREFOUT to GND
Digital Input Voltage to GND
Operating Temperature Range
Industrial
Storage Temperature Range
Junction Temperature (TJ max)
Power Dissipation
MSOP Package (4-Layer Board)
θJA Thermal Impedance
θJC Thermal Impedance
Reflow Soldering Peak Temperature
Pb-Free
Rating
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
−55°C to +105°C
−65°C to +150°C
150°C
(TJ max − TA)/θJA
142°C/W
43.7°C/W
260 (+0/−5)°C
Rev. A | Page 6 of 16
Enhanced Product
AD5623R-EP
VOUTA 1
10
VREFIN/VREFOUT
VOUTB 2
9
VDD
8
DIN
LDAC 4
7
SCLK
CLR 5
6
SYNC
GND 3
AD5623R-EP
TOP VIEW
(Not to Scale)
12105-003
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
1
2
3
4
Mnemonic
VOUTA
VOUTB
GND
LDAC
5
CLR
6
SYNC
7
SCLK
8
DIN
9
VDD
10
VREFIN/VREFOUT
Description
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Ground. Reference point for all circuitry on the device.
Load DAC. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data.
This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently low.
Asynchronous Clear Input. The CLR input is falling edge sensitive. While CLR is low, all LDAC pulses are
ignored. When CLR is activated, zero scale is loaded to all input and DAC registers. This clears the output to 0 V.
The device exits clear code mode on the 24th falling edge of the next write to the device. If CLR is activated during
a write sequence, the write is aborted.
Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data.
When SYNC goes low, it enables the input shift register, and data is transferred in on the falling edges of the
following clocks. The DAC is updated following the 24th clock cycle unless SYNC is taken high before this edge,
in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.
Data can be transferred at rates of up to 50 MHz.
Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the falling edge
of the serial clock input.
Power Supply Input. This device can be operated from 4.5 V to 5.5 V. Decouple the supply with a 10 μF capacitor in
parallel with a 0.1 μF capacitor to GND.
Common Reference Input/Reference Output. When the internal reference is selected, this is the reference output
pin. When using an external reference, this is the reference input pin. The default for this pin is a reference input.
Rev. A | Page 7 of 16
AD5623R-EP
Enhanced Product
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
0.20
VDD = 5V
VREFIN/VREFOUT = 2.5V
0.15 TA = 25°C
VDD = VREFIN/VREFOUT = 5V
0.8 TA = 25°C
0.6
0.10
DNL ERROR (LSB)
0.2
0
–0.2
–0.4
0.05
0
–0.05
–0.10
–0.6
–0.15
–1.0
0
0.5k
1.0k
1.5k
2.0k
2.5k
CODE
3.0k
3.5k
4.0k
12105-007
–0.8
–0.20
0
0.5k
Figure 4. INL, External Reference
0.20
1.5k
2.0k
2.5k
CODE
3.0k
3.5k
4.0k
Figure 7. DNL, at 5 V VDD
8
VDD = VREFIN/VREFOUT = 5V
TA = 25°C
0.15
1.0k
12105-016
INL ERROR (LSB)
0.4
6
MAX INL
0.10
4
0.05
2
ERROR (LSB)
DNL ERROR (LSB)
VDD = VREFIN/VREFOUT = 5V
0
–0.05
MAX DNL
0
MIN DNL
–2
–0.10
–4
–0.15
–6
0
0.5k
1.0k
1.5k
2.0k
2.5k
CODE
3.0k
3.5k
4.0k
–8
–40
12105-010
–0.20
0
20
40
60
TEMPERATURE (°C)
80
100
120
Figure 8. INL Error and DNL Error vs. Temperature
Figure 5. DNL, External Reference
10
1.0
VDD = 5V
VREFIN/VREFOUT = 2.5V
TA = 25°C
0.8
MAX INL
8
6
0.4
4
ERROR (LSB)
0.6
0.2
0
–0.2
VDD = 5V
TA = 25°C
2
MAX DNL
0
MIN DNL
–2
–0.4
–4
–0.6
–6
–0.8
–8
–1.0
0
0.5k
1.0k
1.5k
2.0k
2.5k
CODE
3.0k
3.5k
4.0k
Figure 6. INL, at 5 V VDD
–10
0.75
1.25
1.75
2.25
2.75
3.25
VREF (V)
3.75
4.25
Figure 9. INL Error and DNL Error vs. VREF
Rev. A | Page 8 of 16
4.75
12105-081
MIN INL
12105-013
INL ERROR (LSB)
–20
12105-080
MIN INL
Enhanced Product
AD5623R-EP
8
1.5
6
1.0
MAX INL
ZERO-SCALE ERROR
TA = 25°C
0.5
2
ERROR (mV)
MAX DNL
0
MIN DNL
–2
–4
0
–0.5
–1.0
–1.5
OFFSET ERROR
MIN INL
–6
3.2
3.7
4.2
VDD (V)
4.7
–2.5
–40
12105-082
–8
2.7
–2.0
5.2
Figure 10. INL Error and DNL Error vs. VDD
–20
0
20
40
60
TEMPERATURE (°C)
80
100
12105-024
ERROR (LSB)
4
Figure 13. Zero-Scale Error and Offset Error vs. Temperature
1.0
0
TA = 25°C
VDD = 5V
–0.02
0.5
ZERO-SCALE ERROR
–0.04
GAIN ERROR
0
ERROR (mV)
ERROR (% FSR)
–0.06
–0.08
–0.10
–0.12
–0.14
–0.5
–1.0
–1.5
FULL-SCALE ERROR
–0.16
–2.0
–20
0
20
40
60
TEMPERATURE (°C)
80
100
–2.5
2.7
12105-023
–0.20
–40
Figure 11. Gain Error and Full-Scale Error vs. Temperature
3.2
3.7
4.2
VDD (V)
4.7
5.2
12105-026
OFFSET ERROR
–0.18
Figure 14. Zero-Scale Error and Offset Error vs. VDD
1.0
VDD = 5.5V
TA = 25°C
8
0.5
NUMBER OF UNITS
FULL-SCALE ERROR
–0.5
–1.0
6
4
2
–2.0
2.7
3.2
3.7
4.2
VDD (V)
4.7
5.2
Figure 12. Gain Error and Full-Scale Error vs. VDD
0
0.230
0.235
0.240
0.245
IDD (mA)
0.250
Figure 15. IDD Histogram with External Reference
Rev. A | Page 9 of 16
0.255
12105-090
–1.5
12105-025
ERROR (% FSR)
GAIN ERROR
0
AD5623R-EP
Enhanced Product
0.30
5
TA = 25°C
VDD = 5.5V
TA = 25°C
0.25
VDD = VREFIN/VREFOUT = 5V
0.20
3
IDD (mA)
0.15
2
0.10
1
0.78
0.80
0.82
IDD (mA)
0
–40
12105-091
0
0.05
0.84
–20
0
20
40
60
TEMPERATURE (°C)
80
12105-044
NUMBER OF UNITS
4
100
Figure 19. Supply Current vs. Temperature
Figure 16. IDD Histogram with Internal Reference
0.5
0.4
DAC LOADED WITH
FULL-SCALE
SOURCING CURRENT
DAC LOADED WITH
ZERO-SCALE
SINKING CURRENT
ERROR VOLTAGE (V)
0.3
0.2
VDD = VREFIN/VREFOUT = 5V
TA = 25°C
FULL-SCALE CODE CHANGE
0x0000 TO 0xFFFF
OUTPUT LOADED WITH 2kΩ
AND 200pF TO GND
0.1
0
–0.1
VDD = 5V
VREFIN/VREFOUT = 2.5V
–0.2
VOUT = 909mV/DIV
–0.3
1
–6
–4
–2
0
2
CURRENT (mA)
4
6
8
10
TIME BASE = 4µs/DIV
Figure 20. Full-Scale Settling Time, 5 V
Figure 17. Headroom at Rails vs. Source and Sink Current
6
VDD = 5V
VREFIN/VREFOUT = 2.5V
5 TA = 25C
FULL SCALE
3
MIDSCALE
VDD
2
1
1/4 SCALE
1
MAX(CH2)*
420.0mV
0
2
ZERO SCALE
–20
–10
0
10
CURRENT (mA)
20
VOUT
30
12105-030
VOUT (V)
VDD = VREFIN/VREFOUT = 5V
TA = 25°C
3/4 SCALE
4
–1
–30
12105-060
–8
CH1 2.0V
CH2 500mV
M100µs 125MS/s
A CH1
1.28V
Figure 21. Power-On Reset to 0 V
Figure 18. 5 V VDD Source and Sink Capability
Rev. A | Page 10 of 16
8.0ns/pt
12105-061
–0.5
–10
12105-029
–0.4
Enhanced Product
AD5623R-EP
1
SCLK
VOUT (V)
3
VOUT
VDD = 5V
CH1 5.0V
CH3 5.0V
CH2 500mV
M400ns
A CH1
1.4V
12105-062
2
2.496
2.494
2.492
2.490
2.488
2.486
2.484
2.482
2.480
2.478
2.476
2.474
2.472
2.470
2.468
2.466
2.464
2.462
2.460
2.458
2.456
VDD = VREFIN/VREFOUT = 5V
TA = 25°C
5ns/SAMPLE NUMBER
GLITCH IMPULSE = 9.494nV
1LSB CHANGE AROUND
MIDSCALE (0x8000 TO 0x7FFF)
50
100
150
200 250 300 350
SAMPLE NUMBER
400
450
512
VDD = VREFIN/VREFOUT = 5V
TA = 25°C
DAC LOADED WITH MIDSCALE
0
50
100
150
200 250 300 350
SAMPLE NUMBER
400
450
512
Y AXIS = 2µV/DIV
X AXIS = 4s/DIV
Figure 26. 0.1 Hz to 10 Hz Output Noise Plot, External Reference
Figure 23. Digital-to-Analog Glitch Impulse (Negative)
2.498
VDD = VREFIN/VREFOUT = 5V
TA = 25°C
5ns/SAMPLE NUMBER
ANALOG CROSSTALK = 0.424nV
2.497
12105-063
1
12105-058
VOUT (V)
0
Figure 25. Analog Crosstalk, Internal Reference
Figure 22. Exiting Power-Down to Midscale
2.538
2.537
2.536
2.535
2.534
2.533
2.532
2.531
2.530
2.529
2.528
2.527
2.526
2.525
2.524
2.523
2.522
2.521
VDD = 5V
VREFIN/VREFOUT = 2.5V
TA = 25°C
5ns/SAMPLE NUMBER
ANALOG CROSSTALK = 4.462nV
12105-057
SYNC
VDD = 5V
VREFIN/VREFOUT = 2.5V
TA = 25°C
DAC LOADED WITH MIDSCALE
10µV/DIV
2.495
2.494
1
2.493
2.491
0
50
100
150
200 250 300 350
SAMPLE NUMBER
400
450
512
Figure 24. Analog Crosstalk, External Reference
5s/DIV
Figure 27. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference
Rev. A | Page 11 of 16
12105-064
2.492
12105-059
VOUT (V)
2.496
AD5623R-EP
Enhanced Product
800
5
TA = 25°C
MIDSCALE LOADED
–5
600
–10
500
(dB)
400
300
–20
–25
VDD = 5V
VREFIN/VREFOUT = 2.5V
200
–15
–30
100
0
100
1k
10k
FREQUENCY (Hz)
1M
10M
12105-066
–35
–40
10k
100k
1M
FREQUENCY (Hz)
Figure 28. Noise Spectral Density, Internal Reference
10M
Figure 31. Multiplying Bandwidth
VDD = 5V
TA = 25°C
DAC LOADED WITH FULL SCALE
VREFIN/VREFOUT = 2V ± 0.3V p-p
–30
–40
VOUT A
–50
–60
–70
–80
VOUT B
2k
4k
6k
FREQUENCY (Hz)
8k
10k
Figure 29. Total Harmonic Distortion
VREFIN/VREFOUT = VDD
TA = 25°C
14
12
10
VDD = 5V
4
1
2
3
7
4
5
6
CAPACITANCE (nF)
8
9
10
12105-068
6
0
CH3 5.0V
CH2 1.0V
CH4 1.0V
M200ns A CH3
Figure 32. CLR Pulse Activation Time
16
8
2
Figure 30. Settling Time vs. Capacitive Load
Rev. A | Page 12 of 16
1.10V
12105-050
4
–90
–100
TIME (µs)
CLR
3
12105-067
TOTAL HARMONIC DISTORTION (dB)
–20
12105-069
OUTPUT NOISE (nV/√Hz)
700
VDD = 5V
TA = 25°C
0
Enhanced Product
AD5623R-EP
APPLICATIONS INFORMATION
Because the supply current required by the AD5623R-EP is
extremely low, an alternative option is to use a voltage reference
to supply the required voltage to the device (see Figure 33). This
is especially useful if the power supply is quite noisy or if the
system supply voltages are at some value other than 5 V or 3 V,
for example, 15 V. The voltage reference outputs a steady supply
voltage for the AD5623R-EP. If the ADR293-EP is used, it must
supply ~500 μA of current to the AD5623R-EP, with no load on
the output of the DAC. When the DAC output is loaded, the
ADR293-EP also needs to supply the current to the load. The
total current required (with a 5 kΩ load on the DAC output) is
The load regulation of the ADR293-EP is typically 30 ppm/mA,
which results in a 45 ppm (225 μV) error for the 1.5 mA current
drawn from it. This corresponds to a 0.184 LSB error.
12V
ADR293-EP
3-WIRE
SERIAL
INTERFACE
500 μA + (5 V/5 kΩ) = 1.5 mA
Rev. A | Page 13 of 16
SYNC
SCLK
5V
VDD
VOUT = 0V TO 5V
AD5623R-EP
DIN
12105-041
USING A REFERENCE AS A POWER SUPPLY
Figure 33. ADR293-EP as Power Supply to the AD5623R-EP
AD5623R-EP
Enhanced Product
OUTLINE DIMENSIONS
3.10
3.00
2.90
10
3.10
3.00
2.90
5.15
4.90
4.65
6
1
5
PIN 1
IDENTIFIER
0.50 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.30
0.15
0.70
0.55
0.40
0.23
0.13
6°
0°
COMPLIANT TO JEDEC STANDARDS MO-187-BA
091709-A
0.15
0.05
COPLANARITY
0.10
Figure 34. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD5623RSRMZ-EP-5R7
1
Temperature Range
−55°C to +105°C
Accuracy
±1.5 LSB INL
Internal
Reference
2.5 V
Z = RoHS Compliant Part.
Rev. A | Page 14 of 16
Package Description
10-Lead MSOP
Package
Option
RM-10
Branding
DN9
Enhanced Product
AD5623R-EP
NOTES
Rev. A | Page 15 of 16
AD5623R-EP
Enhanced Product
NOTES
©2014–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12105-0-9/15(A)
Rev. A | Page 16 of 16
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