FEATURES FUNCTIONAL BLOCK DIAGRAM VDD Low drift 2.5 V reference: 2 ppm/°C typical Tiny package: 3 mm × 3 mm, 16-lead LFCSP Total unadjusted error (TUE): ±0.1% of full-scale range (FSR) maximum Offset error: ±1.5 mV maximum Gain error: ±0.1% of FSR maximum High drive capability: 20 mA, 0.5 V from supply rails User selectable gain of 1 or 2 (GAIN pin) Reset to zero scale or midscale (RSTSEL pin) 1.8 V logic compatibility Low glitch: 0.5 nV-sec 400 kHz I2C-compatible serial interface Robust 3.5 kV HBM and 1.5 kV FICDM ESD rating Low power: 3.3 mW at 3 V 2.7 V to 5.5 V power supply −40°C to +105°C temperature range VREF GND AD5697R 2.5V REFERENCE VLOGIC INTERFACE LOGIC SCL SDA A1 INPUT REGISTER DAC REGISTER STRING DAC A VOUTA BUFFER INPUT REGISTER DAC REGISTER STRING DAC B VOUTB BUFFER A0 LDAC RESET POWER-ON RESET GAIN = ×1/×2 RSTSEL GAIN POWERDOWN LOGIC 11253-001 Data Sheet Dual, 12-Bit nanoDAC+ with 2 ppm/°C Reference, I2C Interface AD5697R Figure 1. APPLICATIONS Base station power amplifiers Process controls (programmable logic controller [PLC] I/O cards) Industrial automation Data acquisition systems GENERAL DESCRIPTION The AD5697R, a member of the nanoDAC+™ family, is a low power, dual, 12-bit buffered voltage output digital-to-analog converter (DAC). The device includes a 2.5 V, 2 ppm/°C internal reference (enabled by default) and a gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). The AD5697R operates from a single 2.7 V to 5.5 V supply, is guaranteed monotonic by design, and exhibits less than 0.1% FSR gain error and 1.5 mV offset error performance. The device is available in a 3 mm × 3 mm LFCSP and a TSSOP package. The AD5697R also incorporates a power-on reset circuit and a RSTSEL pin that ensure that the DAC outputs power up to zero scale or midscale and remain there until a valid write takes place. It contains a per channel power-down feature that reduces the current consumption of the device to 4 µA at 3 V while in power-down mode. The AD5697R uses a versatile 2-wire serial interface that operates at clock rates up to 400 kHz and includes a VLOGIC pin intended for 1.8 V/3 V/5 V logic. Rev. A Table 1. Dual nanoDAC+ Devices Interface SPI I2C Reference Internal External Internal External 16-Bit AD5689R AD5689 12-Bit AD5687R AD5687 AD5697R PRODUCT HIGHLIGHTS 1. 2. 3. Precision DC Performance. TUE: ±0.1% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.1% of FSR maximum Low Drift 2.5 V On-Chip Reference. 2 ppm/°C typical temperature coefficient 5 ppm/°C maximum temperature coefficient Two Package Options. 3 mm × 3 mm, 16-lead LFCSP 16-lead TSSOP Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013–2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD5697R Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Serial Operation ......................................................................... 19 Applications ....................................................................................... 1 Write Operation.......................................................................... 19 Functional Block Diagram .............................................................. 1 Read Operation........................................................................... 20 General Description ......................................................................... 1 Multiple DAC Readback Sequence .......................................... 20 Product Highlights ........................................................................... 1 Power-Down Operation ............................................................ 21 Revision History ............................................................................... 2 Load DAC (Hardware LDAC Pin) ........................................... 22 Specifications..................................................................................... 3 LDAC Mask Register ................................................................. 22 AC Characteristics........................................................................ 5 Hardware Reset (RESET) .......................................................... 23 Timing Characteristics ................................................................ 6 Reset Select Pin (RSTSEL) ........................................................ 23 Absolute Maximum Ratings............................................................ 7 Internal Reference Setup ........................................................... 23 ESD Caution .................................................................................. 7 Solder Heat Reflow..................................................................... 23 Pin Configurations and Function Descriptions ........................... 8 Thermal Hysteresis .................................................................... 24 Typical Performance Characteristics ............................................. 9 Applications Information .............................................................. 25 Terminology .................................................................................... 15 Microprocessor Interfacing ....................................................... 25 Theory of Operation ...................................................................... 17 AD5697R-to-ADSP-BF531 Interface ...................................... 25 Digital-to-Analog Converter .................................................... 17 Layout Guidelines....................................................................... 25 Transfer Function ....................................................................... 17 Galvanically Isolated Interface ................................................. 25 DAC Architecture ....................................................................... 17 Outline Dimensions ....................................................................... 26 Serial Interface ............................................................................ 18 Ordering Guide .......................................................................... 26 Write and Update Commands .................................................. 18 REVISION HISTORY 1/14—Rev. 0 to Rev. A Removed Long-Term Stability/Drift Parameter ........................... 3 Removed Figure 7; Renumbered Sequentially.............................. 9 Removed Long-Term Temperature Drift Section and Figure 49; Renumbered Sequentially.............................................................. 23 2/13—Revision 0: Initial Version Rev. A | Page 2 of 28 Data Sheet AD5697R SPECIFICATIONS VDD = 2.7 V to 5.5 V; 1.8 V ≤ VLOGIC ≤ 5.5 V; and all specifications TMIN to TMAX, unless otherwise noted. RL = 2 kΩ; and CL = 200 pF. Table 2. Parameter STATIC PERFORMANCE 1 Resolution Relative Accuracy Differential Nonlinearity Zero-Code Error Offset Error Full-Scale Error Gain Error Total Unadjusted Error Min Short-Circuit Current 4 Load Impedance at Rails 5 Power-Up Time REFERENCE OUTPUT Output Voltage 6 Reference Temperature Coefficient 7, 8 Output Impedance2 Output Voltage Noise2 Output Voltage Noise Density2 Load Regulation Sourcing2 Load Regulation Sinking2 Output Current Load Capability2 Line Regulation2 Thermal Hysteresis2 LOGIC INPUTS2 Input Current Input Low Voltage, VINL Input High Voltage, VINH Pin Capacitance ±0.12 ±1 ±1 1.5 ±1.5 ±0.1 ±0.1 ±0.1 ±0.2 Unit Test Conditions/Comments ±1 ±1 0.15 Bits LSB LSB mV mV % of FSR % of FSR % of FSR % of FSR µV/°C ppm mV/V ±2 ±3 ±2 µV µV/mA µV Due to single channel, full-scale output change Due to load current change Due to powering down (per channel) Gain = 1 Gain = 2, see Figure 25 RL = ∞ RL = 1 kΩ 80 V V nF nF kΩ µV/mA 80 µV/mA 40 25 2.5 mA Ω µs See Figure 25 Coming out of power-down mode; VDD = 5 V V ppm/°C At ambient See the Terminology section Ω µV p-p nV/√Hz µV/mA µV/mA mA µV/V ppm ppm 0.1 Hz to 10 Hz At ambient; f = 10 kHz, CL = 10 nF At ambient At ambient VDD ≥ 3 V At ambient First cycle Additional cycles 0.4 +0.1 +0.01 ±0.02 ±0.01 0 0 Capacitive Load Stability Resistive Load 3 Load Regulation Max 12 Offset Error Drift2 Gain Temperature Coefficient2 DC Power Supply Rejection Ratio2 DC Crosstalk2 OUTPUT CHARACTERISTICS 2 Output Voltage Range Typ VREF 2 × VREF 2 10 1 2.4975 2 2.5025 5 0.04 12 240 20 40 ±5 100 125 25 ±2 0.3 × VLOGIC 0.7 × VLOGIC 2 Rev. A | Page 3 of 28 µA V V pF Guaranteed monotonic by design All 0s loaded to DAC register All 1s loaded to DAC register External reference; gain = 2; TSSOP Internal reference; gain = 1; TSSOP Of FSR/°C DAC code = midscale; VDD = 5 V ± 10% 5 V ± 10%, DAC code = midscale; −30 mA ≤ IOUT ≤ +30 mA 3 V ± 10%, DAC code = midscale; −20 mA ≤ IOUT ≤ +20 mA Per pin AD5697R Parameter LOGIC OUTPUTS (SDA)2 Output Low Voltage, VOL Floating State Output Capacitance POWER REQUIREMENTS VLOGIC ILOGIC VDD IDD Normal Mode 9 All Power-Down Modes 10 Data Sheet Min Typ Max Unit Test Conditions/Comments 0.4 V pF ISINK = 3 mA 5.5 3 5.5 5.5 V µA V V 0.7 1.3 4 6 mA mA µA µA 4 1.8 2.7 VREF + 1.5 0.59 1.1 1 Gain = 1 Gain = 2 VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V Internal reference off Internal reference on, at full scale −40°C to +85°C −40°C to +105°C DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when VREF = VDD with gain = 1 or when VREF/2 = VDD with gain = 2. Linearity calculated using a reduced code range of 12 to 4080. 2 Guaranteed by design and characterization; not production tested. 3 Channel A can have an output current of up to 30 mA. Similarly, Channel B can have an output current of up to 30 mA up to a junction temperature of 100°C. 4 VDD = 5 V. The device includes current limiting that is intended to protect the device during temporary overload conditions. Junction temperature can be exceeded during current limit. Operation above the specified maximum operation junction temperature may impair device reliability. 5 When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output device. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV (see Figure 25). 6 Initial accuracy presolder reflow is ±750 µV; output voltage includes the effects of preconditioning drift. See the Internal Reference Setup section. 7 Reference is trimmed and tested at two temperatures and is characterized from −40°C to +105°C. 8 Reference temperature coefficient is calculated as per the box method. See the Terminology section for further information. 9 Interface inactive. Both DACs active. DAC outputs unloaded. 10 Both DACs powered down. 1 Rev. A | Page 4 of 28 Data Sheet AD5697R AC CHARACTERISTICS VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; 1.8 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Guaranteed by design and characterization; not production tested. Table 3. Parameter 1 Output Voltage Settling Time Slew Rate Digital-to-Analog Glitch Impulse Digital Feedthrough Digital Crosstalk Analog Crosstalk DAC-to-DAC Crosstalk Total Harmonic Distortion (THD) 3 Output Noise Spectral Density Output Noise Signal-to-Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR) Signal-to-Noise-and-Distortion Ratio (SINAD) Min Typ 5 0.8 0.5 0.13 0.1 0.2 0.3 −80 300 6 90 83 80 Max 7 Unit µs V/µs nV-sec nV-sec nV-sec nV-sec nV-sec dB nV/√Hz µV p-p dB dB dB See the Terminology section. Temperature range is −40°C to +105°C, typical at 25°C. 3 Digitally generated sine wave at 1 kHz. 1 2 Rev. A | Page 5 of 28 Test Conditions/Comments 2 ¼ to ¾ scale settling to ±2 LSB 1 LSB change around major carry At ambient, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz DAC code = midscale, 10 kHz; gain = 2 0.1 Hz to 10 Hz At ambient, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz At ambient, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz At ambient, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz AD5697R Data Sheet TIMING CHARACTERISTICS VDD = 2.5 V to 5.5 V; 1.8 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. See Figure 2. Table 4. Min 2.5 0.6 1.3 0.6 100 0 0.6 0.6 1.3 0 20 + 0.1CB 3 20 400 Parameter 1 t1 t2 t3 t4 t5 t6 2 t7 t8 t9 t10 t11 t12 t13 CB 3 Max Unit µs µs µs µs ns µs µs µs µs ns ns ns ns pF 0.9 300 300 400 Test Conditions/Comments SCL cycle time SCL high time, tHIGH SCL low time, tLOW Start/repeated start condition hold time, tHD,STA Data setup time, tSU,DAT Data hold time, tHD,DAT Setup time for repeated start, tSU,STA Stop condition setup time, tSU,STO Bus free time between a stop and a start condition, tBUF Rise time of SCL and SDA when receiving, tR Fall time of SDA and SCL when transmitting/receiving, tF LDAC pulse width SCL rising edge to LDAC rising edge Capacitive load for each bus line Guaranteed by design and characterization; not production tested. A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH minimum of the SCL signal) to bridge the undefined region of the falling edge of the SCL. 3 CB is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD. 1 2 START CONDITION REPEATED START CONDITION STOP CONDITION SDA t9 t10 t11 t4 t3 SCL t4 t2 t6 t1 t5 t7 t8 t12 t13 LDAC1 t12 LDAC2 11253-002 NOTES 1ASYNCHRONOUS 2SYNCHRONOUS LDAC UPDATE MODE. LDAC UPDATE MODE. Figure 2. 2-Wire Serial Interface Timing Diagram Rev. A | Page 6 of 28 Data Sheet AD5697R ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 5. Parameter VDD to GND VLOGIC to GND VOUT to GND VREF to GND Digital Input Voltage to GND 1 SDA and SCL to GND Operating Temperature Range Storage Temperature Range Junction Temperature 16-Lead TSSOP, θJA Thermal Impedance, 0 Airflow (4-Layer Board) 16-Lead LFCSP, θJA Thermal Impedance, 0 Airflow (4-Layer Board) Reflow Soldering Peak Temperature, Pb Free (J-STD-020) ESD 2 FICDM 1 2 Rating −0.3 V to +7 V −0.3 V to +7 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VLOGIC + 0.3 V −0.3 V to +7 V −40°C to +105°C −65°C to +150°C 125°C 112.6°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 70°C/W 260°C 3.5 kV 1.5 kV Excluding SDA and SCL. Human body model (HBM) classification. Rev. A | Page 7 of 28 AD5697R Data Sheet VOUTA 1 GND 2 VDD 3 AD5697R 10 A0 GAIN 8 LDAC 7 SDA 6 VOUTB 5 11253-003 TOP VIEW (Not to Scale) NOTES 1. THE EXPOSED PAD MUST BE TIED TO GND. 2. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. RSTSEL 15 RESET VOUTA 3 14 A1 NC 9 VLOGIC NC 4 16 2 VREF 1 12 A1 11 SCL GND 4 AD5697R 13 SCL VDD 5 TOP VIEW (Not to Scale) 12 A0 NC 6 11 VLOGIC VOUTB 7 10 GAIN SDA 8 9 LDAC NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. Figure 3. 16-Lead LFCSP Pin Configuration 11253-004 13 RESET 14 RSTSEL 16 NC 15 VREF PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 4. 16-Lead TSSOP Pin Configuration Table 6. Pin Function Descriptions LFCSP 1 16 2 3 Pin No. TSSOP 3 2 4 5 Mnemonic VOUTA NC GND VDD 4 5 6 6 7 8 NC VOUTB SDA 7 9 LDAC 8 10 GAIN 9 10 11 11 12 13 VLOGIC A0 SCL 12 13 14 15 A1 RESET 14 16 RSTSEL 15 1 VREF 17 Not applicable EPAD Description Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. No Connect. Do not connect to this pin. Ground Reference Point for All Circuitry on the Part. Power Supply Input. This part can be operated from 2.7 V to 5.5 V. Decouple the supply with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. No Connect. Do not connect to this pin. Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. Serial Data Input. This pin is used in conjunction with the SCL line to clock data into or out of the 24-bit input shift register. SDA is a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up resistor. LDAC can be operated in two modes, asynchronous and synchronous. Pulsing this pin low allows either or both DAC registers to be updated if the input registers have new data. This allows both DAC outputs to simultaneously update. This pin can also be tied permanently low. Gain Select. When this pin is tied to GND, both DAC outputs have a span from 0 V to VREF. If this pin is tied to VLOGIC, both DACs output a span of 0 V to 2 × VREF. Digital Power Supply. Voltage ranges from 1.8 V to 5.5 V. Address Input. Sets the first LSB of the 7-bit slave address. Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 24-bit input register. Address Input. Sets the second LSB of the 7-bit slave address. Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC pulses are ignored. When RESET is activated, the input register and the DAC register are updated with zero scale or midscale, depending on the state of the RSTSEL pin. Power-On Reset Select. Tying this pin to GND powers up both DACs to zero scale. Tying this pin to VLOGIC powers up both DACs to midscale. Reference Voltage. The AD5697R has a common reference pin. When using the internal reference, this is the reference output pin. When using an external reference, this is the reference input pin. The default for this pin is as a reference output. Exposed Pad. The exposed pad must be tied to GND. Rev. A | Page 8 of 28 Data Sheet AD5697R TYPICAL PERFORMANCE CHARACTERISTICS 2.5020 DEVICE 1 DEVICE 2 DEVICE 3 DEVICE 4 DEVICE 5 2.5015 2.5010 VDD = 5V VDD = 5V TA = 25°C T VREF (V) 2.5005 2.5000 1 2.4995 2.4990 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) CH1 10µV Figure 5. Internal Reference Voltage vs. Temperature M1.0s A CH1 160mV 11253-010 2.4980 –40 11253-005 2.4985 Figure 8. Internal Reference Noise, 0.1 Hz to 10 Hz 2.5000 90 VDD = 5V TA = 25°C VDD = 5V 80 2.4999 70 VREF (V) NUMBER OF UNITS 2.4998 60 50 40 30 2.4997 2.4996 2.4995 20 2.4994 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 TEMPERATURE DRIFT (ppm/°C) 2.4993 –0.005 11253-007 0 –0.001 0.001 0.003 0.005 ILOAD (A) Figure 6. Reference Output Temperature Drift Histogram 1600 –0.003 11253-011 10 Figure 9. Internal Reference Voltage vs. Load Current 2.5002 TA = 25°C VDD = 5V TA = 25°C D1 1400 2.5000 1200 VREF (V) 800 600 D3 2.4996 2.4994 400 2.4992 0 10 100 1k 10k 100k 1M FREQUENCY (MHz) 2.4990 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) Figure 10. Internal Reference Voltage vs. Supply Voltage Figure 7. Internal Reference Noise Spectral Density vs. Frequency Rev. A | Page 9 of 28 11253-012 D2 200 11253-009 NSD (nV/ Hz) 2.4998 1000 Data Sheet 10 8 8 6 6 4 4 2 0 –2 2 DNL –2 –4 –4 –6 –6 VDD = 5V TA = 25°C INTERNAL REFERENCE = 2.5V 0 625 1250 1875 2500 3125 3750 4096 CODE –10 0 0.5 0.6 6 0.4 4 ERROR (LSB) 8 0.2 0 –0.2 4.0 4.5 5.0 –8 3750 4096 INL DNL –6 CODE VDD = 5V TA = 25°C INTERNAL REFERENCE = 2.5V –10 2.7 3.2 3.7 4.2 4.7 5.2 SUPPLY VOLTAGE (V) Figure 12. Differential Nonlinearity (DNL) vs. Code Figure 15. INL Error and DNL Error vs. Supply Voltage 0.10 8 0.08 6 0.06 4 0.04 ERROR (% of FSR) 10 INL 0 DNL –2 –4 –6 FULL-SCALE ERROR 0.02 0 GAIN ERROR –0.02 –0.04 –0.06 VDD = 5V TA = 25°C INTERNAL REFERENCE = 2.5V –10 –40 10 –0.08 60 110 TEMPERATURE (°C) 11253-015 ERROR (LSB) 3.5 –2 –4 –8 3.0 0 –0.6 2 2.5 2 –0.4 11253-014 DNL (LSB) 10 0.8 3125 2.0 Figure 14. INL Error and DNL Error vs. VREF 1.0 2500 1.5 VREF (V) Figure 11. Integral Nonlinearity (INL) vs. Code VDD = 5V –0.8 TA = 25°C INTERNAL REFERENCE = 2.5V –1.0 1250 1875 0 625 1.0 11253-017 –10 VDD = 5V TA = 25°C INTERNAL REFERENCE = 2.5V –8 Figure 13. INL Error and DNL Error vs. Temperature VDD = 5V TA = 25°C INTERNAL REFERENCE = 2.5V –0.10 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 16. Gain Error and Full-Scale Error vs. Temperature Rev. A | Page 10 of 28 11253-018 –8 INL 0 11253-016 ERROR (LSB) 10 11253-013 INL (LSB) AD5697R Data Sheet AD5697R 0.10 1.2 0.8 0.6 ZERO-CODE ERROR 0.2 0 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) 0.05 0.04 0.03 0.02 0.01 0 –40 11253-019 OFFSET ERROR 0.06 0.08 0.08 TOTAL UNADJUSTED ERROR (% of FSR) 0.10 ERROR (% of FSR) 0.06 0.04 0.02 GAIN ERROR 0 FULL-SCALE ERROR –0.04 4.7 5.2 11253-020 –0.06 SUPPLY VOLTAGE (V) 60 80 100 120 0.06 0.04 0.02 0 –0.02 –0.04 –0.06 VDD = 5V –0.08 T = 25°C A INTERNAL REFERENCE = 2.5V –0.10 2.7 3.2 3.7 4.2 4.7 5.2 Figure 21. Total Unadjusted Error vs. Supply Voltage, Gain = 1 0 TOTAL UNADJUSTED ERROR (% of FSR) 1.5 1.0 0.5 ZERO-CODE ERROR 0 OFFSET ERROR –0.5 VDD = 5V TA = 25°C INTERNAL REFERENCE = 2.5V –1.5 2.7 3.2 3.7 4.2 4.7 5.2 SUPPLY VOLTAGE (V) 11253-021 ERROR (mV) 40 SUPPLY VOLTAGE (V) Figure 18. Gain Error and Full-Scale Error vs. Supply Voltage –1.0 20 Figure 20. Total Unadjusted Error vs. Temperature 0.10 VDD = 5V –0.08 T = 25°C A INTERNAL REFERENCE = 2.5V –0.10 2.7 3.2 3.7 4.2 0 TEMPERATURE (°C) Figure 17. Zero-Code Error and Offset Error vs. Temperature –0.02 –20 11253-023 0.4 0.07 –0.01 –0.02 –0.03 –0.04 –0.05 –0.06 –0.07 –0.08 VDD = 5V –0.09 T = 25°C A INTERNAL REFERENCE = 2.5V –0.10 0 10000 20000 30000 40000 50000 CODE Figure 22. Total Unadjusted Error vs. Code Figure 19. Zero-Code Error and Offset Error vs. Supply Voltage Rev. A | Page 11 of 28 60000 65535 11253-024 ERROR (mV) 1.0 VDD = 5V 0.09 TA = 25°C INTERNAL REFERENCE = 2.5V 0.08 11253-022 VDD = 5V TA = 25°C INTERNAL REFERENCE = 2.5V TOTAL UNADJUSTED ERROR (% of FSR) 1.4 AD5697R 25 Data Sheet 7 VDD = 5V TA = 25°C EXTERNAL REFERENCE = 2.5V VDD = 5V 6 TA = 25°C GAIN = 2 INTERNAL 5 REFERENCE = 2.5V 20 15 VOUT (V) HITS 4 10 FULL SCALE THREE-QUARTER SCALE 3 MIDSCALE 2 ONE-QUARTER SCALE 1 ZERO SCALE 0 5 560 580 600 620 640 –2 –0.06 11253-025 540 IDD FULL SCALE (V) –0.04 –0.02 0 0.02 0.04 0.06 LOAD CURRENT (A) 11253-028 –1 0 Figure 26. Source and Sink Capability at VDD = 5 V Figure 23. IDD Histogram with External Reference 5 VDD = 5V 30 T = 25°C A INTERNAL REFERENCE = 2.5V 25 VDD = 3V TA = 25°C 4 EXTERNAL REFERENCE = 2.5V GAIN = 1 FULL SCALE 3 VOUT (V) 15 2 THREE-QUARTER SCALE MIDSCALE 1 ONE-QUARTER SCALE 10 0 5 ZERO SCALE –1 1000 1020 1040 1060 1080 1100 1120 1140 IDD FULL SCALE (V) –2 –0.06 11253-026 0 –0.04 –0.02 0 0.02 0.04 0.06 LOAD CURRENT (A) 11253-029 HITS 20 Figure 27. Source and Sink Capability at VDD = 3 V Figure 24. IDD Histogram with Internal Reference, VREFOUT = 2.5 V, Gain = 2 1.0 1.4 0.8 1.2 0.6 0.4 CURRENT (mA) SINKING 5V 0 –0.2 SOURCING 5V –0.4 1.0 ZERO CODE 0.8 0.6 EXTERNAL REFERENCE, FULL SCALE 0.4 –0.6 SOURCING 2.7V 0.2 –1.0 0 5 10 15 20 25 LOAD CURRENT (mA) 30 0 –40 10 60 TEMPERATURE (°C) Figure 28. Supply Current vs. Temperature Figure 25. Headroom/Footroom vs. Load Current Rev. A | Page 12 of 28 110 11253-030 –0.8 11253-027 ∆VOUT (V) SINKING 2.7V 0.2 FULL SCALE Data Sheet AD5697R 4.0 3.5 2.5008 DAC A DAC B 3.0 2.5003 VOUT (V) VOUT (V) 2.5 2.0 2.4998 1.5 1.0 2.4993 160 320 TIME (µs) CHANNEL B TA = 25°C VDD = 5.25V INTERNAL REFERENCE = 2.5V POSITIVE MAJOR CODE TRANSITION ENERGY = 0.227206nV-sec 2.4988 0 4 8 6 10 12 TIME (µs) Figure 29. Settling Time Figure 32. Digital-to-Analog Glitch Impulse 0.06 0.05 2 11253-034 80 11253-031 VDD = 5V 0.5 TA = 25°C INTERNAL REFERENCE = 2.5V ¼ TO ¾ SCALE 0 10 20 40 6 CHANNEL A CHANNEL B VDD 0.003 CHANNEL B 5 3 0.02 2 0.01 1 0 0 VOUT AC-COUPLED (V) 0.03 VDD (V) 4 0.001 0 –0.001 –1 15 TIME (µs) –0.002 0 5 10 15 20 11253-035 10 5 11253-032 TA = 25°C INTERNAL REFERENCE = 2.5V –0.01 –10 –5 0 25 TIME (µs) Figure 30. Power-On Reset to 0 V Figure 33. Analog Crosstalk, Channel A 3 CHANNEL A CHANNEL B SYNC T GAIN = 2 2 VOUT (V) 1 GAIN = 1 0 –5 VDD = 5V TA = 25°C EXTERNAL REFERENCE = 2.5V VDD = 5V TA = 25°C INTERNAL REFERENCE = 2.5V 0 5 TIME (µs) 10 CH1 10µV M1.0s A CH1 802mV Figure 34. 0.1 Hz to 10 Hz Output Noise Plot, External Reference Figure 31. Exiting Power-Down to Midscale Rev. A | Page 13 of 28 11253-036 1 11253-033 VOUT (V) 0.002 0.04 AD5697R Data Sheet 4.0 T 0nF 0.1nF 10nF 0.22nF 4.7nF 3.9 3.8 VDD = 5V TA = 25°C INTERNAL REFERENCE = 2.5V VOUT (V) 3.7 1 3.6 3.5 3.4 3.3 3.2 VDD = 5V TA = 25°C INTERNAL REFERENCE = 2.5V A CH1 802mV VDD = 5V TA = 25°C 1400 INTERNAL REFERENCE = 2.5V 1.600 1.605 1.610 1.615 1.620 1.625 1.630 TIME (ms) Figure 35. 0.1 Hz to 10 Hz Output Noise Plot, 2.5 V Internal Reference 1600 1.595 11253-040 M1.0s 3.0 1.590 11253-038 CH1 10µV 3.1 Figure 38. Settling Time vs. Capacitive Load 0 FULL SCALE MIDSCALE ZERO SCALE –10 BANDWIDTH (dB) NSD (nV/ Hz) 1200 1000 800 600 –20 –30 –40 400 100 1k 10k 100k 1M FREQUENCY (Hz) –60 10k 11253-037 0 10 Figure 36. Noise Spectral Density –20 –60 –80 –100 –120 –140 –160 2000 4000 6000 8000 10000 12000 14000 16000 18000 20000 FREQUENCY (Hz) 11253-039 THD (dBV) –40 0 1M 10M Figure 39. Multiplying Bandwidth, External Reference = 2.5 V, ±0.1 V p-p, 10 kHz to 10 MHz VDD = 5V TA = 25°C INTERNAL REFERENCE = 2.5V –180 100k FREQUENCY (Hz) 20 0 VDD = 5V TA = 25°C EXTERNAL REFERENCE = 2.5V, ±0.1V p-p 11253-041 –50 200 Figure 37. Total Harmonic Distortion at 1 kHz Rev. A | Page 14 of 28 Data Sheet AD5697R TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot is shown in Figure 11. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot can be seen in Figure 12. Zero-Code Error Zero-code error is a measurement of the output error when zero code (0x0000) is loaded to the DAC register. Ideally, the output should be 0 V. The zero-code error is always positive in the AD5697R because the output of the DAC cannot go less than 0 V due to a combination of the offset errors in the DAC and the output amplifier. Zero-code error is expressed in mV. A plot of the zero-code error vs. the temperature can be seen in Figure 17. Full-Scale Error Full-scale error is a measurement of the output error when the full-scale code is loaded to the DAC register. Ideally, the output should be VDD − 1 LSB. Full-scale error is expressed in percent of full-scale range (% of FSR). A plot of the full-scale error vs. the temperature can be seen in Figure 16. Gain Error This is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal expressed as % of FSR. Output Voltage Settling Time Output voltage settling time is the time it takes for the output of a DAC to settle to a specified level for a ¼ to ¾ full-scale input change. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-sec and is measured when the digital input code is changed by 1 LSB at the major carry transition, 0x7FFF to 0x8000 (see Figure 32). Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. It is specified in nV-sec, and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa. Reference Feedthrough Reference feedthrough is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated. It is expressed in dB. Noise Spectral Density This is a measurement of the internally generated random noise. Random noise is characterized as a spectral density (nV/√Hz). It is measured by loading the DAC to midscale and measuring noise at the output. It is measured in nV/√Hz. A plot of noise spectral density is shown in Figure 36. Offset Error Drift This is a measurement of the change in offset error with a change in temperature. It is expressed in µV/°C. DC Crosstalk DC crosstalk is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC (or soft power-down and power-up) while monitoring another DAC kept at midscale. It is expressed in μV. Gain Temperature Coefficient This is a measurement of the change in gain error with changes in temperature. It is expressed in ppm of FSR/°C. DC crosstalk due to load current change is a measure of the impact that a change in load current on one DAC has to another DAC kept at midscale. It is expressed in μV/mA. Offset Error Offset error is a measure of the difference between VOUT (actual) and VOUT (ideal) expressed in mV in the linear region of the transfer function. Offset error is measured on the AD5697R with Code 512 loaded in the DAC register. It can be negative or positive. Digital Crosstalk This is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another DAC. It is measured in standalone mode and is expressed in nV-sec. DC Power Supply Rejection Ratio (PSRR) This indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for full-scale output of the DAC. It is measured in mV/V. VREF is held at 2 V, and VDD is varied by ±10%. Analog Crosstalk This is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa). Then execute a software LDAC and monitor the output of the DAC whose digital code was not changed. The area of the glitch is expressed in nV-sec. Rev. A | Page 15 of 28 AD5697R Data Sheet DAC-to-DAC Crosstalk This is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent analog output change of another DAC. It is measured by loading the attack channel with a full-scale code change (all 0s to all 1s and vice versa), using the write to and update commands while monitoring the output of the victim channel that is at midscale. The energy of the glitch is expressed in nV-sec. Multiplying Bandwidth The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input. Total Harmonic Distortion (THD) THD is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC, and the THD is a measurement of the harmonics present on the DAC output. It is measured in dB. Voltage Reference Temperature Coefficient (TC) Voltage reference TC is a measure of the change in the reference output voltage with a change in temperature. The reference TC is calculated using the box method, which defines the TC as the maximum change in the reference output over a given temperature range expressed in ppm/°C as follows; VREFmax − VREFmin 6 TC = × 10 V × TempRange REFnom where: VREFmax is the maximum reference output measured over the total temperature range. VREFmin is the minimum reference output measured over the total temperature range. VREFnom is the nominal reference output voltage, 2.5 V. TempRange is the specified temperature range of −40°C to +105°C. Rev. A | Page 16 of 28 Data Sheet AD5697R THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER The AD5697R is a dual, 12-bit, serial input, voltage output DAC with an internal reference. The part operates from supply voltages of 2.7 V to 5.5 V. Data is written to the AD5697R in a 24-bit word format via a 2-wire serial interface. The AD5697R incorporates a power-on reset circuit to ensure that the DAC output powers up to a known output state. The device also has a software power-down mode that reduces the typical current consumption to 4 µA. The resistor string structure is shown in Figure 41. It is a string of resistors, each of Value R. The code loaded to the DAC register determines the node on the string where the voltage is to be tapped off and fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic. VREF TRANSFER FUNCTION R The internal reference is on by default. To use an external reference, only a nonreference option is available. Because the input coding to the DAC is straight binary, the ideal output voltage when using an external reference is given by R R TO OUTPUT AMPLIFIER D VOUT = VREF × Gain N 2 DAC ARCHITECTURE The DAC architecture consists of a string DAC followed by an output amplifier. Figure 40 shows a block diagram of the DAC architecture. VREF 2.5V REF REF (+) DAC REGISTER RESISTOR STRING REF (–) GND VOUTX GAIN (GAIN = 1 OR 2) Figure 40. Single DAC Channel Architecture Block Diagram R Figure 41. Resistor String Structure Internal Reference The AD5697R on-chip reference is on at power-up but can be disabled via a write to a control register. See the Internal Reference Setup section for details. The AD5697R has a 2.5 V, 2 ppm/°C reference, giving a full-scale output of 2.5 V or 5 V depending on the state of the GAIN pin. The internal reference associated with the device is available at the VREF pin. This buffered reference is capable of driving external loads of up to 10 mA. Output Amplifiers 11253-042 INPUT REGISTER R 11253-043 where: Gain is the gain of the output amplifier and is set to 1 by default. This can be set to ×1 or ×2 using the gain select pin. When this pin is tied to GND, both DAC outputs have a span from 0 V to VREF. If this pin is tied to VLOGIC, both DAC output a span of 0 V to 2 × VREF. D is the decimal equivalent of the binary code that is loaded to the DAC register as 0 to 4,095 for the 12-bit device. N is the DAC resolution. The output buffer amplifier can generate rail-to-rail voltages on its output, which gives an output range of 0 V to VDD. The actual range depends on the value of VREF, the GAIN pin, the offset error, and the gain error. The GAIN pin selects the gain of the output. • • If GAIN is tied to GND, both outputs have a gain of 1, and the output range is 0 V to VREF. If GAIN is tied to VLOGIC, both outputs have a gain of 2, and the output range is 0 V to 2 × VREF. These amplifiers are capable of driving a load of 1 kΩ in parallel with 2 nF to GND. The slew rate is 0.8 V/µs with a ¼ to ¾ scale settling time of 5 µs. Rev. A | Page 17 of 28 AD5697R Data Sheet Table 8. Address Commands SERIAL INTERFACE The AD5697R has a 2-wire I2C-compatible serial interface (refer to I2C-Bus Specification, Version 2.1, January 2000, available from Philips Semiconductor). See Figure 2 for a timing diagram of a typical write sequence. The AD5697R can be connected to an I2C bus as a slave device, under the control of a master device. The AD5697R can support standard (100 kHz) and fast (400 kHz) data transfer modes. Support is not provided for 12-bit addressing and general call addressing. DAC B 0 1 1 0 0 0 0 Address (n) 0 0 0 0 DAC A 1 0 1 Description DAC A DAC B DAC A and DAC B WRITE AND UPDATE COMMANDS Write to Input Register n (Dependent on LDAC) Command 0001 allows the user to write to the dedicated input register of each DAC individually. When LDAC is low, the input register is transparent (if not controlled by the LDAC mask register). Input Shift Register The input shift register of the AD5697R is 24 bits wide. Data is loaded into the device as a 24-bit word under the control of a serial clock input, SCL. The first eight MSBs make up the command byte. The first four bits are the command bits (C3, C2, C1, and C0) that control the mode of operation of the device (see Table 7). The last four bits of the first byte are the address bits (DAC B, 0, 0, and DAC A, see Table 8). Update DAC Register n with Contents of Input Register n Command 0010 loads the DAC registers/outputs with the contents of the input registers selected and updates the DAC outputs directly. Write to and Update DAC Channel n (Independent of LDAC) The data-word comprises 12-bit input code, followed by four don’t care bits for the AD5697R. These data bits are transferred to the input register on the 24 falling edges of SCL. Command 0011 allows the user to write to the DAC registers and update the DAC outputs directly. Commands can be executed on individual DAC channels or both DAC channels, depending on the address bits selected. Table 7. Command Definitions Command C3 C2 C1 C0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 … 1 0 1 1 1 1 0 … 1 1 0 0 1 1 0 … 1 1 0 1 0 1 0 … 1 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 C3 C2 C1 COMMAND C0 0 DAC B 0 DAC ADDRESS COMMAND BYTE DAC A D11 D10 D9 D8 D7 D6 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 D5 D4 D3 D2 D1 D0 X X X X DAC DATA DAC DATA DATA HIGH BYTE DATA LOW BYTE Figure 42. Input Shift Register Content Rev. A | Page 18 of 28 11253-044 0 Description No operation Write to Input Register n (dependent on LDAC) Update DAC Register n with contents of Input Register n Write to and update DAC Channel n Power down/power up DAC Hardware LDAC mask register Software reset (power-on reset) Internal reference setup register Reserved Reserved Reserved Data Sheet AD5697R 2. SERIAL OPERATION The AD5697R has a 7-bit slave address. The five MSBs are 00011 and the two LSBs (A1 and A0) are set by the state of the A0 and A1 address pins. The ability to make hardwired changes to A0 and A1 allows the user to incorporate up to four of these devices on one bus, as outlined in Table 9. 3. Table 9. Device Address Selection A0 Pin Connection GND VLOGIC GND A1 Pin Connection GND GND VLOGIC A0 0 1 0 A1 0 0 1 VLOGIC VLOGIC 1 1 WRITE OPERATION The 2-wire serial bus protocol operates as follows: When writing to the AD5697R, the user must begin with a start command followed by an address byte (R/W = 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. The AD5697R requires two bytes of data for the DAC and a command byte that controls various DAC functions. Three bytes of data must, therefore, be written to the DAC with the command byte followed by the most significant data byte and the least significant data byte, as shown in Figure 43. All these data bytes are acknowledged by the AD5697R. A stop condition follows. The master initiates data transfer by establishing a start condition when a high-to-low transition on the SDA line occurs while SCL is high. The following byte is the address byte, which consists of the 7-bit slave address. The slave address corresponding to the transmitted address responds by pulling SDA low during the 9th clock pulse (this is termed the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to, or read from, its shift register. 1 9 1 9 SCL 0 SDA 0 0 1 1 A1 A0 DB23 R/W DB22 DB21 DB20 DB19 DB18 DB17 ACK. BY AD5697R START BY MASTER DB16 ACK. BY AD5697R FRAME 1 SLAVE ADDRESS FRAME 2 COMMAND BYTE 1 9 1 9 SCL (CONTINUED) SDA (CONTINUED) DB15 DB14 DB13 DB12 DB11 DB10 FRAME 3 MOST SIGNIFICANT DATA BYTE DB9 DB8 DB7 DB6 ACK. BY AD5697R Figure 43. I2C Write Operation Rev. A | Page 19 of 28 DB5 DB4 DB3 DB2 FRAME 4 LEAST SIGNIFICANT DATA BYTE DB1 DB0 ACK. BY STOP BY AD5697R MASTER 11253-045 1. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL. When all data bits have been read or written, a stop condition is established. In write mode, the master pulls the SDA line high during the 10th clock pulse to establish a stop condition. In read mode, the master issues a no acknowledge for the 9th clock pulse (that is, the SDA line remains high). The master then brings the SDA line low before the 10th clock pulse, and then high during the 10th clock pulse to establish a stop condition. AD5697R Data Sheet READ OPERATION MULTIPLE DAC READBACK SEQUENCE When reading data back from the AD5697R DACs, the user begins with an address byte (R/W = 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. This address byte must be followed by the control byte that determines both the read command that is to follow and the pointer address to read from, which is also acknowledged by the DAC. The user configures which channel to read back and sets the readback command to active using the control byte. Following this, there is a repeated start condition by the master and the address is resent with R/W = 1. This is acknowledged by the DAC, indicating that it is prepared to transmit data. Two bytes of data are then read from the DAC, as shown in Figure 44. A NACK condition from the master, followed by a STOP condition, completes the read sequence. Default readback is Channel A if both DACs are selected. The user begins with an address byte (R/W = 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. This address byte must be followed by the control byte, which is also acknowledged by the DAC. The user configures which channel to start the readback using the control byte. Following this, there is a repeated start condition by the master, and the address is resent with R/W = 1. This is acknowledged by the DAC, indicating that it is prepared to transmit data. The first two bytes of data are then read from DAC Input Register A that is selected using the control byte, most significant byte first, as shown in Figure 44. The next four bytes read back are don’t care bytes, and the next two bytes of data are the contents of DAC Input Register B. Data continues to be read from the DAC input registers in this auto-incremental fashion, until a NACK followed by a stop condition follows. If the contents of DAC Input Register B are read out, the next bytes of data that are read are from the contents of DAC Input Register A. 1 9 1 9 SCL 0 SDA 0 0 1 1 A1 A0 R/W DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 ACK. BY AD5697R START BY MASTER ACK. BY AD5697R FRAME 1 SLAVE ADDRESS FRAME 2 COMMAND BYTE 1 9 1 9 SCL 0 SDA 0 0 REPEATED START BY MASTER 1 1 A1 A0 R/W DB15 DB14 DB13 DB12 DB11 DB10 ACK. BY AD5697R FRAME 3 SLAVE ADDRESS 1 DB9 DB8 ACK. BY AD5697R FRAME 4 MOST SIGNIFICANT DATA BYTE n 9 1 9 SCL (CONTINUED) DB7 DB6 DB5 DB4 DB3 DB2 FRAME 3 SLAVE ADDRESS SIGNIFICANT DATA BYTE n DB1 DB0 DB15 DB14 DB13 DB12 ACK. BY MASTER Figure 44. I2C Read Operation Rev. A | Page 20 of 28 DB11 DB10 FRAME 4 MOST SIGNIFICANT DATA BYTE n – 1 DB9 DB8 NACK. BY AD5697R STOP BY MASTER 11253-046 SDA (CONTINUED) Data Sheet AD5697R POWER-DOWN OPERATION The AD5697R contains three separate power-down modes. Command 0100 is designated for the power-down function (see Table 7). These power-down modes are software programmable by setting eight bits, Bit DB7 to Bit DB0, in the shift register. There are two bits associated with each DAC channel. Table 10 shows how the state of the two bits corresponds to the mode of operation of the device. amplifier to a resistor network of known values. This has the advantage that the output impedance of the part is known while the part is in power-down mode. There are three different powerdown options. The output is connected internally to GND through either a 1 kΩ or a 100 kΩ resistor, or it is left open-circuited (three-state). The output stage is illustrated in Figure 45. AMPLIFIER DAC VOUTX Table 10. Modes of Operation PDx1 0 PDx0 0 0 1 1 1 0 1 POWER-DOWN CIRCUITRY RESISTOR NETWORK 11253-047 Operating Mode Normal Operation Power-Down Modes 1 kΩ to GND 100 kΩ to GND Three-State Figure 45. Output Stage During Power-Down Either or both DACs (DAC A and DAC B) can be powered down to the selected mode by setting the corresponding bits. See Table 11 for the contents of the input shift register during the power-down/ power-up operation. When both Bit PDx1 and Bit PDx0 (where x is the channel selected) in the input shift register are set to 0, the part works normally with its normal power consumption of 4 mA at 5 V. However, for the three power-down modes, the supply current falls to 4 µA at 5 V. Not only does the supply current fall, but the output stage is also internally switched from the output of the The bias generator, output amplifier, resistor string, and other associated linear circuitry are shut down when the power-down mode is activated. However, the contents of the DAC register are unaffected when in power-down. The DAC register can be updated while the device is in power-down mode. The time required to exit power-down is typically 4.5 µs for VDD = 5 V. To reduce the current consumption further, the on-chip reference can be powered off. See the Internal Reference Setup section. Table 11. 24-Bit Input Shift Register Contents of Power-Down/Power-Up Operation 1 DB23 (MSB) 0 DB22 1 DB21 0 DB20 0 Command bits (C3 to C0) 1 DB19 to DB16 X DB15 to DB8 X Address bits, don’t care DB7 PDB1 DB6 PDB0 Power-down, select DAC B X = don’t care. Rev. A | Page 21 of 28 DB5 1 DB4 1 DB3 1 DB2 1 DB1 PDA1 DB0 (LSB) PDA0 Power-down, select DAC A AD5697R Data Sheet LOAD DAC (HARDWARE LDAC PIN) LDAC MASK REGISTER The AD5697R DACs have double buffered interfaces consisting of two banks of registers: input registers and DAC registers. The user can write to any combination of the input registers. Updates to the DAC register are controlled by the LDAC pin. Command 0101 is reserved for this software LDAC mask function, which allows the address bits to be ignored. Writing to the DAC using Command 0101 loads the 4-bit LDAC register (DB3 to DB0). The default for each channel is 0; that is, the LDAC pin works normally. Setting the bits to 1 forces this DAC channel to ignore transitions on the LDAC pin, regardless of the state of the hardware LDAC pin. This flexibility is useful in applications where the user wishes to select which channels respond to the LDAC pin. OUTPUT AMPLIFIER VREF 12-BIT DAC LDAC DAC REGISTER VOUT Table 12. LDAC Overwrite Definition Load LDAC Register INPUT REGISTER 11253-048 SCL SDO LDAC Bits (DB3 or DB0) 0 1 INPUT SHIFT REGISTER LDAC Pin LDAC Operation 1 or 0 X1 Determined by the LDAC pin. DAC channels update and override the LDAC pin. DAC channels see LDAC pin as 1. Figure 46. Simplified Diagram of Input Loading Circuitry for a Single DAC Instantaneous DAC Updating (LDAC Held Low) 1 LDAC is held low while data is clocked into the input register using Command 0001. Both the addressed input register and the DAC register are updated on the 24th clock, and the output begins to change (see Table 14). X = don’t care. The LDAC register gives the user extra flexibility and control over the hardware LDAC pin (see Table 12). Setting the LDAC bits (DB3 or DB0) to 0 for a DAC channel means that the update of the channel is controlled by the hardware LDAC pin. Deferred DAC Updating (LDAC is Pulsed Low) LDAC is held high while data is clocked into the input register using Command 0001. Both DAC outputs are asynchronously updated by taking LDAC low after the 24th clock. The update then occurs on the falling edge of LDAC. Table 13. 24-Bit Input Shift Register Contents for LDAC Operation 1 DB23 (MSB) 0 DB22 0 DB21 0 DB20 1 DB19 X DB18 X Command bits (C3 to C0) 1 DB17 X DB16 X Address bits, don’t care DBB15 to DB4 X Don’t care DB3 DAC B DB2 0 DB1 0 DB0 (LSB) DAC A Setting LDAC to 1 overrides the LDAC pin X = don’t care. Table 14. Write Commands and LDAC Pin Truth Table 1 Command 0001 Description Write to Input Register n (dependent on LDAC) 0010 Update DAC Register n with contents of Input Register n 0011 Write to and update DAC Channel n Hardware LDAC Pin State VLOGIC GND 2 VLOGIC GND VLOGIC GND Input Register Contents Data update Data update No change No change Data update Data update DAC Register Contents No change (no update) Data update Updated with input register contents Updated with input register contents Data update Data update A high-to-low hardware LDAC pin transition always updates the contents of the DAC register with the contents of the input register on channels that are not masked (blocked) by the LDAC mask register. 2 When the LDAC pin is permanently tied low, the LDAC mask bits are ignored. 1 Rev. A | Page 22 of 28 Data Sheet AD5697R HARDWARE RESET (RESET) SOLDER HEAT REFLOW RESET is an active low reset that allows the outputs to be cleared to either zero scale or midscale. The clear code value is user selectable via the power-on reset select (RSTSEL) pin. It is necessary to keep RESET low for a minimum amount of time to complete the operation . When the RESET signal is returned high, the output remains at the cleared value until a new value is programmed. The outputs cannot be updated with a new value while the RESET pin is low. Also, a software executable reset function can reset the DAC to the power-on reset code. Command 0110 is designated for this software reset function (see Table 7). Any events on LDAC or RESET during power-on reset are ignored. As with all IC reference voltage circuits, the reference value experiences a shift induced by the soldering process. Analog Devices, Inc., performs a reliability test called precondition to mimic the effect of soldering a device to a board. The output voltage specification quoted in Table 2 includes the effect of this reliability test. Figure 47 shows the effect of solder heat reflow (SHR) as measured through the reliability test (precondition). 60 POSTSOLDER HEAT REFLOW PRESOLDER HEAT REFLOW 50 RESET SELECT PIN (RSTSEL) 30 20 10 0 INTERNAL REFERENCE SETUP 2.498 Command 0111 is reserved for setting up the internal reference (see Table 7). By default, the on-chip reference is on at power-up. To reduce the supply current, this reference can be turned off by setting the software-programmable bit, DB0, as shown in Table 16. Table 15 shows how the state of the bit corresponds to the mode of operation. 2.499 2.500 2.501 VREF (V) 2.502 11253-049 The AD5697R contains a power-on reset circuit that controls the output voltage during power-up. By connecting the RSTSEL pin low, the output powers up to zero scale. Note that this is outside the linear region of the DAC; by connecting the RSTSEL pin high, VOUT powers up to midscale. The output remains powered up at this level until a valid write sequence is made to the DAC. HITS 40 Figure 47. SHR Reference Voltage Shift Table 15. Reference Setup Register Internal Reference Setup Register (DB0) 0 1 Action Reference on (default) Reference off Table 16. 24-Bit Input Shift Register Contents for Internal Reference Setup Command1 DB23 (MSB) DB22 DB21 0 1 1 Command bits (C3 to C0) 1 DB20 1 DB19 X DB18 DB17 DB16 X X X Address bits (A3 to A0) X = don’t care. Rev. A | Page 23 of 28 DB15 to DB1 X Don’t care DB0 (LSB) 0/1 Reference setup register AD5697R Data Sheet THERMAL HYSTERESIS 9 Thermal hysteresis is the voltage difference induced on the reference voltage by sweeping the temperature from ambient to cold, to hot, and then back to ambient. 8 7 6 5 4 3 2 1 0 –200 –150 –100 –50 DISTORTION (ppm) Figure 48. Thermal Hysteresis Rev. A | Page 24 of 28 0 50 11253-051 HITS Thermal hysteresis data is shown in Figure 48. It is measured by sweeping temperature from ambient to −40°C, then to +105°C, and returning to ambient. The VREF delta is then measured between the two ambient measurements and shown in blue in Figure 48. The same temperature sweep and measurements are immediately repeated, and the results are shown in red in Figure 48. FIRST TEMPERATURE SWEEP SUBSEQUENT TEMPERATURE SWEEPS Data Sheet AD5697R APPLICATIONS INFORMATION MICROPROCESSOR INTERFACING Microprocessor interfacing to the AD5697R is via a serial bus that uses a standard protocol that is compatible with DSP processors and microcontrollers. The communications channel requires a 2-wire interface consisting of a clock signal and a data signal. AD5697R-TO-ADSP-BF531 INTERFACE The I2C interface of the AD5697R is designed to be easily connected to industry-standard DSPs and microcontrollers. Figure 49 shows the AD5697R connected to the Analog Devices Blackfin® DSP (ADSP-BF531). The Blackfin has an integrated I2C port that can be connected directly to the I2C pins of the AD5697R. The AD5697R LFCSP model has an exposed paddle beneath the device. Connect this paddle to the GND supply for the part. For optimum performance, use special considerations to design the motherboard and to mount the package. For enhanced thermal, electrical, and board level performance, solder the exposed paddle on the bottom of the package to the corresponding thermal land paddle on the PCB. Design thermal vias into the PCB land paddle area to further improve heat dissipation. The GND plane on the device can be increased (as shown in Figure 50) to provide a natural heat sinking effect. AD5697R AD5697R ADSP-BF531 BOARD Figure 49. ADSP-BF531 Interface to the AD5338R Figure 50. Paddle Connection to Board LAYOUT GUIDELINES In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. Design the printed circuit board (PCB) on which the AD5697R is mounted so that the AD5697R lies on the analog plane. The AD5697R must have ample supply bypassing of 10 µF in parallel with 0.1 µF on each supply, located as close to the package as possible, ideally right up against the device. The 10 µF capacitor is the tantalum bead type. The 0.1 µF capacitor must have low effective series resistance (ESR) and low effective series inductance (ESI), such as the common ceramic types that provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. GALVANICALLY ISOLATED INTERFACE In many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur. iCoupler® products from Analog Devices provide voltage isolation in excess of 2.5 kV. The serial loading structure of the AD5697R makes the part ideal for isolated interfaces because the number of interface lines is kept to a minimum. Figure 51 shows a 4-channel isolated interface to the AD5697R using the ADuM1400. For further information, visit http://www.analog.com/icouplers. CONTROLLER SERIAL CLOCK IN In systems where there are many devices on one board, it is often useful to provide some heat sinking capability to allow the power to dissipate easily. SERIAL DATA OUT ADuM14001 VIA VOA ENCODE DECODE ENCODE DECODE ENCODE DECODE ENCODE DECODE VIB VOB VIC RESET OUT LOAD DAC OUT 1 VOC VOD VID ADDITIONAL PINS OMITTED FOR CLARITY. Figure 51. Isolated Interface Rev. A | Page 25 of 28 TO SCLK TO SDIN TO RESET TO LDAC 11253-054 LDAC RESET 11253-053 PF9 PF8 GND PLANE SCL SDA 11253-052 GPIO1 GPIO2 AD5697R Data Sheet OUTLINE DIMENSIONS 3.10 3.00 SQ 2.90 PIN 1 INDICATOR 0.30 0.23 0.18 0.50 BSC 13 PIN 1 INDICATOR 16 1 12 EXPOSED PAD 1.75 1.60 SQ 1.45 9 0.80 0.75 0.70 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 0.25 MIN BOTTOM VIEW 08-16-2010-E TOP VIEW 4 5 8 0.50 0.40 0.30 COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6. Figure 52. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 3 mm × 3 mm Body, Very Very Thin Quad (CP-16-22) Dimensions shown in millimeters 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.65 BSC 0.30 0.19 COPLANARITY 0.10 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 53. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD5697RBCPZ-RL7 AD5697RBRUZ AD5697RBRUZ-RL7 EVAL-AD5697RSDZ 1 Resolution 12 Bits 12 Bits 12 Bits Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C Accuracy ±1 LSB INL ±1 LSB INL ±1 LSB INL Reference Temperature Coefficient (ppm/°C) ±5 (max) ±5 (max) ±5 (max) Z = RoHS Compliant Part. Rev. A | Page 26 of 28 Package Description 16-Lead LFCSP_WQ 16-Lead TSSOP 16-Lead TSSOP Evaluation Board Package Option CP-16-22 RU-16 RU-16 Branding DKY Data Sheet AD5697R NOTES Rev. A | Page 27 of 28 AD5697R Data Sheet NOTES ©2013–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11253-0-1/14(A) Rev. A | Page 28 of 28