AD5791-EP: Enhanced Product Data Sheet (Rev. A) PDF

1 ppm, 20-Bit,
±1 LSB INL, Voltage Output DAC
AD5791-EP
Enhanced Product
FEATURES
FUNCTIONAL BLOCK DIAGRAM
VCC
VDD
VREFPF VREFPS
AD5791-EP
IOVCC
A1
6.8kΩ 6.8kΩ
R1
RFB
RFB
INV
SDIN
INPUT
SHIFT
REGISTER
AND
CONTROL
LOGIC
SCLK
SYNC
SDO
20
20
DAC
REG
20-BIT
DAC
VOUT
6kΩ
LDAC
CLR
POWER-ON RESET
AND CLEAR LOGIC
RESET
DGND
VSS
AGND
VREFNF VREFNS
10455-001
1 ppm resolution
1 ppm INL
7.5 nV/√Hz noise spectral density
0.19 LSB long-term linearity stability
<0.05 ppm/°C temperature drift
1 µs settling time
1.4 nV-sec glitch impulse
20-lead TSSOP package
Wide power supply range up to ±16.5 V
35 MHz Schmitt triggered digital interface
1.8 V compatible digital interface
Extended automotive operating temperature range: −55°C
to +125°C
Figure 1.
ENHANCED PRODUCT FEATURES
COMPANION PRODUCTS
Supports defense and aerospace applications (AQEC
standard)
Military temperature range (−55°C to +125°C)
Controlled manufacturing baseline
One assembly/test site
One fabrication site
Enhanced product change notification
Qualification data available on request
Ultra precision op amps: AD8675, AD8676
High voltage op amp: ADA4898-1
Additional companion products on the AD5791 product page
Table 1. Related Device
Part No.
AD5781
Description
18-bit, 0.5 LSB INL, voltage output DAC
APPLICATIONS
Medical instrumentation
Test and measurement
Industrial control
High end scientific and aerospace instrumentation
GENERAL DESCRIPTION
The AD5791-EP1 is a single 20-bit, unbuffered voltage-output
DAC that operates from a bipolar supply of up to 33 V. The
AD5791 accepts a positive reference input in the range 5 V to
VDD − 2.5 V and a negative reference input in the range VSS +
2.5 V to 0 V. The AD5791-EP offers a relative accuracy
specification of ±1 LSB max, and operation is guaranteed
monotonic with a ±1 LSB DNL maximum specification.
The part uses a versatile 3-wire serial interface that operates at
clock rates up to 35 MHz and that is compatible with standard
SPI, QSPI™, MICROWIRE™, and DSP interface standards. The
part incorporates a power-on reset circuit that ensures the DAC
output powers up to 0 V in a known output impedance state
and remains in this state until a valid write to the device takes
1
place. The part provides an output clamp feature that places the
output in a defined load state.
The AD5791-EP is available in a compact, 20-lead TSSOP
package and operates at the extended automotive temperature
range of −55°C to +125°C. Additional application and technical
information can be found in the AD5791 data sheet.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
1 ppm Accuracy.
Wide Power Supply Range up to ±16.5 V.
Operating Temperature Range: −55°C to +125°C.
Low 7.5 nV/√Hz Noise Spectral Density.
Low 0.05 ppm/°C Temperature Drift.
Protected by U.S. Patents No. 7,884,747 and 8,089,380. Other patents pending.
Rev. A
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2012–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD5791-EP
Enhanced Product
TABLE OF CONTENTS
Features .............................................................................................. 1
Specifications .....................................................................................3
Enhanced Product Features ............................................................ 1
Timing Characteristics .................................................................5
Applications ....................................................................................... 1
Absolute Maximum Ratings ............................................................7
Functional Block Diagram .............................................................. 1
ESD Caution...................................................................................7
Companion Products ....................................................................... 1
Pin Configuration and Function Descriptions..............................8
General Description ......................................................................... 1
Typical Performance Characteristics ..............................................9
Product Highlights ........................................................................... 1
Outline Dimensions ....................................................................... 17
Revision History ............................................................................... 2
Ordering Guide .......................................................................... 17
REVISION HISTORY
7/13—Rev. 0 to Rev. A
Changes to t1 Test Conditions/Comments and Endnote 2 ......... 5
Deleted Figure 4 ................................................................................ 7
2/12—Revision 0: Initial Version
Rev. A | Page 2 of 20
Enhanced Product
AD5791-EP
SPECIFICATIONS
VDD = 12.5 V to 16.5 V, VSS = −16.5 V to −12.5 V, VREFP = 10 V, VREFN = −10 V, VCC = 2.7 V to +5.5 V, IOVCC = 1.71 V to 5.5 V,
RL = unloaded, CL = unloaded, all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter 1
STATIC PERFORMANCE 2
Resolution
Integral Nonlinearity Error (Relative Accuracy)
Differential Nonlinearity Error
Min
Typ
Max
Unit
20
−1
±0.25
+1
Bits
LSB
±0.25
±0.5
±1
±0.5
±0.75
±1
0.16
0.19
0.11
±0.1
±0.25
±0.8
±0.1
±0.25
±0.8
±0.02
±0.1
±0.15
±0.75
±0.1
±0.15
±0.75
±0.04
±0.3
±0.4
±0.4
±0.3
±0.4
±0.4
±0.04
0.01
+1.5
+1.5
+3
+1
+1.5
+2.5
−1.5
−1.5
−3
−1
−1.5
−2.5
Linearity Error Long-Term Stability 4
Full-Scale Error
Full-Scale Error Temperature Coefficient
Zero-Scale Error
Zero-Scale Error Temperature Coefficient3
Gain Error
Gain Error Temperature Coefficient3
R1, RFB Matching
OUTPUT CHARACTERISTICS3
Output Voltage Range
Output Slew Rate
Output Voltage Settling Time
Output Noise Spectral Density
Output Voltage Noise
−7
−11
−21
−4
−4
−6
−7
−10
−21
−4
−4
−6
−6
−10
−20
−6
−6
−7
VREFN
+7
+11
+21
+4
+4
+6
+7
+10
+21
+4
+4
+6
+6
+10
+20
+6
+6
+7
VREFP
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
ppm FSR/°C
LSB
LSB
LSB
LSB
LSB
LSB
ppm FSR/°C
ppm FSR
ppm FSR
ppm FSR
ppm FSR
ppm FSR
ppm FSR
ppm FSR/°C
%
50
1
V
V/µs
µs
1
7.5
7.5
7.5
1.1
µs
nV/√Hz
nV/√Hz
nV/√Hz
µV p-p
Rev. A | Page 3 of 20
Test Conditions/Comments
VREFP = +10 V, VREFN = −10 V,
TA = 0°C to 105°C
VREFP = +10 V, VREFN = −10 V
VREFP = 10 V, VREFN = 0 V 3
VREFP = 5 V, VREFN = 0 V3
VREFP = +10 V, VREFN = −10 V
VREFP = 10 V, VREFN = 0 V
VREFP = 5 V, VREFN = 0 V
After 500 hours at TA = 125°C
After 1000 hours at TA = 125°C
After 1000 hours at TA = 100°C
VREFP = +10 V, VREFN = −10 V3
VREFP = 10 V, VREFN = 0 V3
VREFP = 5 V, VREFN = 0 V3
VREFP = +10 V, VREFN = −10 V3, TA = 0°C to 105°C
VREFP = 10 V, VREFN = 0 V3, TA = 0°C to 105°C
VREFP = 5 V, VREFN = 0 V3, TA = 0°C to 105°C
VREFP = +10 V, VREFN = −10 V3
VREFP = 10 V, VREFN = 0 V3
VREFP = 5 V, VREFN = 0 V3
VREFP = +10 V, VREFN = −10 V3, TA = 0°C to 105°C
VREFP = 10 V, VREFN = 0 V3, TA = 0°C to 105°C
VREFP = 5 V, VREFN = 0 V3, TA = 0°C to 105°C
VREFP = +10 V, VREFN = −10 V3
VREFP = 10 V, VREFN = 0 V3
VREFP = 5 V, VREFN = 0 V3
VREFP = +10 V, VREFN = −10 V3, TA = 0°C to 105°C
VREFP = 10 V, VREFN = 0 V3, TA = 0°C to 105°C
VREFP = 5 V, VREFN = 0 V3, TA = 0°C to 105°C
10 V step to 0.02%, using the AD845 buffer
in unity-gain mode
500 code step to ±1 LSB 5
at 1 kHz, DAC code = midscale
at 10 kHz, DAC code = midscale
At 100 kHz, DAC code = midscale
DAC code = midscale, 0.1 Hz to 10 Hz
bandwidth 6
AD5791-EP
Parameter 1
Midscale Glitch Impulse 7
Enhanced Product
Min
MSB Segment Glitch Impulse7
Output Enabled Glitch Impulse
Digital Feedthrough
DC Output Impedance (Normal Mode)
DC Output Impedance (Output Clamped
to Ground)
Spurious Free Dynamic Range
Total Harmonic Distortion
REFERENCE INPUTS3
VREFP Input Range
VREFN Input Range
DC Input Impedance
Input Capacitance
LOGIC INPUTS3
Input Current 8
Input Low Voltage, VIL
Input High Voltage, VIH
Pin Capacitance
LOGIC OUTPUT (SDO)3
Output Low Voltage, VOL
Output High Voltage, VOH
High Impedance Leakage Current
High Impedance Output Capacitance
POWER REQUIREMENTS
VDD
VSS
VCC
IOVCC
IDD
ISS
ICC
IOICC
DC Power Supply Rejection Ratio3, 9
AC Power Supply Rejection Ratio3
Typ
3.1
1.7
1.4
9.1
3.6
1.9
45
0.4
3.4
6
Max
100
97
5
VSS + 2.5 V
5
VDD − 2.5 V
0
Unit
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
kΩ
kΩ
Test Conditions/Comments
VREFP = +10 V, VREFN = −10 V
VREFP = 10 V, VREFN = 0 V
VREFP = 5 V, VREFN = 0 V
VREFP = +10 V, VREFN = −10 V, see Figure 42
VREFP = 10 V, VREFN = 0 V, see Figure 43
VREFP = 5 V, VREFN = 0 V, see Figure 44
On removal of output ground clamp
dB
dB
1 kHz tone, 10 kHz sample rate
1 kHz tone, 10 kHz sample rate
V
6.6
kΩ
15
pF
−1
+1
0.3 × IOVCC
µA
V
V
pF
0.4
V
V
µA
pF
0.7 × IOVCC
5
IOVCC − 0.5 V
±1
3
VREFP, VREFN, code dependent,
typical at midscale code
VREFP, VREFN
IOVCC = 1.71 V to 5.5 V
IOVCC = 1.71 V to 5.5 V
IOVCC = 1.71 V to 5.5 V, sinking 1 mA
IOVCC = 1.71 V to 5.5 V, sourcing 1 mA
All digital inputs at DGND or IOVCC
7.5
VDD − 33
2.7
1.71
4.2
4
600
52
±0.6
±0.6
95
95
VSS + 33
−2.5
5.5
5.5
5.2
4.9
900
140
V
V
V
V
mA
mA
µA
µA
µV/V
µV/V
dB
dB
IOVCC ≤ VCC
SDO disabled
VDD ± 10%, VSS = 15 V
VSS ± 10%, VDD = 15 V
VDD ± 200 mV, 50 Hz/60 Hz, VSS = −15 V
∆VSS ± 200 mV, 50 Hz/60 Hz, VDD = 15 V
Temperature range: −55°C to +125°C, typical at +25°C and VDD = +15 V, VSS = −15 V, VREFP = +10 V, VREFN = −10 V.
Performance characterized with AD8676BRZ voltage reference buffers and AD8675ARZ output buffer.
Guaranteed by design and characterization; not production tested.
4
Linearity error refers to both INL error and DNL error, either parameter can be expected to drift by the amount specified after the length of time specified.
5
AD5791-EP configured in ×2 gain mode, 25 pF compensation capacitor on AD797.
6
Includes noise contribution from AD8676BRZ voltage reference buffers.
7
The AD5791-EP is configured in bias compensation mode with a low-pass RC filter on the output. R = 300 Ω, C = 143 pF (total capacitance seen by the output buffer,
lead capacitance, and so forth).
8
Current flowing in an individual logic pin.
9
Includes PSRR of AD8676BRZ voltage reference buffers.
1
2
3
Rev. A | Page 4 of 20
Enhanced Product
AD5791-EP
TIMING CHARACTERISTICS
VCC = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
t1 2
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22
1
2
Limit 1
IOVCC = 1.71 V to 3.3 V
IOVCC = 3.3 V to 5.5 V
40
28
92
60
15
10
9
5
5
5
2
2
48
40
8
6
9
7
12
7
13
10
20
16
14
11
130
130
130
130
50
50
140
140
0
0
65
60
62
45
0
0
35
35
150
150
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
ns typ
ns min
ns typ
ns min
ns max
ns max
ns min
ns typ
ns typ
Test Conditions/Comments
SCLK cycle time
SCLK cycle time (readback mode)
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
SCLK falling edge to SYNC rising edge hold time
Minimum SYNC high time
SYNC rising edge to next SCLK falling edge ignore
Data setup time
Data hold time
LDAC falling edge to SYNC falling edge
SYNC rising edge to LDAC falling edge
LDAC pulse width low
LDAC falling edge to output response time
SYNC rising edge to output response time (LDAC tied low)
CLR pulse width low
CLR pulse activation time
SYNC falling edge to first SCLK rising edge
SYNC rising edge to SDO tristate (CL = 50 pF)
SCLK rising edge to SDO valid (CL = 50 pF)
SYNC rising edge to SCLK rising edge ignore
RESET pulse width low
RESET pulse activation time
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVCC) and timed from a voltage level of (VIL + VIH)/2.
Maximum SCLK frequency is 35 MHz for write mode and 16 MHz for readback mode.
Rev. A | Page 5 of 20
AD5791-EP
Enhanced Product
t7
t1
SCLK
1
2
24
t3
t6
t2
t4
t5
SYNC
t9
t8
SDIN
DB23
DB0
t10
t12
t11
LDAC
t13
VOUT
t14
VOUT
t15
CLR
t16
VOUT
t21
RESET
10455-002
t22
VOUT
Figure 2. Write Mode Timing Diagram
t1
t17
SCLK
1
24
2
t3
t6
t20
t7
1
2
24
t2
t5
t4
t5
t17
SYNC
SDIN
t9
DB23
DB0
INPUT WORD SPECIFIES
REGISTER TO BE READ
NOP CONDITION
t18
t19
DB23
SDO
REGISTER CONTENTS CLOCKED OUT
Figure 3. Readback Mode Timing Diagram
Rev. A | Page 6 of 20
DB0
10455-003
t8
Enhanced Product
AD5791-EP
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Transient currents of up to
100 mA do not cause SCR latch-up.
Table 4.
Parameter
VDD to AGND
VSS to AGND
VDD to VSS
VCC to DGND
IOVCC to DGND
Digital Inputs to DGND
VOUT to AGND
VREFPF to AGND
VREFPS to AGND
VREFNF to AGND
VREFNS to AGND
DGND to AGND
Operating Temperature Range, TA
Industrial
Storage Temperature Range
Maximum Junction Temperature,
TJ max
Power Dissipation
TSSOP Package
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature
Soldering
ESD (Human Body Model)
Rating
−0.3 V to +34 V
−34 V to +0.3 V
−0.3 V to +34 V
−0.3 V to +7 V
−0.3 V to VCC + 0.3 V or +7 V
(whichever is less)
−0.3 V to IOVCC + 0.3 V or
+7 V (whichever is less)
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
VSS − 0.3 V to + 0.3 V
VSS − 0.3 V to + 0.3 V
−0.3 V to +0.3 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
This device is a high performance integrated circuit with an
ESD rating of 1.5 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
ESD CAUTION
−55°C to + 125°C
−65°C to +150°C
150°C
(TJ max − TA)/θJA
143°C/W
45°C/W
JEDEC industry standard
J-STD-020
1.5 kV
Rev. A | Page 7 of 20
AD5791-EP
Enhanced Product
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
INV
1
20 RFB
VOUT
2
19
VREFPS
3
18
VSS
VREFPF
4
17
VREFNS
TOP VIEW
(Not to Scale)
VDD
5
16
VREFNF
RESET
6
15
DGND
CLR
7
14
SYNC
LDAC
8
13
SCLK
VCC
9
12
SDIN
IOVCC 10
11
SDO
10455-005
AD5791-EP
AGND
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1
2
3
Mnemonic
INV
VOUT
VREFPS
4
VREFPF
5
VDD
6
7
RESET
CLR
8
LDAC
9
10
VCC
IOVCC
11
12
SDO
SDIN
13
SCLK
14
SYNC
15
16
DGND
VREFNF
17
VREFNS
18
VSS
19
20
AGND
RFB
Description
Connection to Inverting Input of External Amplifier.
Analog Output Voltage.
Positive Reference Sense Voltage Input. A voltage range of 5 V to VDD − 2.5 V can be connected. A unity gain
amplifier must be connected at this pin in conjunction with the VREFPF pin.
Positive Reference Force Voltage Input. A voltage range of 5 V to VDD − 2.5 V can be connected. A unity gain
amplifier must be connected at this pin in conjunction with the VREFPS pin.
Positive Analog Supply Connection. A voltage range of 7.5 V to 16.5 V can be connected; VDD should be decoupled
to AGND.
Active Low Reset Logic Input Pin. Asserting this pin returns the AD5791-EP to its power-on status.
Active Low Clear Logic Input Pin. Asserting this pin sets the DAC register to a user defined value and updates the
DAC output. The output value depends on the DAC register coding that is being used, either binary or twos
complement.
Active Low Load DAC Logic Input Pin. This is used to update the DAC register and, consequently, the analog
output. When tied permanently low, the output is updated on the rising edge of SYNC. If LDAC is held high during
the write cycle, the input register is updated, but the output update is held off until the falling edge of LDAC. The
LDAC pin should not be left unconnected.
Digital Supply Connection. A voltage range of 2.7 V to 5.5 V can be connected. VCC should be decoupled to DGND.
Digital Interface Supply Pin. Digital threshold levels are referenced to the voltage applied to this pin. A voltage in
the range of 1.71 V to 5.5 V can be connected. IOVCC should not be allowed to exceed VCC.
Serial Data Output Pin. Data is clocked out on the rising edge of the serial clock input.
Serial Data Input Pin. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of
the serial clock input.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can
be transferred at clock rates of up to 35 MHz.
Active Low Digital Interface Synchronization Input Pin. This is the frame synchronization signal for the input data.
When SYNC is low, it enables the input shift register, and data is then transferred in on the falling edges of the
following clocks. The input shift register is updated on the rising edge of SYNC.
Ground Reference Pin for Digital Circuitry.
Negative Reference Force Voltage Input. A voltage range of VSS + 2.5 V to 0 V can be connected. A unity gain
amplifier must be connected at this pin in conjunction with the VREFNS pin.
Negative Reference Sense Voltage Input. A voltage range of VSS + 2.5 V to 0 V can be connected. A unity gain
amplifier must be connected at this pin in conjunction with the VREFNF pin.
Negative Analog Supply Connection. A voltage range of −16.5 V to −2.5 V can be connected. VSS should be
decoupled to AGND.
Ground Reference Pin for Analog Circuitry.
Feedback Connection for External Amplifier.
Rev. A | Page 8 of 20
Enhanced Product
AD5791-EP
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
0.8
0.8
TA = +125°C
TA = +25°C
TA = –40°C
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
0.6
0.6
0.4
INL ERROR (LSB)
INL ERROR (LSB)
0.4
0.2
0
–0.2
0.2
0
–0.2
–0.4
–0.4
–1.0
600000
400000
DAC CODE
800000
1000000
Figure 5. Integral Nonlinearity Error vs. DAC Code, ±10 V Span
1.5
TA = +125°C
TA = +25°C
TA = –40°C
0
400000
600000
DAC CODE
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
0.8
DNL ERROR (LSB)
0.5
0
–0.5
0
200000
600000
400000
DAC CODE
800000
1000000
0.2
0
–0.2
–0.4
TA = +125°C
TA = +25°C
TA = –40°C
–1.0
0
1.5
TA = +125°C
TA = +25°C
TA = –40°C
DNL ERROR (LSB)
1.0
0.5
0
–0.5
–1.0
–2.5
0
200000
800000
1000000
1000000
0
–0.5
–1.0
400000
600000
DAC CODE
800000
0.5
TA = +125°C
TA = +25°C
TA = –40°C
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
–1.5
10455-008
VREFP = +5V
VREFN = 0V
VDD = +15V
VSS = –15V
400000
600000
DAC CODE
AD8676 REFERENCE BUFFERS VREFP = +10V
VREFN = 0V
AD8675 OUTPUT BUFFER
VDD = +15V
VSS = –15V
1.0
1.5
–2.0
200000
Figure 9. Differential Nonlinearity Error vs. DAC Code, ±10 V Span
2.5
–1.5
VREFP = +10V
VREFN = –10V
VDD = +15V
VSS = –15V
0.4
–0.8
Figure 6. Integral Nonlinearity Error vs. DAC Code, 10 V Span
2.0
1000000
–0.6
VREFP = +10V
VREFN = 0V
VDD = +15V
VSS = –15V
–1.5
800000
1.0
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
0.6
–1.0
INL ERROR (LSB)
200000
Figure 8. Integral Nonlinearity Error vs. DAC Code, ±10 V Span, ×2 Gain Mode
10455-007
INL ERROR (LSB)
1.0
–0.8
10455-010
200000
TA = –40°C
TA = +125°C
TA = +25°C
0
200000
400000
600000
DAC CODE
800000
1000000
Figure 10. Differential Nonlinearity Error vs. DAC Code, 10 V Span
Figure 7. Integral Nonlinearity Error vs. DAC Code, 5 V Span
Rev. A | Page 9 of 20
10455-011
0
10455-006
–0.8
VREFP = +10V
VREFN = 0V
VDD = +15V
VSS = –15V
–0.6
10455-009
VREFP = +10V
VREFN = –10V
VDD = +15V
VSS = –15V
–0.6
AD5791-EP
2.0
TA = +125°C
TA = +25°C
TA = –40°C
1.5
Enhanced Product
1.0
VREFP = +5V
VREFN = 0V
VDD = +15V
VSS = –15V
±10V SPAN MAX DNL
+5V SPAN MAX DNL
+10V SPAN MIN DNL
+10V SPAN MAX DNL
±10V SPAN MIN DNL
+5V SPAN MIN DNL
0.5
0.5
0
–0.5
0
–0.5
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
VDD = +15V
VSS = –15V
–1.0
–1.0
–1.5
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
0
200000
600000
400000
DAC CODE
800000
–1.5
–55
10455-012
–2.0
1000000
5
25
45
65
TEMPERATURE (°C)
85
105
125
0.6
1.0
AD8676 REFERENCE BUFFERS
0.8 AD8675 OUTPUT BUFFER
VREFP = +10V
0.6 VREFN = 0V
VDD = +15V
0.4 VSS = –15V
TA = +25°C
TA = –40°C
TA = +125°C
INL MAX
0.5
INL ERROR (LSB)
0.4
0.2
0
–0.2
–0.4
0.3
TA = 25°C
VREFP = +10V
VREFN = –10V
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
0.2
0.1
0
–0.1
–0.8
–0.2
–1.0
0
200000
400000
600000
DAC CODE
800000
1000000
–0.3
12.5
Figure 12. Differential Nonlinearity Error vs. DAC Code, ±10 V Span,
×2 Gain Mode
13.0
13.5
15.0
14.0
14.5
VDD/|VSS| (V)
15.5
16.0
16.5
10455-016
INL MIN
–0.6
10455-013
DNL ERROR (LSB)
–15
Figure 14. Differential Nonlinearity Error vs. Temperature
Figure 11. Differential Nonlinearity Error vs. DAC Code, 5 V Span
Figure 15. Integral Nonlinearity Error vs. Supply Voltage, ±10 V Span
1.5
2.0
±10V SPAN MAX INL
+5V SPAN MAX INL
+10V SPAN MIN INL
1.5
+10V SPAN MAX INL
±10V SPAN MIN INL
+5V SPAN MIN INL
INL MAX
1.0
INL ERROR (LSB)
1.0
0.5
0
0.5
0
TA = 25°C
VREFP = +5V
VREFN = 0V
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
–0.5
–0.5
–1.0
–1.5
–55
–35
–15
5
25
45
65
TEMPERATURE (°C)
85
105
125
INL MIN
–1.5
7.5
8.5
9.5
10.5
–2.5
–3.9
–5.3
–6.7
11.5 12.5 13.5 14.5 15.5 16.5
VDD (V)
–9.1 –10.5 –12.9 –14.2 –15.5 –16.5
VSS (V)
Figure 16. Integral Nonlinearity Error vs. Supply Voltage, 5 V Span
Figure 13. Integral Nonlinearity Error vs. Temperature
Rev. A | Page 10 of 20
10455-017
–1.0
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
VDD = +15V
VSS = –15V
10455-014
INL ERROR (LSB)
–35
10455-015
DNL ERROR (LSB)
DNL ERROR (LSB)
1.0
Enhanced Product
AD5791-EP
0.6
0.4
TA = 25°C
VREFP = +5V
VREFN = 0V
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
DNL MAX
0.3
ZERO-SCALE ERROR (LSB)
0.5
DNL ERROR (LSB)
0.2
0.1
TA = 25°C
VREFP = +10V
VREFN = –10V
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
0
–0.1
–0.2
0.4
0.3
0.2
0.1
–0.3
13.0
13.5
14.0
14.5
15.0
VDD/|VSS| (V)
15.5
16.0
16.5
0
7.5
8.5
9.5
10.5
–2.5
–3.9
–5.3
–6.7
Figure 17. Differential Nonlinearity Error vs. Supply Voltage, ±10 V Span
Figure 20. Zero-Scale Error vs. Supply Voltage, 5 V Span
0.4
0.20
TA = 25°C
VREFP = +10V
VREFN = –10V
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
DNL MAX
0.2
0.15
–0.2
–0.4
MIDSCALE ERROR (LSB)
DNL ERROR (LSB)
0
TA = 25°C
VREFP = +5V
VREFN = 0V
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
–0.6
DNL MIN
11.5 12.5 13.5 14.5 15.5 16.5
VDD (V)
–9.1 –10.5 –12.9 –14.2 –15.5 –16.5
VSS (V)
10455-021
–0.4
12.5
10455-018
DNL MIN
0.10
0.05
0
–0.05
–0.8
9.5
10.5
–2.5
–3.9
–5.3
–6.7
11.5 12.5 13.5 14.5 15.5 16.5
VDD (V)
–9.1 –10.5 –12.9 –14.2 –15.5 –16.5
VSS (V)
–0.15
12.5
Figure 18. Differential Nonlinearity Error vs. Supply Voltage, 5 V Span
13.0
13.5
14.0
14.5
15.0
VDD/|VSS| (V)
15.5
16.0
16.5
Figure 21. Midscale Error vs. Supply Voltage, ±10 V Span
0.6
0.2
0.1
0.4
0.3
0.2
TA = 25°C
VREFP = +10V
VREFN = –10V
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
–0.1
–0.2
–0.3
–0.4
TA = 25°C
VREFP = +5V
VREFN = 0V
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
–0.5
0.1
–0.6
0
12.5
13.0
13.5
14.0
14.5
15.0
VDD/|VSS| (V)
15.5
16.0
16.5
Figure 19. Zero-Scale Error vs. Supply Voltage, ±10 V Span
–0.7
7.5
8.5
9.5
10.5
–2.5
–3.9
–5.3
–6.7
11.5 12.5 13.5 14.5 15.5 16.5
VDD (V)
–9.1 –10.5 –12.9 –14.2 –15.5 –16.5
VSS (V)
Figure 22. Midscale Error vs. Supply Voltage, 5 V Span
Rev. A | Page 11 of 20
10455-023
MIDSCALE ERROR (LSB)
0
10455-020
ZERO-SCALE ERROR (LSB)
0.5
10455-022
8.5
10455-019
–0.10
–1.0
7.5
AD5791-EP
Enhanced Product
0.10
TA = 25°C
–0.035 VREFP = +10V
VREFN = –10V
–0.055 AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
TA = 25°C
VREFP = +5V
VREFN = 0V
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
0.05
GAIN ERROR (ppm FSR)
0
–0.075
–0.095
–0.115
–0.135
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
–0.155
13.5
14.0
14.5
15.0
VDD/|VSS| (V)
15.5
16.0
16.5
–0.40
7.5
8.5
9.5
10.5
–2.5
–3.9
–5.3
–6.7
Figure 26. Gain Error vs. Supply Voltage, 5 V Span
0.6
0.20
0.4
0.15
0.2
INL ERROR (LSB)
0.25
0.10
TA = 25°C
VREFP = +5V
VREFN = 0V
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
0
–0.05
7.5
8.5
9.5
10.5
–2.5
–3.9
–5.3
–6.7
0
INL MAX
TA = 25°C
VDD = +15V
VSS = –15V
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
–0.2
–0.4
11.5 12.5 13.5 14.5 15.5 16.5
VDD (V)
–9.1 –10.5 –12.9 –14.2 –15.5 –16.5
VSS (V)
–0.6
5.0
INL MIN
5.5
6.0
6.5
10455-025
7.0
7.5
8.0
VREFP /|VREFN | (V)
8.5
9.0
9.5
10.0
Figure 27. Integral Nonlinearity Error vs. Reference Voltage
Figure 24. Full-Scale Error vs. Supply Voltage, 5 V Span
0.4
–0.30
TA = 25°C
VREFP = +10V
VREFN = –10V
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
–0.35
0.2
DNL ERROR (LSB)
–0.40
DNL MAX
0.3
–0.45
–0.50
0.1
0
–0.1
–0.2
TA = 25°C
VDD = +15V
VSS = –15V
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
–0.3
–0.55
–0.4
–0.60
–0.65
12.5
13.0
13.5
14.0
14.5
15.0
VDD/|VSS| (V)
15.5
16.0
16.5
10455-026
–0.5
–0.6
5.0
DNL MIN
5.5
6.0
6.5
7.0
7.5
8.0
VREFP /|VREFN | (V)
8.5
9.0
9.5
10.0
Figure 28. Differential Nonlinearity Error vs. Reference Voltage
Figure 25. Gain Error vs. Supply Voltage, ±10 V Span
Rev. A | Page 12 of 20
10455-029
FULL-SCALE ERROR (LSB)
Figure 23. Full-Scale Error vs. Supply Voltage, ±10 V Span
0.05
11.5 12.5 13.5 14.5 15.5 16.5
VDD (V)
–9.1 –10.5 –12.9 –14.2 –15.5 –16.5
VSS (V)
10455-028
13.0
10455-024
–0.195
12.5
10455-027
–0.35
–0.175
GAIN ERROR (ppm FSR)
FULL-SCALE ERROR (LSB)
–0.015
AD5791-EP
0.60
–0.30
0.55
–0.35
GAIN ERROR (ppm FSR)
0.50
0.45
0.35
–0.45
–0.50
–0.55
5.5
6.0
6.5
7.0
7.5
8.0
VREFP /|VREFN | (V)
8.5
9.0
9.5
10.0
–0.60
5.0
10455-030
0.30
5.0
–0.40
Figure 29. Zero-Scale Error vs. Reference Voltage
6.5
7.0
7.5
8.0
VREFP /|VREFN | (V)
8.5
9.0
9.5
10.0
2.0
1.5
FULL-SCALE ERROR (LSBs)
0.10
MIDSCALE ERROR (LSB)
6.0
Figure 32. Gain Error vs. Reference Voltage
0.15
0.05
0
TA = 25°C
VDD = +15V
VSS = –15V
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
–0.05
–0.10
–0.15
1.0
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
VDD = +15V
VSS = –15V
±10V SPAN
+10V SPAN
+5V SPAN
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
5.5
6.0
6.5
7.0
7.5
8.0
VREFP /|VREFN | (V)
8.5
9.0
9.5
10.0
–3.0
–55
10455-031
–0.20
5.0
5.5
10455-033
0.40
TA = 25°C
VDD = +15V
VSS = –15V
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
TA = 25°C
VDD = +15V
VSS = –15V
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
Figure 30. Midscale Error vs. Reference Voltage
–35
–15
5
25
45
65
TEMPERATURE (°C)
85
105
125
10455-034
ZERO-SCALE ERROR (LSB)
Enhanced Product
Figure 33. Full-Scale Error vs. Temperature
2.0
0.15
±10V SPAN
+10V SPAN
+5V SPAN
1.8
0.10
–0.05
–0.10
–0.15
–0.20
5.0
TA = 25°C
VDD = +15V
VSS = –15V
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
5.5
6.0
6.5
7.0
7.5
8.0
VREFP /|VREFN | (V)
1.4
1.2
1
0.8
0.6
0.4
0.2
8.5
9.0
9.5
10.0
0
–55
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
VDD = +15V
VSS = –15V
–35
–15
5
25
45
65
TEMPERATURE (°C)
85
Figure 34. Midscale Error vs. Temperature
Figure 31. Full-Scale Error vs. Reference Voltage
Rev. A | Page 13 of 20
105
125
10455-035
MIDSCALE ERROR (LSBs)
0
10455-032
FULL-SCALE ERROR (LSB)
1.6
0.05
AD5791-EP
Enhanced Product
5
5
4
4
IDD
3
2
2
IDD, ISS (mA)
3
1
0
–1
–2
1
0
–1
–2
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
VDD = +15V
VSS = –15V
–4
–5
–55
–35
–15
–3
ISS
–4
5
25
45
65
TEMPERATURE (°C)
85
105
125
–5
–20
Figure 35. Zero-Scale Error vs. Temperature
–15
–10
–5
0
5
VDD/VSS (V)
10
15
10455-039
–3
10455-036
ZERO-SCALE ERROR (LSBs)
TA = 25°C
±10V SPAN
+10V SPAN
+5V SPAN
20
Figure 38. Power Supply Currents vs. Power Supply Voltages
4
3
GAIN ERROR (ppm FSR)
2
±10V SPAN
+10V SPAN
+5V SPAN
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
VDD = +15V
VSS = –15V
1
0
VDD = +15V
VSS = –15V
VREFP = +10V
VREFN = –10V
AD8676 REFERENCE BUFFERS
OUTPUT UNBUFFERED
LOAD = 10MΩ||20pF
3
–1
–2
–4
–35
–15
5
25
45
65
TEMPERATURE (°C)
85
105
125
4
10455-037
–5
–55
CH3 5V
TA = 25°C
800
700
IOVCC = 5V, LOGIC VOLTAGE
INCREASING
IOVCC = 5V, LOGIC VOLTAGE
DECREASING
IOVCC = 3V, LOGIC VOLTAGE
INCREASING
IOVCC = 3V, LOGIC VOLTAGE
DECREASING
VDD = +15V
VSS = –15V
VREFP = +10V
VREFN = –10V
AD8676 REFERENCE BUFFERS
OUTPUT UNBUFFERED
LOAD = 10MΩ||20pF
500
3
400
300
100
4
0
0
1
2
3
4
LOGIC INPUT VOLTAGE (V)
5
6
CH3 5V
Figure 37. IOICC vs. Logic Input Voltage
CH4 5V
200ns
Figure 40. Falling Full-Scale Voltage Step
Rev. A | Page 14 of 20
10455-041
200
10455-038
IOICC (µA)
600
200ns
Figure 39. Rising Full-Scale Voltage Step
Figure 36. Gain Error vs. Temperature
900
CH4 5V
10455-040
–3
Enhanced Product
AD5791-EP
10.8
3.0
±10V VREF
OUTPUT GAIN OF 1
BIAS COMPENSATION MODE
20pF COMPENSATION CAPACITOR
RC LOW-PASS FILTER
10.4
10.2
10.0
9.8
2.2
NEGATIVE CODE
CHANGE
POSITIVE CODE
CHANGE
1.8
1.4
1.0
0.6
9.6
0.2
1
2
3
4
5
TIME (µs)
–0.2
16384
65536
114688
163840
212992
262144
311296
360448
409600
458752
507904
557056
606208
655360
704512
753664
802816
851968
901120
950272
999424
0
10455-042
9.4
10455-045
VOUT (mV)
5V VREF
OUTPUT GAIN OF 1
BIAS COMPENSATION MODE
20pF COMPENSATION CAPACITOR
RC LOW-PASS FILTER
2.6
OUTPUT GLITCH (nV–sec)
10.6
CODE
Figure 41. 500 Code Step Settling Time
Figure 44. 6 MSB Segment Glitch Energy for +5 V VREF
10
8
5V VREF
OUTPUT GAIN OF 1
BIAS COMPENSATION MODE
20pF COMPENSATION CAPACITOR
RC LOW-PASS FILTER
40
NEGATIVE CODE
CHANGE
±10V VREF
OUTPUT GAIN OF 1
BIAS COMPENSATION MODE
20pF COMPENSATION CAPACITOR
RC LOW-PASS FILTER
30
7
20
6
5
VOUT (mV)
OUTPUT GLITCH (nV–sec)
9
POSITIVE CODE
CHANGE
4
10
3
0
2
CX = 143pF
CX = 143pF
CX = 143pF
CX = 143pF
–10
CODE
–20
–1.0
10455-043
16384
65536
114688
163840
212992
262144
311296
360448
409600
458752
507904
557056
606208
655360
704512
753664
802816
851968
901120
950272
999424
0
–0.5
2.0
NEGATIVE CODE
CHANGE
2.0
1.5
1.0
TA = 25°C
VDD = +15V
600 VSS = –15V
VREFP = +10V
VREFN = –10V
400
200
0
–200
0.5
–400
0
–600
0
10455-044
CODE
MIDSCALE CODE LOADED
OUTPUT UNBUFFERED
AD8676 REFERENCE BUFFERS
1
2
3
4
5
6
TIME (Seconds)
7
8
9
10
Figure 46. Voltage Output Noise, 0.1 Hz to 10 Hz Bandwidth
Figure 43. 6 MSB Segment Glitch Energy for +10 V VREF
Rev. A | Page 15 of 20
10455-047
POSITIVE CODE
CHANGE
OUTPUT VOLTAGE (nV)
2.5
1.5
800
16384
65536
114688
163840
212992
262144
311296
360448
409600
458752
507904
557056
606208
655360
704512
753664
802816
851968
901120
950272
999424
OUTPUT GLITCH (nV–sec)
3.0
1.0
Figure 45. Midscale Peak-to-Peak Glitch for ±10 V
4.0
3.5
0.5
TIME (µs)
Figure 42. 6 MSB Segment Glitch Energy for ±10 V VREF
10V VREF
OUTPUT GAIN OF 1
BIAS COMPENSATION MODE
20pF COMPENSATION CAPACITOR
RC LOW-PASS FILTER
0
+ 0pF
+ 220pF
+ 470pF
+ 1,000pF
10455-046
1
AD5791-EP
Enhanced Product
NSD (nV/ Hz)
100
VDD = +15V
VSS = –15V
VREFP = +10V
VREFN = –10V
CODE = MIDSCALE
1
0.1
1
10
100
1k
FREQUENCY (Hz)
10k
100k
10455-048
10
Figure 47. Noise Spectral Density vs. Frequency
350
TA = 25°C
VDD = +15V
VSS = –15V
VREFP = +10V
VREFN = –10V
AD8675 OUTPUT BUFFER
250
200
150
100
50
0
–50
–1
0
1
2
3
TIME (µs)
4
5
6
10455-049
OUTPUT VOLTAGE (mV)
300
Figure 48. Glitch Impulse on Removal of Output Clamp
Rev. A | Page 16 of 20
Enhanced Product
AD5791-EP
OUTLINE DIMENSIONS
6.60
6.50
6.40
20
11
4.50
4.40
4.30
6.40 BSC
1
10
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
COPLANARITY
0.10
0.30
0.19
0.20
0.09
SEATING
PLANE
8°
0°
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AC
Figure 49. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD5791SRU-EP
Temperature Range
−55°C to +125°C
INL
±1.5 LSB
Rev. A | Page 17 of 20
Package Description
20-Lead TSSOP
Package Option
RU-20
AD5791-EP
Enhanced Product
NOTES
Rev. A | Page 18 of 20
Enhanced Product
AD5791-EP
NOTES
Rev. A | Page 19 of 20
AD5791-EP
Enhanced Product
NOTES
©2012–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10455-0-7/13(A)
Rev. A | Page 20 of 20
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