AD5668-EP Data Sheet

FEATURES
FUNCTIONAL BLOCK DIAGRAM
Enhanced product features
Supports defense and aerospace applications (AQEC)
Military temperature range (−55°C to +125°C)
Controlled manufacturing baseline
One assembly/test site
One fabrication site
Enhanced product change notification
Qualification data available on request
Low power, smallest pin-compatible octal DAC: 16 bits
16-lead TSSOP
On-chip 1.25 V, 5 ppm/°C reference
Power down to 400 nA at 5 V, 200 nA at 3 V
2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to zero scale or midscale
3 power-down functions
Hardware LDAC and LDAC override function
CLR function to programmable code
Rail-to-rail operation
VREFIN/VREFOUT
VDD
AD5668-EP
LDAC
1.25V/2.5V
REF
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
SCLK
INTERFACE
LOGIC
SYNC
INPUT
REGISTER
INPUT
REGISTER
DIN
INPUT
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
STRING
DAC B
STRING
DAC C
STRING
DAC D
STRING
DAC E
STRING
DAC F
INPUT
REGISTER
DAC
REGISTER
STRING
DAC G
INPUT
REGISTER
DAC
REGISTER
STRING
DAC H
BUFFER
VOUTA
BUFFER
VOUTB
BUFFER
VOUTC
BUFFER
VOUTD
BUFFER
VOUTE
BUFFER
VOUTF
BUFFER
VOUTG
BUFFER
VOUTH
POWER-DOWN
LOGIC
POWER-ON
RESET
GND
LDAC1 CLR1
1RU-16
STRING
DAC A
PACKAGE ONLY
09463-001
Data Sheet
Octal, 16-Bit DAC with 5 ppm/°C
On-Chip Reference in 14-Lead TSSOP
AD5668-EP
Figure 1.
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
GENERAL DESCRIPTION
The AD5668-EP is a low power, octal, 16-bit, buffered voltageoutput digital-to-analog converter (DAC). It operates from a
single 2.7 V to 5.5 V supply and is guaranteed monotonic
by design.
The AD5668-EP has an on-chip reference with an internal gain
of 2. The AD5668-EP has a 1.25 V, 5 ppm/°C reference, giving a
full-scale output range of 2.5 V. The on-board reference is off at
power-up, allowing the use of an external reference, and the
internal reference is enabled via a software write.
DAC channels to simultaneously update. There is also an
asynchronous CLR that updates all DACs to a userprogrammable code—zero scale, midscale, or full scale.
The AD5668-EP uses a versatile 3-wire serial interface that
operates at clock rates up to 50 MHz and is compatible with
standard SPI, QSPI, MICROWIRE, and DSP interface standards.
Additional application and technical information can be found
in the AD5668 data sheet.
PRODUCT HIGHLIGHTS
The part incorporates a power-on-reset circuit that ensures that
the DAC output powers up to 0 V and remains powered up at this
level until a valid write takes place. The part contains a powerdown feature that reduces the current consumption of the device
to 400 nA at 5 V and provides software-selectable output loads
while in power-down mode for any or all DAC channels. The
outputs of all DACs can be updated simultaneously using the
LDAC function, with the added functionality of user-selectable
Rev. A
1.
2.
3.
4.
5.
Octal, 16-bit DAC.
On-chip 1.25 V/2.5 V, 5 ppm/°C reference.
Available in 16-lead TSSOP.
Power-on reset to 0 V or midscale.
Power-down capability. When powered down, the DAC
typically consumes 200 nA at 3 V and 400 nA at 5 V.
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Technical Support
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AD5668-EP
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Timing Characteristics .................................................................5
Applications ....................................................................................... 1
Absolute Maximum Ratings ............................................................6
Functional Block Diagram .............................................................. 1
ESD Caution...................................................................................6
General Description ......................................................................... 1
Pin Configurations and Function Descriptions ............................7
Product Highlights ........................................................................... 1
Typical Performance Characteristics ..............................................8
Revision History ............................................................................... 2
Outline Dimensions ....................................................................... 14
Specifications..................................................................................... 3
Ordering Guide .......................................................................... 14
AC Characteristics........................................................................ 4
REVISION HISTORY
1/15—Rev. 0 to Rev. A
Changes to Ordering Guide .......................................................... 14
10/10—Revision 0: Initial Version
Rev. A | Page 2 of 14
Data Sheet
AD5668-EP
SPECIFICATIONS
VDD = 4.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted.
Temperature range is −55°C to +125°C, typical at +25°C.
Table 1.
Parameter
STATIC PERFORMANCE1
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Code Error
Zero-Code Error Drift
Full-Scale Error
Gain Error
Gain Temperature Coefficient
Offset Error
DC Power Supply Rejection Ratio
DC Crosstalk (External Reference)
Min
DC Output Impedance
Short-Circuit Current
Power-Up Time
REFERENCE INPUTS
Reference Current
Reference Input Range
Reference Input Impedance
REFERENCE OUTPUT
Output Voltage
Reference Temperature Coefficient2
Reference Output Impedance
LOGIC INPUTS2
Input Current
Input Low Voltage, VINL
Input High Voltage, VINH
Pin Capacitance
POWER REQUIREMENTS
VDD
IDD (Normal Mode)3
VDD = 4.5 V to 5.5 V
VDD = 4.5 V to 5.5 V
IDD (All Power-Down Modes)4
VDD = 4.5 V to 5.5 V
Max
±8
±21
±1
14
16
1
±2
−0.2
±2.5
±1
–80
10
5
10
25
10
DC Crosstalk (Internal Reference)
OUTPUT CHARACTERISTICS2
Output Voltage Range
Capacitive Load Stability
Typ
0
−1
±1
±14
VDD
Bits
LSB
LSB
mV
µV/°C
% FSR
% FSR
ppm
mV
dB
µV
µV/mA
µV
µV
µV/mA
V
nF
nF
Ω
mA
µs
2
10
0.5
30
4
40
Unit
Conditions/Comments
See Figure 4
Guaranteed monotonic by design (see Figure 7)
All 0s loaded to DAC register (see Figure 9)
All 1s loaded to DAC register (see Figure 10)
Of FSR/°C
VDD ± 10%
Due to full-scale output change, RL = 2 kΩ to GND or VDD
Due to load current change
Due to powering down (per channel)
Due to full-scale output change, RL = 2 kΩ to GND or VDD
Due to load current change
RL = ∞
RL = 2 kΩ
VDD = 5 V
Coming out of power-down mode, VDD = 5 V
55
VDD
µA
V
kΩ
VREF = VDD = 5.5 V (per DAC channel)
1.253
V
ppm/°C
kΩ
At ambient
±3
0.8
µA
V
V
pF
All digital inputs
VDD = 5 V
VDD = 5 V
5.5
V
1.3
2
1.8
2.6
mA
mA
All digital inputs at 0 or VDD, DAC active, excludes load current
VIH = VDD and VIL = GND
Internal reference off
Internal reference on
0.4
1
µA
VIH = VDD and VIL = GND
0
14.6
1.247
±5
7.5
2
3
4.5
Linearity calculated using a reduced code range of AD5668 (Code 512 to 65,024). Output unloaded.
Guaranteed by design and characterization; not production tested.
3
Interface inactive. All DACs active. DAC outputs unloaded.
4
All eight DACs powered down.
1
2
Rev. A | Page 3 of 14
AD5668-EP
Data Sheet
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted.
Temperature range is −55°C to +125°C, typical at +25°C.
Table 2.
Parameter1
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch Impulse
Digital Feedthrough
Reference Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
Output Noise Spectral Density
Output Noise
1
Min
Typ
6
1.5
4
0.1
−90
0.5
2.5
3
340
−80
120
100
15
Max
10
Unit
µs
V/µs
nV-sec
nV-sec
dB
nV-sec
nV-sec
nV-sec
kHz
dB
nV/√Hz
nV/√Hz
μV p-p
Conditions/Comments
¼ to ¾ scale settling to ±2 LSB
1 LSB change around major carry (see Figure 24)
VREF = 2 V ± 0.1 V p-p, frequency = 10 Hz to 20 MHz
VREF = 2 V ± 0.2 V p-p
VREF = 2 V ± 0.1 V p-p, frequency = 10 kHz
DAC code = 0x8400, 1 kHz
DAC code = 0x8400, 10 kHz
0.1 Hz to 10 Hz
Guaranteed by design and characterization; not production tested.
Rev. A | Page 4 of 14
Data Sheet
AD5668-EP
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
VDD = 2.7 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Limit at TMIN, TMAX
VDD = 2.7 V to 5.5 V
20
8
8
13
4
4
0
15
13
0
10
15
5
0
300
Parameter
t11
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge set-up time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to SCLK fall ignore
SCLK falling edge to SYNC fall ignore
LDAC pulse width low
SCLK falling edge to LDAC rising edge
CLR pulse width low
SCLK falling edge to LDAC falling edge
CLR pulse activation time
Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested.
t10
t1
t9
SCLK
t8
t3
t4
t2
t7
SYNC
t6
t5
DIN
DB31
DB0
t14
t11
LDAC1
t12
LDAC2
CLR
VOUT
t13
t15
09463-002
1
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
Figure 2. Serial Write Operation
Rev. A | Page 5 of 14
AD5668-EP
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter
VDD to GND
Digital Input Voltage to GND
VOUT to GND
VREFIN/VREFOUT to GND
Operating Temperature Range
Industrial
Storage Temperature Range
Junction Temperature (TJ MAX)
TSSOP Package
Power Dissipation
θJA Thermal Impedance
Reflow Soldering Peak Temperature
SnPb
Pb Free
Rating
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−55°C to +125°C
−65°C to +150°C
150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
(TJ MAX − TA)/θJA
150.4°C/W
240°C
260°C
Rev. A | Page 6 of 14
Data Sheet
AD5668-EP
LDAC 1
16
SCLK
SYNC
2
15
DIN
VDD
3
14
GND
VOUTB
VOUTA 4
AD5668-EP
13
VOUTC 5
TOP VIEW
(Not to Scale)
12
VOUTD
VOUTE
6
11
VOUTF
VOUTG
7
10
VOUTH
VREFIN/VREFOUT
8
9
CLR
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Mnemonic
LDAC
SYNC
VDD
VOUTA
VOUTC
VOUTE
VOUTG
VREFIN/VREFOUT
CLR
VOUTH
VOUTF
VOUTD
VOUTB
GND
DIN
SCLK
Rev. A | Page 7 of 14
09463-003
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AD5668-EP
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
10
VDD = VREF = 5V
TA = 25°C
0.6
0.4
DNL ERROR (LSB)
6
4
2
0
–2
0.2
0
–0.2
–4
–0.4
–6
–0.6
–8
–0.8
65000
CODE
Figure 4. INL—External Reference
Figure 7. DNL
10
1.0
VDD = 3V
VREFOUT = 1.25V
TA = 25°C
8
6
0.8
0.6
4
0.4
0
–2
0.2
–0.2
–0.4
–6
–0.6
–8
–0.8
–1.0
–55
65000
–35
–15
09463-005
60000
55000
50000
45000
40000
35000
30000
25000
20000
15000
10000
0
5000
CODE
GAIN ERROR
0
–4
–10
FULL-SCALE ERROR
5
25
45
65
TEMPERATURE (°C)
85
105
125
09463-008
2
125
09463-009
ERROR (% FSR)
INL ERROR (LSB)
09463-007
60000
55000
50000
45000
40000
35000
30000
25000
20000
15000
–1.0
5000
5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k
CODE
10000
0
0
–10
VDD = 3V
VREFOUT = 1.25V
TA = 25°C
0.8
09463-004
INL ERROR (LSB)
8
Figure 8. Gain Error and Full-Scale Error vs. Temperature
Figure 5. INL
1.5
1.0
VDD = VREF = 5V
TA = 25°C
0.8
1.0
0.6
ERROR (mV)
ZERO-SCALE ERROR
0.2
0
–0.2
0
–0.5
–1.0
OFFSET ERROR
–0.4
–1.5
–0.6
–2.0
–0.8
–1.0
0
10k
20k
30k
CODE
40k
50k
60k
09463-006
DNL ERROR (LSB)
0.5
0.4
–2.5
–55
Figure 6. DNL—External Reference
–35
–15
5
25
45
65
TEMPERATURE (°C)
85
105
Figure 9. Zero-Scale Error and Offset Error vs. Temperature
Rev. A | Page 8 of 14
Data Sheet
AD5668-EP
1.0
14
VDD = 3.6V
VDD = 5.5V
12
0.5
10
FREQUENCY
ERROR (% FSR)
GAIN ERROR
0
FULL-SCALE ERROR
–0.5
VREFOUT = 2.5V
VREFOUT = 1.25V
8
6
–1.0
4
–1.5
3.2
3.7
4.2
VDD (V)
4.7
5.2
0
09463-010
–2.0
2.7
2.02 2.04 2.06 2.08 2.10 2.12 2.14 2.16 2.18 2.20 2.22 2.24 2.26 2.28
IDD (mA)
Figure 13. IDD Histogram with Internal Reference
Figure 10. Gain Error and Full-Scale Error vs. Supply Voltage
0.5
1.0
DAC LOADED WITH
FULL-SCALE
SOURCING CURRENT
TA = 25°C
0.4
ZERO-SCALE ERROR
0.3
ERROR VOLTAGE (V)
–0.5
–1.0
–1.5
0.2
VDD = 3V
VREFOUT = 1.25V
0.1
0
–0.1
–0.2
VDD = 5V
VREFOUT = 2.5V
–0.3
3.2
3.7
4.2
VDD (V)
4.7
5.2
–0.4
–0.5
–10
09463-011
–2.5
2.7
OFFSET ERROR
–6
–4
–2
0
2
CURRENT (mA)
4
6
8
10
Figure 14. Headroom at Rails vs. Source and Sink
Figure 11. Zero-Scale Error and Offset Error vs. Supply Voltage
6
20
VDD = 3.6V
VDD = 5.5V
5
16
VDD = 5V
VREFOUT = 2.5V
TA = 25°C
FULL SCALE
3/4 SCALE
4
14
VOUT (V)
12
10
8
3
MIDSCALE
2
1/4 SCALE
6
1
4
0
ZERO SCALE
2
0
1.20 1.22 1.24 1.26 1.28 1.30 1.32 1.34 1.36 1.38 1.40 1.42 1.44
IDD (mA)
–1
–30
09463-012
FREQUENCY
–8
–20
–10
0
10
CURRENT (mA)
Figure 15. Source and Sink Capability
Figure 12. IDD Histogram with External Reference
Rev. A | Page 9 of 14
20
30
09463-015
ERROR (mV)
0
–2.0
DAC LOADED WITH
ZERO-SCALE
SINKING CURRENT
09463-014
0.5
18
09463-013
2
AD5668-EP
2.0
Data Sheet
TA = 25°C
8
VDD = VREF = 5V
1.8
TA = 25°C
7
1.6
6
5
1.2
VDD = VREF = 3V
IDD (mA)
IDD (mA)
1.4
1.0
0.8
4
VDD = 5V
3
0.6
2
0.4
10512
20512
30512
40512
CODE
50512
60512
0
09463-017
0
512
1
2
3
VLOGIC (V)
4
5
6
Figure 19. Supply Current vs. Logic Input Voltage
Figure 16. Supply Current vs. Code
1.6
VDD = 3V
0
VDD = VREFIN = 5.5V
1.4
1.2
IDD (mA)
VDD = VREF = 5V
TA = 25°C
FULL-SCALE CODE CHANGE
0x0000 TO 0xFFFF
OUTPUT LOADED WITH 2kΩ
AND 200pF TO GND
VDD = VREFIN = 3.6V
1.0
0.8
0.6
VOUT = 909mV/DIV
0.4
1
–20
0
20
40
60
TEMPERATURE (°C)
80
100
TIME BASE = 4µs/DIV
Figure 20. Full-Scale Settling Time, 5 V
Figure 17. Supply Current vs. Temperature
1.6
09463-021
0
–40
09463-018
0.2
TA = 25°C
VDD = VREF = 5V
TA = 25°C
1.4
1.2
0.8
VDD
1
0.6
0.4
MAX(C2)*
420.0mV
2
0.2
VOUT
3.2
3.7
4.2
VDD (V)
4.7
5.2
CH1 2.0V
CH2 500mV
M100µs 125MS/s
A CH1
1.28V
Figure 21. Power-On Reset to 0 V
Figure 18. Supply Current vs. Supply Voltage
Rev. A | Page 10 of 14
8.0ns/pt
09463-022
0
2.7
09463-019
IDD (mA)
1.0
09463-020
1
0.2
Data Sheet
AD5668-EP
2.5000
VDD = VREF = 5V
TA = 25°C
2.4995
2.4990
2.4985
VOUT (V)
VDD
1
2.4980
2.4975
2.4970
2.4965
2.4960
M100µs 125MS/s
A CH1
1.28V
8.0ns/pt
2.4950
0
64
Figure 22. Power-On Reset to Midscale
128
192
256
320
SAMPLE
384
448
512
09463-026
CH2 1.0V
09463-023
CH1 2.0V
VDD = 5V
VREFOUT = 2.5V
TA = 25°C
4ns/SAMPLE NUMBER
2.4955
VOUT
512
09463-027
2
Figure 25. Analog Crosstalk
2.4900
SYNC
2.4895
1
SLCK
2.4890
3
VOUT (V)
2.4885
2.4880
2.4875
2.4870
VDD = 5V
2.4865
2
CH2 500mV
M400ns
A CH1
1.4V
09463-024
CH1 5.0V
CH3 5.0V
2.4855
0
Figure 23. Exiting Power-Down to Midscale
0
64
128
192
256
320
SAMPLE
384
128
192
256
320
SAMPLE
384
448
VDD = VREF = 5V
TA = 25°C
DAC LOADED WITH MIDSCALE
VDD = 5V
VREFOUT = 2.5V
TA = 25°C
4ns/SAMPLE NUMBER
GLITCH IMPULSE = 3.55nV-s
1 LSB CHANGE AROUND
MIDSCALE (0x8000 TO 0x7FFF)
2µV/DIV
2.505
2.504
2.503
2.502
2.501
2.500
2.499
2.498
2.497
2.496
2.495
2.494
2.493
2.492
2.491
2.490
2.489
2.488
2.487
2.486
2.485
64
Figure 26. DAC-to-DAC Crosstalk
448
512
09463-025
VOUT (V)
VDD = 5V
VREFOUT = 2.5V
TA = 25°C
4ns/SAMPLE NUMBER
2.4860
1
4s/DIV
Figure 27. 0.1 Hz to 10 Hz Output Noise Plot, External Reference
Figure 24. Digital-to-Analog Glitch Impulse (Negative)
Rev. A | Page 11 of 14
09463-028
VOUT
AD5668-EP
Data Sheet
–20
VDD = 5V
VREFOUT = 2.5V
TA = 25°C
DAC LOADED WITH MIDSCALE
–30
–50
(dB)
10µV/DIV
–40
VDD = 5V
TA = 25°C
DAC LOADED WITH FULL SCALE
VREF = 2V ± 0.3V p-p
1
–60
–70
–80
5s/DIV
09463-032
09463-029
–90
–100
2k
Figure 28. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference
4k
6k
FREQUENCY (Hz)
8k
10k
Figure 31. Total Harmonic Distortion
16
VDD = 3V
VREFOUT = 1.25V
TA = 25°C
DAC LOADED WITH MIDSCALE
VREF = VDD
TA = 25°C
14
VDD = 3V
TIME (µs)
5µV/DIV
12
1
10
VDD = 5V
8
4s/DIV
4
0
Figure 29. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference
1
2
3
4
5
6
7
CAPACITANCE (nF)
8
9
10
09463-033
09463-030
6
Figure 32. Settling Time vs. Capacitive Load
800
TA = 25°C
MIDSCALE LOADED
700
CLR
600
VOUTF
500
400
300
VDD = 5V
VREFOUT = 2.5V
VOUTB
4
VDD = 3V
VREFOUT = 1.25V
100
0
100
1k
2
10k
FREQUENCY (Hz)
100k
1M
Figure 30. Noise Spectral Density, Internal Reference
CH3 5.0V
CH2 1.0V
CH4 1.0V
M200ns A CH3
Figure 33. Hardware CLR
Rev. A | Page 12 of 14
1.10V
09463-034
200
09463-031
OUTPUT NOISE (nV/ Hz)
3
Data Sheet
AD5668-EP
5
VDD = 5V
TA = 25°C
0
–5
–15
–20
–25
–30
–35
–40
10k
100k
1M
FREQUENCY (Hz)
10M
09463-035
(dB)
–10
Figure 34. Multiplying Bandwidth
Rev. A | Page 13 of 14
AD5668-EP
Data Sheet
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.30
0.19
0.65
BSC
COPLANARITY
0.10
SEATING
PLANE
0.75
0.60
0.45
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 35. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD5668SRU-EP-1
AD5668SRU-EP-1RL7
Temperature Range
−55°C to +125°C
−55°C to +125°C
Package Description
16-Lead TSSOP
16-Lead TSSOP
©2010–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09463-0-1/15(A)
Rev. A | Page 14 of 14
Package
Option
RU-16
RU-16
Power-On
Reset to Code
Zero
Zero
Accuracy
±21 LSB INL
±21 LSB INL
Internal
Reference
1.25 V
1.25 V
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