14-Bit, 210 MSPS TxDAC® D/A Converter AD9744 Data Sheet FEATURES APPLICATIONS High performance member of pin-compatible TxDAC product family Excellent spurious-free dynamic range performance SFDR to Nyquist 83 dBc at 5 MHz output 80 dBc at 10 MHz output 73 dBc at 20 MHz output SNR at 5 MHz output, 125 MSPS: 77 dB Twos complement or straight binary data format Differential current outputs: 2 mA to 20 mA Power dissipation: 135 mW at 3.3 V Power-down mode: 15 mW at 3.3 V On-chip 1.2 V reference CMOS-compatible digital interface 28-lead SOIC, 28-lead TSSOP, and 32-lead LFCSP packages Edge-triggered latches Wideband communication transmit channel Direct IFs Base stations Wireless local loops Digital radio links Direct digital synthesis (DDS) Instrumentation FUNCTIONAL BLOCK DIAGRAM 3.3V REFLO 1.2V REF REFIO FS ADJ RSET 3.3V CURRENT SOURCE ARRAY DVDD DCOM CLOCK AVDD 150pF ACOM AD9744 IOUTA SEGMENTED SWITCHES CLOCK LSB SWITCHES IOUTB LATCHES DIGITAL DATA INPUTS (DB13–DB0) SLEEP MODE 02913-001 0.1µF Figure 1. GENERAL DESCRIPTION The AD9744 1 is a 14-bit resolution, wideband, third generation member of the TxDAC series of high performance, low power CMOS digital-to-analog converters (DACs). The TxDAC family, consisting of pin-compatible 8-, 10-, 12-, and 14-bit DACs, is specifically optimized for the transmit signal path of communication systems. All of the devices share the same interface options, small outline package, and pinout, providing an upward or downward component selection path based on performance, resolution, and cost. The AD9744 offers exceptional ac and dc performance while supporting update rates up to 210 MSPS. The AD9744’s low power dissipation makes it well suited for portable and low power applications. Its power dissipation can be further reduced to a mere 60 mW with a slight degradation in performance by lowering the full-scale current output. Also, a power-down mode reduces the standby power dissipation to approximately 15 mW. A segmented current source architecture is combined with a proprietary switching technique to reduce spurious components and enhance dynamic performance. Edge-triggered input latches and a 1.2 V temperature compensated band gap reference have been integrated to provide a complete monolithic DAC solution. The digital inputs support 3 V CMOS logic families. PRODUCT HIGHLIGHTS 1. The AD9744 is the 14-bit member of the pin compatible TxDAC family, which offers excellent INL and DNL performance. 2. Data input supports twos complement or straight binary data coding. 3. High speed, single-ended CMOS clock input supports 210 MSPS conversion rate. 4. Low power: Complete CMOS DAC function operates on 135 mW from a 2.7 V to 3.6 V single supply. The DAC fullscale current can be reduced for lower power operation, and a sleep mode is provided for low power idle periods. 5. On-chip voltage reference: The AD9744 includes a 1.2 V temperature compensated band gap voltage reference. 6. Industry-standard 28-lead SOIC, 28-lead TSSOP, and 32-lead LFCSP packages. Protected by U.S. Patent Numbers 5568145, 5689257, and 5703519. 1 Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2003–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD9744 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Reference Control Amplifier .................................................... 13 Applications ....................................................................................... 1 DAC Transfer Function ............................................................. 14 Functional Block Diagram .............................................................. 1 Analog Outputs .......................................................................... 14 General Description ......................................................................... 1 Digital Inputs .............................................................................. 15 Product Highlights ........................................................................... 1 Clock Input.................................................................................. 15 Revision History ............................................................................... 2 DAC Timing................................................................................ 16 Specifications..................................................................................... 3 Power Dissipation....................................................................... 16 DC Specifications ......................................................................... 3 Applying the AD9744 ................................................................ 17 Dynamic Specifications ............................................................... 4 Differential Coupling Using a Transformer............................ 17 Digital Specifications ................................................................... 5 Differential Coupling Using an Op Amp ................................ 17 Absolute Maximum Ratings............................................................ 6 Single-Ended Unbuffered Voltage Output .............................. 18 Thermal Characteristics .............................................................. 6 Single-Ended, Buffered Voltage Output Configuration ........ 18 ESD Caution .................................................................................. 6 Pin Configurations and Function Descriptions ........................... 7 Power and Grounding Considerations, Power Supply Rejection ...................................................................................... 18 Typical Performance Characteristics ............................................. 8 Evaluation Board ............................................................................ 20 Terminology .................................................................................... 12 General Description ................................................................... 20 Functional Description .................................................................. 13 Outline Dimensions ....................................................................... 30 Reference Operation .................................................................. 13 Ordering Guide............................................................................... 31 REVISION HISTORY 12/13—Rev. B to Rev. C Added Table 5; Renumbered Sequentially .................................... 6 Added Exposed Pad Note to Figure 4 and Table 6, Pin Configurations and Function Descriptions Section .................... 7 Moved Terminology Section ......................................................... 12 Updated Outline Dimensions ....................................................... 30 Changes to Ordering Guide .......................................................... 31 4/05—Rev. A to Rev. B Updated Format .................................................................. Universal Changes to General Description .................................................... 1 Changes to Product Highlights....................................................... 1 Changes to DC Specifications ......................................................... 3 Changes to Dynamic Specifications ............................................... 4 Changes to Pin Function Description ........................................... 7 Changes to Figure 6 and Figure 9 ................................................... 9 Inserted New Figure 10; Renumbered Sequentially .................... 9 Changes to Figure 12, Figure 13, Figure 14, and Figure 15 ...... 10 Changes to Figure 22 Caption ...................................................... 11 Inserted New Figure 23; Renumbered Sequentially .................. 11 Changes to Functional Description ............................................. 13 Changes to Reference Operation Section .................................... 13 Added Figure 25; Renumbered Sequentially .............................. 13 Changes to Digital Inputs Section ................................................ 15 Changes to Figure 31 and Figure 32............................................. 16 Updated Outline Dimensions ....................................................... 30 Changes to Ordering Guide .......................................................... 31 5/03—Rev. 0 to Rev. A Added 32-Lead LFCSP Package ....................................... Universal Edits to Features.................................................................................1 Edits to Product Highlights..............................................................1 Edits to DC Specifications ................................................................2 Edits to Dynamic Specifications ......................................................3 Edits to Digital Specifications ..........................................................4 Edits to Absolute Maximum Ratings ..............................................5 Edits to Thermal Characteristics .....................................................5 Edits to Ordering Guide ...................................................................5 Edits to Pin Configuration ...............................................................6 Edits to Pin Function Descriptions .................................................6 Edits to Figure 2 .................................................................................7 Replaced TPCs 1, 4, 7, and 8 ............................................................8 Edits to Figure 3 .............................................................................. 10 Edits to Functional Description ................................................... 10 Added Clock Input Section ........................................................... 12 Added Figure 7 ............................................................................... 12 Edits to DAC Timing Section ....................................................... 12 Edits to Sleep Mode Operation Section....................................... 13 Edits to Power Dissipation Section .............................................. 13 Renumbered Figures 8 to Figure 26 ............................................. 13 Added Figure 11 ............................................................................. 13 Added Figure 27 to Figure 35 ....................................................... 21 Updated Outline Dimensions ....................................................... 26 Rev. C | Page 2 of 32 Data Sheet AD9744 SPECIFICATIONS DC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted. Table 1. Parameter RESOLUTION DC ACCURACY 1 Integral Linearity Error (INL) Differential Nonlinearity (DNL) ANALOG OUTPUT Offset Error Gain Error (Without Internal Reference) Gain Error (With Internal Reference) Full-Scale Output Current 2 Output Compliance Range Output Resistance Output Capacitance REFERENCE OUTPUT Reference Voltage Reference Output Current 3 REFERENCE INPUT Input Compliance Range Reference Input Resistance (External Reference) Small Signal Bandwidth TEMPERATURE COEFFICIENTS Offset Drift Gain Drift (Without Internal Reference) Gain Drift (With Internal Reference) Reference Voltage Drift POWER SUPPLY Supply Voltages AVDD DVDD CLKVDD Analog Supply Current (IAVDD) Digital Supply Current (IDVDD) 4 Clock Supply Current (ICLKVDD) Supply Current Sleep Mode (IAVDD) Power Dissipation4 Power Dissipation 5 Power Supply Rejection Ratio—AVDD 6 Power Supply Rejection Ratio—DVDD6 OPERATING RANGE Min 14 Typ Max Unit Bits −5 −3 ±0.8 ±0.5 +5 +3 LSB LSB +0.02 +0.5 +0.5 20 +1.25 % of FSR % of FSR % of FSR mA V kΩ pF 1.26 V nA 1.25 7 0.5 V kΩ MHz 0 ±50 ±100 ±50 ppm of FSR/°C ppm of FSR/°C ppm of FSR/°C ppm/°C −0.02 −0.5 −0.5 2 −1 ±0.1 ±0.1 100 5 1.14 1.20 100 0.1 2.7 2.7 2.7 −1 −0.04 −40 3.3 3.3 3.3 33 8 5 5 135 145 3.6 3.6 3.6 36 9 6 6 145 +1 +0.04 +85 Measured at IOUTA, driving a virtual ground. Nominal full-scale current, IOUTFS, is 32 times the IREF current. 3 An external buffer amplifier with input bias current <100 nA should be used to drive any external load. 4 Measured at fCLOCK = 25 MSPS and fOUT = 1 MHz. 5 Measured as unbuffered voltage output with IOUTFS = 20 mA and 50 Ω RLOAD at IOUTA and IOUTB, fCLOCK = 100 MSPS and fOUT = 40 MHz. 6 ±5% power supply variation. 1 2 Rev. C | Page 3 of 32 V V V mA mA mA mA mW mW % of FSR/V % of FSR/V °C AD9744 Data Sheet DYNAMIC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, differential transformer coupled output, 50 Ω doubly terminated, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE Maximum Output Update Rate (fCLOCK) Output Settling Time (tST) (to 0.1%) 1 Output Propagation Delay (tPD) Glitch Impulse Output Rise Time (10% to 90%)1 Output Fall Time (10% to 90%)1 Output Noise (IOUTFS = 20 mA) 2 Output Noise (IOUTFS = 2 mA)2 Noise Spectral Density 3 AC LINEARITY Spurious-Free Dynamic Range to Nyquist fCLOCK = 25 MSPS; fOUT = 1.00 MHz 0 dBFS Output −6 dBFS Output −12 dBFS Output −18 dBFS Output fCLOCK = 65 MSPS; fOUT = 1.00 MHz fCLOCK = 65 MSPS; fOUT = 2.51 MHz fCLOCK = 65 MSPS; fOUT = 10 MHz fCLOCK = 65 MSPS; fOUT = 15 MHz fCLOCK = 65 MSPS; fOUT = 25 MHz fCLOCK = 165 MSPS; fOUT = 21 MHz fCLOCK = 165 MSPS; fOUT = 41 MHz fCLOCK = 210 MSPS; fOUT = 41 MHz fCLOCK = 210 MSPS; fOUT = 69 MHz Spurious-Free Dynamic Range Within a Window fCLOCK = 25 MSPS; fOUT = 1.00 MHz; 2 MHz Span fCLOCK = 50 MSPS; fOUT = 5.02 MHz; 2 MHz Span fCLOCK = 65 MSPS; fOUT = 5.03 MHz; 2.5 MHz Span fCLOCK = 125 MSPS; fOUT = 5.04 MHz; 4 MHz Span Total Harmonic Distortion fCLOCK = 25 MSPS; fOUT = 1.00 MHz fCLOCK = 50 MSPS; fOUT = 2.00 MHz fCLOCK = 65 MSPS; fOUT = 2.00 MHz fCLOCK = 125 MSPS; fOUT = 2.00 MHz Signal-to-Noise Ratio fCLOCK = 65 MSPS; fOUT = 5 MHz; IOUTFS = 20 mA fCLOCK = 65 MSPS; fOUT = 5 MHz; IOUTFS = 5 mA fCLOCK = 125 MSPS; fOUT = 5 MHz; IOUTFS = 20 mA fCLOCK = 125 MSPS; fOUT = 5 MHz; IOUTFS = 5 mA fCLOCK = 165 MSPS; fOUT = 5 MHz; IOUTFS = 20 mA fCLOCK = 165 MSPS; fOUT = 5 MHz; IOUTFS = 5 mA fCLOCK = 210 MSPS; fOUT = 5 MHz; IOUTFS = 20 mA fCLOCK = 210 MSPS; fOUT = 5 MHz; IOUTFS = 5 mA Min Typ Max 210 11 1 5 2.5 2.5 50 30 −155 MSPS ns ns pV-s ns ns pA/√Hz pA/√Hz dBm/Hz 77 90 87 82 82 85 84 80 75 74 73 60 68 64 dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc 84 90 90 87 87 dBc dBc dBc dBc −86 −77 −77 −77 82 88 77 78 70 70 74 67 Rev. C | Page 4 of 32 Unit −77 dBc dBc dBc dBc dB dB dB dB dB dB dB dB Data Sheet AD9744 Parameter Multitone Power Ratio (8 Tones at 400 kHz Spacing) fCLOCK = 78 MSPS; fOUT = 15.0 MHz to 18.2 MHz 0 dBFS Output −6 dBFS Output −12 dBFS Output −18 dBFS Output 1 2 3 Min Typ Max 66 68 62 61 Unit dBc dBc dBc dBc Measured single-ended into 50 Ω load. Output noise is measured with a full-scale output set to 20 mA with no conversion activity. It is a measure of the thermal noise only. Noise spectral density is the average noise power normalized to a 1 Hz bandwidth, with the DAC converting and producing an output tone. DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted. Table 3. Parameter DIGITAL INPUTS 1 Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Input Capacitance Input Setup Time (tS) Input Hold Time (tH) Latch Pulse Width (tLPW) CLK INPUTS 2 Input Voltage Range Common-Mode Voltage Differential Voltage 2 Typ 2.1 3 0 Max 0.9 +10 +10 −10 −10 5 2.0 1.5 1.5 0 0.75 0.5 3 2.25 1.5 1.5 Includes CLOCK pin on SOIC/TSSOP packages and CLK+ pin on LFCSP package in single-ended clock input mode. Applicable to CLK+ and CLK– inputs when configured for differential or PECL clock input mode. DB0–DB13 tS tH CLOCK tLPW tPD IOUTA OR IOUTB tST 0.1% Figure 2. Timing Diagram Rev. C | Page 5 of 32 0.1% 02913-002 1 Min Unit V V µA µA pF ns ns ns V V V AD9744 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 4. Parameter AVDD DVDD CLKVDD ACOM ACOM DCOM AVDD AVDD DVDD CLOCK, SLEEP Digital Inputs, MODE IOUTA, IOUTB REFIO, REFLO, FS ADJ CLK+, CLK−, CMODE Junction Temperature Storage Temperature Lead Temperature (10 sec) With Respect to ACOM DCOM CLKCOM DCOM CLKCOM CLKCOM DVDD CLKVDD CLKVDD DCOM DCOM Min −0.3 −0.3 −0.3 −0.3 −0.3 −0.3 −3.9 −3.9 −3.9 −0.3 −0.3 Max +3.9 +3.9 +3.9 +0.3 +0.3 +0.3 +3.9 +3.9 +3.9 DVDD + 0.3 DVDD + 0.3 Unit V V V V V V V V V V V ACOM ACOM −1.0 −0.3 AVDD + 0.3 AVDD + 0.3 V V CLKCOM −0.3 CLKVDD + 0.3 150 V +150 °C 300 °C −65 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL CHARACTERISTICS Thermal impedance measurements were taken on a 4-layer board in still air, in accordance with EIA/JESD51-7. Table 5. Thermal Resistance Package Type 28-Lead 300-Mil SOIC 28-Lead TSSOP 32-Lead LFCSP ESD CAUTION °C Rev. C | Page 6 of 32 θJA 55.9 67.7 32.5 Unit °C/W °C/W °C/W Data Sheet AD9744 27 DVDD DB11 3 26 DCOM DB10 4 25 MODE 32 31 30 29 28 27 26 25 28 CLOCK DB12 2 24 AVDD DB9 5 DB7 DB6 DVDD DB5 DB4 DB3 DB2 DB1 AD9744 DB5 9 20 ACOM DB4 10 19 NC DB3 11 18 FS ADJ DB2 12 17 REFIO DB1 13 16 REFLO (LSB) DB0 14 15 SLEEP AD9744 TOP VIEW (Not to Scale) NC = NO CONNECT Figure 3. 28-Lead SOIC and TSSOP (LSB) DB0 DCOM CLKVDD CLK+ CLK– CLKCOM CMODE MODE 21 IOUTB 02913-003 DB6 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 23 RESERVED TOP VIEW DB7 7 (Not to Scale) 22 IOUTA DB8 6 24 23 22 21 20 19 18 17 FS ADJ REFIO ACOM IOUTA IOUTB ACOM AVDD AVDD 02913-004 (MSB) DB13 1 DB8 DB9 DB10 DB11 DB12 DB13 (MSB) DCOM SLEEP PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS NOTES 1. CONNECT THE EXPOSED PAD THERMALLY TO A COPPER GROUND PLANE FOR ENHANCED ELECTRICAL AND THERMAL PERFORMANCE. Figure 4. 32-Lead LFCSP Table 6. Pin Function Descriptions SOIC/TSSOP Pin No. 1 2 to 13 14 15 LFCSP Pin No. 27 28 to 32, 1, 2, 4 to 8 9 25 Mnemonic DB13 DB12 to DB1 DB0 SLEEP 16 N/A REFLO 17 23 REFIO 18 19 20 21 22 23 24 25 N/A 24 N/A 19, 22 20 21 N/A 17, 18 16 15 FS ADJ NC ACOM IOUTB IOUTA RESERVED AVDD MODE CMODE 26 27 28 N/A N/A N/A N/A N/A 10, 26 3 N/A 12 13 11 14 EPAD DCOM DVDD CLOCK CLK+ CLK− CLKVDD CLKCOM EPAD Description Most Significant Data Bit (MSB). Data Bits 12 to 1. Least Significant Data Bit (LSB). Power-Down Control Input. Active high. Contains active pull-down circuit; it may be left unterminated if not used. Reference Ground when Internal 1.2 V Reference Used. Connect to ACOM for both internal and external reference operation modes. Reference Input/Output. Serves as reference input when using external reference. Serves as 1.2 V reference output when using internal reference. Requires 0.1 µF capacitor to ACOM when using internal reference. Full-Scale Current Output Adjust. No Internal Connection. Analog Common. Complementary DAC Current Output. Full-scale current when all data bits are 0s. DAC Current Output. Full-scale current when all data bits are 1s. Reserved. Do not connect to common or supply. Analog Supply Voltage (3.3 V). Selects Input Data Format. Connect to DCOM for straight binary, DVDD for twos complement. Clock Mode Selection. Connect to CLKCOM for single-ended clock receiver (drive CLK+ and float CLK−). Connect to CLKVDD for differential receiver. Float for PECL receiver (terminations on-chip). Digital Common. Digital Supply Voltage (3.3 V). Clock Input. Data latched on positive edge of clock. Differential Clock Input. Differential Clock Input. Clock Supply Voltage (3.3 V). Clock Common. Exposed Pad. Connect the exposed pad thermally to a copper ground plane for enhanced electrical and thermal performance. Rev. C | Page 7 of 32 AD9744 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 95 95 210MSPS (LFCSP) 90 90 125MSPS –6dBFS (LFCSP) 85 85 165MSPS (LFCSP) 210MSPS 70 165MSPS 125MSPS (LFCSP) 70 65 60 60 55 55 50 50 45 1 10 100 fOUT (MHz) –12dBFS 0dBFS (LFCSP) –6dBFS 45 0 10 40 30 20 95 90 90 85 0dBFS (LFCSP) –6dBFS (LFCSP) 85 –6dBFS –12dBFS (LFCSP) 0dBFS SFDR (dBc) 80 75 –12dBFS 70 65 75 70 65 60 60 55 55 50 50 5 10 15 20 25 fOUT (MHz) 0dBFS –12dBFS –6dBFS 45 02913-009 45 0 60 Figure 8. SFDR vs. fOUT at 165 MSPS 95 80 50 fOUT (MHz) Figure 5. SFDR vs. fOUT at 0 dBFS SFDR (dBc) 0dBFS 0 10 20 30 40 50 60 70 80 fOUT (MHz) Figure 6. SFDR vs. fOUT at 65 MSPS 02913-055 65 75 02913-007 SFDR (dBc) 75 –12dBFS (LFCSP) 80 65MSPS 02913-006 SFDR (dBc) 80 Figure 9. SFDR vs. fOUT at 210 MSPS 95 95 90 90 85 85 80 80 SFDR (dBc) –6dBFS 70 –12dBFS 65 55 50 50 45 5 10 15 20 25 30 35 fOUT (MHz) 5mA 65 55 0 10mA 70 60 0dBFS 60 75 40 45 45 0 5 10 15 20 25 fOUT (MHz) Figure 10. SFDR vs. fOUT and IOUTFS at 65 MSPS and 0 dBFS Figure 7. SFDR vs. fOUT at 125 MSPS Rev. C | Page 8 of 32 02913-010 75 02913-012 SFDR (dBc) 20mA Data Sheet AD9744 95 95 90 90 85 85 65MSPS 75 75 210MSPS 65 125MSPS 165MSPS 60 210MSPS (29,31) 125MSPS (16.9, 18.9) 60 50 50 –15 210MSPS (29,31) LFCSP 65 55 –20 –10 –5 0 AOUT (dBFS) 45 –25 –20 –15 –10 –5 0 AOUT (dBFS) Figure 11. Single-Tone SFDR vs. AOUT at fOUT = fCLOCK/11 Figure 14. Dual-Tone IMD vs. AOUT at fOUT = fCLOCK/7 1.5 95 165MSPS (LFCSP) 90 1.0 65MSPS 85 125MSPS (LFCSP) 80 0.5 ERROR (LSB) SFDR (dBc) 78MSPS (10.1, 12.1) 70 55 45 –25 165MSPS (22.6, 24.6) 02913-014 70 SFDR (dBc) 80 02913-013 SFDR (dBc) 210MSPS (LFCSP) 80 65MSPS (8.3,10.3) 75 70 65 0 –0.5 60 165MSPS 125MSPS 210MSPS (LFCSP) 55 –1.0 02913-015 16384 –20 –15 –10 –5 0 AOUT (dBFS) 02913-008 –1.5 45 –25 0 4096 8192 12288 CODE Figure 15. Typical INL Figure 12. Single-Tone SFDR vs. AOUT at fOUT = fCLOCK/5 90 1.0 IOUTFS = 20mA LFCSP 0.8 85 IOUTFS = 20mA 80 0.6 IOUTFS = 10mA LFCSP 0.4 ERROR (LSB) 75 70 IOUTFS = 10mA 65 0.2 0 –0.2 –0.4 IOUTFS = 5mA 60 IOUTFS = 5mA LFCSP –0.6 55 –0.8 50 0 30 60 90 120 150 180 210 fCLOCK (MSPS) 02913-011 SNR (dB) 16384 02913-018 210MSPS 50 Figure 13. SNR vs. fCLOCK and IOUTFS at fOUT = 5 MHz and 0 dBFS –1.0 0 4096 8192 12288 CODE Figure 16. Typical DNL Rev. C | Page 9 of 32 AD9744 Data Sheet 0 95 85 –20 80 –30 75 fCLOCK = 78MSPS fOUT1 = 15.0MHz fOUT2 = 15.4MHz fOUT3 = 15.8MHz fOUT4 = 16.2MHz SFDR = 75dBc AMPLITUDE = 0dBFS –10 4MHz MAGNITUDE (dBm) SFDR (dBc) 90 19MHz 70 65 34MHz 60 –40 –50 –60 –70 55 –80 50 –90 20 40 60 80 TEMPERATURE (°C) –100 1 6 11 Figure 17. SFDR vs. Temperature at 165 MSPS, 0 dBFS –20 fCLOCK = 78MSPS –10 26 31 SFDR = 79dBc AMPLITUDE = 0dBFS –40 MAGNITUDE (dBm) –30 –40 –50 –60 –70 –50 –60 –70 –80 –90 –80 –100 –90 –110 –100 –120 C12 C0 C12 C0 C11 C11 CU1 CU1 6 11 16 21 26 31 36 FREQUENCY (MHz) 02913-016 CU2 1 36 –39.01dBm 29.38000000MHz CHPWR –19.26dBm ACP UP –64.98dB ACP LOW +0.55dB ALT1 UP –66.26dB ALT1 LOW –64.23dB –30 fOUT = 15.0MHz –20 CENTER 33.22 MHz 3 MHz CU2 SPAN 30 MHz FREQUENCY (MHz) Figure 21. Two-Carrier UMTS Spectrum, fCLOCK = 122.88 MSPS (ACLR = 64 dB) LFCSP Package Figure 18. Single-Tone SFDR 0 –20 –30 –40 MAGNITUDE (dBm) –20 –40 –50 –60 –70 –50 –60 –70 –80 –90 –100 –90 –110 –100 6 11 16 21 26 FREQUENCY (MHz) 31 36 02913-019 –80 1 RES BW = 30kHz VBW = 300kHz ATTEN = 8dB AVG = 50 –30 –120 CENTER 10MHz FREQ OFFSET 5.000MHz Figure 19. Dual-Tone SFDR REF BW 3.840MHz LOWER dBc dBm –74.62 –84.12 SPAN 18MHz UPPER dBc dBm –75.04 –84.54 Figure 22. Single-Carrier UMTS Spectrum, fCLOCK = 61.44 MSPS (ACLR = 74 dB) LFCSP Package Rev. C | Page 10 of 32 02913-056 fCLOCK = 78MSPS fOUT1 = 15.0MHz fOUT2 = 15.4MHz SFDR = 77dBc AMPLITUDE = 0dBFS –10 MAGNITUDE (dBm) 21 Figure 20. Four-Tone SFDR 0 MAGNITUDE (dBm) 16 FREQUENCY (MHz) 02913-017 0 –20 02913-020 45 –40 02913-021 49MHz Data Sheet AD9744 3.3V REFLO +1.2V REF REFIO IREF 0.1µF RSET 2kΩ 3.3V FS ADJ AD9744 PMOS CURRENT SOURCE ARRAY VDIFF = VOUTA – VOUTB DVDD DCOM CLOCK ACOM CLOCK IOUTA IOUTA SEGMENTED SWITCHES FOR DB13–DB5 LSB SWITCHES LATCHES IOUTB IOUTB MODE SLEEP DIGITAL DATA INPUTS (DB13–DB0) Figure 23. Simplified Block Diagram (SOIC/TSSOP Packages) Rev. C | Page 11 of 32 VOUTA VOUTB RLOAD 50Ω RLOAD 50Ω 02913-022 VREFIO AVDD 150pF AD9744 Data Sheet TERMINOLOGY Linearity Error (Also Called Integral Nonlinearity or INL) It is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Power Supply Rejection The maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages. Differential Nonlinearity (or DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Settling Time The time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. Monotonicity A DAC is monotonic if the output either increases or remains constant as the digital input increases. Glitch Impulse Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse. It is specified as the net area of the glitch in pV-s. Offset Error The deviation of the output current from the ideal of zero is called the offset error. For IOUTA, 0 mA output is expected when the inputs are all 0s. For IOUTB, 0 mA output is expected when all inputs are set to 1s. Spurious-Free Dynamic Range The difference, in dB, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. Gain Error The difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to 1s minus the output when all inputs are set to 0s. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. It is expressed as a percentage or in decibels (dB). Output Compliance Range The range of allowable voltage at the output of a current output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance. Multitone Power Ratio The spurious-free dynamic range containing multiple carrier tones of equal amplitude. It is measured as the difference between the rms amplitude of a carrier tone to the peak spurious signal in the region of a removed tone. Temperature Drift It is specified as the maximum change from the ambient (25°C) value to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per °C. For reference drift, the drift is reported in ppm per °C. 3.3V REFLO AVDD 150pF REFIO PMOS CURRENT SOURCE ARRAY FS ADJ RSET 2kΩ 3.3V DVDD DCOM 50Ω RETIMED CLOCK OUTPUT* LECROY 9210 PULSE GENERATOR RHODE & SCHWARZ FSEA30 SPECTRUM ANALYZER IOUTA LSB SWITCHES SEGMENTED SWITCHES FOR DB13–DB5 CLOCK DVDD DCOM MINI-CIRCUITS T1-1T LATCHES IOUTB MODE 50Ω SLEEP 50Ω CLOCK OUTPUT DIGITAL DATA TEKTRONIX AWG-2021 WITH OPTION 4 *AWG2021 CLOCK RETIMED SO THAT THE DIGITAL DATA TRANSITIONS ON FALLING EDGE OF 50% DUTY CYCLE CLOCK. Figure 24. Basic AC Characterization Test Set-Up (SOIC/TSSOP Packages) Rev. C | Page 12 of 32 02913-005 0.1µF ACOM AD9744 1.2V REF Data Sheet AD9744 FUNCTIONAL DESCRIPTION The analog and digital sections of the AD9744 have separate power supply inputs, that is, AVDD and DVDD, that can operate independently over a 2.7 V to 3.6 V range. The digital section, which is capable of operating at a rate of up to 210 MSPS, consists of edge-triggered latches and segment decoding logic circuitry. The analog section includes the PMOS current sources, the associated differential switches, a 1.2 V band gap voltage reference, and a reference control amplifier. The DAC full-scale output current is regulated by the reference control amplifier and can be set from 2 mA to 20 mA via an external resistor, RSET, connected to the full-scale adjust (FS ADJ) pin. The external resistor, in combination with both the reference control amplifier and voltage reference VREFIO, sets the reference current IREF, which is replicated to the segmented current sources with the proper scaling factor. The full-scale current, IOUTFS, is 32 times IREF. AVDD 84µA REFIO 7kΩ REFLO Figure 25. Equivalent Circuit of Internal Reference 3.3V OPTIONAL EXTERNAL REF BUFFER REFLO REFIO 0.1µF 2kΩ CURRENT SOURCE ARRAY FS ADJ 02913-023 ADDITIONAL LOAD AD9744 Figure 26. Internal Reference Configuration An external reference can be applied to REFIO, as shown in Figure 27. The external reference may provide either a fixed reference voltage to enhance accuracy and drift performance or a varying reference voltage for gain control. Note that the 0.1 µF compensation capacitor is not required since the internal reference is overridden, and the relatively high input impedance of REFIO minimizes any loading of the external reference. 3.3V REFLO AVDD AVDD 150pF +1.2V REF VREFIO EXTERNAL REF REFIO FS ADJ RSET IREF = VREFIO/RSET AD9744 REFERENCE OPERATION The AD9744 contains an internal 1.2 V band gap reference. The internal reference cannot be disabled, but can be easily overridden by an external reference with no effect on performance. Figure 25 shows an equivalent circuit of the band gap reference. REFIO serves as either an output or an input depending on whether the internal or an external reference is used. To use the internal reference, simply decouple the REFIO pin to ACOM with a 0.1 µF capacitor and connect REFLO to ACOM via a resistance less than 5 Ω. The internal reference voltage will be present at REFIO. If the voltage at REFIO is to be used anywhere else in the circuit, an external buffer amplifier with an input bias AVDD 150pF +1.2V REF CURRENT SOURCE ARRAY REFERENCE CONTROL AMPLIFIER 02913-024 All of these current sources are switched to one or the other of the two output nodes, that is, IOUTA or IOUTB, via PMOS differential current switches. The switches are based on the architecture that was pioneered in the AD9764 family, with further refinements to reduce distortion contributed by the switching transient. This switch architecture also reduces various timing errors and provides matching complementary drive signals to the inputs of the differential current switches. current of less than 100 nA should be used. An example of the use of the internal reference is shown in Figure 26. 02913-057 Figure 23 shows a simplified block diagram of the AD9744. The AD9744 consists of a DAC, digital control logic, and full-scale output current control. The DAC contains a PMOS current source array capable of providing up to 20 mA of full-scale current (IOUTFS). The array is divided into 31 equal currents that make up the five most significant bits (MSBs). The next four bits, or middle bits, consist of 15 equal current sources whose value is 1/16th of an MSB current source. The remaining LSBs are binary weighted fractions of the middle bits current sources. Implementing the middle and lower bits with current sources, instead of an R-2R ladder, enhances its dynamic performance for multitone or low amplitude signals and helps maintain the DAC’s high output impedance (that is, >100 kΩ). Figure 27. External Reference Configuration REFERENCE CONTROL AMPLIFIER The AD9744 contains a control amplifier that is used to regulate the full-scale output current, IOUTFS. The control amplifier is configured as a V-I converter, as shown in Figure 26, so that its current output, IREF, is determined by the ratio of the VREFIO and an external resistor, RSET, as stated in Equation 4. IREF is copied to the segmented current sources with the proper scale factor to set IOUTFS, as stated in Equation 3. Rev. C | Page 13 of 32 AD9744 Data Sheet The control amplifier allows a wide (10:1) adjustment span of IOUTFS over a 2 mA to 20 mA range by setting IREF between 62.5 µA and 625 µA. The wide adjustment span of IOUTFS provides several benefits. The first relates directly to the power dissipation of the AD9744, which is proportional to IOUTFS (refer to the Power Dissipation section). The second relates to the 20 dB adjustment, which is useful for system gain control purposes. Equation 7 and Equation 8 highlight some of the advantages of operating the AD9744 differentially. First, the differential operation helps cancel common-mode error sources associated with IOUTA and IOUTB, such as noise, distortion, and dc offsets. Second, the differential code dependent current and subsequent voltage, VDIFF, is twice the value of the single-ended voltage output (that is, VOUTA or VOUTB), thus providing twice the signal power to the load. The small signal bandwidth of the reference control amplifier is approximately 500 kHz and can be used for low frequency small signal multiplying applications. Note that the gain drift temperature performance for a singleended (VOUTA and VOUTB) or differential output (VDIFF) of the AD9744 can be enhanced by selecting temperature tracking resistors for RLOAD and RSET due to their ratiometric relationship, as shown in Equation 8. DAC TRANSFER FUNCTION Both DACs in the AD9744 provide complementary current outputs, IOUTA and IOUTB. IOUTA provides a near full-scale current output, IOUTFS, when all bits are high (that is, DAC CODE = 16383), while IOUTB, the complementary output, provides no current. The current output appearing at IOUTA and IOUTB is a function of both the input code and IOUTFS and can be expressed as IOUTA = (DAC CODE /16384 ) × I OUTFS (1) IOUTB = (16383 − DAC CODE )/16384 × I OUTFS (2) where DAC CODE = 0 to 16383 (that is, decimal representation). As mentioned previously, IOUTFS is a function of the reference current IREF, which is nominally set by a reference voltage, VREFIO, and external resistor, RSET. It can be expressed as I OUTFS = 32 × I REF (3) where I REF = VREFIO / RSET (4) The two current outputs will typically drive a resistive load directly or via a transformer. If dc coupling is required, IOUTA and IOUTB should be directly connected to matching resistive loads, RLOAD, that are tied to analog common, ACOM. Note that RLOAD may represent the equivalent load resistance seen by IOUTA or IOUTB as would be the case in a doubly terminated 50 Ω or 75 Ω cable. The single-ended voltage output appearing at the IOUTA and IOUTB nodes is simply VOUTA = IOUTA × RLOAD (5) VOUTB = IOUTB × RLOAD (6) Note that the full-scale value of VOUTA and VOUTB should not exceed the specified output compliance range to maintain specified distortion and linearity performance. VDIFF = (IOUTA − IOUTB ) × RLOAD (7) Substituting the values of IOUTA, IOUTB, IREF, and VDIFF can be expressed as [ V DIFF = (2 × DAC CODE − 16383 )/16384 (32 × RLOAD / RSET )× VREFIO ] (8) ANALOG OUTPUTS The complementary current outputs in each DAC, IOUTA, and IOUTB may be configured for single-ended or differential operation. IOUTA and IOUTB can be converted into complementary single-ended voltage outputs, VOUTA and VOUTB, via a load resistor, RLOAD, as described in the DAC Transfer Function section by Equation 5 through Equation 8. The differential voltage, VDIFF, existing between VOUTA and VOUTB, can also be converted to a single-ended voltage via a transformer or differential amplifier configuration. The ac performance of the AD9744 is optimum and specified using a differential transformer-coupled output in which the voltage swing at IOUTA and IOUTB is limited to ±0.5 V. The distortion and noise performance of the AD9744 can be enhanced when it is configured for differential operation. The common-mode error sources of both IOUTA and IOUTB can be significantly reduced by the common-mode rejection of a transformer or differential amplifier. These common-mode error sources include even-order distortion products and noise. The enhancement in distortion performance becomes more significant as the frequency content of the reconstructed waveform increases and/or its amplitude decreases. This is due to the first-order cancellation of various dynamic commonmode distortion mechanisms, digital feedthrough, and noise. Performing a differential-to-single-ended conversion via a transformer also provides the ability to deliver twice the reconstructed signal power to the load (assuming no source termination). Since the output currents of IOUTA and IOUTB are complementary, they become additive when processed differentially. A properly selected transformer will allow the AD9744 to provide the required power and voltage levels to different loads. The output impedance of IOUTA and IOUTB is determined by the equivalent parallel combination of the PMOS switches associated with the current sources and is typically 100 kΩ in parallel with 5 pF. It is also slightly dependent on the output voltage (that is, VOUTA and VOUTB) due to the nature of a PMOS device. As a result, maintaining IOUTA and/or IOUTB at a virtual ground via an I-V op amp configuration will result in the optimum dc linearity. Note that the INL/DNL specifications Rev. C | Page 14 of 32 Data Sheet AD9744 for the AD9744 are measured with IOUTA maintained at a virtual ground via an op amp. CLOCK INPUT IOUTA and IOUTB also have a negative and positive voltage compliance range that must be adhered to in order to achieve optimum performance. The negative output compliance range of −1 V is set by the breakdown limits of the CMOS process. Operation beyond this maximum limit may result in a breakdown of the output stage and affect the reliability of the AD9744. The 28-lead package options have a single-ended clock input (CLOCK) that must be driven to rail-to-rail CMOS levels. The quality of the DAC output is directly related to the clock quality, and jitter is a key concern. Any noise or jitter in the clock will translate directly into the DAC output. Optimal performance will be achieved if the CLOCK input has a sharp rising edge, since the DAC latches are positive edge triggered. SOIC/TSSOP Packages The positive output compliance range is slightly dependent on the full-scale output current, IOUTFS. It degrades slightly from its nominal 1.2 V for an IOUTFS = 20 mA to 1 V for an IOUTFS = 2 mA. The optimum distortion performance for a single-ended or differential output is achieved when the maximum full-scale signal at IOUTA and IOUTB does not exceed 0.5 V. DIGITAL INPUTS The AD9744 digital section consists of 14 input bit channels and a clock input. The 14-bit parallel data inputs follow standard positive binary coding, where DB13 is the most significant bit (MSB) and DB0 is the least significant bit (LSB). IOUTA produces a full-scale output current when all data bits are at Logic 1. IOUTB produces a complementary output with the full-scale current split between the two outputs as a function of the input code. DVDD LFCSP Package A configurable clock input is available in the LFCSP package, which allows for one single-ended and two differential modes. The mode selection is controlled by the CMODE input, as summarized in Table 7. Connecting CMODE to CLKCOM selects the single-ended clock input. In this mode, the CLK+ input is driven with rail-to-rail swings and the CLK– input is left floating. If CMODE is connected to CLKVDD, the differential receiver mode is selected. In this mode, both inputs are high impedance. The final mode is selected by floating CMODE. This mode is also differential, but internal terminations for positive emitter-coupled logic (PECL) are activated. There is no significant performance difference among any of the three clock input modes. Table 7. Clock Mode Selection CMODE Pin CLKCOM CLKVDD Float 02913-025 DIGITAL INPUT Clock Input Mode Single-Ended Differential PECL The single-ended input mode operates in the same way as the CLOCK input in the 28-lead packages, as previously described. Figure 28. Equivalent Digital Input The digital interface is implemented using an edge-triggered master/slave latch. The DAC output updates on the rising edge of the clock and is designed to support a clock rate as high as 210 MSPS. The clock can be operated at any duty cycle that meets the specified latch pulse width. The setup and hold times can also be varied within the clock cycle as long as the specified minimum times are met, although the location of these transition edges may affect digital feedthrough and distortion performance. Best performance is typically achieved when the input data transitions on the falling edge of a 50% duty cycle clock. In the differential input mode, the clock input functions as a high impedance differential pair. The common-mode level of the CLK+ and CLK− inputs can vary from 0.75 V to 2.25 V, and the differential voltage can be as low as 0.5 V p-p. This mode can be used to drive the clock with a differential sine wave since the high gain bandwidth of the differential inputs will convert the sine wave into a single-ended square wave internally. The final clock mode allows for a reduced external component count when the DAC clock is distributed on the board using PECL logic. The internal termination configuration is shown in Figure 29. These termination resistors are untrimmed and can vary up to ±20%. However, matching between the resistors should generally be better than ±1%. Rev. C | Page 15 of 32 AD9744 Data Sheet POWER DISSIPATION AD9744 The power dissipation, PD, of the AD9744 is dependent on several factors that include: CLOCK RECEIVER CLK– • 50Ω 02913-026 50Ω TO DAC CORE VTT = 1.3V NOM • • • Figure 29. Clock Termination in PECL Mode DAC TIMING Input Clock and Data Timing Relationship Dynamic performance in a DAC is dependent on the relationship between the position of the clock edges and the time at which the input data changes. The AD9744 is rising edge triggered, and so exhibits dynamic performance sensitivity when the data transition is close to this edge. In general, the goal when applying the AD9744 is to make the data transition close to the falling clock edge. This becomes more important as the sample rate increases. Figure 30 shows the relationship of SFDR to clock placement with different sample rates. Note that at the lower sample rates, more tolerance is allowed in clock placement, while at higher rates, more care must be taken. The power supply voltages (AVDD, CLKVDD, and DVDD) The full-scale current output IOUTFS The update rate fCLOCK The reconstructed digital input waveform The power dissipation is directly proportional to the analog supply current, IAVDD, and the digital supply current, IDVDD. IAVDD is directly proportional to IOUTFS, as shown in Figure 31, and is insensitive to fCLOCK. Conversely, IDVDD is dependent on both the digital input waveform, fCLOCK, and digital supply DVDD. Figure 32 shows IDVDD as a function of full-scale sine wave output ratios (fOUT/fCLOCK) for various update rates with DVDD = 3.3 V. 75 70 35 30 25 IAVDD (mA) CLK+ 20 15 65 0 50MHz SFDR 2 50 6 8 10 12 IOUTFS (mA) 14 16 18 20 Figure 31. IAVDD vs. IOUTFS 45 20 40 50MHz SFDR –2 18 –1 0 ns 1 2 3 210MSPS 02913-027 35 –3 4 02913-028 55 16 Sleep Mode Operation The AD9744 has a power-down function that turns off the output current and reduces the supply current to less than 6 mA over the specified supply range of 2.7 V to 3.6 V and temperature range. This mode can be activated by applying a logic level 1 to the SLEEP pin. The SLEEP pin logic threshold is equal to 0.5 Ω AVDD. This digital input also contains an active pull-down circuit that ensures that the AD9744 remains enabled if this input is left disconnected. The AD9744 takes less than 50 ns to power down and approximately 5 µs to power back up. Rev. C | Page 16 of 32 IDVDD (mA) 14 Figure 30. SFDR vs. Clock Placement at fOUT = 20 MHz and 50 MHz 165MSPS 12 10 125MSPS 8 6 65MSPS 4 2 0 0.01 0.1 RATIO (fOUT/fCLOCK) Figure 32. IDVDD vs. Ratio at DVDD = 3.3 V 1 02913-029 dB 10 20MHz SFDR 60 Data Sheet AD9744 11 for impedance matching purposes. Note that the transformer provides ac coupling only. 10 9 MINI-CIRCUITS T1-1T IOUTA 22 7 DIFF RLOAD AD9744 PECL IOUTB 21 5 OPTIONAL RDIFF 4 SE Figure 34. Differential Output Using a Transformer 3 2 0 0 50 100 150 fCLOCK (MSPS) 200 250 02913-030 1 Figure 33. ICLKVDD vs. fCLOCK and Clock Mode APPLYING THE AD9744 Output Configurations The following sections illustrate some typical output configurations for the AD9744. Unless otherwise noted, it is assumed that IOUTFS is set to a nominal 20 mA. For applications requiring the optimum dynamic performance, a differential output configuration is suggested. A differential output configuration may consist of either an RF transformer or a differential op amp configuration. The transformer configuration provides the optimum high frequency performance and is recommended for any application that allows ac coupling. The differential op amp configuration is suitable for applications requiring dc coupling, a bipolar output, signal gain, and/or level shifting within the bandwidth of the chosen op amp. A single-ended output is suitable for applications requiring a unipolar voltage output. A positive unipolar output voltage results if IOUTA and/or IOUTB are connected to an appropriately sized load resistor, RLOAD, referred to ACOM. This configuration may be more suitable for a single-supply system requiring a dc-coupled, ground referred output voltage. Alternatively, an amplifier could be configured as an I-V converter, thus converting IOUTA or IOUTB into a negative unipolar voltage. This configuration provides the best dc linearity since IOUTA or IOUTB is maintained at a virtual ground. The center tap on the primary side of the transformer must be connected to ACOM to provide the necessary dc current path for both IOUTA and IOUTB. The complementary voltages appearing at IOUTA and IOUTB (that is, VOUTA and VOUTB) swing symmetrically around ACOM and should be maintained with the specified output compliance range of the AD9744. A differential resistor, RDIFF, may be inserted in applications where the output of the transformer is connected to the load, RLOAD, via a passive reconstruction filter or cable. RDIFF is determined by the transformer’s impedance ratio and provides the proper source termination that results in a low VSWR. Note that approximately half the signal power will be dissipated across RDIFF. DIFFERENTIAL COUPLING USING AN OP AMP An op amp can also be used to perform a differential-to-singleended conversion, as shown in Figure 35. The AD9744 is configured with two equal load resistors, RLOAD, of 25 Ω. The differential voltage developed across IOUTA and IOUTB is converted to a single-ended signal via the differential op amp configuration. An optional capacitor can be installed across IOUTA and IOUTB, forming a real pole in a low-pass filter. The addition of this capacitor also enhances the op amp’s distortion performance by preventing the DAC’s high slewing output from overloading the op amp’s input. 500 AD9744 225 IOUTA 22 225 IOUTB 21 AD8047 COPT 500 25 DIFFERENTIAL COUPLING USING A TRANSFORMER 25 02913-032 6 02913-031 ICLKVDD (mA) 8 Figure 35. DC Differential Coupling Using an Op Amp An RF transformer can be used to perform a differential-to-singleended signal conversion, as shown in Figure 34. A differentially coupled transformer output provides the optimum distortion performance for output signals whose spectral content lies within the transformer’s pass band. An RF transformer, such as the Mini-Circuits T1–1T, provides excellent rejection of common-mode distortion (that is, even-order harmonics) and noise over a wide frequency range. It also provides electrical isolation and the ability to deliver twice the power to the load. Transformers with different impedance ratios may also be used The common-mode rejection of this configuration is typically determined by the resistor matching. In this circuit, the differential op amp circuit using the AD8047 is configured to provide some additional signal gain. The op amp must operate off a dual supply since its output is approximately ±1 V. A high speed amplifier capable of preserving the differential performance of the AD9744 while meeting other system level objectives (such as cost or power) should be selected. The op amp’s differential gain, gain setting resistor values, and full-scale output swing capabilities should all be considered when optimizing this circuit. Rev. C | Page 17 of 32 AD9744 Data Sheet The differential circuit shown in Figure 36 provides the necessary level shifting required in a single-supply system. In this case, AVDD, which is the positive analog supply for both the AD9744 and the op amp, is also used to level-shift the differential output of the AD9744 to midsupply (that is, AVDD/2). The AD8041 is a suitable op amp for this application. COPT RFB 200Ω IOUTFS = 10mA AD9744 IOUTA 22 U1 500Ω 200Ω 02913-035 AD9744 VOUT = IOUTFS × RFB IOUTB 21 225Ω IOUTA 22 1kΩ AVDD 1kΩ 25Ω 25Ω POWER AND GROUNDING CONSIDERATIONS, POWER SUPPLY REJECTION Figure 36. Single-Supply DC Differential Coupled Circuit SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT Figure 37 shows the AD9744 configured to provide a unipolar output range of approximately 0 V to 0.5 V for a doubly terminated 50 Ω cable since the nominal full-scale current, IOUTFS, of 20 mA flows through the equivalent RLOAD of 25 Ω. In this case, RLOAD represents the equivalent load resistance seen by IOUTA or IOUTB. The unused output (IOUTA or IOUTB) can be connected to ACOM directly or via a matching RLOAD. Different values of IOUTFS and RLOAD can be selected as long as the positive compliance range is adhered to. One additional consideration in this mode is the integral nonlinearity (INL), discussed in the Analog Outputs section. For optimum INL performance, the singleended, buffered voltage output configuration is suggested. AD9744 IOUTFS = 20mA VOUTA = 0V TO 0.5V IOUTA 22 50Ω 50Ω 25Ω 02913-034 IOUTB 21 Many applications seek high speed and high performance under less than ideal operating conditions. In these application circuits, the implementation and construction of the printed circuit board is as important as the circuit design. Proper RF techniques must be used for device selection, placement, and routing as well as power supply bypassing and grounding to ensure optimum performance. Figure 43 to Figure 46 illustrate the recommended printed circuit board ground, power, and signal plane layouts implemented on the AD9744 evaluation board. One factor that can measurably affect system performance is the ability of the DAC output to reject dc variations or ac noise superimposed on the analog or digital dc power distribution. This is referred to as the power supply rejection ratio (PSRR). For dc variations of the power supply, the resulting performance of the DAC directly corresponds to a gain error associated with the DAC’s full-scale current, IOUTFS. AC noise on the dc supplies is common in applications where the power distribution is generated by a switching power supply. Typically, switching power supply noise will occur over the spectrum from tens of kHz to several MHz. The PSRR vs. frequency of the AD9744 AVDD supply over this frequency range is shown in Figure 39. 85 Figure 37. 0 V to 0.5 V Unbuffered Voltage Output 80 SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT CONFIGURATION 75 Figure 38 shows a buffered single-ended output configuration in which the op amp U1 performs an I-V conversion on the AD9744 output current. U1 maintains IOUTA (or IOUTB) at a virtual ground, minimizing the nonlinear output impedance effect on the DAC’s INL performance as described in the Analog Outputs section. Although this single-ended configuration typically provides the best dc linearity performance, its ac distortion performance at higher DAC update rates may be limited by U1’s slew rate capabilities. U1 provides a negative unipolar output voltage, and its full-scale output voltage is simply the product of RFB and IOUTFS. The full-scale output should be set within U1’s voltage output swing capabilities by scaling IOUTFS and/or RFB. An improvement in ac distortion performance may result with a reduced IOUTFS since the signal current U1 will be required to sink less signal current. PSRR (dB) 70 65 60 55 50 45 40 0 2 4 6 8 FREQUENCY (MHz) 10 12 02913-036 COPT 02913-033 IOUTB 21 Figure 38. Unipolar Buffered Voltage Output AD8041 225Ω Figure 39. Power Supply Rejection Ratio (PSRR) vs. Frequency Note that the ratio in Figure 39 is calculated as amps out/volts in. Noise on the analog power supply has the effect of modulating the internal switches, and therefore the output current. The voltage noise on AVDD, therefore, will be added in a nonlinear manner to the desired IOUT. Due to the relative different size of Rev. C | Page 18 of 32 Data Sheet AD9744 An example serves to illustrate the effect of supply noise on the analog supply. Suppose a switching regulator with a switching frequency of 250 kHz produces 10 mV of noise and, for simplicity’s sake (ignoring harmonics), all of this noise is concentrated at 250 kHz. To calculate how much of this undesired noise will appear as current noise superimposed on the DAC’s full-scale current, IOUTFS, one must determine the PSRR in dB using Figure 39 at 250 kHz. To calculate the PSRR for a given RLOAD, such that the units of PSRR are converted from A/V to V/V, adjust the curve in Figure 39 by the scaling factor 20 Ω log (RLOAD). For instance, if RLOAD is 50 Ω, the PSRR is reduced by 34 dB (that is, PSRR of the DAC at 250 kHz, which is 85 dB in Figure 39, becomes 51 dB VOUT/VIN). AD9744 features separate analog and digital supplies and ground pins to optimize the management of analog and digital ground currents in a system. In general, AVDD, the analog supply, should be decoupled to ACOM, the analog common, as close to the chip as physically possible. Similarly, DVDD, the digital supply, should be decoupled to DCOM as close to the chip as physically possible. For those applications that require a single 3.3 V supply for both the analog and digital supplies, a clean analog supply may be generated using the circuit shown in Figure 40. The circuit consists of a differential LC filter with separate power supply and return lines. Lower noise can be attained by using low ESR type electrolytic and tantalum capacitors. FERRITE BEADS TTL/CMOS LOGIC CIRCUITS AVDD 100µF ELECT. 10µF–22µF TANT. 0.1µF CER. ACOM 3.3V POWER SUPPLY Figure 40. Differential LC Filter for Single 3.3 V Applications Proper grounding and decoupling should be a primary objective in any high speed, high resolution system. The Rev. C | Page 19 of 32 02913-037 these switches, the PSRR is very code dependent. This can produce a mixing effect that can modulate low frequency power supply noise to higher frequencies. Worst-case PSRR for either one of the differential DAC outputs will occur when the full-scale current is directed toward that output. As a result, the PSRR measurement in Figure 39 represents a worst-case condition in which the digital inputs remain static and the full-scale output current of 20 mA is directed to the DAC output being measured. AD9744 Data Sheet EVALUATION BOARD GENERAL DESCRIPTION The TxDAC family evaluation boards allow for easy setup and testing of any TxDAC product in the SOIC and LFCSP packages. Careful attention to layout and circuit design, combined with a prototyping area, allows the user to evaluate the AD9744 easily and effectively in any application where high resolution, high speed conversion is required. This board allows the user the flexibility to operate the AD9744 in various configurations. Possible output configurations include transformer coupled, resistor terminated, and single and differential outputs. The digital inputs are designed to be driven from various word generators, with the on-board option to add a resistor network for proper load termination. Provisions are also made to operate the AD9744 with either the internal or external reference or to exercise the power-down feature. JP3 CKEXTX L2 BEAD RED TP2 DVDD TB1 1 C7 0.1µF 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 DB13X DB12X DB11X DB10X DB9X DB8X DB7X DB6X DB5X DB4X DB3X DB2X DB1X DB0X BLK TP4 + C4 10µF 25V C6 0.1µF BLK TP7 1 DCOM 2 R1 3 R2 4 R3 5 R4 6 R5 7 R6 8 R7 9 R8 10 R9 RP3 RP3 RP3 RP3 RP3 RP3 RP3 RP3 RP4 RP4 RP4 RP4 RP4 RP4 RP4 8 RP4 CKEXTX RIBBON RP5 OPT RP1 OPT 22Ω 16 22Ω 15 22Ω 14 22Ω 13 22Ω 12 22Ω 11 22Ω 10 22Ω 9 22Ω 16 22Ω 15 22Ω 14 22Ω 13 22Ω 12 22Ω 11 22Ω 10 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 22Ω 9 RP6 OPT CKEXT DCOM 1 R1 2 R2 3 R3 4 R4 5 R5 6 R6 7 R7 8 R8 9 R9 10 DB13X DB12X DB11X DB10X DB9X DB8X DB7X DB6X DB5X DB4X DB3X DB2X DB1X DB0X 1 2 3 4 5 6 7 8 9 10 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 DCOM 1 R1 2 R2 3 R3 4 R4 5 R5 6 R6 7 R7 8 R8 9 R9 10 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 DCOM R1 R2 R3 R4 R5 R6 R7 R8 R9 J1 RP2 OPT BLK TP8 TB1 2 L3 BEAD RED TP5 C9 0.1µF BLK TP6 + C5 10µF 25V C8 0.1µF BLK TP10 BLK TP9 TB1 4 Figure 41. SOIC Evaluation Board—Power Supply and Digital Inputs Rev. C | Page 20 of 32 02913-038 AVDD TB1 3 Data Sheet AD9744 AVDD + C14 10µF 16V C16 0.1µF CUT UNDER DUT C17 0.1µF JP6 DVDD C18 0.1µF DVDD C19 0.1µF R5 OPT CKEXT 3 R11 50Ω S5 JP4 AVDD JP10 A B 2 S2 IOUTA CLOCK DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 IX 1 2 3 4 5 6 7 8 9 10 11 12 13 14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 CLOCK DVDD DCOM MODE AVDD RESERVED IOUTA U1 AD9742 IOUTB ACOM NC FS ADJ REFIO REFLO SLEEP 2 A B 3 1 EXT JP5 INT REF 28 27 26 25 24 23 22 21 20 19 18 17 16 15 CLOCK TP1 WHT DVDD R4 50Ω R2 10kΩ C13 OPT DVDD JP8 JP2 IOUT MODE AVDD 3 T1 5 2 R6 OPT 4 S3 6 1 T1-1T REF R1 2kΩ TP3 WHT C11 0.1µF C1 0.1µF C2 0.1µF C12 OPT JP9 AVDD SLEEP TP11 WHT R10 50Ω S1 IOUTB R3 10kΩ IY Figure 42. SOIC Evaluation Board—Output Signal Conditioning Rev. C | Page 21 of 32 1 2 A B 3 JP11 02913-039 + C15 10µF 16V Data Sheet 02913-040 AD9744 02913-041 Figure 43. SOIC Evaluation Board—Primary Side Figure 44. SOIC Evaluation Board—Secondary Side Rev. C | Page 22 of 32 AD9744 02913-042 Data Sheet 02913-043 Figure 45. SOIC Evaluation Board—Ground Plane Figure 46. SOIC Evaluation Board—Power Plane Rev. C | Page 23 of 32 Data Sheet 02913-044 AD9744 02913-045 Figure 47. SOIC Evaluation Board Assembly—Primary Side Figure 48. SOIC Evaluation Board Assembly—Secondary Side Rev. C | Page 24 of 32 Data Sheet AD9744 RED TP12 TB1 CVDD 1 C3 0.1µF TB1 BLK C10 0.1µF C2 10µF 6.3V TP2 2 2 4 1 3 6 5 8 7 DB10X 10 9 DB9X 11 DB8X 13 DB7X 15 DB6X 17 DB5X 19 DB4X 21 DB3X 23 DB2X 25 DB1X 27 DB0X 12 L2 BEAD TB3 16 DVDD 1 C7 0.1µF TB3 14 RED TP13 18 20 BLK C6 0.1µF C4 10µF 6.3V TP4 22 24 26 2 28 RED TP5 L3 BEAD C9 0.1µF TB4 32 AVDD 1 BLK 36 C8 0.1µF C5 10µF 6.3V TP6 34 DB12X DB11X 29 31 33 35 JP3 CKEXTX 37 39 38 40 2 DB13X J1 R3 100Ω R4 100Ω R15 100Ω R16 100Ω R17 100Ω R18 100Ω R19 100Ω DB13X DB12X DB11X DB10X DB9X DB8X DB7X DB6X DB5X DB4X DB3X DB2X DB1X DB0X CKEXTX R21 100Ω R24 100Ω R25 100Ω R26 100Ω R27 100Ω R20 100Ω 1 RP3 22Ω 16 2 RP3 22Ω 15 3 RP3 22Ω 14 4 RP3 22Ω 13 5 RP3 22Ω 12 6 RP3 22Ω 11 7 RP3 22Ω 10 8 RP3 22Ω 9 1 RP4 22Ω 16 2 RP4 22Ω 15 3 RP4 22Ω 14 4 RP4 22Ω 13 5 RP4 22Ω 12 6 RP4 7 RP4 22Ω 11 22Ω 10 8 RP4 22Ω 9 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 CKEXT R28 100Ω 02913-046 TB4 30 HEADER STRAIGHT UP MALE NO SHROUD L1 BEAD Figure 49. LFCSP Evaluation Board Schematic—Power Supply and Digital Inputs Rev. C | Page 25 of 32 AD9744 Data Sheet AVDD DVDD CVDD C19 0.1µF 0.1 C17 0.1µF C32 0.1µF SLEEP TP11 WHT R29 10kΩ DB7 DB6 DVDD DB5 DB4 DB3 DB2 DB1 DB0 CVDD CLK CLKB CMODE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DB7 DB6 DVDD DB5 DB4 DB3 DB2 DB1 DB0 DCOM U1 CVDD CLK CLKB CCOM CMODE MODE DB8 DB9 DB10 DB11 DB12 DB13 DCOM1 SLEEP FS ADJ REFIO ACOM IA IB ACOM1 AVDD AVDD1 32 31 30 29 28 27 DB8 DB9 DB10 DB11 DB12 DB13 R11 50Ω DNP C13 26 25 24 23 22 TP3 TP1 WHT WHT JP8 IOUT 3 21 20 19 18 17 TP7 4 S3 AGND: 3, 4, 5 5 2 6 1 AVDD T1 – 1T C11 0.1µF JP9 AD9744LFCSP WHT T1 DNP C12 R30 10kΩ R10 50Ω CVDD R1 2kΩ 0.1% JP1 02913-047 MODE Figure 50. LFCSP Evaluation Board Schematic—Output Signal Conditioning CVDD 1 7 U4 C35 0.1µF C20 10µF 16V 2 AGND: 5 CVDD: 8 CVDD R5 120Ω 3 JP2 CKEXT CLK U4 6 S5 AGND: 3, 4, 5 4 AGND: 5 CVDD: 8 R2 120Ω C34 0.1µF R6 50Ω 02913-048 CLKB Figure 51. LFCSP Evaluation Board Schematic—Clock Input Rev. C | Page 26 of 32 AD9744 02913-049 Data Sheet 02913-050 Figure 52. LFCSP Evaluation Board Layout—Primary Side Figure 53. LFCSP Evaluation Board Layout—Secondary Side Rev. C | Page 27 of 32 Data Sheet 02913-051 AD9744 02913-052 Figure 54. LFCSP Evaluation Board Layout—Ground Plane Figure 55. LFCSP Evaluation Board Layout—Power Plane Rev. C | Page 28 of 32 AD9744 02913-053 Data Sheet 02913-054 Figure 56. LFCSP Evaluation Board Layout Assembly—Primary Side Figure 57. LFCSP Evaluation Board Layout Assembly—Secondary Side Rev. C | Page 29 of 32 AD9744 Data Sheet OUTLINE DIMENSIONS 9.80 9.70 9.60 28 15 4.50 4.40 4.30 6.40 BSC 1 14 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 COPLANARITY 0.10 0.30 0.19 SEATING PLANE 8° 0° 0.20 0.09 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AE Figure 58. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters 18.10 (0.7126) 17.70 (0.6969) 15 28 7.60 (0.2992) 7.40 (0.2913) 14 2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 10.65 (0.4193) 10.00 (0.3937) 1.27 (0.0500) BSC 0.51 (0.0201) 0.31 (0.0122) SEATING PLANE 0.75 (0.0295) 45° 0.25 (0.0098) 8° 0° 0.33 (0.0130) 0.20 (0.0079) COMPLIANT TO JEDEC STANDARDS MS-013-AE CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 59. 28-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-28) Dimensions shown in millimeters and (inches) Rev. C | Page 30 of 32 1.27 (0.0500) 0.40 (0.0157) 06-07-2006-A 1 Data Sheet AD9744 0.30 0.25 0.18 32 25 0.50 BSC TOP VIEW 0.80 0.75 0.70 8 16 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 3.25 3.10 SQ 2.95 EXPOSED PAD 17 0.50 0.40 0.30 PIN 1 INDICATOR 1 24 9 BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. 112408-A PIN 1 INDICATOR 5.10 5.00 SQ 4.90 Figure 60. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 5 mm × 5 mm Body, Very Very Thin Quad (CP-32-7) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD9744AR AD9744ARZ AD9744ARZRL AD9744ARU AD9744ARURL7 AD9744ARUZ AD9744ARUZRL7 AD9744ACPZ AD9744ACPZRL7 AD9744-EBZ AD9744ACP-PCBZ 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 28-Lead, 300-Mil SOIC_W 28-Lead, 300-Mil SOIC_W 28-Lead, 300-Mil SOIC_W 28-Lead TSSOP 28-Lead TSSOP 28-Lead TSSOP 28-Lead TSSOP 32-Lead LFCSP_WQ 32-Lead LFCSP_WQ Evaluation Board (SOIC) Evaluation Board (LFCSP) Z = RoHS Compliant Part. Rev. C | Page 31 of 32 Package Options RW-28 RW-28 RW-28 RU-28 RU-28 RU-28 RU-28 CP-32-7 CP-32-7 AD9744 Data Sheet NOTES ©2003–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02913-0-12/13(C) Rev. C | Page 32 of 32